date:20160217

Re: [PATCH V4 0/6] perf/amd/iommu: Enable multi-IOMMU support

2016-02-17 Thread Suravee Suthikulpanit


Hi All,

I am wondering if there are any other concerns for this patch series.

Thanks,
Suravee

On 2/11/16 16:15, Suravee Suthikulpanit wrote:

From: Suravee Suthikulpanit 

This patch series modifies the existing perf_event_amd_iommu driver
to support systems with multiple IOMMUs. It introduces new AMD IOMMU APIs,
which are used by the AMD IOMMU Perf driver to access performance
counters in multiple IOMMUs.

In addition, this series should also fix current AMD IOMMU PMU driver
initialization issue in some existing KV and CZ platform, where it fails
to write to IOMMU perf counter as reported by Andreas Hartmann here
(http://comments.gmane.org/gmane.linux.kernel.pci/49147).

Git branch containing this patch series is available here:

 https://github.com/ssuthiku/linux.git  perf-iommu-v4

Changes from V3 (https://lkml.org/lkml/2016/2/9/845)
   * Rebase the code to tip/master per Boris suggestion
   * Most changes are in patch 5/6:
 * Fix several spelling and styling issues per Boris review comment
 * Remove unnecessary pr_debug in the perf amd iommu driver (per Boris)
 * Rename several function to make it less confusing (per Boris)
 * Properly handle errors when fails to set registers/counters
   on multiple IOMMUs. (per Boris)

Changes from V2 ( https://lkml.org/lkml/2016/1/1/141)
   * Ported to 4.5.0-rc2
   * Add reviewed by Joerg for patch 1 and 2
   * Remove EXPORT_SYMBOL from patch 3 (per Joerg suggestion)
   * Merge patch 4/6 and 6/6 from V2 into 5/5 in V3 and add
 more description in the commit message and in code comment.
   * Patch 5: modify the logic to update counts to get rid off
 un-necessary local64_cmpxchg().

Changes from V1 (https://lkml.org/lkml/2015/12/22/535):
   * Update patch3 and 6 to use amd_iommus_present instead of introducing
 amd_iommu_cnt static variable since they are the same thing

Suravee Suthikulpanit (6):
   perf/amd/iommu: Consolidate and move perf_event_amd_iommu header
   perf/amd/iommu: Modify functions to query max banks and counters
   iommu/amd: Introduce amd_iommu_get_num_iommus()
   perf/amd/iommu: Introduce get_iommu_bnk_cnt_evt_idx
   perf/amd/iommu: Enable support for multiple IOMMUs
   perf/amd/iommu: Declar pr_fmt and remove unnecessary pr_debug

  arch/x86/events/amd/iommu.c   | 197 ++
  arch/x86/events/amd/iommu.h   |  40 ---
  arch/x86/include/asm/perf/amd/iommu.h |  42 
  drivers/iommu/amd_iommu_init.c| 136 +++
  drivers/iommu/amd_iommu_proto.h   |   7 --
  5 files changed, 286 insertions(+), 136 deletions(-)
  delete mode 100644 arch/x86/events/amd/iommu.h
  create mode 100644 arch/x86/include/asm/perf/amd/iommu.h


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Re: [PATCH v8 3/5] memory: mediatek: Add SMI driver

2016-02-17 Thread Yong Wu

On Tue, 2016-02-16 at 15:11 +0100, Joerg Roedel wrote:
> On Sun, Jan 31, 2016 at 12:00:41PM +0100, Matthias Brugger wrote:
> > 
> > 
> > On 26/01/16 05:12, Yong Wu wrote:
> > >This patch add SMI(Smart Multimedia Interface) driver. This driver
> > >is responsible to enable/disable iommu and control the power domain
> > >and clocks of each local arbiter.
> > >
> > >Signed-off-by: Yong Wu 
> > >Tested-by: Philipp Zabel 
> > >---
> > 
> > Signed-off-by: Matthias Brugger 
> > 
> > Joerg would you mind to take this through your branch?
> 
> Hmm, I somehow missed the patch-set, at least I can't find the v8
> patches in my inbox.
> 
> Yong, can you please re-send with all Acks and other tags added?

Hi Joerg,
  
 I have re-sent v9[1] which has added all the tags yesterday.

 Could you find them in your inbox? If not again, please tell me.

 Thanks.

[1]:http://lists.linuxfoundation.org/pipermail/iommu/2016-February/015713.html

> 
> 
> Thanks,
> 
>   Joerg
> 


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Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

2016-02-17 Thread Alex Williamson

On Wed, 17 Feb 2016 17:15:09 +0530
Jayachandran Chandrashekaran Nair
 wrote:

> On Wed, Feb 17, 2016 at 3:55 AM, Alex Williamson
>  wrote:
> > On Wed, 17 Feb 2016 02:38:24 +0530
> > Jayachandran Chandrashekaran Nair
> >  wrote:
> >  
> >> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
> >>  wrote:  
> >> > On Mon, 15 Feb 2016 12:20:23 -0600
> >> > Bjorn Helgaas  wrote:
> >> >  
> >> >> [+cc Alex, iommu list]
> >> >>
> >> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:  
> >> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
> >> >> > that should not be considered during DMA alias search. This is
> >> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
> >> >> > that has internal bridges which have either missing or wrong PCIe
> >> >> > capabilities.  
> >> >
> >> > I figured this would come at some point, the right answer is of course
> >> > to follow the PCIe spec and implement the required PCIe capability in
> >> > the hardware.  
> >>
> >> There are  PCIe controllers on the chip that follows the spec, the issue is
> >> how it is integrated to the northbridge (equivalent) on the chip, I have
> >> tried to explain it below.
> >>  
> >> >> This needs more explanation, like what exactly is wrong with this
> >> >> device?  A missing PCIe capability might cause other problems.
> >> >>
> >> >> What problem does this fix?  Without these patches, do we merely add
> >> >> aliases that are unnecessary?  Do we crash because something goes
> >> >> wrong in the pci_pcie_type() switch because of the incorrect
> >> >> capability?  
> >>
> >> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
> >> processor will look like:
> >>
> >>
> >> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
> >> |  +--1.a.1[4]-4.0.0---[5]5.0.0
> >> |  .
> >> |  ... etc...
> >> |
> >> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
> >>+-10.a.1[13]---13.0.0---[14]---14.0.0
> >>.
> >>... etc...  
> >
> > So we have:
> >
> > "Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
> >   (no pcie)  (pci/x-pcie)  
> 
> The top level is one glue bridge per chip in a multi-chip board,
> but otherwise this is accurate.
> 
> >>
> >> The devices 0.0.x and x.a.x are glue bridges that are there to
> >> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
> >> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
> >> have a PCIe capability (type 8) and 0.0.x does not have any pcie
> >> capability.
> >>
> >> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
> >> driver code does dma alias walk to find the device id to use
> >> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
> >> since they are type root port, but will continue on up and end
> >> up with incorrect device id.
> >>
> >> The flag I have added is to make the pci_for_each_dma_alias()
> >> ignore the last 2 levels of glue/internal bridges.  
> >
> > Per the PCIe spec, I'm not even sure what you have is a valid
> > hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
> > bridge.  So really you're pretending that the downstream "glue bridge"
> > is your host bridge and therefore root complex, but the PCI topology
> > would clearly dictate that the top-most bus is conventional PCI and
> > therefore everything is an alias of everything else and the DMA alias
> > code is doing exactly what it should.  
> 
> Yes, I am not arguing that there is any issue in the current code. I
> am trying to figure out the correct way to implement the quirk. We
> have to support the hardware we have, not the hardware we want to
> have :)
> 
> > Also note that the caller of pci_for_each_dma_alias() owns the callback
> > function triggered for each alias, that function could choose to prune
> > out these "glue bridges" itself if that's the appropriate thing to do.  
> 
> I had implemented this first, but moved to the current approach because
> it is needed in multiple places. The problem is: "On vulcan, while
> going up the pcie bus heirarchy for finding aliases, skip the glue bridges",
> So the logical place to put the fix is in pci_for_each_dma_alias()
> 
> > Where do the SMMU and ITS actually reside in the above diagram?  You
> > can use the callout function to stop the traversal anywhere you wish,
> > it's free to return a -errno to stop or positive number, which the
> > caller can interpret as error or non-failure stop condition.  
> 
> The SMMU (for translation requests) and ITS (for MSI writes for
> interrupts) are connected directly to the proper PCIe controller
> (2/4/11/13.0.0 above)


If the translation unit is on the root port then DMA aliases

Re: [PATCH 1/2] iommu: call detach also for default_domain before attaching to new one

2016-02-17 Thread Marek Szyprowski


Hello,

On 2016-02-17 12:14, Joerg Roedel wrote:

On Wed, Feb 17, 2016 at 08:35:10AM +0100, Marek Szyprowski wrote:

Huh, I wasn't aware of this change in the iommu drivers api. For some
drivers attach/detach callbacks does something more than just programming
page table base register, like for example in case of exynos iommu it is
enabling runtime power management and clocks. The code is really
much simpler
if those calls are balanced, but if the goal is to allow multiple
unballanced
attach calls, I will try to fix this in our driver.

Maybe it should be documented somewhere, that attach calls can be
unbalanced?

Well, when your driver uses default-domains, the detach_dev call-back is
not used anymore. The attach_dev call-back is supposed to just overwrite
any existing binding that may exist for the device. So the calls are not
unbalanced, the detach_dev calls just don't happen anymore.


From driver perspective the default_domains don't really differ from the
'other' domains. They are just allocated from the IOMMU core and used by
the IOMMU/DMA-mapping glue code. That's what I got from reading the code.

There should be also a way to detach the driver even from the default domain
to implement the arch_tear_down_dma_ops function.

Best regards
--
Marek Szyprowski, PhD
Samsung R Institute Poland

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Re: [PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

2016-02-17 Thread Robin Murphy


On 17/02/16 14:31, Will Deacon wrote:

Hi Robin,

On Thu, Jan 28, 2016 at 01:41:29PM +, Robin Murphy wrote:

On 27/01/16 01:16, Yong Wu wrote:

On Tue, 2016-01-26 at 17:13 +, Robin Murphy wrote:

Add a nearly-complete ARMv7 short descriptor implementation, omitting
only a few legacy and CPU-centric aspects which shouldn't be necessary
for IOMMU API use anyway.

Signed-off-by: Yong Wu 
Signed-off-by: Robin Murphy 


This looks good to me.
And actually our disp/vdec/venc works well on your v2.

You could choose the two below,
Reviewed-by: Yong Wu 
Tested-by: Yong Wu 


Great, thanks!

Will, it seems to make the most sense for Joerg to pick these patches up
directly with the MTK series that depends on them - any objections?


As discussed with Joerg, I'll pick these up and send him a pull request
containing all the pgtable bits. I've taken the liberty of updating
MAINTAINERS too, assuming you don't mind being a reviewer for this?


Sure, that's fine by me.


Will

--->8

 From bccb08d096703bd790fcf2f934553dd9c8503fc9 Mon Sep 17 00:00:00 2001
From: Will Deacon 
Date: Wed, 17 Feb 2016 14:18:00 +
Subject: [PATCH] MAINTAINERS: update ARM SMMU entry

Ensure that the short-descriptor page table code is included under the
SMMU entry, and add Robin as a designated reviewer.

Cc: Robin Murphy 


s/Cc/Acked-by/

Robin.


Signed-off-by: Will Deacon 
---
  MAINTAINERS | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cc2f753cb357..a01bae148b89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1793,11 +1793,13 @@ F:  drivers/edac/synopsys_edac.c

  ARM SMMU DRIVERS
  M:Will Deacon 
+R: Robin Murphy 
  L:linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
  S:Maintained
  F:drivers/iommu/arm-smmu.c
  F:drivers/iommu/arm-smmu-v3.c
  F:drivers/iommu/io-pgtable-arm.c
+F: drivers/iommu/io-pgtable-arm-v7s.c

  ARM64 PORT (AARCH64 ARCHITECTURE)
  M:Catalin Marinas 



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Re: [PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

2016-02-17 Thread Will Deacon

Hi Robin,

On Thu, Jan 28, 2016 at 01:41:29PM +, Robin Murphy wrote:
> On 27/01/16 01:16, Yong Wu wrote:
> >On Tue, 2016-01-26 at 17:13 +, Robin Murphy wrote:
> >>Add a nearly-complete ARMv7 short descriptor implementation, omitting
> >>only a few legacy and CPU-centric aspects which shouldn't be necessary
> >>for IOMMU API use anyway.
> >>
> >>Signed-off-by: Yong Wu 
> >>Signed-off-by: Robin Murphy 
> >
> >This looks good to me.
> >And actually our disp/vdec/venc works well on your v2.
> >
> >You could choose the two below,
> >Reviewed-by: Yong Wu 
> >Tested-by: Yong Wu 
> 
> Great, thanks!
> 
> Will, it seems to make the most sense for Joerg to pick these patches up
> directly with the MTK series that depends on them - any objections?

As discussed with Joerg, I'll pick these up and send him a pull request
containing all the pgtable bits. I've taken the liberty of updating
MAINTAINERS too, assuming you don't mind being a reviewer for this?

Will

--->8

>From bccb08d096703bd790fcf2f934553dd9c8503fc9 Mon Sep 17 00:00:00 2001
From: Will Deacon 
Date: Wed, 17 Feb 2016 14:18:00 +
Subject: [PATCH] MAINTAINERS: update ARM SMMU entry

Ensure that the short-descriptor page table code is included under the
SMMU entry, and add Robin as a designated reviewer.

Cc: Robin Murphy 
Signed-off-by: Will Deacon 
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cc2f753cb357..a01bae148b89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1793,11 +1793,13 @@ F:  drivers/edac/synopsys_edac.c
 
 ARM SMMU DRIVERS
 M: Will Deacon 
+R: Robin Murphy 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
 F: drivers/iommu/arm-smmu.c
 F: drivers/iommu/arm-smmu-v3.c
 F: drivers/iommu/io-pgtable-arm.c
+F: drivers/iommu/io-pgtable-arm-v7s.c
 
 ARM64 PORT (AARCH64 ARCHITECTURE)
 M: Catalin Marinas 
-- 
2.1.4

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Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

2016-02-17 Thread Jayachandran Chandrashekaran Nair

On Wed, Feb 17, 2016 at 3:55 AM, Alex Williamson
 wrote:
> On Wed, 17 Feb 2016 02:38:24 +0530
> Jayachandran Chandrashekaran Nair
>  wrote:
>
>> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
>>  wrote:
>> > On Mon, 15 Feb 2016 12:20:23 -0600
>> > Bjorn Helgaas  wrote:
>> >
>> >> [+cc Alex, iommu list]
>> >>
>> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:
>> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
>> >> > that should not be considered during DMA alias search. This is
>> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
>> >> > that has internal bridges which have either missing or wrong PCIe
>> >> > capabilities.
>> >
>> > I figured this would come at some point, the right answer is of course
>> > to follow the PCIe spec and implement the required PCIe capability in
>> > the hardware.
>>
>> There are  PCIe controllers on the chip that follows the spec, the issue is
>> how it is integrated to the northbridge (equivalent) on the chip, I have
>> tried to explain it below.
>>
>> >> This needs more explanation, like what exactly is wrong with this
>> >> device?  A missing PCIe capability might cause other problems.
>> >>
>> >> What problem does this fix?  Without these patches, do we merely add
>> >> aliases that are unnecessary?  Do we crash because something goes
>> >> wrong in the pci_pcie_type() switch because of the incorrect
>> >> capability?
>>
>> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
>> processor will look like:
>>
>>
>> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
>> |  +--1.a.1[4]-4.0.0---[5]5.0.0
>> |  .
>> |  ... etc...
>> |
>> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
>>+-10.a.1[13]---13.0.0---[14]---14.0.0
>>.
>>... etc...
>
> So we have:
>
> "Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
>   (no pcie)  (pci/x-pcie)

The top level is one glue bridge per chip in a multi-chip board,
but otherwise this is accurate.

>>
>> The devices 0.0.x and x.a.x are glue bridges that are there to
>> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
>> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
>> have a PCIe capability (type 8) and 0.0.x does not have any pcie
>> capability.
>>
>> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
>> driver code does dma alias walk to find the device id to use
>> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
>> since they are type root port, but will continue on up and end
>> up with incorrect device id.
>>
>> The flag I have added is to make the pci_for_each_dma_alias()
>> ignore the last 2 levels of glue/internal bridges.
>
> Per the PCIe spec, I'm not even sure what you have is a valid
> hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
> bridge.  So really you're pretending that the downstream "glue bridge"
> is your host bridge and therefore root complex, but the PCI topology
> would clearly dictate that the top-most bus is conventional PCI and
> therefore everything is an alias of everything else and the DMA alias
> code is doing exactly what it should.

Yes, I am not arguing that there is any issue in the current code. I
am trying to figure out the correct way to implement the quirk. We
have to support the hardware we have, not the hardware we want to
have :)

> Also note that the caller of pci_for_each_dma_alias() owns the callback
> function triggered for each alias, that function could choose to prune
> out these "glue bridges" itself if that's the appropriate thing to do.

I had implemented this first, but moved to the current approach because
it is needed in multiple places. The problem is: "On vulcan, while
going up the pcie bus heirarchy for finding aliases, skip the glue bridges",
So the logical place to put the fix is in pci_for_each_dma_alias()

> Where do the SMMU and ITS actually reside in the above diagram?  You
> can use the callout function to stop the traversal anywhere you wish,
> it's free to return a -errno to stop or positive number, which the
> caller can interpret as error or non-failure stop condition.

The SMMU (for translation requests) and ITS (for MSI writes for
interrupts) are connected directly to the proper PCIe controller
(2/4/11/13.0.0 above)

> You could even think about changing what Linux considers to be the host
> bridge.  Maybe these glue bridges shouldn't even be visible to Linux,
> would that also solve the issue with the broken BAR?

The glue bridges have to seen by Linux for assigning resources like
bus ranges and memory windows. So these are required bridges in
the topology and will work with the standard linux code
(provided we skip them for

Re: [PATCH 1/2] iommu: call detach also for default_domain before attaching to new one

2016-02-17 Thread Joerg Roedel

On Wed, Feb 17, 2016 at 08:35:10AM +0100, Marek Szyprowski wrote:
> Huh, I wasn't aware of this change in the iommu drivers api. For some
> drivers attach/detach callbacks does something more than just programming
> page table base register, like for example in case of exynos iommu it is
> enabling runtime power management and clocks. The code is really
> much simpler
> if those calls are balanced, but if the goal is to allow multiple
> unballanced
> attach calls, I will try to fix this in our driver.
> 
> Maybe it should be documented somewhere, that attach calls can be
> unbalanced?

Well, when your driver uses default-domains, the detach_dev call-back is
not used anymore. The attach_dev call-back is supposed to just overwrite
any existing binding that may exist for the device. So the calls are not
unbalanced, the detach_dev calls just don't happen anymore.



Joerg

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[PATCH v9 5/5] dts: mt8173: Add iommu/smi nodes for mt8173

2016-02-17 Thread Yong Wu

This patch add the iommu/larbs nodes for mt8173

Signed-off-by: Yong Wu 
Reviewed-by: Daniel Kurtz 
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 81 
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index ec135ea..8048811 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -277,6 +278,17 @@
reg = <0 0x10200620 0 0x20>;
};
 
+   iommu: iommu@10205000 {
+   compatible = "mediatek,mt8173-m4u";
+   reg = <0 0x10205000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = <  
+   >;
+   #iommu-cells = <1>;
+   };
+
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
@@ -589,29 +601,98 @@
status = "disabled";
};
 
+   larb0: larb@14021000 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x14021000 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB0>,
+< CLK_MM_SMI_LARB0>;
+   clock-names = "apb", "smi";
+   };
+
+   smi_common: smi@14022000 {
+   compatible = "mediatek,mt8173-smi-common";
+   reg = <0 0x14022000 0 0x1000>;
+   power-domains = < MT8173_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON>,
+< CLK_MM_SMI_COMMON>;
+   clock-names = "apb", "smi";
+   };
+
+   larb4: larb@14027000 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x14027000 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB4>,
+< CLK_MM_SMI_LARB4>;
+   clock-names = "apb", "smi";
+   };
+
imgsys: clock-controller@1500 {
compatible = "mediatek,mt8173-imgsys", "syscon";
reg = <0 0x1500 0 0x1000>;
#clock-cells = <1>;
};
 
+   larb2: larb@15001000 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x15001000 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_ISP>;
+   clocks = < CLK_IMG_LARB2_SMI>,
+< CLK_IMG_LARB2_SMI>;
+   clock-names = "apb", "smi";
+   };
+
vdecsys: clock-controller@1600 {
compatible = "mediatek,mt8173-vdecsys", "syscon";
reg = <0 0x1600 0 0x1000>;
#clock-cells = <1>;
};
 
+   larb1: larb@1601 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x1601 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_VDEC>;
+   clocks = < CLK_VDEC_CKEN>,
+< CLK_VDEC_LARB_CKEN>;
+   clock-names = "apb", "smi";
+   };
+
vencsys: clock-controller@1800 {
compatible = "mediatek,mt8173-vencsys", "syscon";
reg = <0 0x1800 0 0x1000>;
#clock-cells = <1>;
};
 
+   larb3: larb@18001000 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x18001000 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_VENC>;
+   clocks = < CLK_VENC_CKE1>,
+< CLK_VENC_CKE0>;
+   clock-names = "apb", "smi";
+   };
+
vencltsys: clock-controller@1900 {
compatible = "mediatek,mt8173-vencltsys", "syscon";
reg = <0

[PATCH v9 4/5] iommu/mediatek: Add mt8173 IOMMU driver

2016-02-17 Thread Yong Wu

This patch adds support for mediatek m4u (MultiMedia Memory Management
Unit).

Signed-off-by: Yong Wu 
Reviewed-by: Robin Murphy 
---
 drivers/iommu/Kconfig |  16 +
 drivers/iommu/Makefile|   1 +
 drivers/iommu/mtk_iommu.c | 732 ++
 3 files changed, 749 insertions(+)
 create mode 100644 drivers/iommu/mtk_iommu.c

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index a1e75cb..4922aa8 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -318,4 +318,20 @@ config S390_IOMMU
help
  Support for the IOMMU API for s390 PCI devices.
 
+config MTK_IOMMU
+   bool "MTK IOMMU Support"
+   depends on ARM || ARM64
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   select IOMMU_API
+   select IOMMU_DMA
+   select IOMMU_IO_PGTABLE_ARMV7S
+   select MEMORY
+   select MTK_SMI
+   help
+ Support for the M4U on certain Mediatek SOCs. M4U is MultiMedia
+ Memory Management Unit. This option enables remapping of DMA memory
+ accesses for the multimedia subsystem.
+
+ If unsure, say N here.
+
 endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 42fc0c2..44ae2e0 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
 obj-$(CONFIG_INTEL_IOMMU_SVM) += intel-svm.o
 obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
 obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
+obj-$(CONFIG_MTK_IOMMU) += mtk_iommu.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
 obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
new file mode 100644
index 000..60fe97b
--- /dev/null
+++ b/drivers/iommu/mtk_iommu.c
@@ -0,0 +1,732 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "io-pgtable.h"
+
+#define REG_MMU_PT_BASE_ADDR   0x000
+
+#define REG_MMU_INVALIDATE 0x020
+#define F_ALL_INVLD0x2
+#define F_MMU_INV_RANGE0x1
+
+#define REG_MMU_INVLD_START_A  0x024
+#define REG_MMU_INVLD_END_A0x028
+
+#define REG_MMU_INV_SEL0x038
+#define F_INVLD_EN0BIT(0)
+#define F_INVLD_EN1BIT(1)
+
+#define REG_MMU_STANDARD_AXI_MODE  0x048
+#define REG_MMU_DCM_DIS0x050
+
+#define REG_MMU_CTRL_REG   0x110
+#define F_MMU_PREFETCH_RT_REPLACE_MOD  BIT(4)
+#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
+
+#define REG_MMU_IVRP_PADDR 0x114
+#define F_MMU_IVRP_PA_SET(pa)  ((pa) >> 1)
+
+#define REG_MMU_INT_CONTROL0   0x120
+#define F_L2_MULIT_HIT_EN  BIT(0)
+#define F_TABLE_WALK_FAULT_INT_EN  BIT(1)
+#define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
+#define F_MISS_FIFO_OVERFLOW_INT_ENBIT(3)
+#define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
+#define F_MISS_FIFO_ERR_INT_EN BIT(6)
+#define F_INT_CLR_BIT  BIT(12)
+
+#define REG_MMU_INT_MAIN_CONTROL   0x124
+#define F_INT_TRANSLATION_FAULTBIT(0)
+#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
+#define F_INT_INVALID_PA_FAULT BIT(2)
+#define F_INT_ENTRY_REPLACEMENT_FAULT  BIT(3)
+#define F_INT_TLB_MISS_FAULT   BIT(4)
+#define F_INT_MISS_TRANSACTION_FIFO_FAULT  BIT(5)
+#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT   BIT(6)
+
+#define REG_MMU_CPE_DONE   0x12C
+
+#define REG_MMU_FAULT_ST1  0x134
+
+#define REG_MMU_FAULT_VA   0x13c
+#define F_MMU_FAULT_VA_MSK 0xf000
+#define F_MMU_FAULT_VA_WRITE_BIT   BIT(1)
+#define F_MMU_FAULT_VA_LAYER_BIT   BIT(0)
+
+#define REG_MMU_INVLD_PA   0x140
+#define REG_MMU_INT_ID 0x150
+#define F_MMU0_INT_ID_LARB_ID(a)   (((a) >> 7)

[PATCH v9 1/5] dt-bindings: iommu: Add binding for mediatek IOMMU

2016-02-17 Thread Yong Wu

This patch add mediatek iommu dts binding document.

Signed-off-by: Yong Wu 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/iommu/mediatek,iommu.txt   | 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt 
b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
new file mode 100644
index 000..cd1b1cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -0,0 +1,68 @@
+* Mediatek IOMMU Architecture Implementation
+
+  Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which
+uses the ARM Short-Descriptor translation table format for address translation.
+
+  About the M4U Hardware Block Diagram, please check below:
+
+  EMI (External Memory Interface)
+   |
+  m4u (Multimedia Memory Management Unit)
+   |
+   SMI Common(Smart Multimedia Interface Common)
+   |
+   ++---
+   ||
+   ||
+   SMI larb0SMI larb1   ... SoCs have several SMI local arbiter(larb).
+   (display) (vdec)
+   ||
+   ||
+ +-+-+ +++
+ | | | |||
+ | | |...  |||  ... There are different ports in each larb.
+ | | | |||
+OVL0 RDMA0 WDMA0  MC   PP   VLD
+
+  As above, The Multimedia HW will go through SMI and M4U while it
+access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
+smi local arbiter and smi common. It will control whether the Multimedia
+HW should go though the m4u for translation or bypass it and talk
+directly with EMI. And also SMI help control the power domain and clocks for
+each local arbiter.
+  Normally we specify a local arbiter(larb) for each multimedia HW
+like display, video decode, and camera. And there are different ports
+in each larb. Take a example, There are many ports like MC, PP, VLD in the
+video decode local arbiter, all these ports are according to the video HW.
+
+Required properties:
+- compatible : must be "mediatek,mt8173-m4u".
+- reg : m4u register base and size.
+- interrupts : the interrupt of m4u.
+- clocks : must contain one entry for each clock-names.
+- clock-names : must be "bclk", It is the block clock of m4u.
+- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
+   Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
+   according to the local arbiter index, like larb0, larb1, larb2...
+- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
+   Specifies the mtk_m4u_id as defined in
+   dt-binding/memory/mt8173-larb-port.h.
+
+Example:
+   iommu: iommu@10205000 {
+   compatible = "mediatek,mt8173-m4u";
+   reg = <0 0x10205000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = < >;
+   #iommu-cells = <1>;
+   };
+
+Example for a client device:
+   display {
+   compatible = "mediatek,mt8173-disp";
+   iommus = < M4U_PORT_DISP_OVL0>,
+< M4U_PORT_DISP_RDMA0>;
+   ...
+   };
-- 
1.8.1.1.dirty

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[PATCH v9 3/5] memory: mediatek: Add SMI driver

2016-02-17 Thread Yong Wu

This patch add SMI(Smart Multimedia Interface) driver. This driver
is responsible to enable/disable iommu and control the power domain
and clocks of each local arbiter.

Signed-off-by: Yong Wu 
Tested-by: Philipp Zabel 
Reviewed-by: Daniel Kurtz 
Tested-by: Daniel Kurtz 
Signed-off-by: Matthias Brugger 
---
 drivers/memory/Kconfig |   8 ++
 drivers/memory/Makefile|   1 +
 drivers/memory/mtk-smi.c   | 272 +
 include/soc/mediatek/smi.h |  58 ++
 4 files changed, 339 insertions(+)
 create mode 100644 drivers/memory/mtk-smi.c
 create mode 100644 include/soc/mediatek/smi.h

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 6f31546..51d5cd2 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -114,6 +114,14 @@ config JZ4780_NEMC
  the Ingenic JZ4780. This controller is used to handle external
  memory devices such as NAND and SRAM.
 
+config MTK_SMI
+   bool
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   help
+ This driver is for the Memory Controller module in MediaTek SoCs,
+ mainly help enable/disable iommu and control the power domain and
+ clocks for each local arbiter.
+
 source "drivers/memory/tegra/Kconfig"
 
 endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 1c46af5..890bdf4 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)  += jz4780-nemc.o
+obj-$(CONFIG_MTK_SMI)  += mtk-smi.o
 
 obj-$(CONFIG_TEGRA_MC) += tegra/
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
new file mode 100644
index 000..702f0d2
--- /dev/null
+++ b/drivers/memory/mtk-smi.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SMI_LARB_MMU_EN0xf00
+
+struct mtk_smi {
+   struct device   *dev;
+   struct clk  *clk_apb, *clk_smi;
+};
+
+struct mtk_smi_larb { /* larb: local arbiter */
+   struct mtk_smi  smi;
+   void __iomem*base;
+   struct device   *smi_common_dev;
+   u32 *mmu;
+};
+
+static int mtk_smi_enable(const struct mtk_smi *smi)
+{
+   int ret;
+
+   ret = pm_runtime_get_sync(smi->dev);
+   if (ret < 0)
+   return ret;
+
+   ret = clk_prepare_enable(smi->clk_apb);
+   if (ret)
+   goto err_put_pm;
+
+   ret = clk_prepare_enable(smi->clk_smi);
+   if (ret)
+   goto err_disable_apb;
+
+   return 0;
+
+err_disable_apb:
+   clk_disable_unprepare(smi->clk_apb);
+err_put_pm:
+   pm_runtime_put_sync(smi->dev);
+   return ret;
+}
+
+static void mtk_smi_disable(const struct mtk_smi *smi)
+{
+   clk_disable_unprepare(smi->clk_smi);
+   clk_disable_unprepare(smi->clk_apb);
+   pm_runtime_put_sync(smi->dev);
+}
+
+int mtk_smi_larb_get(struct device *larbdev)
+{
+   struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
+   struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
+   int ret;
+
+   /* Enable the smi-common's power and clocks */
+   ret = mtk_smi_enable(common);
+   if (ret)
+   return ret;
+
+   /* Enable the larb's power and clocks */
+   ret = mtk_smi_enable(>smi);
+   if (ret) {
+   mtk_smi_disable(common);
+   return ret;
+   }
+
+   /* Configure the iommu info for this larb */
+   writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
+
+   return 0;
+}
+
+void mtk_smi_larb_put(struct device *larbdev)
+{
+   struct mtk_smi_larb *larb = dev_get_drvdata(larbdev);
+   struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
+
+   /*
+* Don't de-configure the iommu info for this larb since there may be
+* several modules in this larb.
+* The iommu info will be reset after power off.
+*/
+
+   mtk_smi_disable(>smi);
+   mtk_smi_disable(common);
+}
+
+static int
+mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
+{
+   struct mtk_smi_larb *larb = dev_get_drvdata(dev);
+

[PATCH v9 2/5] dt-bindings: mediatek: Add smi dts binding

2016-02-17 Thread Yong Wu

This patch add smi binding document and smi local arbiter header file.

Signed-off-by: Yong Wu 
Acked-by: Rob Herring 
---
 .../memory-controllers/mediatek,smi-common.txt |  24 +
 .../memory-controllers/mediatek,smi-larb.txt   |  25 +
 include/dt-bindings/memory/mt8173-larb-port.h  | 111 +
 3 files changed, 160 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
 create mode 100644 
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
 create mode 100644 include/dt-bindings/memory/mt8173-larb-port.h

diff --git 
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
new file mode 100644
index 000..06a83ce
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -0,0 +1,24 @@
+SMI (Smart Multimedia Interface) Common
+
+The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
+
+Required properties:
+- compatible : must be "mediatek,mt8173-smi-common"
+- reg : the register and size of the SMI block.
+- power-domains : a phandle to the power domain of this local arbiter.
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : must contain 2 entries, as follows:
+  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
+   the register.
+  - "smi" : It's the clock for transfer data and command.
+  They may be the same if both source clocks are the same.
+
+Example:
+   smi_common: smi@14022000 {
+   compatible = "mediatek,mt8173-smi-common";
+   reg = <0 0x14022000 0 0x1000>;
+   power-domains = < MT8173_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON>,
+< CLK_MM_SMI_COMMON>;
+   clock-names = "apb", "smi";
+   };
diff --git 
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 
b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
new file mode 100644
index 000..55ff3b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -0,0 +1,25 @@
+SMI (Smart Multimedia Interface) Local Arbiter
+
+The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
+
+Required properties:
+- compatible : must be "mediatek,mt8173-smi-larb"
+- reg : the register and size of this local arbiter.
+- mediatek,smi : a phandle to the smi_common node.
+- power-domains : a phandle to the power domain of this local arbiter.
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names: must contain 2 entries, as follows:
+  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
+   the register.
+  - "smi" : It's the clock for transfer data and command.
+
+Example:
+   larb1: larb@1601 {
+   compatible = "mediatek,mt8173-smi-larb";
+   reg = <0 0x1601 0 0x1000>;
+   mediatek,smi = <_common>;
+   power-domains = < MT8173_POWER_DOMAIN_VDEC>;
+   clocks = < CLK_VDEC_CKEN>,
+< CLK_VDEC_LARB_CKEN>;
+   clock-names = "apb", "smi";
+   };
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h 
b/include/dt-bindings/memory/mt8173-larb-port.h
new file mode 100644
index 000..5fef5d1
--- /dev/null
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DTS_IOMMU_PORT_MT8173_H
+#define __DTS_IOMMU_PORT_MT8173_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)(((id) >> 5) & 0x7)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)((id) & 0x1f)
+
+#define M4U_LARB0_ID   0
+#define M4U_LARB1_ID   1
+#define M4U_LARB2_ID   2
+#define M4U_LARB3_ID   3
+#define M4U_LARB4_ID   4
+#define M4U_LARB5_ID   5
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R

[PATCH v9 0/5] MT8173 IOMMU SUPPORT

2016-02-17 Thread Yong Wu

  This patch set adds support for m4u(Multimedia Memory Management Unit),
Currently it only support the m4u with 2 levels of pagetable on mt8173.

  It's based on Robin Murphy's Short-descriptor v3[1].
 
  Please check the hardware block diagram of Mediatek IOMMU.
 
  m4u (Multimedia Memory Management Unit)
   |
   SMI Common(Smart Multimedia Interface Common)
   |
   ++---
   ||
   ||
   SMI larb0SMI larb1   ... SoCs have several SMI local arbiter(larb).
   (display) (vdec)
   ||
   ||
 +-+-+ +++
 | | | |||
 | | |...  |||  ... There are different ports in each larb.
 | | | |||
OVL0 RDMA0 WDMA0  MC   PP   VLD

  As above, The Multimedia HW will go through SMI and M4U while it
access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
smi local arbiter and smi common. It will control whether the Multimedia
HW should go though the m4u for translation or bypass it and talk
directly with EMI. And also SMI help control the power domain and clocks for
each local arbiter.
  Normally we specify a local arbiter(larb) for each multimedia HW
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.

[1] : http://thread.gmane.org/gmane.linux.kernel.iommu/12007

v9:
 - rebase onto Robin's Short-descriptor v3.
 - add the Acks and other tags for all the patches(No change the code).

v8: http://thread.gmane.org/gmane.linux.kernel.iommu/11974
 - rebase onto v4.5-rc1.
 - add depends on (ARM || ARM64) for MTK_IOMMU in Kconfig to avoid build fail
   in other ARCHs.
 - delete COHERENCE_EN bit.
 - delete a *if* while config iommu information since the iommu is always
   enabled currently.

v7: http://lists.linuxfoundation.org/pipermail/iommu/2015-December/015214.html
- rebase onto Robin's short v2:
  http://lists.linuxfoundation.org/pipermail/iommu/2015-December/015210.html
- Adjust the iommu probe sequence to meet the expectant flow that the iommu
  core help create the domain.
- use component additional data instead of the interface mtk_smi_config_port.
- reconstruct the SMI help function.

v6: http://lists.linuxfoundation.org/pipermail/iommu/2015-December/015105.html
-rebase onto v4.4-rc1.
-Use Robin's reposting Short-decriptor.
 http://lists.linuxfoundation.org/pipermail/iommu/2015-December/015088.html
-Add component for m4u and smi since m4u should depend on smi-larb.
 The master device is the m4u device, and the client one is the smi-larb 
device. 
-Change mtk iommu-cells from 2 to 1 since the mapping between larb and port is
 fixed. Compare this with v2, we redefine MTK_M4U_ID following this register
 REG_MMU_INT_ID.
-About SMI: Add some help funcion and rename some function and struction for
 more readable. 
 These three above are according to Daniel Kurtz's suggestion.

v5: http://lists.linuxfoundation.org/pipermail/iommu/2015-October/014586.html
-rebase onto v4.3-rc1.
-About MTK iommu: don't return the same domain while domain_alloc, change the
 domain's flow according to the M4U HW.
-About Short-descriptor: Improve many error-handles, NO_PERMS quirk, and 
 add TLBI_MAP quirk following Will's Suggestion; Add io-pgtable don't use 
 dma_to_phys; Add a loop in arm_short_unmap since iommu_unmap don't care the 
 physical address align.
-About SMI driver: Add a help funcion for some similar code. Add PROPRE_DEFER
 for power-domain as MTK SCPSYS is module_init currently.

v4: http://lists.linuxfoundation.org/pipermail/iommu/2015-August/013903.html
-use only one iommu domain here based on the Robin's DMA-v5:
 http://lists.linuxfoundation.org/pipermail/iommu/2015-July/013900.html
-remove flush_pgtable.
-change writel to writel_relaxed.
-about Short-descriptor: move dma_map_single into io-pgtable-arm-short.
 Improve the flow of free pgtable and add NO_XN+NO_PERMS quirk following
 Will's suggestion.
-Change two sytle issues in dtsi according to Daniel's suggestion.

v3: http://lists.linuxfoundation.org/pipermail/iommu/2015-July/013632.html
-rebased onto v4.2-rc1
-improve iommu flow based on the Robin's DMA v3:
 http://lists.linuxfoundation.org/pipermail/iommu/2015-July/013597.html
-change mtk iommu-cells from 1 to 2.
-about Short-descriptor: add split function; add self-test; add some other bits 
like nG,
 XN according to the spec; add SUPERSECTION and MTK quirk; move 
io_pgtable_ops_to_pgtable
 out from LPAE to the header file.
-about SMI: move from driver/soc/mediatek to driver/memory; change the clocks 
from
 clk[2] to clk_apb and clk_smi; add pm.
-add iommu suspend/resume to backup/restore register.

v2: http://lists.linuxfoundation.org/pipermail/iommu/2015-May/013028.html
-add arm short descriptor support.

Re: [PATCH V4 0/6] perf/amd/iommu: Enable multi-IOMMU support

Re: [PATCH v8 3/5] memory: mediatek: Add SMI driver

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

Re: [PATCH 1/2] iommu: call detach also for default_domain before attaching to new one

Re: [PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

Re: [PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

Re: [PATCH 1/2] iommu: call detach also for default_domain before attaching to new one

[PATCH v9 5/5] dts: mt8173: Add iommu/smi nodes for mt8173

[PATCH v9 4/5] iommu/mediatek: Add mt8173 IOMMU driver

[PATCH v9 1/5] dt-bindings: iommu: Add binding for mediatek IOMMU

[PATCH v9 3/5] memory: mediatek: Add SMI driver

[PATCH v9 2/5] dt-bindings: mediatek: Add smi dts binding

[PATCH v9 0/5] MT8173 IOMMU SUPPORT

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