Re: [PATCH v1 08/16] arm64: dts: mt8195: Add power domains controller
Hi Krzysztof,
After discussing your message with our power team,
we realized that we need your help to ensure we fully understand you.
On Mon, 2022-07-04 at 14:38 +0200, Krzysztof Kozlowski wrote:
> On 04/07/2022 12:00, Tinghan Shen wrote:
> > Add power domains controller node for mt8195.
> >
> > Signed-off-by: Weiyi Lu
> > Signed-off-by: Tinghan Shen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 327 +++
> > 1 file changed, 327 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 8d59a7da3271..d52e140d9271 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > / {
> > compatible = "mediatek,mt8195";
> > @@ -338,6 +339,332 @@
> > #interrupt-cells = <2>;
> > };
> >
> > + scpsys: syscon@10006000 {
> > + compatible = "syscon", "simple-mfd";
>
> These compatibles cannot be alone.
the scpsys sub node has the compatible of the power domain driver.
do you suggest that the compatible in the sub node should move to here?
> > + reg = <0 0x10006000 0 0x1000>;
> > + #power-domain-cells = <1>;
>
> If it is simple MFD, then probably it is not a power domain provider.
> Decide.
this MFD device is the power controller on mt8195. Some features need
to do some operations on registers in this node. We think that implement
the operation of these registers as the MFD device can provide flexibility
for future use. We want to clarify if you're saying that an MFD device
cannot be a power domain provider.
Best regards,
TingHan
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Re: [PATCH v1 03/16] dt-bindings: power: mediatek: Refine multiple level power domain nodes
On Tue, 2022-07-05 at 14:57 -0600, Rob Herring wrote: > On Mon, Jul 04, 2022 at 06:00:15PM +0800, Tinghan Shen wrote: > > Extract duplicated properties and support more levels of power > > domain nodes. > > > > This change fix following error when do dtbs_check, > > arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: > > power-domain@15: > > power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', > > 'power-domain@21' do not > > match any of the regexes: 'pinctrl-[0-9]+' > > From schema: > > Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > > > Signed-off-by: Tinghan Shen > > --- > > .../power/mediatek,power-controller.yaml | 132 ++ > > 1 file changed, 12 insertions(+), 120 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > index 135c6f722091..09a537a802b8 100644 > > --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > > @@ -39,8 +39,17 @@ properties: > >'#size-cells': > > const: 0 > > > > +required: > > + - compatible > > + > > +additionalProperties: false > > + > > patternProperties: > >"^power-domain@[0-9a-f]+$": > > +$ref: "#/$defs/power-domain-node" > > + > > +$defs: > > + power-domain-node: > > type: object > > description: | > >Represents the power domains within the power controller node as > > documented > > @@ -98,127 +107,10 @@ patternProperties: > > $ref: /schemas/types.yaml#/definitions/phandle > > description: phandle to the device containing the SMI register > > range. > > > > -patternProperties: > > - "^power-domain@[0-9a-f]+$": > > -type: object > > -description: | > > - Represents a power domain child within a power domain parent > > node. > > - > > -properties: > > - > > - '#power-domain-cells': > > -description: > > - Must be 0 for nodes representing a single PM domain and 1 > > for nodes > > - providing multiple PM domains. > > - > > - '#address-cells': > > -const: 1 > > - > > - '#size-cells': > > -const: 0 > > - > > - reg: > > -maxItems: 1 > > - > > - clocks: > > -description: | > > - A number of phandles to clocks that need to be enabled > > during domain > > - power-up sequencing. > > - > > - clock-names: > > -description: | > > - List of names of clocks, in order to match the power-up > > sequencing > > - for each power domain we need to group the clocks by name. > > BASIC > > - clocks need to be enabled before enabling the corresponding > > power > > - domain, and should not have a '-' in their name (i.e mm, > > mfg, venc). > > - SUSBYS clocks need to be enabled before releasing the bus > > protection, > > - and should contain a '-' in their name (i.e mm-0, isp-0, > > cam-0). > > - > > - In order to follow properly the power-up sequencing, the > > clocks must > > - be specified by order, adding first the BASIC clocks > > followed by the > > - SUSBSYS clocks. > > - > > - domain-supply: > > -description: domain regulator supply. > > - > > - mediatek,infracfg: > > -$ref: /schemas/types.yaml#/definitions/phandle > > -description: phandle to the device containing the INFRACFG > > register range. > > - > > - mediatek,smi: > > -$ref: /schemas/types.yaml#/definitions/phandle > > -description: phandle to the device containing the SMI register > > range. > > - > > -patternProperties: > > - "^power-domain@[0-9a-f]+$": > > -type: object > > -description: | > > - Represents a power domain child within a power domain parent > > node. > > - > > -properties: > > + required: > > +- reg > > > > - '#power-domain-cells': > > -description: > > - Must be 0 for nodes representing a single PM domain and > > 1 for nodes > > - providing multiple PM domains. > > - > > - '#address-cells': > > -const: 1 > > - > > - '#size-cells': > > -const: 0 > > - > > - reg: > > -maxItems: 1 > > - > > - clocks: > > -description: | > > - A number of phandles to clocks that need to be enabled > > during domain > > - power-up sequencing. > > - > > - clock-names: > > -description: | > >
Re: [PATCH v1 01/16] dt-bindings: iommu: mediatek: Increase max interrupt number
On Tue, 2022-07-05 at 14:49 -0600, Rob Herring wrote: > On Mon, Jul 04, 2022 at 06:00:13PM +0800, Tinghan Shen wrote: > > mt8195 infra iommu has max 5 interrupts. > > > > Signed-off-by: Tinghan Shen > > --- > > .../devicetree/bindings/iommu/mediatek,iommu.yaml| 12 +++- > > 1 file changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > index 2ae3bbad7f1a..27eb9f6aa3ce 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > @@ -91,7 +91,8 @@ properties: > > maxItems: 1 > > > >interrupts: > > -maxItems: 1 > > +minItems: 1 > > +maxItems: 5 > > > >clocks: > > items: > > @@ -175,9 +176,18 @@ allOf: > >const: mediatek,mt8195-iommu-infra > > > > then: > > + properties: > > +interrupts: > > + maxItems: 1 > > + > >required: > > - mediatek,larbs > > > > +else: > > + properties: > > +interrupts: > > + maxItems: 5 > > 5 is already the max. > > minItems: 5 > Ok, I'll update in the next version. Thanks, TingHan ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
On Mon, 2022-07-04 at 14:39 +0200, Krzysztof Kozlowski wrote:
> On 04/07/2022 12:00, Tinghan Shen wrote:
> > From: "Jason-JH.Lin"
> >
> > Add display node for vdosys0 of mt8195.
> >
> > Signed-off-by: Jason-JH.Lin
> > Signed-off-by: Tinghan Shen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 724c6ca837b6..faea8ef33e5a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1961,6 +1961,7 @@
> > vdosys0: syscon@1c01a000 {
> > compatible = "mediatek,mt8195-mmsys", "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > + mboxes = < 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1976,6 +1977,114 @@
> > power-domains = < MT8195_POWER_DOMAIN_VENC_CORE1>;
> > };
> >
> > + ovl0: ovl@1c00 {
> > + compatible = "mediatek,mt8195-disp-ovl",
> > +"mediatek,mt8183-disp-ovl";
> > + reg = <0 0x1c00 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_OVL0>;
> > + iommus = <_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x 0x1000>;
> > + };
> > +
> > + rdma0: rdma@1c002000 {
> > + compatible = "mediatek,mt8195-disp-rdma";
> > + reg = <0 0x1c002000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_RDMA0>;
> > + iommus = <_vdo M4U_PORT_L0_DISP_RDMA0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x2000 0x1000>;
> > + };
> > +
> > + color0: color@1c003000 {
> > + compatible = "mediatek,mt8195-disp-color",
> > +"mediatek,mt8173-disp-color";
> > + reg = <0 0x1c003000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_COLOR0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x3000 0x1000>;
> > + };
> > +
> > + ccorr0: ccorr@1c004000 {
> > + compatible = "mediatek,mt8195-disp-ccorr",
> > +"mediatek,mt8192-disp-ccorr";
> > + reg = <0 0x1c004000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_CCORR0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x4000 0x1000>;
> > + };
> > +
> > + aal0: aal@1c005000 {
> > + compatible = "mediatek,mt8195-disp-aal",
> > +"mediatek,mt8183-disp-aal";
> > + reg = <0 0x1c005000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_AAL0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x5000 0x1000>;
> > + };
> > +
> > + gamma0: gamma@1c006000 {
> > + compatible = "mediatek,mt8195-disp-gamma",
> > +"mediatek,mt8183-disp-gamma";
> > + reg = <0 0x1c006000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_GAMMA0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x6000 0x1000>;
> > + };
> > +
> > + dither0: dither@1c007000 {
> > + compatible = "mediatek,mt8195-disp-dither",
> > +"mediatek,mt8183-disp-dither";
> > + reg = <0 0x1c007000 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_DITHER0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x7000 0x1000>;
> > + };
> > +
> > + dsc0: dsc@1c009000 {
> > + compatible =
Re: [PATCH v1 02/16] dt-bindings: memory: mediatek: Update condition for mt8195 smi node
On Mon, 2022-07-04 at 14:36 +0200, Krzysztof Kozlowski wrote: > On 04/07/2022 12:00, Tinghan Shen wrote: > > The max clock items for the dts node with compatible > > 'mediatek,mt8195-smi-sub-common' should be 3. > > > > However, the dtbs_check of such node will get following message, > > arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@1401: clock-names: > > ['apb', 'smi', 'gals0'] > > is too long > > From schema: > > Documentation/devicetree/bindings/memory-controllers/mediatek,smi- > > common.yaml > > > > Remove the last 'else' checking to fix this error. > > Missing fixes tag. > > > > > Signed-off-by: Tinghan Shen > > --- > > .../memory-controllers/mediatek,smi-common.yaml| 10 +- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > index a98b359bf909..e5f553e2e12a 100644 > > --- > > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > +++ > > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > @@ -143,7 +143,15 @@ allOf: > > - const: gals0 > > - const: gals1 > > > > -else: # for gen2 HW that don't have gals > > + - if: # for gen2 HW that don't have gals > > + properties: > > +compatible: > > + enum: > > +- mediatek,mt2712-smi-common > > +- mediatek,mt8167-smi-common > > +- mediatek,mt8173-smi-common > > + > > Without looking at the code, it's impossible to understand what you are > doing here. The commit msg says one, but you are doing something else. > > Write commit msg explaining what you want to achieve and what you are doing. > > > Best regards, > Krzysztof Ok, I'll update in next version. Thanks, TingHan ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
On Mon, 2022-07-04 at 12:44 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/07/22 12:00, Tinghan Shen ha scritto:
> > From: "Jason-JH.Lin"
> >
> > Add display node for vdosys0 of mt8195.
> >
> > Signed-off-by: Jason-JH.Lin
> > Signed-off-by: Tinghan Shen
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 724c6ca837b6..faea8ef33e5a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1961,6 +1961,7 @@
> > vdosys0: syscon@1c01a000 {
> > compatible = "mediatek,mt8195-mmsys", "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > + mboxes = < 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1976,6 +1977,114 @@
> > power-domains = < MT8195_POWER_DOMAIN_VENC_CORE1>;
> > };
> >
> > + ovl0: ovl@1c00 {
> > + compatible = "mediatek,mt8195-disp-ovl",
> > +"mediatek,mt8183-disp-ovl";
>
> This fits in one line, please fix, here and all of the other instances of
> that.
>
> > + reg = <0 0x1c00 0 0x1000>;
> > + interrupts = ;
> > + power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = < CLK_VDO0_DISP_OVL0>;
> > + iommus = <_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> > + mediatek,gce-client-reg =
> > +< SUBSYS_1c00 0x 0x1000>;
>
> Same for gce-client-reg.
>
> Regards,
> Angelo
Ok, I'll update in next version.
Thanks,
TingHan
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Re: [PATCH v1 04/16] arm64: dts: mt8195: Disable watchdog external reset signal
On Mon, 2022-07-04 at 12:30 +0200, AngeloGioacchino Del Regno wrote: > Il 04/07/22 12:00, Tinghan Shen ha scritto: > > Disable external output reset signal in first round of watchdog reset > > to reserve wdt reset reason for debugging watchdog issue. > > If my understanding of the commit decription is right, then we can clarify > that with something like: "[...] for debugging eventual watchdog issues". > > Otherwise, if this implies that disable-extrst is needed to avoid losing > the reset reason stored in the WDT, you could say something like: > > "Disable external output reset signal in the first round of watchdog reset > to avoid losing the reset reason stored in the watchdog registers" > > After which: > > Reviewed-by: AngeloGioacchino Del Regno > > Ok, I'll update it in next version. Thanks, TingHan ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v1 02/16] dt-bindings: memory: mediatek: Update condition for mt8195 smi node
On Mon, 2022-07-04 at 12:25 +0200, AngeloGioacchino Del Regno wrote: > Il 04/07/22 12:00, Tinghan Shen ha scritto: > > The max clock items for the dts node with compatible > > 'mediatek,mt8195-smi-sub-common' should be 3. > > > > However, the dtbs_check of such node will get following message, > > arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@1401: clock-names: > > ['apb', 'smi', 'gals0'] > > is too long > > From schema: > > Documentation/devicetree/bindings/memory-controllers/mediatek,smi- > > common.yaml > > > > Remove the last 'else' checking to fix this error. > > > > Signed-off-by: Tinghan Shen > > --- > > .../memory-controllers/mediatek,smi-common.yaml| 10 +- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > index a98b359bf909..e5f553e2e12a 100644 > > --- > > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > +++ > > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > @@ -143,7 +143,15 @@ allOf: > > - const: gals0 > > - const: gals1 > > > > -else: # for gen2 HW that don't have gals > > + - if: # for gen2 HW that don't have gals > > + properties: > > +compatible: > > + enum: > > +- mediatek,mt2712-smi-common > > MT6795 also doesn't have any GALS, please add it in here. Ok, I'll update it in next version. Thanks, TingHan ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v1 15/16] arm64: dts: mt8195: Add gce node
From: "Jason-JH.Lin"
Add gce node and gce alias to mt8195 device tree.
Signed-off-by: Jason-JH.Lin
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index cb2b79dc08d1..724c6ca837b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include
+#include
#include
#include
#include
@@ -19,6 +20,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gce0 =
+ gce1 =
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -739,6 +745,22 @@
#iommu-cells = <1>;
};
+ gce0: mailbox@1032 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x1032 0 0x4000>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ clocks = <_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@1033 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x1033 0 0x4000>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ clocks = <_ao CLK_INFRA_AO_GCE2>;
+ };
+
scp: scp@1050 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x1050 0 0x10>,
--
2.18.0
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[PATCH v1 13/16] arm64: dts: mt8195: Specify audio reset controller
From: Trevor Wu
Specify audio reset controller for audio hardware resetting.
Signed-off-by: Trevor Wu
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 0e5614108c12..618fb2fa195a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -681,6 +681,7 @@
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
@@ -783,6 +784,8 @@
mediatek,topckgen = <>;
power-domains = < MT8195_POWER_DOMAIN_AUDIO>;
interrupts = ;
+ resets = < 14>;
+ reset-names = "audiosys";
clocks = <>,
< CLK_APMIXED_APLL1>,
< CLK_APMIXED_APLL2>,
--
2.18.0
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[PATCH v1 12/16] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
From: YC Hung
Add adsp node and adsp mailbox nodes for mt8195.
Signed-off-by: YC Hung
Signed-off-by: Allen-KH Cheng
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 1776f5dcde03..0e5614108c12 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -740,6 +740,43 @@
#clock-cells = <1>;
};
+ adsp: adsp@10803000 {
+ compatible = "mediatek,mt8195-dsp";
+ reg = <0 0x10803000 0 0x1000>,
+ <0 0x1084 0 0x4>;
+ reg-names = "cfg", "sram";
+ clocks = < CLK_TOP_ADSP>,
+<>,
+< CLK_TOP_AUDIO_LOCAL_BUS>,
+< CLK_TOP_MAINPLL_D7_D2>,
+<_adsp CLK_SCP_ADSP_AUDIODSP>,
+< CLK_TOP_AUDIO_H>;
+ clock-names = "adsp_sel",
+"clk26m_ck",
+"audio_local_bus",
+"mainpll_d7_d2",
+"scp_adsp_audiodsp",
+"audio_h";
+ power-domains = < MT8195_POWER_DOMAIN_ADSP>;
+ mbox-names = "rx", "tx";
+ mboxes = <_mailbox0>, <_mailbox1>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@10816000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10816000 0 0x1000>;
+ interrupts = ;
+ };
+
+ adsp_mailbox1: mailbox@10817000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10817000 0 0x1000>;
+ interrupts = ;
+ };
+
afe: mt8195-afe-pcm@1089 {
compatible = "mediatek,mt8195-audio";
reg = <0 0x1089 0 0x1>;
--
2.18.0
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[PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0
From: "Jason-JH.Lin"
Add display node for vdosys0 of mt8195.
Signed-off-by: Jason-JH.Lin
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 724c6ca837b6..faea8ef33e5a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1961,6 +1961,7 @@
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = < 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
@@ -1976,6 +1977,114 @@
power-domains = < MT8195_POWER_DOMAIN_VENC_CORE1>;
};
+ ovl0: ovl@1c00 {
+ compatible = "mediatek,mt8195-disp-ovl",
+"mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c00 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_OVL0>;
+ iommus = <_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x 0x1000>;
+ };
+
+ rdma0: rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_RDMA0>;
+ iommus = <_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x2000 0x1000>;
+ };
+
+ color0: color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+"mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x3000 0x1000>;
+ };
+
+ ccorr0: ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+"mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x4000 0x1000>;
+ };
+
+ aal0: aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+"mediatek,mt8183-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x5000 0x1000>;
+ };
+
+ gamma0: gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+"mediatek,mt8183-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x6000 0x1000>;
+ };
+
+ dither0: dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+"mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = < CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+< SUBSYS_1c00 0x7000 0x1000>;
+ };
+
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = ;
+ power-domains = < MT8195_POWER_DOMAIN_VDOSYS0>;
+
[PATCH v1 07/16] arm64: dts: mt8195: Add vdosys and vppsys clock nodes
Add display clock nodes.
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 900aaa16f862..8d59a7da3271 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -983,6 +983,12 @@
#clock-cells = <1>;
};
+ vppsys0: clock-controller@1400 {
+ compatible = "mediatek,mt8195-vppsys0";
+ reg = <0 0x1400 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
wpesys: clock-controller@14e0 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e0 0 0x1000>;
@@ -1001,6 +1007,12 @@
#clock-cells = <1>;
};
+ vppsys1: clock-controller@14f0 {
+ compatible = "mediatek,mt8195-vppsys1";
+ reg = <0 0x14f0 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
imgsys: clock-controller@1500 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x1500 0 0x1000>;
@@ -1108,5 +1120,17 @@
reg = <0 0x1b00 0 0x1000>;
#clock-cells = <1>;
};
+
+ vdosys0: syscon@1c01a000 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c01a000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdosys1: syscon@1c10 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c10 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
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[PATCH v1 14/16] arm64: dts: mt8195: Add iommu and smi nodes
Add iommu nodes and smi nodes for mt8195.
Signed-off-by: Yong Wu
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 451 +++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 618fb2fa195a..cb2b79dc08d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -725,6 +726,19 @@
assigned-clock-parents = <
CLK_TOP_ULPOSC1_D10>;
};
+ iommu_infra: infra-iommu@10315000 {
+ compatible = "mediatek,mt8195-iommu-infra";
+ reg = <0 0x10315000 0 0x5000>;
+ interrupts = ,
+,
+,
+,
+;
+ clocks = <>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ };
+
scp: scp@1050 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x1050 0 0x10>,
@@ -1439,6 +1453,64 @@
#clock-cells = <1>;
};
+ smi_sub_common_vpp0_vpp1_2x1: smi@1401 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x1401 0 0x1000>;
+ clocks = < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <_common_vpp>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = < CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+< CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+< CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <_common_vpp>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_common_vpp: smi@14012000 {
+ compatible = "mediatek,mt8195-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = < CLK_VPP0_SMI_COMMON_LARB4>,
+ < CLK_VPP0_SMI_COMMON_LARB4>,
+ < CLK_VPP0_SMI_RSI>,
+ < CLK_VPP0_SMI_RSI>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: larb@14013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <_sub_common_vpp0_vpp1_2x1>;
+ clocks = < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ iommu_vpp: iommu@14018000 {
+ compatible = "mediatek,mt8195-iommu-vpp";
+ reg = <0 0x14018000 0 0x1000>;
+ mediatek,larbs = <
+
+
+ >;
+ interrupts = ;
+ clocks = < CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
wpesys: clock-controller@14e0 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e0 0 0x1000>;
@@ -1457,24 +1529,116 @@
#clock-cells = <1>;
};
+ larb7: larb@14e04000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <_common_vdo>;
+ clocks = < CLK_WPE_SMI_LARB7>,
+< CLK_WPE_SMI_LARB7>;
+ clock-names = "apb", "smi";
+
[PATCH v1 08/16] arm64: dts: mt8195: Add power domains controller
Add power domains controller node for mt8195.
Signed-off-by: Weiyi Lu
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 327 +++
1 file changed, 327 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8d59a7da3271..d52e140d9271 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8195";
@@ -338,6 +339,332 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
+ reg = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG1 {
+ reg =
;
+ clocks = <
CLK_APMIXED_MFGPLL>;
+ clock-names = "mfg";
+ mediatek,infracfg =
<_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+
power-domain@MT8195_POWER_DOMAIN_MFG2 {
+ reg =
;
+ #power-domain-cells =
<0>;
+ };
+
+
power-domain@MT8195_POWER_DOMAIN_MFG3 {
+ reg =
;
+ #power-domain-cells =
<0>;
+ };
+
+
power-domain@MT8195_POWER_DOMAIN_MFG4 {
+ reg =
;
+ #power-domain-cells =
<0>;
+ };
+
+
power-domain@MT8195_POWER_DOMAIN_MFG5 {
+ reg =
;
+ #power-domain-cells =
<0>;
+ };
+
+
power-domain@MT8195_POWER_DOMAIN_MFG6 {
+ reg =
;
+ #power-domain-cells =
<0>;
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
+ reg = ;
+ clocks = < CLK_TOP_VPP>,
+< CLK_TOP_CAM>,
+< CLK_TOP_CCU>,
+< CLK_TOP_IMG>,
+< CLK_TOP_VENC>,
+< CLK_TOP_VDEC>,
+< CLK_TOP_WPE_VPP>,
+< CLK_TOP_CFG_VPP0>,
+< CLK_VPP0_SMI_COMMON>,
+<
CLK_VPP0_GALS_VDO0_LARB0>,
+<
CLK_VPP0_GALS_VDO0_LARB1>,
+<
CLK_VPP0_GALS_VENCSYS>,
+<
CLK_VPP0_GALS_VENCSYS_CORE1>,
+< CLK_VPP0_GALS_INFRA>,
+<
CLK_VPP0_GALS_CAMSYS>,
+<
CLK_VPP0_GALS_VPP1_LARB5>,
+
[PATCH v1 11/16] arm64: dts: mt8195: Add audio related nodes
Add audio related nodes for mt8195.
Signed-off-by: Trevor Wu
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 543bb719a445..1776f5dcde03 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -226,6 +226,17 @@
<>, <>, <>, <>;
};
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ };
+
+ sound: mt8195-sound {
+ mediatek,platform = <>;
+ status = "disabled";
+ };
+
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -729,6 +740,53 @@
#clock-cells = <1>;
};
+ afe: mt8195-afe-pcm@1089 {
+ compatible = "mediatek,mt8195-audio";
+ reg = <0 0x1089 0 0x1>;
+ mediatek,topckgen = <>;
+ power-domains = < MT8195_POWER_DOMAIN_AUDIO>;
+ interrupts = ;
+ clocks = <>,
+ < CLK_APMIXED_APLL1>,
+ < CLK_APMIXED_APLL2>,
+ < CLK_TOP_APLL12_DIV0>,
+ < CLK_TOP_APLL12_DIV1>,
+ < CLK_TOP_APLL12_DIV2>,
+ < CLK_TOP_APLL12_DIV3>,
+ < CLK_TOP_APLL12_DIV9>,
+ < CLK_TOP_A1SYS_HP>,
+ < CLK_TOP_AUD_INTBUS>,
+ < CLK_TOP_AUDIO_H>,
+ < CLK_TOP_AUDIO_LOCAL_BUS>,
+ < CLK_TOP_DPTX_MCK>,
+ < CLK_TOP_I2SO1_MCK>,
+ < CLK_TOP_I2SO2_MCK>,
+ < CLK_TOP_I2SI1_MCK>,
+ < CLK_TOP_I2SI2_MCK>,
+ <_ao CLK_INFRA_AO_AUDIO_26M_B>,
+ <_adsp CLK_SCP_ADSP_AUDIODSP>;
+ clock-names = "clk26m",
+ "apll1_ck",
+ "apll2_ck",
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div3",
+ "apll12_div9",
+ "a1sys_hp_sel",
+ "aud_intbus_sel",
+ "audio_h_sel",
+ "audio_local_bus_sel",
+ "dptx_m_sel",
+ "i2so1_m_sel",
+ "i2so2_m_sel",
+ "i2si1_m_sel",
+ "i2si2_m_sel",
+ "infra_ao_audio_26m_b",
+ "scp_adsp_audiodsp";
+ status = "disabled";
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart",
"mediatek,mt6577-uart";
--
2.18.0
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[PATCH v1 02/16] dt-bindings: memory: mediatek: Update condition for mt8195 smi node
The max clock items for the dts node with compatible 'mediatek,mt8195-smi-sub-common' should be 3. However, the dtbs_check of such node will get following message, arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@1401: clock-names: ['apb', 'smi', 'gals0'] is too long From schema: Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml Remove the last 'else' checking to fix this error. Signed-off-by: Tinghan Shen --- .../memory-controllers/mediatek,smi-common.yaml| 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index a98b359bf909..e5f553e2e12a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -143,7 +143,15 @@ allOf: - const: gals0 - const: gals1 -else: # for gen2 HW that don't have gals + - if: # for gen2 HW that don't have gals + properties: +compatible: + enum: +- mediatek,mt2712-smi-common +- mediatek,mt8167-smi-common +- mediatek,mt8173-smi-common + +then: properties: clocks: minItems: 2 -- 2.18.0 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v1 04/16] arm64: dts: mt8195: Disable watchdog external reset signal
Disable external output reset signal in first round of watchdog reset
to reserve wdt reset reason for debugging watchdog issue.
Signed-off-by: Fengquan Chen
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708..436687ba826f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -327,6 +327,7 @@
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
};
--
2.18.0
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[PATCH v1 06/16] arm64: dts: mt8195: Add cpufreq node
From: YT Lee
Add cpufreq node for mt8195.
Signed-off-by: YT Lee
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8032b839dfe8..900aaa16f862 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
+ performance-domains = < 0>;
clock-frequency = <170100>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <_off_l _off_l>;
@@ -38,6 +39,7 @@
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ performance-domains = < 0>;
clock-frequency = <170100>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <_off_l _off_l>;
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
+ performance-domains = < 0>;
clock-frequency = <170100>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <_off_l _off_l>;
@@ -62,6 +65,7 @@
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
+ performance-domains = < 0>;
clock-frequency = <170100>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <_off_l _off_l>;
@@ -74,6 +78,7 @@
compatible = "arm,cortex-a78";
reg = <0x400>;
enable-method = "psci";
+ performance-domains = < 1>;
clock-frequency = <217100>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <_off_b _off_b>;
@@ -86,6 +91,7 @@
compatible = "arm,cortex-a78";
reg = <0x500>;
enable-method = "psci";
+ performance-domains = < 1>;
clock-frequency = <217100>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <_off_b _off_b>;
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a78";
reg = <0x600>;
enable-method = "psci";
+ performance-domains = < 1>;
clock-frequency = <217100>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <_off_b _off_b>;
@@ -110,6 +117,7 @@
compatible = "arm,cortex-a78";
reg = <0x700>;
enable-method = "psci";
+ performance-domains = < 1>;
clock-frequency = <217100>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <_off_b _off_b>;
@@ -231,6 +239,12 @@
clock-output-names = "clk32k";
};
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <>;
--
2.18.0
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[PATCH v1 01/16] dt-bindings: iommu: mediatek: Increase max interrupt number
mt8195 infra iommu has max 5 interrupts. Signed-off-by: Tinghan Shen --- .../devicetree/bindings/iommu/mediatek,iommu.yaml| 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 2ae3bbad7f1a..27eb9f6aa3ce 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -91,7 +91,8 @@ properties: maxItems: 1 interrupts: -maxItems: 1 +minItems: 1 +maxItems: 5 clocks: items: @@ -175,9 +176,18 @@ allOf: const: mediatek,mt8195-iommu-infra then: + properties: +interrupts: + maxItems: 1 + required: - mediatek,larbs +else: + properties: +interrupts: + maxItems: 5 + additionalProperties: false examples: -- 2.18.0 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v1 00/16] Add driver nodes for MT8195 SoC
Add driver nodes for MT8195 SoC. Patchset 12 depends on https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git/commit/?id=009b21f392759ca7be91bc4be9d9534f6cee2878 Jason-JH.Lin (2): arm64: dts: mt8195: Add gce node arm64: dts: mt8195: Add display node for vdosys0 Tinghan Shen (10): dt-bindings: iommu: mediatek: Increase max interrupt number dt-bindings: memory: mediatek: Update condition for mt8195 smi node dt-bindings: power: mediatek: Refine multiple level power domain nodes arm64: dts: mt8195: Disable watchdog external reset signal arm64: dts: mt8195: Add vdosys and vppsys clock nodes arm64: dts: mt8195: Add power domains controller arm64: dts: mt8195: Add spmi node arm64: dts: mt8195: Add scp node arm64: dts: mt8195: Add audio related nodes arm64: dts: mt8195: Add iommu and smi nodes Trevor Wu (1): arm64: dts: mt8195: Specify audio reset controller Tzung-Bi Shih (1): arm64: dts: mt8195: Disable I2C0 node YC Hung (1): arm64: dts: mt8195: Add adsp node and adsp mailbox nodes YT Lee (1): arm64: dts: mt8195: Add cpufreq node .../bindings/iommu/mediatek,iommu.yaml| 12 +- .../mediatek,smi-common.yaml | 10 +- .../power/mediatek,power-controller.yaml | 132 +- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1073 - 4 files changed, 1104 insertions(+), 123 deletions(-) -- 2.18.0 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v1 10/16] arm64: dts: mt8195: Add scp node
Add scp node for mt8195.
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 456612d9d508..543bb719a445 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -713,6 +713,16 @@
assigned-clock-parents = <
CLK_TOP_ULPOSC1_D10>;
};
+ scp: scp@1050 {
+ compatible = "mediatek,mt8195-scp";
+ reg = <0 0x1050 0 0x10>,
+ <0 0x1072 0 0xe>,
+ <0 0x1070 0 0x8000>;
+ reg-names = "sram", "cfg", "l1tcm";
+ interrupts = ;
+ status = "disabled";
+ };
+
scp_adsp: clock-controller@1072 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x1072 0 0x1000>;
--
2.18.0
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[PATCH v1 05/16] arm64: dts: mt8195: Disable I2C0 node
From: Tzung-Bi Shih
The I2C0 node doesn't need to be enabled in dtsi.
Signed-off-by: Tzung-Bi Shih
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 436687ba826f..8032b839dfe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -829,7 +829,7 @@
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
- status = "okay";
+ status = "disabled";
};
i2c1: i2c@11e01000 {
--
2.18.0
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[PATCH v1 09/16] arm64: dts: mt8195: Add spmi node
Add spmi node to mt8195.
Signed-off-by: Henry Chen
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d52e140d9271..456612d9d508 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -698,6 +698,21 @@
assigned-clock-parents = <
CLK_TOP_ULPOSC1_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt8195-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <_ao CLK_INFRA_AO_PMIC_AP>,
+<_ao CLK_INFRA_AO_PMIC_TMR>,
+< CLK_TOP_SPMI_M_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = < CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <
CLK_TOP_ULPOSC1_D10>;
+ };
+
scp_adsp: clock-controller@1072 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x1072 0 0x1000>;
--
2.18.0
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[PATCH v1 03/16] dt-bindings: power: mediatek: Refine multiple level power domain nodes
Extract duplicated properties and support more levels of power domain nodes. This change fix following error when do dtbs_check, arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml Signed-off-by: Tinghan Shen --- .../power/mediatek,power-controller.yaml | 132 ++ 1 file changed, 12 insertions(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 135c6f722091..09a537a802b8 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -39,8 +39,17 @@ properties: '#size-cells': const: 0 +required: + - compatible + +additionalProperties: false + patternProperties: "^power-domain@[0-9a-f]+$": +$ref: "#/$defs/power-domain-node" + +$defs: + power-domain-node: type: object description: | Represents the power domains within the power controller node as documented @@ -98,127 +107,10 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. -patternProperties: - "^power-domain@[0-9a-f]+$": -type: object -description: | - Represents a power domain child within a power domain parent node. - -properties: - - '#power-domain-cells': -description: - Must be 0 for nodes representing a single PM domain and 1 for nodes - providing multiple PM domains. - - '#address-cells': -const: 1 - - '#size-cells': -const: 0 - - reg: -maxItems: 1 - - clocks: -description: | - A number of phandles to clocks that need to be enabled during domain - power-up sequencing. - - clock-names: -description: | - List of names of clocks, in order to match the power-up sequencing - for each power domain we need to group the clocks by name. BASIC - clocks need to be enabled before enabling the corresponding power - domain, and should not have a '-' in their name (i.e mm, mfg, venc). - SUSBYS clocks need to be enabled before releasing the bus protection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). - - In order to follow properly the power-up sequencing, the clocks must - be specified by order, adding first the BASIC clocks followed by the - SUSBSYS clocks. - - domain-supply: -description: domain regulator supply. - - mediatek,infracfg: -$ref: /schemas/types.yaml#/definitions/phandle -description: phandle to the device containing the INFRACFG register range. - - mediatek,smi: -$ref: /schemas/types.yaml#/definitions/phandle -description: phandle to the device containing the SMI register range. - -patternProperties: - "^power-domain@[0-9a-f]+$": -type: object -description: | - Represents a power domain child within a power domain parent node. - -properties: + required: +- reg - '#power-domain-cells': -description: - Must be 0 for nodes representing a single PM domain and 1 for nodes - providing multiple PM domains. - - '#address-cells': -const: 1 - - '#size-cells': -const: 0 - - reg: -maxItems: 1 - - clocks: -description: | - A number of phandles to clocks that need to be enabled during domain - power-up sequencing. - - clock-names: -description: | - List of names of clocks, in order to match the power-up sequencing - for each power domain we need to group the clocks by name. BASIC - clocks need to be enabled before enabling the corresponding power - domain, and should not have a '-' in their name (i.e mm, mfg, venc). - SUSBYS clocks need to be enabled before releasing the bus protection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). - - In order to follow properly the power-up sequencing, the clocks must - be specified by order, adding first the BASIC clocks followed by the
