Re: [PATCH 13/13] arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes

[Evan Green]

On Mon, Dec 31, 2018 at 8:53 PM Yong Wu  wrote:
>
> After adding device_link between the IOMMU consumer and smi,
> the mediatek,larb is unnecessary now.
>
> CC: Matthias Brugger 
> Signed-off-by: Yong Wu 

Reviewed-by: Evan Green 
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[PATCH 13/13] arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes

[Yong Wu]

After adding device_link between the IOMMU consumer and smi,
the mediatek,larb is unnecessary now.

CC: Matthias Brugger 
Signed-off-by: Yong Wu 
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index abd2f15..8babd71 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -895,7 +895,6 @@
 < CLK_MM_MUTEX_32K>;
power-domains = < MT8173_POWER_DOMAIN_MM>;
iommus = < M4U_PORT_MDP_RDMA0>;
-   mediatek,larb = <>;
mediatek,vpu = <>;
};
 
@@ -906,7 +905,6 @@
 < CLK_MM_MUTEX_32K>;
power-domains = < MT8173_POWER_DOMAIN_MM>;
iommus = < M4U_PORT_MDP_RDMA1>;
-   mediatek,larb = <>;
};
 
mdp_rsz0: rsz@14003000 {
@@ -936,7 +934,6 @@
clocks = < CLK_MM_MDP_WDMA>;
power-domains = < MT8173_POWER_DOMAIN_MM>;
iommus = < M4U_PORT_MDP_WDMA>;
-   mediatek,larb = <>;
};
 
mdp_wrot0: wrot@14007000 {
@@ -945,7 +942,6 @@
clocks = < CLK_MM_MDP_WROT0>;
power-domains = < MT8173_POWER_DOMAIN_MM>;
iommus = < M4U_PORT_MDP_WROT0>;
-   mediatek,larb = <>;
};
 
mdp_wrot1: wrot@14008000 {
@@ -954,7 +950,6 @@
clocks = < CLK_MM_MDP_WROT1>;
power-domains = < MT8173_POWER_DOMAIN_MM>;
iommus = < M4U_PORT_MDP_WROT1>;
-   mediatek,larb = <>;
};
 
ovl0: ovl@1400c000 {
@@ -964,7 +959,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_OVL0>;
iommus = < M4U_PORT_DISP_OVL0>;
-   mediatek,larb = <>;
};
 
ovl1: ovl@1400d000 {
@@ -974,7 +968,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_OVL1>;
iommus = < M4U_PORT_DISP_OVL1>;
-   mediatek,larb = <>;
};
 
rdma0: rdma@1400e000 {
@@ -984,7 +977,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_RDMA0>;
iommus = < M4U_PORT_DISP_RDMA0>;
-   mediatek,larb = <>;
};
 
rdma1: rdma@1400f000 {
@@ -994,7 +986,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_RDMA1>;
iommus = < M4U_PORT_DISP_RDMA1>;
-   mediatek,larb = <>;
};
 
rdma2: rdma@1401 {
@@ -1004,7 +995,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_RDMA2>;
iommus = < M4U_PORT_DISP_RDMA2>;
-   mediatek,larb = <>;
};
 
wdma0: wdma@14011000 {
@@ -1014,7 +1004,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_WDMA0>;
iommus = < M4U_PORT_DISP_WDMA0>;
-   mediatek,larb = <>;
};
 
wdma1: wdma@14012000 {
@@ -1024,7 +1013,6 @@
power-domains = < MT8173_POWER_DOMAIN_MM>;
clocks = < CLK_MM_DISP_WDMA1>;
iommus = < M4U_PORT_DISP_WDMA1>;
-   mediatek,larb = <>;
};
 
color0: color@14013000 {
@@ -1268,7 +1256,6 @@
  <0 0x16027800 0 0x800>,   /* VDEC_HWB */
  <0 0x16028400 0 0x400>;   /* VDEC_HWG */
interrupts = ;
-   mediatek,larb = <>;
iommus = < M4U_PORT_HW_VDEC_MC_EXT>,
 < M4U_PORT_HW_VDEC_PP_EXT>,
 < M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1329,8 +1316,6 @@
  <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
interrupts = ,
 ;
-   mediatek,larb = <>,
-   <>;
iommus = < M4U_PORT_VENC_RCPU>,
 < M4U_PORT_VENC_REC>,
 < M4U_PORT_VENC_BSDMA>,
-- 
1.9.1