Add iommu nodes and smi nodes for mt8195.
Signed-off-by: Yong Wu
Signed-off-by: Tinghan Shen
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 451 +++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 618fb2fa195a..cb2b79dc08d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -725,6 +726,19 @@
assigned-clock-parents = <
CLK_TOP_ULPOSC1_D10>;
};
+ iommu_infra: infra-iommu@10315000 {
+ compatible = "mediatek,mt8195-iommu-infra";
+ reg = <0 0x10315000 0 0x5000>;
+ interrupts = ,
+,
+,
+,
+;
+ clocks = <>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ };
+
scp: scp@1050 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x1050 0 0x10>,
@@ -1439,6 +1453,64 @@
#clock-cells = <1>;
};
+ smi_sub_common_vpp0_vpp1_2x1: smi@1401 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x1401 0 0x1000>;
+ clocks = < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <_common_vpp>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = < CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+< CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+< CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <_common_vpp>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_common_vpp: smi@14012000 {
+ compatible = "mediatek,mt8195-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = < CLK_VPP0_SMI_COMMON_LARB4>,
+ < CLK_VPP0_SMI_COMMON_LARB4>,
+ < CLK_VPP0_SMI_RSI>,
+ < CLK_VPP0_SMI_RSI>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: larb@14013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <_sub_common_vpp0_vpp1_2x1>;
+ clocks = < CLK_VPP0_GALS_VPP1_WPE>,
+ < CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ iommu_vpp: iommu@14018000 {
+ compatible = "mediatek,mt8195-iommu-vpp";
+ reg = <0 0x14018000 0 0x1000>;
+ mediatek,larbs = <
+
+
+ >;
+ interrupts = ;
+ clocks = < CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ power-domains = < MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
wpesys: clock-controller@14e0 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e0 0 0x1000>;
@@ -1457,24 +1529,116 @@
#clock-cells = <1>;
};
+ larb7: larb@14e04000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <_common_vdo>;
+ clocks = < CLK_WPE_SMI_LARB7>,
+< CLK_WPE_SMI_LARB7>;
+ clock-names = "apb", "smi";
+
