Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
On 2017/5/22 23:06, Robin Murphy wrote: IORT revision C has been published with a number of new SMMU implementation identifiers. Since IORT doesn't have any way of falling back to a more generic model code, we really need Linux to know about these before vendors start updating their firmware tables to use them. CC: Rafael J. Wysocki CC: Robert Moore CC: Lv Zheng Acked-by: Robert Richter Tested-by: Robert Richter Signed-off-by: Robin Murphy --- v2: Update more comments, add Robert's tags. I'm including this here as a kernel patch just for context - once I've figured out how we actually submit patches to ACPICA directly, I'll do that per the preferred process. Robin. include/acpi/actbl2.h | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index faa9f2c0d5de..f469ea41f2fd 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -663,7 +663,7 @@ struct acpi_ibft_target { * IORT - IO Remapping Table * * Conforms to "IO Remapping Table System Software on ARM Platforms", - * Document number: ARM DEN 0049B, October 2015 + * Document number: ARM DEN 0049C, May 2017 * **/ @@ -778,6 +778,8 @@ struct acpi_iort_smmu { #define ACPI_IORT_SMMU_V2 0x0001/* Generic SMMUv2 */ #define ACPI_IORT_SMMU_CORELINK_MMU400 0x0002/* ARM Corelink MMU-400 */ #define ACPI_IORT_SMMU_CORELINK_MMU500 0x0003/* ARM Corelink MMU-500 */ +#define ACPI_IORT_SMMU_CORELINK_MMU401 0x0004 /* ARM Corelink MMU-401 */ +#define ACPI_IORT_SMMU_CAVIUM_SMMUV20x0005 /* Cavium ThunderX SMMUv2 */ /* Masks for Flags field above */ @@ -798,13 +800,19 @@ struct acpi_iort_smmu_v3 { u32 flags; u32 reserved; u64 vatos_address; - u32 model; /* O: generic SMMUv3 */ + u32 model; u32 event_gsiv; u32 pri_gsiv; u32 gerr_gsiv; u32 sync_gsiv; }; +/* Values for Model field above */ + +#define ACPI_IORT_SMMU_V3 0x /* Generic SMMUv3 */ +#define ACPI_IORT_SMMU_HISILICON_HI161X 0x0001 /* HiSilicon Hi161x SMMUv3 */ +#define ACPI_IORT_SMMU_CAVIUM_CN99XX0x0002 /* Cavium CN99xx SMMUv3 */ + /* Masks for Flags field above */ #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) Looks good to me, Reviewed-by: Hanjun Guo By the way, how will this patch be merged? There are pending patches on top of it, Rafael suggested to work with ACPICA upstream first [1], Robin, will work on that? [1]: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1394295.html Thanks Hanjun ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
On 30/05/17 10:12, Joerg Roedel wrote: > On Mon, May 22, 2017 at 04:06:37PM +0100, Robin Murphy wrote: >> IORT revision C has been published with a number of new SMMU >> implementation identifiers. Since IORT doesn't have any way of falling >> back to a more generic model code, we really need Linux to know about >> these before vendors start updating their firmware tables to use them. >> >> CC: Rafael J. Wysocki >> CC: Robert Moore >> CC: Lv Zheng >> Acked-by: Robert Richter >> Tested-by: Robert Richter >> Signed-off-by: Robin Murphy >> --- >> >> v2: Update more comments, add Robert's tags. > > I generally prefer 'Fixes'-tags, can you please add them too? This patch isn't a fix, though, it's merely adding some new stuff from a new release of the IORT spec. Either way, since I discovered we do actually have approval to contribute to ACPICA directly, I now intend to route the header change that way per Rafaels' preference[1] - patch 2/2 will take care of itself in the meantime. Thanks, Robin. [1]:https://www.mail-archive.com/iommu@lists.linux-foundation.org/msg17602.html ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
On Mon, May 22, 2017 at 04:06:37PM +0100, Robin Murphy wrote: > IORT revision C has been published with a number of new SMMU > implementation identifiers. Since IORT doesn't have any way of falling > back to a more generic model code, we really need Linux to know about > these before vendors start updating their firmware tables to use them. > > CC: Rafael J. Wysocki > CC: Robert Moore > CC: Lv Zheng > Acked-by: Robert Richter > Tested-by: Robert Richter > Signed-off-by: Robin Murphy > --- > > v2: Update more comments, add Robert's tags. I generally prefer 'Fixes'-tags, can you please add them too? ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
On 22.05.17 17:49:17, Robert Richter wrote: > On 22.05.17 16:06:37, Robin Murphy wrote: > > IORT revision C has been published with a number of new SMMU > > implementation identifiers. Since IORT doesn't have any way of falling > > back to a more generic model code, we really need Linux to know about > > these before vendors start updating their firmware tables to use them. > > > > CC: Rafael J. Wysocki > > CC: Robert Moore > > CC: Lv Zheng > > Acked-by: Robert Richter > > Tested-by: Robert Richter > > Signed-off-by: Robin Murphy > > Robin, the stable tag is missing here, but we will need it for #2. I just noticed the additional #defines in #2. So no need to mark this one stable too. -Robert ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
On 22.05.17 16:06:37, Robin Murphy wrote: > IORT revision C has been published with a number of new SMMU > implementation identifiers. Since IORT doesn't have any way of falling > back to a more generic model code, we really need Linux to know about > these before vendors start updating their firmware tables to use them. > > CC: Rafael J. Wysocki > CC: Robert Moore > CC: Lv Zheng > Acked-by: Robert Richter > Tested-by: Robert Richter > Signed-off-by: Robin Murphy Robin, the stable tag is missing here, but we will need it for #2. Thanks, -Robert ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v2 1/2] ACPICA: IORT: Update SMMU models for IORT rev. C
IORT revision C has been published with a number of new SMMU implementation identifiers. Since IORT doesn't have any way of falling back to a more generic model code, we really need Linux to know about these before vendors start updating their firmware tables to use them. CC: Rafael J. Wysocki CC: Robert Moore CC: Lv Zheng Acked-by: Robert Richter Tested-by: Robert Richter Signed-off-by: Robin Murphy --- v2: Update more comments, add Robert's tags. I'm including this here as a kernel patch just for context - once I've figured out how we actually submit patches to ACPICA directly, I'll do that per the preferred process. Robin. include/acpi/actbl2.h | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index faa9f2c0d5de..f469ea41f2fd 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -663,7 +663,7 @@ struct acpi_ibft_target { * IORT - IO Remapping Table * * Conforms to "IO Remapping Table System Software on ARM Platforms", - * Document number: ARM DEN 0049B, October 2015 + * Document number: ARM DEN 0049C, May 2017 * **/ @@ -778,6 +778,8 @@ struct acpi_iort_smmu { #define ACPI_IORT_SMMU_V2 0x0001 /* Generic SMMUv2 */ #define ACPI_IORT_SMMU_CORELINK_MMU400 0x0002 /* ARM Corelink MMU-400 */ #define ACPI_IORT_SMMU_CORELINK_MMU500 0x0003 /* ARM Corelink MMU-500 */ +#define ACPI_IORT_SMMU_CORELINK_MMU401 0x0004 /* ARM Corelink MMU-401 */ +#define ACPI_IORT_SMMU_CAVIUM_SMMUV20x0005 /* Cavium ThunderX SMMUv2 */ /* Masks for Flags field above */ @@ -798,13 +800,19 @@ struct acpi_iort_smmu_v3 { u32 flags; u32 reserved; u64 vatos_address; - u32 model; /* O: generic SMMUv3 */ + u32 model; u32 event_gsiv; u32 pri_gsiv; u32 gerr_gsiv; u32 sync_gsiv; }; +/* Values for Model field above */ + +#define ACPI_IORT_SMMU_V3 0x /* Generic SMMUv3 */ +#define ACPI_IORT_SMMU_HISILICON_HI161X 0x0001 /* HiSilicon Hi161x SMMUv3 */ +#define ACPI_IORT_SMMU_CAVIUM_CN99XX0x0002 /* Cavium CN99xx SMMUv3 */ + /* Masks for Flags field above */ #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) -- 2.12.2.dirty ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu