Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
On Wed, 22 Jul 2020 09:01:27 +0800 Lu Baolu wrote: > > > > Not sure what state is this patch in, there is a bug in this patch > > (see below), shall I send out an updated version of this one only? > > or another incremental patch. > > Please send an updated version. I hope Joerg could pick these as 5.8 > fix. OK, will do. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
Hi Jacob,
On 7/22/20 12:50 AM, Jacob Pan wrote:
Hi Baolu,
Not sure what state is this patch in, there is a bug in this patch
(see below), shall I send out an updated version of this one only? or
another incremental patch.
Please send an updated version. I hope Joerg could pick these as 5.8
fix.
Best regards,
baolu
Thanks,
Jacob
On Mon, 6 Jul 2020 17:12:51 -0700
Jacob Pan wrote:
From: Liu Yi L
Address information for device TLB invalidation comes from userspace
when device is directly assigned to a guest with vIOMMU support.
VT-d requires page aligned address. This patch checks and enforce
address to be page aligned, otherwise reserved bits can be set in the
invalidation descriptor. Unrecoverable fault will be reported due to
non-zero value in the reserved bits.
Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation
cache types")
Acked-by: Lu Baolu
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
drivers/iommu/intel/dmar.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index d9f973fa1190..b2c53bada905 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct
intel_iommu *iommu, u16 sid, u16 pfsid,
* Max Invs Pending (MIP) is set to 0 for now until we have
DIT in
* ECAP.
*/
- desc.qw1 |= addr & ~mask;
- if (size_order)
+ if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
+ pr_warn_ratelimited("Invalidate non-aligned address
%llx, order %d\n", addr, size_order); +
+ /* Take page address */
+ desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
+
+ if (size_order) {
+ /*
+* Existing 0s in address below size_order may be
the least
+* significant bit, we must set them to 1s to avoid
having
+* smaller size than desired.
+*/
+ desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT,
+ VTD_PAGE_SHIFT);
Yi reported the issue, it should be:
desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
VTD_PAGE_SHIFT);
+ /* Clear size_order bit to indicate size */
+ desc.qw1 &= ~mask;
+ /* Set the S bit to indicate flushing more than 1
page */ desc.qw1 |= QI_DEV_EIOTLB_SIZE;
+ }
qi_submit_sync(iommu, , 1, 0);
}
[Jacob Pan]
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Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
Hi Baolu,
Not sure what state is this patch in, there is a bug in this patch
(see below), shall I send out an updated version of this one only? or
another incremental patch.
Thanks,
Jacob
On Mon, 6 Jul 2020 17:12:51 -0700
Jacob Pan wrote:
> From: Liu Yi L
>
> Address information for device TLB invalidation comes from userspace
> when device is directly assigned to a guest with vIOMMU support.
> VT-d requires page aligned address. This patch checks and enforce
> address to be page aligned, otherwise reserved bits can be set in the
> invalidation descriptor. Unrecoverable fault will be reported due to
> non-zero value in the reserved bits.
>
> Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation
> cache types")
> Acked-by: Lu Baolu
> Signed-off-by: Liu Yi L
> Signed-off-by: Jacob Pan
>
> ---
> drivers/iommu/intel/dmar.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index d9f973fa1190..b2c53bada905 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct
> intel_iommu *iommu, u16 sid, u16 pfsid,
>* Max Invs Pending (MIP) is set to 0 for now until we have
> DIT in
>* ECAP.
>*/
> - desc.qw1 |= addr & ~mask;
> - if (size_order)
> + if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
> + pr_warn_ratelimited("Invalidate non-aligned address
> %llx, order %d\n", addr, size_order); +
> + /* Take page address */
> + desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
> +
> + if (size_order) {
> + /*
> + * Existing 0s in address below size_order may be
> the least
> + * significant bit, we must set them to 1s to avoid
> having
> + * smaller size than desired.
> + */
> + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT,
> + VTD_PAGE_SHIFT);
Yi reported the issue, it should be:
desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
VTD_PAGE_SHIFT);
> + /* Clear size_order bit to indicate size */
> + desc.qw1 &= ~mask;
> + /* Set the S bit to indicate flushing more than 1
> page */ desc.qw1 |= QI_DEV_EIOTLB_SIZE;
> + }
>
> qi_submit_sync(iommu, , 1, 0);
> }
[Jacob Pan]
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Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
Hi Jacob,
On 7/7/20 2:12 AM, Jacob Pan wrote:
> From: Liu Yi L
>
> Address information for device TLB invalidation comes from userspace
> when device is directly assigned to a guest with vIOMMU support.
> VT-d requires page aligned address. This patch checks and enforce
> address to be page aligned, otherwise reserved bits can be set in the
> invalidation descriptor. Unrecoverable fault will be reported due to
> non-zero value in the reserved bits.
>
> Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation
> cache types")
> Acked-by: Lu Baolu
> Signed-off-by: Liu Yi L
> Signed-off-by: Jacob Pan
Reviewed-by: Eric Auger
Thanks
Eric
>
> ---
> drivers/iommu/intel/dmar.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index d9f973fa1190..b2c53bada905 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu
> *iommu, u16 sid, u16 pfsid,
>* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
>* ECAP.
>*/
> - desc.qw1 |= addr & ~mask;
> - if (size_order)
> + if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
> + pr_warn_ratelimited("Invalidate non-aligned address %llx, order
> %d\n", addr, size_order);
> +
> + /* Take page address */
> + desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
> +
> + if (size_order) {
> + /*
> + * Existing 0s in address below size_order may be the least
> + * significant bit, we must set them to 1s to avoid having
> + * smaller size than desired.
> + */
> + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT,
> + VTD_PAGE_SHIFT);
> + /* Clear size_order bit to indicate size */
> + desc.qw1 &= ~mask;
> + /* Set the S bit to indicate flushing more than 1 page */
> desc.qw1 |= QI_DEV_EIOTLB_SIZE;
> + }
>
> qi_submit_sync(iommu, , 1, 0);
> }
>
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RE: [kbuild-all] Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
> Subject: [kbuild-all] Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned > address > > Hi Jacob, > > Thank you for the patch! Perhaps something to improve: > > [auto build test WARNING on iommu/next] > [also build test WARNING on linux/master linus/master v5.8-rc4 next-20200707] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use as documented in > https://git-scm.com/docs/git-format-patch] > > url:https://github.com/0day-ci/linux/commits/Jacob-Pan/iommu-vt-d-Misc- > tweaks-and-fixes-for-vSVA/20200707-081026 > base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next > config: x86_64-randconfig-m031-20200707 (attached as .config) > compiler: gcc-9 (Debian 9.3.0-14) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot > > All warnings (new ones prefixed by >>): Kindly ignore this, which is related to [-Wtype-limits], and is under discussion to move such warning from W=1 to W=2 as it may not suitable to fix which can hurt code readability. Refer to https://lore.kernel.org/lkml/CAHk-=wiKCXEWKJ9dWUimGbrVRo_N2RosESUw8E7m9AEtyZcu=w...@mail.gmail.com/ for the discussion. > >In file included from include/linux/string.h:6, > from include/linux/uuid.h:12, > from include/linux/mod_devicetable.h:13, > from include/linux/pci.h:27, > from drivers/iommu/intel/dmar.c:19: >drivers/iommu/intel/dmar.c: In function 'qi_flush_dev_iotlb_pasid': >include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 > is > always false [-Wtype-limits] > 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) > |^ >include/linux/compiler.h:58:52: note: in definition of macro > '__trace_if_var' > 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : > __trace_if_value(cond)) > |^~~~ > >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' > 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) > | ^~ >include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' > 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ > | ^ >include/linux/bits.h:45:3: note: in expansion of macro > 'GENMASK_INPUT_CHECK' > 45 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) > | ^~~ >drivers/iommu/intel/dmar.c:1459:13: note: in expansion of macro > 'GENMASK_ULL' > 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) > | ^~~ >include/linux/bits.h:26:40: warning: comparison of unsigned expression < 0 > is > always false [-Wtype-limits] > 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) > |^ >include/linux/compiler.h:58:52: note: in definition of macro > '__trace_if_var' > 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : > __trace_if_value(cond)) > |^~~~ > >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' > 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) > | ^~ >include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' > 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ > | ^ >include/linux/bits.h:45:3: note: in expansion of macro > 'GENMASK_INPUT_CHECK' > 45 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) > | ^~~ >drivers/iommu/intel/dmar.c:1459:13: note: in expansion of macro > 'GENMASK_ULL' > 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) > | ^~~ >include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 > is > always false [-Wtype-limits] > 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) > |^ >include/linux/compiler.h:58:61: note: in definition of macro > '__trace_if_var' > 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : > __trace_if_value(cond)) > | ^~~~ > >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' > 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHI
Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
Hi Jacob, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on iommu/next] [also build test WARNING on linux/master linus/master v5.8-rc4 next-20200707] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Jacob-Pan/iommu-vt-d-Misc-tweaks-and-fixes-for-vSVA/20200707-081026 base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next config: x86_64-randconfig-m031-20200707 (attached as .config) compiler: gcc-9 (Debian 9.3.0-14) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): In file included from include/linux/string.h:6, from include/linux/uuid.h:12, from include/linux/mod_devicetable.h:13, from include/linux/pci.h:27, from drivers/iommu/intel/dmar.c:19: drivers/iommu/intel/dmar.c: In function 'qi_flush_dev_iotlb_pasid': include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) |^ include/linux/compiler.h:58:52: note: in definition of macro '__trace_if_var' 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond)) |^~~~ >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ | ^ include/linux/bits.h:45:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 45 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) | ^~~ drivers/iommu/intel/dmar.c:1459:13: note: in expansion of macro 'GENMASK_ULL' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~~ include/linux/bits.h:26:40: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) |^ include/linux/compiler.h:58:52: note: in definition of macro '__trace_if_var' 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond)) |^~~~ >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ | ^ include/linux/bits.h:45:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 45 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) | ^~~ drivers/iommu/intel/dmar.c:1459:13: note: in expansion of macro 'GENMASK_ULL' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~~ include/linux/bits.h:26:28: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) |^ include/linux/compiler.h:58:61: note: in definition of macro '__trace_if_var' 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond)) | ^~~~ >> drivers/iommu/intel/dmar.c:1459:2: note: in expansion of macro 'if' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~ include/linux/bits.h:25:3: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 25 | (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ | ^ include/linux/bits.h:45:3: note: in expansion of macro 'GENMASK_INPUT_CHECK' 45 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) | ^~~ drivers/iommu/intel/dmar.c:1459:13: note: in expansion of macro 'GENMASK_ULL' 1459 | if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) | ^~~ include/linux/bits.h:26:40: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 26 | __builtin_constant_p((l) > (h)), (l) > (h), 0))) |^ include/linux/compiler.h:58:61: note: in definition of macro '__trace_if_var' 58 | #define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond))
[PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
From: Liu Yi L
Address information for device TLB invalidation comes from userspace
when device is directly assigned to a guest with vIOMMU support.
VT-d requires page aligned address. This patch checks and enforce
address to be page aligned, otherwise reserved bits can be set in the
invalidation descriptor. Unrecoverable fault will be reported due to
non-zero value in the reserved bits.
Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation
cache types")
Acked-by: Lu Baolu
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
drivers/iommu/intel/dmar.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index d9f973fa1190..b2c53bada905 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu,
u16 sid, u16 pfsid,
* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
* ECAP.
*/
- desc.qw1 |= addr & ~mask;
- if (size_order)
+ if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
+ pr_warn_ratelimited("Invalidate non-aligned address %llx, order
%d\n", addr, size_order);
+
+ /* Take page address */
+ desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
+
+ if (size_order) {
+ /*
+* Existing 0s in address below size_order may be the least
+* significant bit, we must set them to 1s to avoid having
+* smaller size than desired.
+*/
+ desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT,
+ VTD_PAGE_SHIFT);
+ /* Clear size_order bit to indicate size */
+ desc.qw1 &= ~mask;
+ /* Set the S bit to indicate flushing more than 1 page */
desc.qw1 |= QI_DEV_EIOTLB_SIZE;
+ }
qi_submit_sync(iommu, , 1, 0);
}
--
2.7.4
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