Re: [PATCH v6 3/5] iommu/vt-d: Add debugfs support to show register contents

[Andy Shevchenko]

On Tue, 2018-01-09 at 19:48 -0800, Sohil Mehta wrote:

> Debugfs extension to dump all the register contents for each IOMMU
> device to the user space via debugfs.
> 
> example:
> root@OTC-KBLH-01:~# cat /sys/kernel/debug/intel_iommu/iommu_regset
> 
> DMAR: dmar1: reg_base_addr fed9
> Name Offset Contents
> VER  0x00   0x0010
> CAP  0x08   0x01cc40660462
> ECAP 0x10   0x019e2ff0505e
> GCMD 0x18   0x
> GSTS 0x1c   0xc700
> RTADDR   0x20   0x0004558d6800
> CCMD 0x28   0x0800
> FSTS 0x34   0x
> FECTL0x38   0x
> FEDATA   0x3c   0xfee0100c4141

> + seq_printf(m, "\nDMAR: %s: reg_base_addr %llx\n",
> iommu->name,
> +base);

Can we get rid of leading '\n'?

-- 
Andy Shevchenko 
Intel Finland Oy
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[PATCH v6 3/5] iommu/vt-d: Add debugfs support to show register contents

[Sohil Mehta]

From: Gayatri Kammela 

Debugfs extension to dump all the register contents for each IOMMU
device to the user space via debugfs.

example:
root@OTC-KBLH-01:~# cat /sys/kernel/debug/intel_iommu/iommu_regset

DMAR: dmar1: reg_base_addr fed9
Name Offset Contents
VER  0x00   0x0010
CAP  0x08   0x01cc40660462
ECAP 0x10   0x019e2ff0505e
GCMD 0x18   0x
GSTS 0x1c   0xc700
RTADDR   0x20   0x0004558d6800
CCMD 0x28   0x0800
FSTS 0x34   0x
FECTL0x38   0x
FEDATA   0x3c   0xfee0100c4141

Cc: Sohil Mehta 
Cc: Fenghua Yu 
Cc: Jacob Pan 
Cc: Ashok Raj 
Signed-off-by: Gayatri Kammela 
---

v6: No change

v5: No change

v4: Fix checkpatch.pl warnings
Remove error reporting for debugfs_create_file function
Remove redundant IOMMU null check under for_each_active_iommu

v3: Use a macro for seq file operations 
Change the intel_iommu_regset file name to iommu_regset
Add information for MTRR registers

v2: Fix seq_printf formatting

 drivers/iommu/intel-iommu-debug.c | 78 +++
 include/linux/intel-iommu.h   |  2 +
 2 files changed, 80 insertions(+)

diff --git a/drivers/iommu/intel-iommu-debug.c 
b/drivers/iommu/intel-iommu-debug.c
index d5b0eea..9ee9a50 100644
--- a/drivers/iommu/intel-iommu-debug.c
+++ b/drivers/iommu/intel-iommu-debug.c
@@ -125,6 +125,81 @@ static int dmar_translation_struct_show(struct seq_file 
*m, void *unused)
 
 DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
 
+static int iommu_regset_show(struct seq_file *m, void *unused)
+{
+   struct dmar_drhd_unit *drhd;
+   struct intel_iommu *iommu;
+   unsigned long long base;
+   int i;
+   struct regset {
+   int offset;
+   char *regs;
+   };
+
+   static const struct regset regstr[] = {{DMAR_VER_REG, "VER"},
+  {DMAR_CAP_REG, "CAP"},
+  {DMAR_ECAP_REG, "ECAP"},
+  {DMAR_GCMD_REG, "GCMD"},
+  {DMAR_GSTS_REG, "GSTS"},
+  {DMAR_RTADDR_REG, "RTADDR"},
+  {DMAR_CCMD_REG, "CCMD"},
+  {DMAR_FSTS_REG, "FSTS"},
+  {DMAR_FECTL_REG, "FECTL"},
+  {DMAR_FEDATA_REG, "FEDATA"},
+  {DMAR_FEADDR_REG, "FEADDR"},
+  {DMAR_FEUADDR_REG, "FEUADDR"},
+  {DMAR_AFLOG_REG, "AFLOG"},
+  {DMAR_PMEN_REG, "PMEN"},
+  {DMAR_PLMBASE_REG, "PLMBASE"},
+  {DMAR_PLMLIMIT_REG, "PLMLIMIT"},
+  {DMAR_PHMBASE_REG, "PHMBASE"},
+  {DMAR_PHMLIMIT_REG,  "PHMLIMIT"},
+  {DMAR_IQH_REG, "IQH"},
+  {DMAR_IQT_REG, "IQT"},
+  {DMAR_IQ_SHIFT, "IQ"},
+  {DMAR_IQA_REG, "IQA"},
+  {DMAR_ICS_REG, "ICS"},
+  {DMAR_IRTA_REG, "IRTA"},
+  {DMAR_PQH_REG, "PQH"},
+  {DMAR_PQT_REG, "PQT"},
+  {DMAR_PQA_REG, "PQA"},
+  {DMAR_PRS_REG, "PRS"},
+  {DMAR_PECTL_REG, "PECTL"},
+  {DMAR_PEDATA_REG, "PEDATA"},
+  {DMAR_PEADDR_REG, "PEADDR"},
+  {DMAR_PEUADDR_REG, "PEUADDR"},
+  {DMAR_MTRRCAP_REG, "MTRRCAP"},
+  {DMAR_MTRRDEF_REG, "MTRRDEF"} };
+
+   rcu_read_lock();
+   for_each_active_iommu(iommu, drhd) {
+   if (!drhd->reg_base_addr) {
+   seq_puts(m, "IOMMU: Invalid base address\n");
+   rcu_read_unlock();
+   return -EINVAL;
+   }
+
+   base = drhd->reg_base_addr;
+   seq_printf(m, "\nDMAR: %s: reg_base_addr