Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
Hi Rafael, Lv, On Thu, Jun 08, 2017 at 07:13:24PM +0200, Rafael J. Wysocki wrote: > On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi > wrote: > > On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: > >> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > >> 1. Errata ID #74 > >>SMMU register alias Page 1 is not implemented > >> 2. Errata ID #126 > >>SMMU doesnt support unique IRQ lines and also MSI for gerror, > >>eventq and cmdq-sync > >> > >> The following patchset does software workaround for these two erratas. > >> > >> This series is based on patchset. > >> https://www.spinics.net/lists/arm-kernel/msg578443.html > > > > Yes so it is not standalone. How are we going to merge these > > ACPI IORT/ACPICA/SMMU patches - inclusive of: > > > > [1] https://www.spinics.net/lists/arm-kernel/msg586458.html > > > > Rafael, do ACPICA patches go upstream via the ACPI tree pull request ? > > Not as a rule. So I take it as the can they go in as separate pull (standalone ACPICA updates) ? > > To remove dependency on ACPICA changes this series needs updating > > anyway and for [1] above I think the only solution is for all the > > patches to go via the ACPI tree (if ACPICA updates go upstream with it). > > I think we may ask Lv to backport the header changes once they have > been merged into Linux. > > Lv, would that work? I was asking to understand how to queue some patches for the upcoming merge window that have an ACPICA dependency, how are we supposed to handle that ? I would like to avoid cross tree dependencies, that's why I asked about the ACPI pull request, so that IORT patches could go via ACPI tree too this time along with ACPICA changes just trying to make it simple. Please let us know, thanks a lot. Lorenzo ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
On 08/06/17 18:13, Rafael J. Wysocki wrote: > On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi > wrote: >> On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: >>> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. >>> 1. Errata ID #74 >>>SMMU register alias Page 1 is not implemented >>> 2. Errata ID #126 >>>SMMU doesnt support unique IRQ lines and also MSI for gerror, >>>eventq and cmdq-sync >>> >>> The following patchset does software workaround for these two erratas. >>> >>> This series is based on patchset. >>> https://www.spinics.net/lists/arm-kernel/msg578443.html >> >> Yes so it is not standalone. How are we going to merge these >> ACPI IORT/ACPICA/SMMU patches - inclusive of: >> >> [1] https://www.spinics.net/lists/arm-kernel/msg586458.html >> >> Rafael, do ACPICA patches go upstream via the ACPI tree pull request ? > > Not as a rule. > >> To remove dependency on ACPICA changes this series needs updating >> anyway and for [1] above I think the only solution is for all the >> patches to go via the ACPI tree (if ACPICA updates go upstream with it). > > I think we may ask Lv to backport the header changes once they have > been merged into Linux. > > Lv, would that work? FWIW, I have already sent a PR for the header patch for the new model IDs to ACPICA upstream. I briefly considered the actual table update as well, but didn't find time to comprehend the code changes that appeared to be necessary for that. Robin. > > Thanks, > Rafael > ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
On Thu, Jun 8, 2017 at 6:32 PM, Lorenzo Pieralisi wrote: > On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: >> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. >> 1. Errata ID #74 >>SMMU register alias Page 1 is not implemented >> 2. Errata ID #126 >>SMMU doesnt support unique IRQ lines and also MSI for gerror, >>eventq and cmdq-sync >> >> The following patchset does software workaround for these two erratas. >> >> This series is based on patchset. >> https://www.spinics.net/lists/arm-kernel/msg578443.html > > Yes so it is not standalone. How are we going to merge these > ACPI IORT/ACPICA/SMMU patches - inclusive of: > > [1] https://www.spinics.net/lists/arm-kernel/msg586458.html > > Rafael, do ACPICA patches go upstream via the ACPI tree pull request ? Not as a rule. > To remove dependency on ACPICA changes this series needs updating > anyway and for [1] above I think the only solution is for all the > patches to go via the ACPI tree (if ACPICA updates go upstream with it). I think we may ask Lv to backport the header changes once they have been merged into Linux. Lv, would that work? Thanks, Rafael ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
On Tue, May 30, 2017 at 05:33:38PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. > > This series is based on patchset. > https://www.spinics.net/lists/arm-kernel/msg578443.html Yes so it is not standalone. How are we going to merge these ACPI IORT/ACPICA/SMMU patches - inclusive of: [1] https://www.spinics.net/lists/arm-kernel/msg586458.html Rafael, do ACPICA patches go upstream via the ACPI tree pull request ? To remove dependency on ACPICA changes this series needs updating anyway and for [1] above I think the only solution is for all the patches to go via the ACPI tree (if ACPICA updates go upstream with it). Thanks, Lorenzo > Changes since v6: >- Changed device tree compatible string to vendor specific. >- Rebased on Robin's latest "Update SMMU models for IORT rev. C" v2 patch. > https://www.spinics.net/lists/arm-kernel/msg582809.html > > Changes since v5: > - Rebased on Robin's "Update SMMU models for IORT rev. C" patch. > https://www.spinics.net/lists/arm-kernel/msg580728.html > - Replaced ACPI_IORT_SMMU_V3_CAVIUM_CN99XX macro with > ACPI_IORT_SMMU_CAVIUM_CN99XX > > Changes since v4: > - Replaced all page1 offset macros ARM_SMMU_EVTQ/PRIQ_PROD/CONS with > arm_smmu_page1_fixup(ARM_SMMU_EVTQ/PRIQ_PROD/CONS, smmu) > > Changes since v3: > - Merged patches 1, 2 and 4 of Version 3. > - Modified the page1_offset_adjust() and get_irq_flags() implementation as >suggested by Robin. > > Changes since v2: > - Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document > with >new SMMU option used to enable errata workaround. > > Changes since v1: > - Since the use of MIDR register is rejected and SMMU_IIDR is broken on this >silicon, as suggested by Will Deacon modified the patches to use ThunderX2 >SMMUv3 IORT model number to enable errata workaround. > > Geetha Sowjanya (1): > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 > > Linu Cherian (2): > ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 > model > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum > #74 > > Documentation/arm64/silicon-errata.txt |2 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt |6 ++ > drivers/acpi/arm64/iort.c | 10 ++- > drivers/iommu/arm-smmu-v3.c| 93 > > 4 files changed, 91 insertions(+), 20 deletions(-) > ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
On 30.05.17 17:33:38, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. > > This series is based on patchset. > https://www.spinics.net/lists/arm-kernel/msg578443.html > > Changes since v6: >- Changed device tree compatible string to vendor specific. >- Rebased on Robin's latest "Update SMMU models for IORT rev. C" v2 patch. > https://www.spinics.net/lists/arm-kernel/msg582809.html > > Changes since v5: > - Rebased on Robin's "Update SMMU models for IORT rev. C" patch. > https://www.spinics.net/lists/arm-kernel/msg580728.html > - Replaced ACPI_IORT_SMMU_V3_CAVIUM_CN99XX macro with > ACPI_IORT_SMMU_CAVIUM_CN99XX > > Changes since v4: > - Replaced all page1 offset macros ARM_SMMU_EVTQ/PRIQ_PROD/CONS with > arm_smmu_page1_fixup(ARM_SMMU_EVTQ/PRIQ_PROD/CONS, smmu) > > Changes since v3: > - Merged patches 1, 2 and 4 of Version 3. > - Modified the page1_offset_adjust() and get_irq_flags() implementation as >suggested by Robin. > > Changes since v2: > - Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document > with >new SMMU option used to enable errata workaround. > > Changes since v1: > - Since the use of MIDR register is rejected and SMMU_IIDR is broken on this >silicon, as suggested by Will Deacon modified the patches to use ThunderX2 >SMMUv3 IORT model number to enable errata workaround. > > Geetha Sowjanya (1): > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 > > Linu Cherian (2): > ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 > model > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum > #74 > > Documentation/arm64/silicon-errata.txt |2 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt |6 ++ > drivers/acpi/arm64/iort.c | 10 ++- > drivers/iommu/arm-smmu-v3.c| 93 > > 4 files changed, 91 insertions(+), 20 deletions(-) For the whole series: Reviewed-by: Robert Richter ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software workaround for these two erratas. This series is based on patchset. https://www.spinics.net/lists/arm-kernel/msg578443.html Changes since v6: - Changed device tree compatible string to vendor specific. - Rebased on Robin's latest "Update SMMU models for IORT rev. C" v2 patch. https://www.spinics.net/lists/arm-kernel/msg582809.html Changes since v5: - Rebased on Robin's "Update SMMU models for IORT rev. C" patch. https://www.spinics.net/lists/arm-kernel/msg580728.html - Replaced ACPI_IORT_SMMU_V3_CAVIUM_CN99XX macro with ACPI_IORT_SMMU_CAVIUM_CN99XX Changes since v4: - Replaced all page1 offset macros ARM_SMMU_EVTQ/PRIQ_PROD/CONS with arm_smmu_page1_fixup(ARM_SMMU_EVTQ/PRIQ_PROD/CONS, smmu) Changes since v3: - Merged patches 1, 2 and 4 of Version 3. - Modified the page1_offset_adjust() and get_irq_flags() implementation as suggested by Robin. Changes since v2: - Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with new SMMU option used to enable errata workaround. Changes since v1: - Since the use of MIDR register is rejected and SMMU_IIDR is broken on this silicon, as suggested by Will Deacon modified the patches to use ThunderX2 SMMUv3 IORT model number to enable errata workaround. Geetha Sowjanya (1): iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Linu Cherian (2): ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Documentation/arm64/silicon-errata.txt |2 + .../devicetree/bindings/iommu/arm,smmu-v3.txt |6 ++ drivers/acpi/arm64/iort.c | 10 ++- drivers/iommu/arm-smmu-v3.c| 93 4 files changed, 91 insertions(+), 20 deletions(-) ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
