Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Jayachandran Chandrashekaran Nair]

On Wed, Feb 17, 2016 at 8:58 PM, Alex Williamson
 wrote:
> On Wed, 17 Feb 2016 17:15:09 +0530
> Jayachandran Chandrashekaran Nair
>  wrote:
>
>> On Wed, Feb 17, 2016 at 3:55 AM, Alex Williamson
>>  wrote:
>> > On Wed, 17 Feb 2016 02:38:24 +0530
>> > Jayachandran Chandrashekaran Nair
>> >  wrote:
>> >
>> >> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
>> >>  wrote:
>> >> > On Mon, 15 Feb 2016 12:20:23 -0600
>> >> > Bjorn Helgaas  wrote:
>> >> >
>> >> >> [+cc Alex, iommu list]
>> >> >>
>> >> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:
>> >> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
>> >> >> > that should not be considered during DMA alias search. This is
>> >> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
>> >> >> > that has internal bridges which have either missing or wrong PCIe
>> >> >> > capabilities.
>> >> >
>> >> > I figured this would come at some point, the right answer is of course
>> >> > to follow the PCIe spec and implement the required PCIe capability in
>> >> > the hardware.
>> >>
>> >> There are  PCIe controllers on the chip that follows the spec, the issue 
>> >> is
>> >> how it is integrated to the northbridge (equivalent) on the chip, I have
>> >> tried to explain it below.
>> >>
>> >> >> This needs more explanation, like what exactly is wrong with this
>> >> >> device?  A missing PCIe capability might cause other problems.
>> >> >>
>> >> >> What problem does this fix?  Without these patches, do we merely add
>> >> >> aliases that are unnecessary?  Do we crash because something goes
>> >> >> wrong in the pci_pcie_type() switch because of the incorrect
>> >> >> capability?
>> >>
>> >> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
>> >> processor will look like:
>> >>
>> >>
>> >> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
>> >> |  +--1.a.1[4]-4.0.0---[5]5.0.0
>> >> |  .
>> >> |  ... etc...
>> >> |
>> >> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
>> >>+-10.a.1[13]---13.0.0---[14]---14.0.0
>> >>.
>> >>... etc...
>> >
>> > So we have:
>> >
>> > "Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
>> >   (no pcie)  (pci/x-pcie)
>>
>> The top level is one glue bridge per chip in a multi-chip board,
>> but otherwise this is accurate.
>>
>> >>
>> >> The devices 0.0.x and x.a.x are glue bridges that are there to
>> >> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
>> >> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
>> >> have a PCIe capability (type 8) and 0.0.x does not have any pcie
>> >> capability.
>> >>
>> >> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
>> >> driver code does dma alias walk to find the device id to use
>> >> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
>> >> since they are type root port, but will continue on up and end
>> >> up with incorrect device id.
>> >>
>> >> The flag I have added is to make the pci_for_each_dma_alias()
>> >> ignore the last 2 levels of glue/internal bridges.
>> >
>> > Per the PCIe spec, I'm not even sure what you have is a valid
>> > hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
>> > bridge.  So really you're pretending that the downstream "glue bridge"
>> > is your host bridge and therefore root complex, but the PCI topology
>> > would clearly dictate that the top-most bus is conventional PCI and
>> > therefore everything is an alias of everything else and the DMA alias
>> > code is doing exactly what it should.
>>
>> Yes, I am not arguing that there is any issue in the current code. I
>> am trying to figure out the correct way to implement the quirk. We
>> have to support the hardware we have, not the hardware we want to
>> have :)
>>
>> > Also note that the caller of pci_for_each_dma_alias() owns the callback
>> > function triggered for each alias, that function could choose to prune
>> > out these "glue bridges" itself if that's the appropriate thing to do.
>>
>> I had implemented this first, but moved to the current approach because
>> it is needed in multiple places. The problem is: "On vulcan, while
>> going up the pcie bus heirarchy for finding aliases, skip the glue bridges",
>> So the logical place to put the fix is in pci_for_each_dma_alias()
>>
>> > Where do the SMMU and ITS actually reside in the above diagram?  You
>> > can use the callout function to stop the traversal anywhere you wish,
>> > it's free to return a -errno to stop or positive number, which the
>> > caller can interpret as error or non-failure stop condition.
>>
>> The SMMU (for translation requests) and ITS (for MSI 

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Alex Williamson]

On Wed, 17 Feb 2016 17:15:09 +0530
Jayachandran Chandrashekaran Nair
 wrote:

> On Wed, Feb 17, 2016 at 3:55 AM, Alex Williamson
>  wrote:
> > On Wed, 17 Feb 2016 02:38:24 +0530
> > Jayachandran Chandrashekaran Nair
> >  wrote:
> >  
> >> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
> >>  wrote:  
> >> > On Mon, 15 Feb 2016 12:20:23 -0600
> >> > Bjorn Helgaas  wrote:
> >> >  
> >> >> [+cc Alex, iommu list]
> >> >>
> >> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:  
> >> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
> >> >> > that should not be considered during DMA alias search. This is
> >> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
> >> >> > that has internal bridges which have either missing or wrong PCIe
> >> >> > capabilities.  
> >> >
> >> > I figured this would come at some point, the right answer is of course
> >> > to follow the PCIe spec and implement the required PCIe capability in
> >> > the hardware.  
> >>
> >> There are  PCIe controllers on the chip that follows the spec, the issue is
> >> how it is integrated to the northbridge (equivalent) on the chip, I have
> >> tried to explain it below.
> >>  
> >> >> This needs more explanation, like what exactly is wrong with this
> >> >> device?  A missing PCIe capability might cause other problems.
> >> >>
> >> >> What problem does this fix?  Without these patches, do we merely add
> >> >> aliases that are unnecessary?  Do we crash because something goes
> >> >> wrong in the pci_pcie_type() switch because of the incorrect
> >> >> capability?  
> >>
> >> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
> >> processor will look like:
> >>
> >>
> >> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
> >> |  +--1.a.1[4]-4.0.0---[5]5.0.0
> >> |  .
> >> |  ... etc...
> >> |
> >> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
> >>+-10.a.1[13]---13.0.0---[14]---14.0.0
> >>.
> >>... etc...  
> >
> > So we have:
> >
> > "Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
> >   (no pcie)  (pci/x-pcie)  
> 
> The top level is one glue bridge per chip in a multi-chip board,
> but otherwise this is accurate.
> 
> >>
> >> The devices 0.0.x and x.a.x are glue bridges that are there to
> >> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
> >> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
> >> have a PCIe capability (type 8) and 0.0.x does not have any pcie
> >> capability.
> >>
> >> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
> >> driver code does dma alias walk to find the device id to use
> >> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
> >> since they are type root port, but will continue on up and end
> >> up with incorrect device id.
> >>
> >> The flag I have added is to make the pci_for_each_dma_alias()
> >> ignore the last 2 levels of glue/internal bridges.  
> >
> > Per the PCIe spec, I'm not even sure what you have is a valid
> > hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
> > bridge.  So really you're pretending that the downstream "glue bridge"
> > is your host bridge and therefore root complex, but the PCI topology
> > would clearly dictate that the top-most bus is conventional PCI and
> > therefore everything is an alias of everything else and the DMA alias
> > code is doing exactly what it should.  
> 
> Yes, I am not arguing that there is any issue in the current code. I
> am trying to figure out the correct way to implement the quirk. We
> have to support the hardware we have, not the hardware we want to
> have :)
> 
> > Also note that the caller of pci_for_each_dma_alias() owns the callback
> > function triggered for each alias, that function could choose to prune
> > out these "glue bridges" itself if that's the appropriate thing to do.  
> 
> I had implemented this first, but moved to the current approach because
> it is needed in multiple places. The problem is: "On vulcan, while
> going up the pcie bus heirarchy for finding aliases, skip the glue bridges",
> So the logical place to put the fix is in pci_for_each_dma_alias()
> 
> > Where do the SMMU and ITS actually reside in the above diagram?  You
> > can use the callout function to stop the traversal anywhere you wish,
> > it's free to return a -errno to stop or positive number, which the
> > caller can interpret as error or non-failure stop condition.  
> 
> The SMMU (for translation requests) and ITS (for MSI writes for
> interrupts) are connected directly to the proper PCIe controller
> (2/4/11/13.0.0 above)


If the translation unit is on the root port then DMA aliases 

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Jayachandran Chandrashekaran Nair]

On Wed, Feb 17, 2016 at 3:55 AM, Alex Williamson
 wrote:
> On Wed, 17 Feb 2016 02:38:24 +0530
> Jayachandran Chandrashekaran Nair
>  wrote:
>
>> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
>>  wrote:
>> > On Mon, 15 Feb 2016 12:20:23 -0600
>> > Bjorn Helgaas  wrote:
>> >
>> >> [+cc Alex, iommu list]
>> >>
>> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:
>> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
>> >> > that should not be considered during DMA alias search. This is
>> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
>> >> > that has internal bridges which have either missing or wrong PCIe
>> >> > capabilities.
>> >
>> > I figured this would come at some point, the right answer is of course
>> > to follow the PCIe spec and implement the required PCIe capability in
>> > the hardware.
>>
>> There are  PCIe controllers on the chip that follows the spec, the issue is
>> how it is integrated to the northbridge (equivalent) on the chip, I have
>> tried to explain it below.
>>
>> >> This needs more explanation, like what exactly is wrong with this
>> >> device?  A missing PCIe capability might cause other problems.
>> >>
>> >> What problem does this fix?  Without these patches, do we merely add
>> >> aliases that are unnecessary?  Do we crash because something goes
>> >> wrong in the pci_pcie_type() switch because of the incorrect
>> >> capability?
>>
>> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
>> processor will look like:
>>
>>
>> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
>> |  +--1.a.1[4]-4.0.0---[5]5.0.0
>> |  .
>> |  ... etc...
>> |
>> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
>>+-10.a.1[13]---13.0.0---[14]---14.0.0
>>.
>>... etc...
>
> So we have:
>
> "Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
>   (no pcie)  (pci/x-pcie)

The top level is one glue bridge per chip in a multi-chip board,
but otherwise this is accurate.

>>
>> The devices 0.0.x and x.a.x are glue bridges that are there to
>> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
>> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
>> have a PCIe capability (type 8) and 0.0.x does not have any pcie
>> capability.
>>
>> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
>> driver code does dma alias walk to find the device id to use
>> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
>> since they are type root port, but will continue on up and end
>> up with incorrect device id.
>>
>> The flag I have added is to make the pci_for_each_dma_alias()
>> ignore the last 2 levels of glue/internal bridges.
>
> Per the PCIe spec, I'm not even sure what you have is a valid
> hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
> bridge.  So really you're pretending that the downstream "glue bridge"
> is your host bridge and therefore root complex, but the PCI topology
> would clearly dictate that the top-most bus is conventional PCI and
> therefore everything is an alias of everything else and the DMA alias
> code is doing exactly what it should.

Yes, I am not arguing that there is any issue in the current code. I
am trying to figure out the correct way to implement the quirk. We
have to support the hardware we have, not the hardware we want to
have :)

> Also note that the caller of pci_for_each_dma_alias() owns the callback
> function triggered for each alias, that function could choose to prune
> out these "glue bridges" itself if that's the appropriate thing to do.

I had implemented this first, but moved to the current approach because
it is needed in multiple places. The problem is: "On vulcan, while
going up the pcie bus heirarchy for finding aliases, skip the glue bridges",
So the logical place to put the fix is in pci_for_each_dma_alias()

> Where do the SMMU and ITS actually reside in the above diagram?  You
> can use the callout function to stop the traversal anywhere you wish,
> it's free to return a -errno to stop or positive number, which the
> caller can interpret as error or non-failure stop condition.

The SMMU (for translation requests) and ITS (for MSI writes for
interrupts) are connected directly to the proper PCIe controller
(2/4/11/13.0.0 above)

> You could even think about changing what Linux considers to be the host
> bridge.  Maybe these glue bridges shouldn't even be visible to Linux,
> would that also solve the issue with the broken BAR?

The glue bridges have to seen by Linux for assigning resources like
bus ranges and memory windows. So these are required bridges in
the topology and will work with the standard linux code
(provided we skip them for 

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Alex Williamson]

On Wed, 17 Feb 2016 02:38:24 +0530
Jayachandran Chandrashekaran Nair
 wrote:

> On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
>  wrote:
> > On Mon, 15 Feb 2016 12:20:23 -0600
> > Bjorn Helgaas  wrote:
> >  
> >> [+cc Alex, iommu list]
> >>
> >> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:  
> >> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
> >> > that should not be considered during DMA alias search. This is
> >> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
> >> > that has internal bridges which have either missing or wrong PCIe
> >> > capabilities.  
> >
> > I figured this would come at some point, the right answer is of course
> > to follow the PCIe spec and implement the required PCIe capability in
> > the hardware.  
> 
> There are  PCIe controllers on the chip that follows the spec, the issue is
> how it is integrated to the northbridge (equivalent) on the chip, I have
> tried to explain it below.
> 
> >> This needs more explanation, like what exactly is wrong with this
> >> device?  A missing PCIe capability might cause other problems.
> >>
> >> What problem does this fix?  Without these patches, do we merely add
> >> aliases that are unnecessary?  Do we crash because something goes
> >> wrong in the pci_pcie_type() switch because of the incorrect
> >> capability?  
> 
> Here's how (for example) how the PCI enumeration of a 2 node Vulcan
> processor will look like:
> 
> 
> [0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
> |  +--1.a.1[4]-4.0.0---[5]5.0.0
> |  .
> |  ... etc...
> |
> +-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
>+-10.a.1[13]---13.0.0---[14]---14.0.0
>.
>... etc...

So we have:

"Glue Bridge"---"Glue Bridges"---Root Ports---Endpoints
  (no pcie)  (pci/x-pcie)

> 
> The devices 0.0.x and x.a.x are glue bridges that are there to
> bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
> 11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
> have a PCIe capability (type 8) and 0.0.x does not have any pcie
> capability.
> 
> In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
> driver code does dma alias walk to find the device id to use
> in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
> since they are type root port, but will continue on up and end
> up with incorrect device id.
> 
> The flag I have added is to make the pci_for_each_dma_alias()
> ignore the last 2 levels of glue/internal bridges.

Per the PCIe spec, I'm not even sure what you have is a valid
hierarchy, root ports sit on root complexes, not behind a PCI-to-PCIe
bridge.  So really you're pretending that the downstream "glue bridge"
is your host bridge and therefore root complex, but the PCI topology
would clearly dictate that the top-most bus is conventional PCI and
therefore everything is an alias of everything else and the DMA alias
code is doing exactly what it should.

Also note that the caller of pci_for_each_dma_alias() owns the callback
function triggered for each alias, that function could choose to prune
out these "glue bridges" itself if that's the appropriate thing to do.
Where do the SMMU and ITS actually reside in the above diagram?  You
can use the callout function to stop the traversal anywhere you wish,
it's free to return a -errno to stop or positive number, which the
caller can interpret as error or non-failure stop condition.

You could even think about changing what Linux considers to be the host
bridge.  Maybe these glue bridges shouldn't even be visible to Linux,
would that also solve the issue with the broken BAR?

> > The change takes the same code path as it would for a real PCIe bridge
> > port (downstream/upstream/root), which means they want to skip adding
> > this bridge as an alias of the device.  So we're adding in aliases that
> > don't exist, the bridge itself.
> >
> > If anything I'd suggest a flag that actually tries to address the
> > problem rather than a symptom of the problem.  For example, maybe the
> > flag should be PCI_DEV_FLAGS_IS_PCIE.  Maybe pci_is_pcie() should even
> > take that into account.  That has some trickle through for
> > pci_pcie_type() and all the accessor functions, but maybe it's a
> > cleaner solution overall (or maybe it explodes further).  Thanks,  
> 
> I didn't really want to mark the glue bridges as PCIe or have fake
> PCIe capability there, the obvious simple solution was to add
> the flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS
> 
> Any suggestions/comments on how to do this better would be welcome.

I definitely don't think either flag idea is the right solution, I
think you've actually already got the tools you need to solve it by
putting the intelligence in the callback function or by going 

Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Jayachandran Chandrashekaran Nair]

On Tue, Feb 16, 2016 at 1:09 AM, Alex Williamson
 wrote:
> On Mon, 15 Feb 2016 12:20:23 -0600
> Bjorn Helgaas  wrote:
>
>> [+cc Alex, iommu list]
>>
>> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:
>> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
>> > that should not be considered during DMA alias search. This is
>> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
>> > that has internal bridges which have either missing or wrong PCIe
>> > capabilities.
>
> I figured this would come at some point, the right answer is of course
> to follow the PCIe spec and implement the required PCIe capability in
> the hardware.

There are  PCIe controllers on the chip that follows the spec, the issue is
how it is integrated to the northbridge (equivalent) on the chip, I have
tried to explain it below.

>> This needs more explanation, like what exactly is wrong with this
>> device?  A missing PCIe capability might cause other problems.
>>
>> What problem does this fix?  Without these patches, do we merely add
>> aliases that are unnecessary?  Do we crash because something goes
>> wrong in the pci_pcie_type() switch because of the incorrect
>> capability?

Here's how (for example) how the PCI enumeration of a 2 node Vulcan
processor will look like:


[0] +-0.0.0--[1]---+--1.a.0[2]-2.0.0---[3]3.0.0
|  +--1.a.1[4]-4.0.0---[5]5.0.0
|  .
|  ... etc...
|
+-0.0.1--[10]--+-10.a.0[11]---11.0.0---[12]---12.0.0
   +-10.a.1[13]---13.0.0---[14]---14.0.0
   .
   ... etc...

The devices 0.0.x and x.a.x are glue bridges that are there to
bring the real PCIe controllers (pcie cap type 4) 2.0.0, 4.0.0,
11.0.0, 13.0.0 under a single PCI hierarchy. The x.a.x bridges
have a PCIe capability (type 8) and 0.0.x does not have any pcie
capability.

In case of Vulcan, both the GICv3 ITS driver code and the SMMUv3
driver code does dma alias walk to find the device id to use
in ITS and SMMU. In both cases it will ignore the x.0.0 bridges
since they are type root port, but will continue on up and end
up with incorrect device id.

The flag I have added is to make the pci_for_each_dma_alias()
ignore the last 2 levels of glue/internal bridges.

> The change takes the same code path as it would for a real PCIe bridge
> port (downstream/upstream/root), which means they want to skip adding
> this bridge as an alias of the device.  So we're adding in aliases that
> don't exist, the bridge itself.
>
> If anything I'd suggest a flag that actually tries to address the
> problem rather than a symptom of the problem.  For example, maybe the
> flag should be PCI_DEV_FLAGS_IS_PCIE.  Maybe pci_is_pcie() should even
> take that into account.  That has some trickle through for
> pci_pcie_type() and all the accessor functions, but maybe it's a
> cleaner solution overall (or maybe it explodes further).  Thanks,

I didn't really want to mark the glue bridges as PCIe or have fake
PCIe capability there, the obvious simple solution was to add
the flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

Any suggestions/comments on how to do this better would be welcome.

Thanks,
JC.
[Using gmail due to IT transition, hope the ascii art makes it thru]
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Re: [RFC PATCH 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS

[Alex Williamson]

On Mon, 15 Feb 2016 12:20:23 -0600
Bjorn Helgaas  wrote:

> [+cc Alex, iommu list]
> 
> On Mon, Feb 15, 2016 at 03:35:00AM +0530, Jayachandran C wrote:
> > Add a new flag PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS to indicate bridges
> > that should not be considered during DMA alias search. This is
> > to support hardware (in this case Broadcom Vulcan PCIe subsystem)
> > that has internal bridges which have either missing or wrong PCIe
> > capabilities.  

I figured this would come at some point, the right answer is of course
to follow the PCIe spec and implement the required PCIe capability in
the hardware.

> 
> This needs more explanation, like what exactly is wrong with this
> device?  A missing PCIe capability might cause other problems.
> 
> What problem does this fix?  Without these patches, do we merely add
> aliases that are unnecessary?  Do we crash because something goes
> wrong in the pci_pcie_type() switch because of the incorrect
> capability?

The change takes the same code path as it would for a real PCIe bridge
port (downstream/upstream/root), which means they want to skip adding
this bridge as an alias of the device.  So we're adding in aliases that
don't exist, the bridge itself.

If anything I'd suggest a flag that actually tries to address the
problem rather than a symptom of the problem.  For example, maybe the
flag should be PCI_DEV_FLAGS_IS_PCIE.  Maybe pci_is_pcie() should even
take that into account.  That has some trickle through for
pci_pcie_type() and all the accessor functions, but maybe it's a
cleaner solution overall (or maybe it explodes further).  Thanks,

Alex

> > Update the function pci_for_each_dma_alias() to skip bridges with
> > this flag set.
> > 
> > Signed-off-by: Jayachandran C 
> > ---
> > 
> > This patch is an RFC, if there is a better way to do this, please
> > let me know.
> > 
> > Thanks,
> > JC.
> > 
> >  drivers/pci/search.c | 2 ++
> >  include/linux/pci.h  | 2 ++
> >  2 files changed, 4 insertions(+)
> > 
> > diff --git a/drivers/pci/search.c b/drivers/pci/search.c
> > index a20ce7d..e5296aa 100644
> > --- a/drivers/pci/search.c
> > +++ b/drivers/pci/search.c
> > @@ -55,6 +55,8 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
> > continue;
> >  
> > tmp = bus->self;
> > +   if (tmp->dev_flags & PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS)
> > +   continue;
> >  
> > /*
> >  * PCIe-to-PCI/X bridges alias transactions from downstream
> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 27df4a6..b4d8215 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -182,6 +182,8 @@ enum pci_dev_flags {
> > PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
> > /* Get VPD from function 0 VPD */
> > PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
> > +   /* Bridge should be ignored for alias search  */
> > +   PCI_DEV_FLAGS_BRIDGE_SKIP_ALIAS = (__force pci_dev_flags_t) (1 << 9),
> >  };
> >  
> >  enum pci_irq_reroute_variant {
> > -- 
> > 1.9.1
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > the body of a message to majord...@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html  

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