[valgrind] [Bug 379925] PPC64, mtffs does not set the FPCC and C bits in the FPSCR register

[Carl Love]

https://bugs.kde.org/show_bug.cgi?id=379925

Carl Love  changed:

   What|Removed |Added

 Status|RESOLVED|CLOSED

--- Comment #3 from Carl Love  ---
No issues seen in the nightly regression test.  Closing.

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[valgrind] [Bug 379925] PPC64, mtffs does not set the FPCC and C bits in the FPSCR register

[Carl Love]

https://bugs.kde.org/show_bug.cgi?id=379925

Carl Love  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Carl Love  ---
Committed patch
Vex commit 3375,  Valgrind commit 16396

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[valgrind] [Bug 379925] PPC64, mtffs does not set the FPCC and C bits in the FPSCR register

[Carl Love]

https://bugs.kde.org/show_bug.cgi?id=379925

--- Comment #1 from Carl Love  ---
Created attachment 105610
  --> https://bugs.kde.org/attachment.cgi?id=105610=edit
patch for the mffs and additional issues


Some additional fixes:

- Fix mffs instruction, FPSCR, C_FPCC field access is not working correctly. 
- Fix xscmpexpdp again still had a bug.
- Remove duplicate tests from test_isa_3_0.c
- Comment out he tests for the new ISA 3.0B instructions.  There seem to be
some issues between the simulator and early HW that need to be sorted out.

Update the expected output again using the ISA 3.0 HW output instead of the
simulator output.  Patch with updated expected output not included in patch

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