Re: [Kicad-developers] OT: Trends in number of on-chip I/Os...

[Jon Evans]

Here are some approaches I know about (some of these available in KiCad
today, some of them not until tomorrow :-)

- Splitting up the part into logical blocks as Mark said

- Depending on user preference / company policy, using component attributes
to map all power and ground pins rather than showing them on the schematic
(i.e. hidden pins)

- Importing symbol pinout from a spreadsheet -- the vendor typically will
provide a spreadsheet (or tool for generating spreadsheet based on how you
choose the alternate functions of pins), and then you import this into your
library tool.

- Some tools can even generate the symbols from a spreadsheet (you just
have a column in the spreadsheet that assigns the pins to a logical block,
and each block gets a symbol generated)

- High-end EDA tools usually have DRC rules for checking that you have
appropriate number of bypass capacitors for the power pins, and that they
are located close enough to the power pins.

- When it comes time to do the layout, with large BGAs, some tools have
nice ways to break them up into zones and apply different fan-out behavior
based on the zone, to maximize the escape pathways (and thereby minimize
the number of layers needed for fan-out):  See page 167 of this somewhat
interesting book:
http://www.aetpcb.com/aet/net_resources/help/BGA_Breakouts_and_Routing.pdf

Food for thought...

-Jon

On Tue, Feb 14, 2017 at 9:20 AM, Mark Roszko  wrote:

> You split up the one part into multiple blocks with common
> functionality grouped the same way you may have a U9A and U9B of a
> logic IC with two gates. You'll just use quite a few pages
>
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Re: [Kicad-developers] OT: Trends in number of on-chip I/Os...

[Mark Roszko]

You split up the one part into multiple blocks with common
functionality grouped the same way you may have a U9A and U9B of a
logic IC with two gates. You'll just use quite a few pages

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[Kicad-developers] OT: Trends in number of on-chip I/Os...

[Clemens Koller]

Hi,

just for fun/information from the (german) news:
http://www.elektroniknet.de/markt-technik/halbleiter/details-zu-power9-138554.html

The Power9 Processor Family has internally 2359 Signals, 7370 Power (10 
different voltages) and 9909 Ground-Pins.

This is of course (not yet) on board level, but how do they visualize this 
bunch in an schematic?

Regards,

Clemens

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