[PATCH RESEND v2 1/8] ARM: KVM: Allow creating the VGIC after VCPUs
Rework the VGIC initialization slightly to allow initialization of the
vgic cpu-specific state even if the irqchip (the VGIC) hasn't been
created by user space yet. This is safe, because the vgic data
structures are already allocated when the CPU is allocated if VGIC
support is compiled into the kernel. Further, the init process does not
depend on any other information and the sacrifice is a slight
performance degradation for creating VMs in the no-VGIC case.
The reason is that the new device control API doesn't mandate creating
the VGIC before creating the VCPU and it is unreasonable to require user
space to create the VGIC before creating the VCPUs.
At the same time move the irqchip_in_kernel check out of
kvm_vcpu_first_run_init and into the init function to make the per-vcpu
and global init functions symmetric and add comments on the exported
functions making it a bit easier to understand the init flow by only
looking at vgic.c.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
arch/arm/kvm/arm.c |7 ---
virt/kvm/arm/vgic.c | 22 +++---
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 9c697db..2b1091a 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -461,6 +461,8 @@ static void update_vttbr(struct kvm *kvm)
static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
{
+ int ret;
+
if (likely(vcpu-arch.has_run_once))
return 0;
@@ -470,9 +472,8 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
* Initialize the VGIC before running a vcpu the first time on
* this VM.
*/
- if (irqchip_in_kernel(vcpu-kvm)
- unlikely(!vgic_initialized(vcpu-kvm))) {
- int ret = kvm_vgic_init(vcpu-kvm);
+ if (unlikely(!vgic_initialized(vcpu-kvm))) {
+ ret = kvm_vgic_init(vcpu-kvm);
if (ret)
return ret;
}
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 685fc72..5ce100f 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -1243,15 +1243,19 @@ static irqreturn_t vgic_maintenance_handler(int irq,
void *data)
return IRQ_HANDLED;
}
+/**
+ * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
+ * @vcpu: pointer to the vcpu struct
+ *
+ * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
+ * this vcpu and enable the VGIC for this VCPU
+ */
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
struct vgic_cpu *vgic_cpu = vcpu-arch.vgic_cpu;
struct vgic_dist *dist = vcpu-kvm-arch.vgic;
int i;
- if (!irqchip_in_kernel(vcpu-kvm))
- return 0;
-
if (vcpu-vcpu_id = VGIC_MAX_CPUS)
return -EBUSY;
@@ -1383,10 +1387,22 @@ out:
return ret;
}
+/**
+ * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
+ * @kvm: pointer to the kvm struct
+ *
+ * Map the virtual CPU interface into the VM before running any VCPUs. We
+ * can't do this at creation time, because user space must first set the
+ * virtual CPU interface address in the guest physical address space. Also
+ * initialize the ITARGETSRn regs to 0 on the emulated distributor.
+ */
int kvm_vgic_init(struct kvm *kvm)
{
int ret = 0, i;
+ if (!irqchip_in_kernel(kvm))
+ return 0;
+
mutex_lock(kvm-lock);
if (vgic_initialized(kvm))
--
1.7.10.4
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[PATCH RESEND v2 0/8] Support VGIC save/restore using device control API
Implement save/restore of the VGIC state using the newer KVM Device Control API. This requries some number of changes to existing code in addition to actually supporting save/restore of the necessary state. The first patches (01-03) support creating the VGIC using the Device Control API. This change is necessary because there are no other suitable KVM APIs that we can leverage to access the VGIC state from user space and the device control API was crafted exactly for this purpose. Subsequent patches add the missing infrastructure and user space API pieces necessary to actually save and restore the VGIC state. The GIC v2.0 architecture specification already specifies registers that can be used to save and restore the complete VGIC state for suspend/resume purposes on real hardware, and we can resuse this interface for the VGIC. The API is therefore based on the memory-mapped register accesses defined in the specs. See the individual patches for details. The patches are based on kvm-arm-next: git://git.linaro.org/people/cdall/linux-kvm-arm.git kvm-arm-next This patch series based on the above can be cloned from: git://git.linaro.org/people/cdall/linux-kvm-arm.git vgic-migrate-v2 User space patches for QEMU also posted on the list. Tested on Versatile Express TC2. Changelogs in the individual patches. Christoffer Dall (8): ARM: KVM: Allow creating the VGIC after VCPUs KVM: arm-vgic: Support KVM_CREATE_DEVICE for VGIC KVM: arm-vgic: Set base addr through device API irqchip: arm-gic: Define additional MMIO offsets and masks KVM: arm-vgic: Make vgic mmio functions more generic KVM: arm-vgic: Add vgic reg access from dev attr KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers KVM: arm-vgic: Support CPU interface reg access Documentation/virtual/kvm/api.txt |6 +- Documentation/virtual/kvm/devices/arm-vgic.txt | 71 arch/arm/include/uapi/asm/kvm.h|8 + arch/arm/kvm/arm.c | 10 +- include/kvm/arm_vgic.h |2 +- include/linux/irqchip/arm-gic.h| 14 + include/linux/kvm_host.h |1 + include/uapi/linux/kvm.h |1 + virt/kvm/arm/vgic.c| 494 ++-- virt/kvm/kvm_main.c|5 + 10 files changed, 580 insertions(+), 32 deletions(-) create mode 100644 Documentation/virtual/kvm/devices/arm-vgic.txt -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND v2 6/8] KVM: arm-vgic: Add vgic reg access from dev attr
Add infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS groups
and defining the semantics of the attr field to be the MMIO offset as
specified in the GICv2 specs.
Missing register accesses or other changes in individual register access
functions to support save/restore of the VGIC state is added in
subsequent patches.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
Changelog[v2]:
- Added implementation specific format for the GICC_APRn registers.
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 50 +
virt/kvm/arm/vgic.c| 143
2 files changed, 193 insertions(+)
diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt
b/Documentation/virtual/kvm/devices/arm-vgic.txt
index c9febb2..e6416f8e 100644
--- a/Documentation/virtual/kvm/devices/arm-vgic.txt
+++ b/Documentation/virtual/kvm/devices/arm-vgic.txt
@@ -19,3 +19,53 @@ Groups:
KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
Base address in the guest physical address space of the GIC virtual cpu
interface register mappings.
+
+ KVM_DEV_ARM_VGIC_GRP_DIST_REGS
+ Attributes:
+The attr field of kvm_device_attr encodes two values:
+bits: | 63 40 | 39 .. 32 | 31 0 |
+values: |reserved | cpu id | offset |
+
+All distributor regs are (rw, 32-bit)
+
+The offset is relative to the Distributor base address as defined in the
+GICv2 specs. Getting or setting such a register has the same effect as
+reading or writing the register on the actual hardware from the cpu
+specified with cpu id field. Note that most distributor fields are not
+banked, but return the same value regardless of the cpu id used to access
+the register.
+ Limitations:
+- Priorities are not implemented, and registers are RAZ/WI
+ Errors:
+- ENODEV: Getting or setting this register is not yet supported
+
+ KVM_DEV_ARM_VGIC_GRP_CPU_REGS
+ Attributes:
+The attr field of kvm_device_attr encodes two values:
+bits: | 63 40 | 39 .. 32 | 31 0 |
+values: |reserved | cpu id | offset |
+
+All CPU regs are (rw, 32-bit)
+
+The offset specifies the offset from the CPU interface base address as
+defined in the GICv2 specs. Getting or setting such a register has the
+same effect as reading or writing the register on the actual hardware.
+
+The Active Priorities Registers APRn are implementation defined, so we set
a
+fixed format for our implementation that fits with the model of a GICv2
+impementation without the security extensions which we present to the
+guest. This interface always exposes four register APR[0-3] describing the
+maximum possible 128 preemption levels. The semantics of the register
+indicate if any interrupts in a given preemption level are in the active
+state by setting the corresponding bit.
+
+Thus, preemption level X has one or more active interrupts if and only if:
+
+ APRn[X mod 32] == 0b1, where n = X / 32
+
+Bits for undefined preemption levels are RAZ/WI.
+
+ Limitations:
+- Priorities are not implemented, and registers are RAZ/WI
+ Errors:
+- ENODEV: Getting or setting this register is not yet supported
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 1148a2e..f2dc72a 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -589,11 +589,29 @@ static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
return false;
}
+static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
+ struct kvm_exit_mmio *mmio,
+ phys_addr_t offset)
+{
+ return false;
+}
+
+static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
+ struct kvm_exit_mmio *mmio,
+ phys_addr_t offset)
+{
+ return false;
+}
+
/*
* I would have liked to use the kvm_bus_io_*() API instead, but it
* cannot cope with banked registers (only the VM pointer is passed
* around, and we need the vcpu). One of these days, someone please
* fix it!
+ *
+ * Note that the handle_mmio implementations should not use the phys_addr
+ * field from the kvm_exit_mmio struct as this will not have any sane values
+ * when used to save/restore state from user space.
*/
struct mmio_range {
phys_addr_t base;
@@ -663,6 +681,16 @@ static const struct mmio_range vgic_dist_ranges[] = {
.len= 4,
.handle_mmio= handle_mmio_sgi_reg,
},
+ {
+ .base = GIC_DIST_SGI_CLEAR,
+ .len= VGIC_NR_SGIS,
+ .handle_mmio= handle_mmio_sgi_clear,
+ },
+ {
+
[PATCH RESEND v2 4/8] irqchip: arm-gic: Define additional MMIO offsets and masks
Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner t...@linutronix.de Signed-off-by: Christoffer Dall christoffer.d...@linaro.org Reviewed-by: Alexander Graf ag...@suse.de --- include/linux/irqchip/arm-gic.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 0e5d9ec..28b28fc 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -17,6 +17,9 @@ #define GIC_CPU_EOI0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -31,6 +34,8 @@ #define GIC_DIST_TARGET0x800 #define GIC_DIST_CONFIG0xc00 #define GIC_DIST_SOFTINT 0xf00 +#define GIC_DIST_SGI_CLEAR 0xf10 +#define GIC_DIST_SGI_SET 0xf20 #define GICH_HCR 0x0 #define GICH_VTR 0x4 @@ -54,6 +59,15 @@ #define GICH_LR_ACTIVE_BIT (1 29) #define GICH_LR_EOI(1 19) +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK(0x21f GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT27 +#define GICH_VMCR_PRIMASK_MASK (0x1f GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK(0x7 GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 GICH_VMCR_ALIAS_BINPOINT_SHIFT) + #define GICH_MISR_EOI (1 0) #define GICH_MISR_U(1 1) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND v2 7/8] KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers
Handle MMIO accesses to the two registers which should support both the
case where the VMs want to read/write either of these registers and the
case where user space reads/writes these registers to do save/restore of
the VGIC state.
Note that the added complexity compared to simple set/clear enable
registers stems from the bookkeping of source cpu ids. It may be
possible to change the underlying data structure to simplify the
complexity, but since this is not in the critical path, at all, this is
left as an interesting excercise to the reader.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
Changelog[v2]:
- Use struct kvm_exit_mmio accessors for -data field.
---
virt/kvm/arm/vgic.c | 114 ++-
1 file changed, 112 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index f2dc72a..4e8c3ab 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -589,18 +589,128 @@ static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
return false;
}
+static void read_sgi_set_clear(struct kvm_vcpu *vcpu,
+ struct kvm_exit_mmio *mmio,
+ phys_addr_t offset)
+{
+ struct vgic_dist *dist = vcpu-kvm-arch.vgic;
+ struct vgic_cpu *vgic_cpu = vcpu-arch.vgic_cpu;
+ int i, sgi, cpu;
+ int min_sgi = (offset ~0x3) * 4;
+ int max_sgi = min_sgi + 3;
+ int vcpu_id = vcpu-vcpu_id;
+ u32 lr, reg = 0;
+
+ /* Copy source SGIs from distributor side */
+ for (sgi = min_sgi; sgi = max_sgi; sgi++) {
+ int shift = 8 * (sgi - min_sgi);
+ reg |= (u32)dist-irq_sgi_sources[vcpu_id][sgi] shift;
+ }
+
+ /* Copy source SGIs already on LRs */
+ for_each_set_bit(i, vgic_cpu-lr_used, vgic_cpu-nr_lr) {
+ lr = vgic_cpu-vgic_lr[i];
+ sgi = lr GICH_LR_VIRTUALID;
+ cpu = (lr GICH_LR_PHYSID_CPUID) GICH_LR_PHYSID_CPUID_SHIFT;
+ if (sgi = min_sgi sgi = max_sgi) {
+ if (lr GICH_LR_STATE)
+ reg |= (1 cpu) (8 * (sgi - min_sgi));
+ }
+ }
+
+ mmio_data_write(mmio, ~0, reg);
+}
+
static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
struct kvm_exit_mmio *mmio,
phys_addr_t offset)
{
- return false;
+ struct vgic_dist *dist = vcpu-kvm-arch.vgic;
+ struct vgic_cpu *vgic_cpu = vcpu-arch.vgic_cpu;
+ int i, sgi, cpu;
+ int min_sgi = (offset ~0x3) * 4;
+ int max_sgi = min_sgi + 3;
+ int vcpu_id = vcpu-vcpu_id;
+ u32 *lr, reg;
+ bool updated = false;
+
+ if (!mmio-is_write) {
+ read_sgi_set_clear(vcpu, mmio, offset);
+ return false;
+ }
+
+ reg = mmio_data_read(mmio, ~0);
+
+ /* Clear pending SGIs on distributor side */
+ for (sgi = min_sgi; sgi = max_sgi; sgi++) {
+ u8 mask = reg (8 * (sgi - min_sgi));
+ if (dist-irq_sgi_sources[vcpu_id][sgi] mask)
+ updated = true;
+ dist-irq_sgi_sources[vcpu_id][sgi] = ~mask;
+ }
+
+ /* Clear SGIs already on LRs */
+ for_each_set_bit(i, vgic_cpu-lr_used, vgic_cpu-nr_lr) {
+ lr = vgic_cpu-vgic_lr[i];
+ sgi = *lr GICH_LR_VIRTUALID;
+ cpu = (*lr GICH_LR_PHYSID_CPUID)
GICH_LR_PHYSID_CPUID_SHIFT;
+
+ if (sgi = min_sgi sgi = max_sgi) {
+ if (reg ((1 cpu) (8 * (sgi - min_sgi {
+ if (*lr GICH_LR_PENDING_BIT)
+ updated = true;
+ *lr = GICH_LR_PENDING_BIT;
+ }
+ }
+ }
+
+ return updated;
}
static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
struct kvm_exit_mmio *mmio,
phys_addr_t offset)
{
- return false;
+ struct vgic_dist *dist = vcpu-kvm-arch.vgic;
+ struct vgic_cpu *vgic_cpu = vcpu-arch.vgic_cpu;
+ int i, sgi, cpu;
+ int min_sgi = (offset ~0x3) * 4;
+ int max_sgi = min_sgi + 3;
+ int vcpu_id = vcpu-vcpu_id;
+ u32 *lr, reg;
+ bool updated = false;
+
+ if (!mmio-is_write) {
+ read_sgi_set_clear(vcpu, mmio, offset);
+ return false;
+ }
+
+ reg = mmio_data_read(mmio, ~0);
+
+ /* Set pending SGIs on distributor side */
+ for (sgi = min_sgi; sgi = max_sgi; sgi++) {
+ u8 mask = reg (8 * (sgi - min_sgi));
+ if ((dist-irq_sgi_sources[vcpu_id][sgi] mask) != mask)
+ updated = true;
+ dist-irq_sgi_sources[vcpu_id][sgi] |= mask;
+ }
+
+ /* Set active
[PATCH RESEND v2 8/8] KVM: arm-vgic: Support CPU interface reg access
Implement support for the CPU interface register access driven by MMIO
address offsets from the CPU interface base address. Useful for user
space to support save/restore of the VGIC state.
This commit adds support only for the same logic as the current VGIC
support, and no more. For example, the active priority registers are
handled as RAZ/WI, just like setting priorities on the emulated
distributor.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
virt/kvm/arm/vgic.c | 81 ++-
1 file changed, 73 insertions(+), 8 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 4e8c3ab..3cfdd4d 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -71,6 +71,10 @@
#define VGIC_ADDR_UNDEF(-1)
#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
+#define PRODUCT_ID_KVM 0x4b/* ASCII code K */
+#define IMPLEMENTER_ARM0x43b
+#define GICC_ARCH_VERSION_V2 0x2
+
/* Physical address of vgic virtual cpu interface */
static phys_addr_t vgic_vcpu_base;
@@ -312,7 +316,7 @@ static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
u32 word_offset = offset 3;
switch (offset ~3) {
- case 0: /* CTLR */
+ case 0: /* GICD_CTLR */
reg = vcpu-kvm-arch.vgic.enabled;
vgic_reg_access(mmio, reg, word_offset,
ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
@@ -323,15 +327,15 @@ static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
}
break;
- case 4: /* TYPER */
+ case 4: /* GICD_TYPER */
reg = (atomic_read(vcpu-kvm-online_vcpus) - 1) 5;
reg |= (VGIC_NR_IRQS 5) - 1;
vgic_reg_access(mmio, reg, word_offset,
ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
break;
- case 8: /* IIDR */
- reg = 0x4B00043B;
+ case 8: /* GICD_IIDR */
+ reg = (PRODUCT_ID_KVM 24) | (IMPLEMENTER_ARM 0);
vgic_reg_access(mmio, reg, word_offset,
ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
break;
@@ -1682,9 +1686,70 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type,
u64 *addr, bool write)
static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
struct kvm_exit_mmio *mmio, phys_addr_t offset)
{
- return true;
+ struct vgic_cpu *vgic_cpu = vcpu-arch.vgic_cpu;
+ u32 reg, mask = 0, shift = 0;
+ bool updated = false;
+
+ switch (offset ~0x3) {
+ case GIC_CPU_CTRL:
+ mask = GICH_VMCR_CTRL_MASK;
+ shift = GICH_VMCR_CTRL_SHIFT;
+ break;
+ case GIC_CPU_PRIMASK:
+ mask = GICH_VMCR_PRIMASK_MASK;
+ shift = GICH_VMCR_PRIMASK_SHIFT;
+ break;
+ case GIC_CPU_BINPOINT:
+ mask = GICH_VMCR_BINPOINT_MASK;
+ shift = GICH_VMCR_BINPOINT_SHIFT;
+ break;
+ case GIC_CPU_ALIAS_BINPOINT:
+ mask = GICH_VMCR_ALIAS_BINPOINT_MASK;
+ shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT;
+ break;
+ }
+
+ if (!mmio-is_write) {
+ reg = (vgic_cpu-vgic_vmcr mask) shift;
+ mmio_data_write(mmio, ~0, reg);
+ } else {
+ reg = mmio_data_read(mmio, ~0);
+ reg = (reg shift) mask;
+ if (reg != (vgic_cpu-vgic_vmcr mask))
+ updated = true;
+ vgic_cpu-vgic_vmcr = ~mask;
+ vgic_cpu-vgic_vmcr |= reg;
+ }
+ return updated;
}
+static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
+struct kvm_exit_mmio *mmio, phys_addr_t offset)
+{
+ return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
+}
+
+static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
+ struct kvm_exit_mmio *mmio,
+ phys_addr_t offset)
+{
+ u32 reg;
+
+ if (mmio-is_write)
+ return false;
+
+ /* GICC_IIDR */
+ reg = (PRODUCT_ID_KVM 20) |
+ (GICC_ARCH_VERSION_V2 16) |
+ (IMPLEMENTER_ARM 0);
+ mmio_data_write(mmio, ~0, reg);
+ return false;
+}
+
+/*
+ * CPU Interface Register accesses - these are not accessed by the VM, but by
+ * user space for saving and restoring VGIC state.
+ */
static const struct mmio_range vgic_cpu_ranges[] = {
{
.base = GIC_CPU_CTRL,
@@ -1694,17 +1759,17 @@ static const struct mmio_range vgic_cpu_ranges[] = {
{
.base = GIC_CPU_ALIAS_BINPOINT,
.len= 4,
-
[PATCH RESEND v2 3/8] KVM: arm-vgic: Set base addr through device API
Support setting the distributor and cpu interface base addresses in the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition to the ARM specific API.
This has the added benefit of being able to share more code in user
space and do things in a uniform maner.
Also deprecate the older API at the same time, but backwards
compatibility will be maintained.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/api.txt |6 +-
Documentation/virtual/kvm/devices/arm-vgic.txt | 11 +++
arch/arm/include/uapi/asm/kvm.h|9 +++
arch/arm/kvm/arm.c |2 +-
include/kvm/arm_vgic.h |2 +-
virt/kvm/arm/vgic.c| 90
6 files changed, 105 insertions(+), 15 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 858aecf..d68b6c2 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2324,7 +2324,7 @@ This ioctl returns the guest registers that are supported
for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
-4.84 KVM_ARM_SET_DEVICE_ADDR
+4.84 KVM_ARM_SET_DEVICE_ADDR (deprecated)
Capability: KVM_CAP_ARM_SET_DEVICE_ADDR
Architectures: arm, arm64
@@ -2362,6 +2362,10 @@ must be called after calling KVM_CREATE_IRQCHIP, but
before calling
KVM_RUN on any of the VCPUs. Calling this ioctl twice for any of the
base addresses will return -EEXIST.
+Note, this IOCTL is deprecated and the more flexible SET/GET_DEVICE_ATTR API
+should be used instead.
+
+
4.85 KVM_PPC_RTAS_DEFINE_TOKEN
Capability: KVM_CAP_PPC_RTAS
diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt
b/Documentation/virtual/kvm/devices/arm-vgic.txt
index 38f27f7..c9febb2 100644
--- a/Documentation/virtual/kvm/devices/arm-vgic.txt
+++ b/Documentation/virtual/kvm/devices/arm-vgic.txt
@@ -8,3 +8,14 @@ Only one VGIC instance may be instantiated through either this
API or the
legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt
controller, requiring emulated user-space devices to inject interrupts to the
VGIC instead of directly to CPUs.
+
+Groups:
+ KVM_DEV_ARM_VGIC_GRP_ADDR
+ Attributes:
+KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
+ Base address in the guest physical address space of the GIC distributor
+ register mappings.
+
+KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
+ Base address in the guest physical address space of the GIC virtual cpu
+ interface register mappings.
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index 1c85102..587f1ae 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -142,6 +142,15 @@ struct kvm_arch_memory_slot {
#define KVM_REG_ARM_VFP_FPINST 0x1009
#define KVM_REG_ARM_VFP_FPINST20x100A
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
+#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
+#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL
KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT0
+#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xULL
KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index ab96af2..3ecee45 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -773,7 +773,7 @@ static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm,
case KVM_ARM_DEVICE_VGIC_V2:
if (!vgic_present)
return -ENXIO;
- return kvm_vgic_set_addr(kvm, type, dev_addr-addr);
+ return kvm_vgic_addr(kvm, type, dev_addr-addr, true);
default:
return -ENODEV;
}
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 7e2d158..be85127 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -144,7 +144,7 @@ struct kvm_run;
struct kvm_exit_mmio;
#ifdef CONFIG_KVM_ARM_VGIC
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
+int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 79a8bae..d9c0fc5 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -1479,6 +1479,12 @@ static int vgic_ioaddr_assign(struct kvm *kvm,
phys_addr_t *ioaddr,
{
int ret;
+ if (addr ~KVM_PHYS_MASK)
+ return -E2BIG;
+
+ if (addr (SZ_4K - 1))
+ return -EINVAL;
+
if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
[PATCH RESEND v2 2/8] KVM: arm-vgic: Support KVM_CREATE_DEVICE for VGIC
Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses in
a more generic API than the ARM-specific one and is useful for
save/restore of VGIC state.
Adds KVM_CAP_DEVICE_CTRL to ARM capabilities.
Note that we change the check for creating a VGIC from bailing out if
any VCPUs were created to bailing if any VCPUs were ever run. This is
an important distinction that doesn't break anything, but allows
creating the VGIC after the VCPUs have been created.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 10 ++
arch/arm/include/uapi/asm/kvm.h|1 -
arch/arm/kvm/arm.c |1 +
include/linux/kvm_host.h |1 +
include/uapi/linux/kvm.h |1 +
virt/kvm/arm/vgic.c| 46 ++--
virt/kvm/kvm_main.c|5 +++
7 files changed, 62 insertions(+), 3 deletions(-)
create mode 100644 Documentation/virtual/kvm/devices/arm-vgic.txt
diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt
b/Documentation/virtual/kvm/devices/arm-vgic.txt
new file mode 100644
index 000..38f27f7
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-vgic.txt
@@ -0,0 +1,10 @@
+ARM Virtual Generic Interrupt Controller (VGIC)
+===
+
+Device types supported:
+ KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0
+
+Only one VGIC instance may be instantiated through either this API or the
+legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt
+controller, requiring emulated user-space devices to inject interrupts to the
+VGIC instead of directly to CPUs.
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index c1ee007..1c85102 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -142,7 +142,6 @@ struct kvm_arch_memory_slot {
#define KVM_REG_ARM_VFP_FPINST 0x1009
#define KVM_REG_ARM_VFP_FPINST20x100A
-
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 2b1091a..ab96af2 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -187,6 +187,7 @@ int kvm_dev_ioctl_check_extension(long ext)
case KVM_CAP_IRQCHIP:
r = vgic_present;
break;
+ case KVM_CAP_DEVICE_CTRL:
case KVM_CAP_USER_MEMORY:
case KVM_CAP_SYNC_MMU:
case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index ca645a0..2906b79 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1065,6 +1065,7 @@ struct kvm_device *kvm_device_from_filp(struct file
*filp);
extern struct kvm_device_ops kvm_mpic_ops;
extern struct kvm_device_ops kvm_xics_ops;
+extern struct kvm_device_ops kvm_arm_vgic_ops;
#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 99c2533..2d50233 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -843,6 +843,7 @@ struct kvm_device_attr {
#define KVM_DEV_TYPE_FSL_MPIC_20 1
#define KVM_DEV_TYPE_FSL_MPIC_42 2
#define KVM_DEV_TYPE_XICS 3
+#define KVM_DEV_TYPE_ARM_VGIC_V2 4
/*
* ioctls for VM fds
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index 5ce100f..79a8bae 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -1434,15 +1434,23 @@ out:
int kvm_vgic_create(struct kvm *kvm)
{
- int ret = 0;
+ int i, ret = 0;
+ struct kvm_vcpu *vcpu;
mutex_lock(kvm-lock);
- if (atomic_read(kvm-online_vcpus) || kvm-arch.vgic.vctrl_base) {
+ if (kvm-arch.vgic.vctrl_base) {
ret = -EEXIST;
goto out;
}
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ if (vcpu-arch.has_run_once) {
+ ret = -EBUSY;
+ goto out;
+ }
+ }
+
spin_lock_init(kvm-arch.vgic.lock);
kvm-arch.vgic.vctrl_base = vgic_vctrl_base;
kvm-arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
@@ -1511,3 +1519,37 @@ int kvm_vgic_set_addr(struct kvm *kvm, unsigned long
type, u64 addr)
mutex_unlock(kvm-lock);
return r;
}
+
+static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+ return -ENXIO;
+}
+
+static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+ return -ENXIO;
+}
+
+static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+ return -ENXIO;
+}
[PATCH RESEND v2 5/8] KVM: arm-vgic: Make vgic mmio functions more generic
Rename the vgic_ranges array to vgic_dist_ranges to be more specific and
to prepare for handling CPU interface register access as well (for
save/restore of VGIC state).
Pass offset from distributor or interface MMIO base to
find_matching_range function instead of the physical address of the
access in the VM memory map. This allows other callers unaware of the
VM specifics, but with generic VGIC knowledge to reuse the function.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
Reviewed-by: Alexander Graf ag...@suse.de
---
virt/kvm/arm/vgic.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
index d9c0fc5..1148a2e 100644
--- a/virt/kvm/arm/vgic.c
+++ b/virt/kvm/arm/vgic.c
@@ -602,7 +602,7 @@ struct mmio_range {
phys_addr_t offset);
};
-static const struct mmio_range vgic_ranges[] = {
+static const struct mmio_range vgic_dist_ranges[] = {
{
.base = GIC_DIST_CTRL,
.len= 12,
@@ -669,14 +669,13 @@ static const struct mmio_range vgic_ranges[] = {
static const
struct mmio_range *find_matching_range(const struct mmio_range *ranges,
struct kvm_exit_mmio *mmio,
- phys_addr_t base)
+ phys_addr_t offset)
{
const struct mmio_range *r = ranges;
- phys_addr_t addr = mmio-phys_addr - base;
while (r-len) {
- if (addr = r-base
- (addr + mmio-len) = (r-base + r-len))
+ if (offset = r-base
+ (offset + mmio-len) = (r-base + r-len))
return r;
r++;
}
@@ -713,7 +712,8 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run
*run,
return true;
}
- range = find_matching_range(vgic_ranges, mmio, base);
+ offset = mmio-phys_addr - base;
+ range = find_matching_range(vgic_dist_ranges, mmio, offset);
if (unlikely(!range || !range-handle_mmio)) {
pr_warn(Unhandled access %d %08llx %d\n,
mmio-is_write, mmio-phys_addr, mmio-len);
--
1.7.10.4
--
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Re: [v4][PATCH] KVM: PPC: Book3E HV: call RECONCILE_IRQ_STATE to sync the software state
On Mon, 2013-10-21 at 17:57 +0800, Tiejun Chen wrote: +#ifdef CONFIG_64BIT + /* + * We enter with interrupts disabled in hardware, but + * we need to call SOFT_DISABLE_INTS anyway to ensure + * that the software state is kept in sync. + */ + RECONCILE_IRQ_STATE(r3,r5) +#endif s/SOFT_DISABLE_INTS/RECONCILE_IRQ_STATE/ in the comment. -Scott -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/11] asmlinkage, kvm: Make kvm_rebooting visible
From: Andi Kleen a...@linux.intel.com kvm_rebooting is referenced from assembler code, thus needs to be visible. Cc: g...@redhat.com Cc: pbonz...@redhat.com Cc: kvm@vger.kernel.org Signed-off-by: Andi Kleen a...@linux.intel.com --- virt/kvm/kvm_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index a9dd682..6ca3564 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -95,7 +95,7 @@ static void hardware_disable_all(void); static void kvm_io_bus_destroy(struct kvm_io_bus *bus); -bool kvm_rebooting; +__visible bool kvm_rebooting; EXPORT_SYMBOL_GPL(kvm_rebooting); static bool largepages_enabled = true; -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
CfP: Virtualisation and IaaS DevRoom at FOSDEM'14
https://groups.google.com/forum/#!forum/fosdem14-virt-and-iaas-devroom Call for Participation The scope for this devroom is open source, openly-developed projects in the areas of virtualisation and IaaS type clouds, ranging from low level to data center, up to cloud management platforms and cloud resource orchestration. Sessions should always target a developer audience. Bonus points for collaborative sessions that would be appealing to developers from multiple projects. We are particularly interested in the following themes: - low level virtualisation aspects - new features in classic and container-based virtualisation technologies - new use cases for virtualisation, such as virtualisation in mobile, automotive and embedded in general - other resource virtualisation technologies: networking, storage, … - deep technical dives into specific IaaS or virtualisation management projects features - relationship between IaaS projects and specific dependencies (not just virtualisation) - integration and development leveraging solutions from multiple projects Important dates Submission deadline: Sunday, December 1st, 2013 Acceptance notifications: Sunday, December 15th, 2013 Final schedule announcement: Friday January 10th, 2014 Devroom @ FOSDEM'14: February 1st 2nd, 2014 Practical Submissions should be 40 minutes, and consist of a 30 minute presentation with 10 minutes of QA or 40 minutes of discussions (e.g., requests for feedback, open discussions, etc.). Interactivity is encouraged, but optional. Talks are in English only. We do not provide travel assistance or reimbursement of travel expenses for accepted speakers. Submissions should be made via the FOSDEM submission page at https://penta.fosdem.org/submission/FOSDEM14 : - If necessary, create a Pentabarf account and activate it - In the “Person” section, provide First name, Last name (in the “General” tab), Email (in the “Contact” tab) and Bio (“Abstract” field in the “Description” tab) - Submit a proposal by clicking on “Create event - Important! Select the Virtualisation and IaaS track (on the “General” tab) - Provide the title of your talk (“Event title” in the “General” tab) - Provide a 250-word description of the subject of the talk and the intended audience (in the “Abstract” field of the “Description” tab) - Provide a rough outline of the talk or goals of the session (a short list of bullet points covering topics that will be discussed) in the “Full description” field in the “Description” tab Contact For questions w.r.t. the Virtualisation and IaaS DevRoom at FOSDEM'14, please contact the organizers via fosdem14-virt-and-iaas-devr...@googlegroups.com (or via https://groups.google.com/forum/#!forum/fosdem14-virt-and-iaas-devroom). -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[v5][PATCH] KVM: PPC: Book3E HV: call RECONCILE_IRQ_STATE to sync the software state
We enter with interrupts disabled in hardware, but we need to call RECONCILE_IRQ_STATE anyway to ensure that the software state is kept in sync instead of calling hard_irq_disable() directly. Signed-off-by: Tiejun Chen tiejun.c...@windriver.com --- v5: Fix one typo in the comment. v4: Fix one typo in the patch description. v3: Base on the latest tree, now we can use RECONCILE_IRQ_STATE instead of SOFT_DISABLE_INTS. v2: Move SOFT_DISABLE_INTS[1] earlier to avoid clobbering the arguments we want to pass to kvmppc_handle_exit. arch/powerpc/kvm/booke.c | 11 --- arch/powerpc/kvm/bookehv_interrupts.S | 11 +++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 15d0149..0d211ff 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -899,17 +899,6 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, int s; int idx; -#ifdef CONFIG_PPC64 - WARN_ON(local_paca-irq_happened != 0); -#endif - - /* -* We enter with interrupts disabled in hardware, but -* we need to call hard_irq_disable anyway to ensure that -* the software state is kept in sync. -*/ - hard_irq_disable(); - /* update before a new last_exit_type is rewritten */ kvmppc_update_timing_stats(vcpu); diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index e8ed7d6..191c32b 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -33,6 +33,8 @@ #ifdef CONFIG_64BIT #include asm/exception-64e.h +#include asm/hw_irq.h +#include asm/irqflags.h #else #include ../kernel/head_booke.h /* for THREAD_NORMSAVE() */ #endif @@ -465,6 +467,15 @@ _GLOBAL(kvmppc_resume_host) mtspr SPRN_EPCR, r3 isync +#ifdef CONFIG_64BIT + /* +* We enter with interrupts disabled in hardware, but +* we need to call RECONCILE_IRQ_STATE anyway to ensure +* that the software state is kept in sync. +*/ + RECONCILE_IRQ_STATE(r3,r5) +#endif + /* Switch to kernel stack and jump to handler. */ PPC_LL r3, HOST_RUN(r1) mr r5, r14 /* intno */ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [v4][PATCH] KVM: PPC: Book3E HV: call RECONCILE_IRQ_STATE to sync the software state
On Mon, 2013-10-21 at 17:57 +0800, Tiejun Chen wrote: +#ifdef CONFIG_64BIT + /* + * We enter with interrupts disabled in hardware, but + * we need to call SOFT_DISABLE_INTS anyway to ensure + * that the software state is kept in sync. + */ + RECONCILE_IRQ_STATE(r3,r5) +#endif s/SOFT_DISABLE_INTS/RECONCILE_IRQ_STATE/ in the comment. -Scott -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[v5][PATCH] KVM: PPC: Book3E HV: call RECONCILE_IRQ_STATE to sync the software state
We enter with interrupts disabled in hardware, but we need to call RECONCILE_IRQ_STATE anyway to ensure that the software state is kept in sync instead of calling hard_irq_disable() directly. Signed-off-by: Tiejun Chen tiejun.c...@windriver.com --- v5: Fix one typo in the comment. v4: Fix one typo in the patch description. v3: Base on the latest tree, now we can use RECONCILE_IRQ_STATE instead of SOFT_DISABLE_INTS. v2: Move SOFT_DISABLE_INTS[1] earlier to avoid clobbering the arguments we want to pass to kvmppc_handle_exit. arch/powerpc/kvm/booke.c | 11 --- arch/powerpc/kvm/bookehv_interrupts.S | 11 +++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 15d0149..0d211ff 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -899,17 +899,6 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, int s; int idx; -#ifdef CONFIG_PPC64 - WARN_ON(local_paca-irq_happened != 0); -#endif - - /* -* We enter with interrupts disabled in hardware, but -* we need to call hard_irq_disable anyway to ensure that -* the software state is kept in sync. -*/ - hard_irq_disable(); - /* update before a new last_exit_type is rewritten */ kvmppc_update_timing_stats(vcpu); diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index e8ed7d6..191c32b 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -33,6 +33,8 @@ #ifdef CONFIG_64BIT #include asm/exception-64e.h +#include asm/hw_irq.h +#include asm/irqflags.h #else #include ../kernel/head_booke.h /* for THREAD_NORMSAVE() */ #endif @@ -465,6 +467,15 @@ _GLOBAL(kvmppc_resume_host) mtspr SPRN_EPCR, r3 isync +#ifdef CONFIG_64BIT + /* +* We enter with interrupts disabled in hardware, but +* we need to call RECONCILE_IRQ_STATE anyway to ensure +* that the software state is kept in sync. +*/ + RECONCILE_IRQ_STATE(r3,r5) +#endif + /* Switch to kernel stack and jump to handler. */ PPC_LL r3, HOST_RUN(r1) mr r5, r14 /* intno */ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
