Re: [PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register
On 2016/1/7 18:14, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > This register resets as unknown in 64bit mode while it resets as zero
>> > in 32bit mode. Here we choose to reset it as zero for consistency.
>> >
>> > PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
>> > accessed from EL0. Add some check helpers to handle the access from EL0.
>> >
>> > When these bits are zero, only reading PMUSERENR will trap to EL2 and
>> > writing PMUSERENR or reading/writing other PMU registers will trap to
>> > EL1 other than EL2 when HCR.TGE==0. To current KVM configuration
>> > (HCR.TGE==0) there is no way to get these traps. Here we write 0xf to
>> > physical PMUSERENR register on VM entry, so that it will trap PMU access
>> > from EL0 to EL2. Within the register access handler we check the real
>> > value of guest PMUSERENR register to decide whether this access is
>> > allowed. If not allowed, forward this trap to EL1.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/include/asm/pmu.h | 9
>> > arch/arm64/kvm/hyp/switch.c | 3 ++
>> > arch/arm64/kvm/sys_regs.c| 122
>> > +--
>> > 3 files changed, 129 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
>> > index 2588f9c..1238ade 100644
>> > --- a/arch/arm64/include/asm/pmu.h
>> > +++ b/arch/arm64/include/asm/pmu.h
>> > @@ -67,4 +67,13 @@
>> > #define ARMV8_EXCLUDE_EL0 (1 << 30)
>> > #define ARMV8_INCLUDE_EL2 (1 << 27)
>> >
>> > +/*
>> > + * PMUSERENR: user enable reg
>> > + */
>> > +#define ARMV8_USERENR_MASK0xf /* Mask for writable
>> > bits */
>> > +#define ARMV8_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
>> > +#define ARMV8_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
>> > +#define ARMV8_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
>> > +#define ARMV8_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
>> > +
>> > #endif /* __ASM_PMU_H */
>> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
>> > index ca8f5a5..a85375f 100644
>> > --- a/arch/arm64/kvm/hyp/switch.c
>> > +++ b/arch/arm64/kvm/hyp/switch.c
>> > @@ -37,6 +37,8 @@ static void __hyp_text __activate_traps(struct kvm_vcpu
>> > *vcpu)
>> >/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
>> >write_sysreg(1 << 15, hstr_el2);
>> >write_sysreg(CPTR_EL2_TTA | CPTR_EL2_TFP, cptr_el2);
>> > + /* Make sure we trap PMU access from EL0 to EL2 */
>> > + write_sysreg(15, pmuserenr_el0);
> Please use the ARMV8_USERENR_* constants here instead of a magic number
> (since you went through the hassle of defining them!).
>
Ok.
>> >write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
>> > }
>> >
>> > @@ -45,6 +47,7 @@ static void __hyp_text __deactivate_traps(struct
>> > kvm_vcpu *vcpu)
>> >write_sysreg(HCR_RW, hcr_el2);
>> >write_sysreg(0, hstr_el2);
>> >write_sysreg(read_sysreg(mdcr_el2) & MDCR_EL2_HPMN_MASK, mdcr_el2);
>> > + write_sysreg(0, pmuserenr_el0);
>> >write_sysreg(0, cptr_el2);
>> > }
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index 04281f1..ac0cbf8 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -453,11 +453,47 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const
>> > struct sys_reg_desc *r)
>> >vcpu_sys_reg(vcpu, r->reg) = val;
>> > }
>> >
>> > +static inline bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
> Please drop all the inline attributes. The compiler knows its stuff well
> enough to do it automagically, and this is hardly a fast path...
>
>> > +{
>> > + u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>> > +
>> > + return !((reg & ARMV8_USERENR_EN) || vcpu_mode_priv(vcpu));
>> > +}
>> > +
>> > +static inline bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
>> > +{
>> > + u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>> > +
>> &g
Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register
On 2015/12/22 16:08, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.z...@linaro.org>
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoid taking care
> of big endian.
>
> When writing to these registers, create a perf_event for the selected
> event type.
>
> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
> ---
> arch/arm64/kvm/sys_regs.c | 156
> +-
> 1 file changed, 154 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2552db1..ed2939b 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
> sys_reg_params *p,
> return true;
> }
>
> +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
> +{
> + u64 pmcr, val;
> +
> + pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
> + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> + if (idx >= val && idx != ARMV8_CYCLE_IDX)
> + return false;
> +
> + return true;
> +}
> +
> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params
> *p,
> +const struct sys_reg_desc *r)
> +{
> + u64 idx, reg;
> +
> + if (r->CRn == 9) {
> + /* PMXEVTYPER_EL0 */
> + reg = 0;
> + } else {
> + if (!p->is_aarch32) {
> + /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
> + reg = r->reg;
> + } else {
> + if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
> + reg = PMCCFILTR_EL0;
> + } else {
> + reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> + reg += PMEVTYPER0_EL0;
> + }
> + }
> + }
> +
> + switch (reg) {
> + case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
> + idx = reg - PMEVTYPER0_EL0;
> + if (!pmu_counter_idx_valid(vcpu, idx))
> + return true;
Hi Marc,
Here should we return false to inject an UND since there is no
PMEVTYPER(idx)_EL0? The ARMv8 spec says it should.
Thanks,
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Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>> > The access handler translates all aarch32 register offsets to aarch64
>> > ones and uses vcpu_sys_reg() to access their values to avoid taking care
>> > of big endian.
>> >
>> > When writing to these registers, create a perf_event for the selected
>> > event type.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 156
>> > +-
>> > 1 file changed, 154 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index 2552db1..ed2939b 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu,
>> > struct sys_reg_params *p,
>> >return true;
>> > }
>> >
>> > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
>> > + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
>> > + if (idx >= val && idx != ARMV8_CYCLE_IDX)
>> > + return false;
>> > +
>> > + return true;
>> > +}
>> > +
>> > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct
>> > sys_reg_params *p,
>> > + const struct sys_reg_desc *r)
>> > +{
>> > + u64 idx, reg;
>> > +
>> > + if (r->CRn == 9) {
>> > + /* PMXEVTYPER_EL0 */
>> > + reg = 0;
> Is there any particular reason why you're not setting reg to PMSELR_EL0,
> since this is what you're using?
>
>> > + } else {
>> > + if (!p->is_aarch32) {
>> > + /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
>> > + reg = r->reg;
>> > + } else {
>> > + if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
>> > + reg = PMCCFILTR_EL0;
>> > + } else {
>> > + reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
>> > + reg += PMEVTYPER0_EL0;
>> > + }
>> > + }
>> > + }
>> > +
>> > + switch (reg) {
>> > + case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
>> > + idx = reg - PMEVTYPER0_EL0;
>> > + if (!pmu_counter_idx_valid(vcpu, idx))
>> > + return true;
>> > + break;
>> > + case PMCCFILTR_EL0:
>> > + idx = ARMV8_CYCLE_IDX;
>> > + break;
>> > + default:
> This would allow this case to be more precise, and we could have the
> default case as a bug handler.
>
Ah, you're right. Will fix this.
Thanks,
--
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Re: [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register
On 2016/1/7 18:43, Marc Zyngier wrote:
> On 22/12/15 08:07, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
>> > handler for PMCR.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 39 +--
>> > 1 file changed, 37 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index e8bf374..c60047e 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -34,6 +34,7 @@
>> > #include
>> > #include
>> > #include
>> > +#include
>> >
>> > #include
>> >
>> > @@ -439,6 +440,40 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const
>> > struct sys_reg_desc *r)
>> >vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>> > }
>> >
>> > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc
>> > *r)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>> > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN
>> > + * except PMCR.E resetting to zero.
>> > + */
>> > + val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad))
>> > +& (~ARMV8_PMCR_E);
>> > + vcpu_sys_reg(vcpu, r->reg) = val;
>> > +}
>> > +
>> > +static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> > + const struct sys_reg_desc *r)
>> > +{
>> > + u64 val;
>> > +
>> > + if (p->is_write) {
>> > + /* Only update writeable bits of PMCR */
>> > + val = vcpu_sys_reg(vcpu, r->reg);
>> > + val &= ~ARMV8_PMCR_MASK;
>> > + val |= p->regval & ARMV8_PMCR_MASK;
>> > + vcpu_sys_reg(vcpu, r->reg) = val;
>> > + } else {
>> > + /* PMCR.P & PMCR.C are RAZ */
>> > + val = vcpu_sys_reg(vcpu, r->reg)
>> > +& ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
>> > + p->regval = val;
>> > + }
> How can that work for 32bit, where r->reg is not populated from the trap
> table? You *know* that you are accessing PMCR, so just use PMCR_EL0 as
> an index into vcpu_sys_reg() in all cases. You can then drop PMCR_EL0
> from the 64bit trap table entry.
>
Oh, sorry for this bug. Will fix this and those in other places.
Thanks,
--
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Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>> > The access handler translates all aarch32 register offsets to aarch64
>> > ones and uses vcpu_sys_reg() to access their values to avoid taking care
>> > of big endian.
>> >
>> > When writing to these registers, create a perf_event for the selected
>> > event type.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 156
>> > +-
>> > 1 file changed, 154 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index 2552db1..ed2939b 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu,
>> > struct sys_reg_params *p,
>> >return true;
>> > }
>> >
>> > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
>> > + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
>> > + if (idx >= val && idx != ARMV8_CYCLE_IDX)
>> > + return false;
>> > +
>> > + return true;
>> > +}
>> > +
>> > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct
>> > sys_reg_params *p,
>> > + const struct sys_reg_desc *r)
>> > +{
>> > + u64 idx, reg;
>> > +
>> > + if (r->CRn == 9) {
>> > + /* PMXEVTYPER_EL0 */
>> > + reg = 0;
> Is there any particular reason why you're not setting reg to PMSELR_EL0,
> since this is what you're using?
>
>> > + } else {
>> > + if (!p->is_aarch32) {
>> > + /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
>> > + reg = r->reg;
>> > + } else {
>> > + if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
>> > + reg = PMCCFILTR_EL0;
>> > + } else {
>> > + reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
>> > + reg += PMEVTYPER0_EL0;
>> > + }
>> > + }
>> > + }
>> > +
>> > + switch (reg) {
>> > + case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
>> > + idx = reg - PMEVTYPER0_EL0;
>> > + if (!pmu_counter_idx_valid(vcpu, idx))
>> > + return true;
>> > + break;
>> > + case PMCCFILTR_EL0:
>> > + idx = ARMV8_CYCLE_IDX;
>> > + break;
>> > + default:
> This would allow this case to be more precise, and we could have the
> default case as a bug handler.
>
It turns out that I refactor this function like below:
+static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 idx, reg = 0;
+
+ if (r->CRn == 9) {
+ /* PMXEVTYPER_EL0 */
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+ reg = PMEVTYPER0_EL0 + idx;
+ } else {
+ if (r->CRm == 15 && r->Op2 == 7) {
+ idx = ARMV8_CYCLE_IDX;
+ reg = PMCCFILTR_EL0;
+ } else {
+ /* PMEVTYPERn_EL0 */
+ idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+ reg = PMEVTYPER0_EL0 + idx;
+ }
+ }
+
+ BUG_ON(reg == 0);
+
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return false;
+
+ if (p->is_write) {
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+ vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
+ }
+
+ return true;
+}
How about this?
Thanks,
--
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Re: [PATCH 1/2] arm: KVM: Do not update PC if the trap handler has updated it
On 2015/12/22 17:55, Marc Zyngier wrote:
> Assuming we trap a coprocessor access, and decide that the access
> is illegal, we will inject an exception in the guest. In this
> case, we shouldn't increment the PC, or the vcpu will miss the
> first instruction of the handler, leading to a mildly confused
> guest.
>
> Solve this by snapshoting PC before the access is performed,
> and checking if it has moved or not before incrementing it.
>
> Reported-by: Shannon Zhao <shannon.z...@linaro.org>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Shannon Zhao <shannon.z...@linaro.org>
> ---
> arch/arm/kvm/coproc.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
> index f3d88dc..f4ad2f2 100644
> --- a/arch/arm/kvm/coproc.c
> +++ b/arch/arm/kvm/coproc.c
> @@ -447,12 +447,22 @@ static int emulate_cp15(struct kvm_vcpu *vcpu,
> r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
>
> if (likely(r)) {
> + unsigned long pc = *vcpu_pc(vcpu);
> +
> /* If we don't have an accessor, we should never get here! */
> BUG_ON(!r->access);
>
> if (likely(r->access(vcpu, params, r))) {
> - /* Skip instruction, since it was emulated */
> - kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
> + /*
> + * Skip the instruction if it was emulated
> + * without PC having changed. This allows us
> + * to detect a fault being injected
> + * (incrementing the PC here would cause the
> + * vcpu to skip the first instruction of its
> + * fault handler).
> + */
> + if (pc == *vcpu_pc(vcpu))
> + kvm_skip_instr(vcpu,
> kvm_vcpu_trap_il_is32bit(vcpu));
> return 1;
> }
> /* If access function fails, it should complain. */
>
--
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Re: [PATCH 2/2] arm64: KVM: Do not update PC if the trap handler has updated it
On 2015/12/22 17:55, Marc Zyngier wrote:
> Assuming we trap a system register, and decide that the access is
> illegal, we will inject an exception in the guest. In this
> case, we shouldn't increment the PC, or the vcpu will miss the
> first instruction of the handler, leading to a mildly confused
> guest.
>
> Solve this by snapshoting PC before the access is performed,
> and checking if it has moved or not before incrementing it.
>
Thanks a lot. This solves the problem of guest PMU failing to inject EL1
fault to guest.
Tested-by: Shannon Zhao <shannon.z...@linaro.org>
Reviewed-by: Shannon Zhao <shannon.z...@linaro.org>
> Reported-by: Shannon Zhao <shannon.z...@linaro.org>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
> ---
> arch/arm64/kvm/sys_regs.c | 73
> +++
> 1 file changed, 36 insertions(+), 37 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index d2650e8..9c87e0c 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -966,6 +966,39 @@ static const struct sys_reg_desc *find_reg(const struct
> sys_reg_params *params,
> return NULL;
> }
>
> +/* Perform the sysreg access, returns 0 on success */
> +static int access_sys_reg(struct kvm_vcpu *vcpu,
> + struct sys_reg_params *params,
> + const struct sys_reg_desc *r)
> +{
> + u64 pc = *vcpu_pc(vcpu);
> +
> + if (unlikely(!r))
> + return -1;
> +
> + /*
> + * Not having an accessor means that we have configured a trap
> + * that we don't know how to handle. This certainly qualifies
> + * as a gross bug that should be fixed right away.
> + */
> + BUG_ON(!r->access);
> +
> + if (likely(r->access(vcpu, params, r))) {
> + /*
> + * Skip the instruction if it was emulated without PC
> + * having changed. This allows us to detect a fault
> + * being injected (incrementing the PC here would
> + * cause the vcpu to skip the first instruction of its
> + * fault handler).
> + */
> + if (pc == *vcpu_pc(vcpu))
> + kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
> + return 0;
> + }
> +
> + return -1;
> +}
> +
> int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
> {
> kvm_inject_undefined(vcpu);
> @@ -994,26 +1027,7 @@ static int emulate_cp(struct kvm_vcpu *vcpu,
>
> r = find_reg(params, table, num);
>
> - if (r) {
> - /*
> - * Not having an accessor means that we have
> - * configured a trap that we don't know how to
> - * handle. This certainly qualifies as a gross bug
> - * that should be fixed right away.
> - */
> - BUG_ON(!r->access);
> -
> - if (likely(r->access(vcpu, params, r))) {
> - /* Skip instruction, since it was emulated */
> - kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
> - }
> -
> - /* Handled */
> - return 0;
> - }
> -
> - /* Not handled */
> - return -1;
> + return access_sys_reg(vcpu, params, r);
> }
>
> static void unhandled_cp_access(struct kvm_vcpu *vcpu,
> @@ -1178,27 +1192,12 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu,
> if (!r)
> r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
>
> - if (likely(r)) {
> - /*
> - * Not having an accessor means that we have
> - * configured a trap that we don't know how to
> - * handle. This certainly qualifies as a gross bug
> - * that should be fixed right away.
> - */
> - BUG_ON(!r->access);
> -
> - if (likely(r->access(vcpu, params, r))) {
> - /* Skip instruction, since it was emulated */
> - kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
> - return 1;
> - }
> - /* If access function fails, it should complain. */
> - } else {
> + if (access_sys_reg(vcpu, params, r)) {
> kvm_err("Unsupported guest sys_reg access at: %lx\n",
> *vcpu_pc(vcpu));
> print_sys_reg_instr(params);
> + kvm_inject_undefined(vcpu);
> }
> - kvm_inject_undefined(vcpu);
> return 1;
> }
>
>
--
Shannon
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[PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register
From: Shannon Zhao <shannon.z...@linaro.org>
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e8bf374..c60047e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
@@ -439,6 +440,40 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
}
+static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+ u64 pmcr, val;
+
+ asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
+ /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN
+* except PMCR.E resetting to zero.
+*/
+ val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad))
+ & (~ARMV8_PMCR_E);
+ vcpu_sys_reg(vcpu, r->reg) = val;
+}
+
+static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 val;
+
+ if (p->is_write) {
+ /* Only update writeable bits of PMCR */
+ val = vcpu_sys_reg(vcpu, r->reg);
+ val &= ~ARMV8_PMCR_MASK;
+ val |= p->regval & ARMV8_PMCR_MASK;
+ vcpu_sys_reg(vcpu, r->reg) = val;
+ } else {
+ /* PMCR.P & PMCR.C are RAZ */
+ val = vcpu_sys_reg(vcpu, r->reg)
+ & ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
+ p->regval = val;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -623,7 +658,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMCR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
- trap_raz_wi },
+ access_pmcr, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
trap_raz_wi },
@@ -885,7 +920,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
/* PMU */
- { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
--
2.0.4
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[PATCH v8 15/20] KVM: ARM64: Add a helper to forward trap to guest EL1
From: Shannon Zhao <shannon.z...@linaro.org>
This helper forward the trap caused by MRS/MSR for arch64 and MCR/MRC,
MCRR/MRRC for arch32 CP15 to guest EL1.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_emulate.h | 1 +
arch/arm64/kvm/inject_fault.c| 52 +++-
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm64/include/asm/kvm_emulate.h
index 3066328..88b2958 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -36,6 +36,7 @@ unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
+void kvm_forward_trap_to_el1(struct kvm_vcpu *vcpu);
void kvm_inject_undefined(struct kvm_vcpu *vcpu);
void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index 648112e..052ef25 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -27,7 +27,10 @@
#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
PSR_I_BIT | PSR_D_BIT)
-#define EL1_EXCEPT_SYNC_OFFSET 0x200
+#define EL1_EXCEPT_BAD_SYNC_OFFSET 0x0
+#define EL1_EXCEPT_SYNC_OFFSET 0x200
+#define EL0_EXCEPT_SYNC_OFFSET_64 0x400
+#define EL0_EXCEPT_SYNC_OFFSET_32 0x600
static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
{
@@ -201,3 +204,50 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
else
inject_undef64(vcpu);
}
+
+/**
+ * kvm_forward_trap_to_el1 - forward access trap to the guest EL1
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_forward_trap_to_el1(struct kvm_vcpu *vcpu)
+{
+ unsigned long cpsr;
+ u32 esr = vcpu->arch.fault.esr_el2;
+ u32 esr_ec = (esr & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT;
+
+ if (esr_ec == ESR_ELx_EC_SYS64) {
+ u64 exc_offset;
+
+ cpsr = *vcpu_cpsr(vcpu);
+ *vcpu_spsr(vcpu) = cpsr;
+ *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+
+ *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
+
+ switch (cpsr & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
+ case PSR_MODE_EL0t:
+ exc_offset = EL0_EXCEPT_SYNC_OFFSET_64;
+ break;
+ case PSR_MODE_EL1t:
+ exc_offset = EL1_EXCEPT_BAD_SYNC_OFFSET;
+ break;
+ case PSR_MODE_EL1h:
+ exc_offset = EL1_EXCEPT_SYNC_OFFSET;
+ break;
+ default:
+ exc_offset = EL0_EXCEPT_SYNC_OFFSET_32;
+ }
+
+ *vcpu_pc(vcpu) = vcpu_sys_reg(vcpu, VBAR_EL1) + exc_offset;
+
+ if (kvm_vcpu_trap_il_is32bit(vcpu))
+ esr |= ESR_ELx_IL;
+
+ vcpu_sys_reg(vcpu, ESR_EL1) = esr;
+ } else if (esr_ec == ESR_ELx_EC_CP15_32 ||
+ esr_ec == ESR_ELx_EC_CP15_64) {
+ prepare_fault32(vcpu, COMPAT_PSR_MODE_UND, 4);
+ }
+}
--
2.0.4
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[PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register
From: Shannon Zhao <shannon.z...@linaro.org>
This register resets as unknown in 64bit mode while it resets as zero
in 32bit mode. Here we choose to reset it as zero for consistency.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from EL0.
When these bits are zero, only reading PMUSERENR will trap to EL2 and
writing PMUSERENR or reading/writing other PMU registers will trap to
EL1 other than EL2 when HCR.TGE==0. To current KVM configuration
(HCR.TGE==0) there is no way to get these traps. Here we write 0xf to
physical PMUSERENR register on VM entry, so that it will trap PMU access
from EL0 to EL2. Within the register access handler we check the real
value of guest PMUSERENR register to decide whether this access is
allowed. If not allowed, forward this trap to EL1.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/pmu.h | 9
arch/arm64/kvm/hyp/switch.c | 3 ++
arch/arm64/kvm/sys_regs.c| 122 +--
3 files changed, 129 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index 2588f9c..1238ade 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -67,4 +67,13 @@
#defineARMV8_EXCLUDE_EL0 (1 << 30)
#defineARMV8_INCLUDE_EL2 (1 << 27)
+/*
+ * PMUSERENR: user enable reg
+ */
+#define ARMV8_USERENR_MASK 0xf /* Mask for writable bits */
+#define ARMV8_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
+#define ARMV8_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
+#define ARMV8_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
+#define ARMV8_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
+
#endif /* __ASM_PMU_H */
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index ca8f5a5..a85375f 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -37,6 +37,8 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
write_sysreg(1 << 15, hstr_el2);
write_sysreg(CPTR_EL2_TTA | CPTR_EL2_TFP, cptr_el2);
+ /* Make sure we trap PMU access from EL0 to EL2 */
+ write_sysreg(15, pmuserenr_el0);
write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
}
@@ -45,6 +47,7 @@ static void __hyp_text __deactivate_traps(struct kvm_vcpu
*vcpu)
write_sysreg(HCR_RW, hcr_el2);
write_sysreg(0, hstr_el2);
write_sysreg(read_sysreg(mdcr_el2) & MDCR_EL2_HPMN_MASK, mdcr_el2);
+ write_sysreg(0, pmuserenr_el0);
write_sysreg(0, cptr_el2);
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 04281f1..ac0cbf8 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -453,11 +453,47 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, r->reg) = val;
}
+static inline bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & ARMV8_USERENR_EN) || vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & (ARMV8_USERENR_SW | ARMV8_USERENR_EN))
+|| vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & (ARMV8_USERENR_CR | ARMV8_USERENR_EN))
+|| vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & (ARMV8_USERENR_ER | ARMV8_USERENR_EN))
+|| vcpu_mode_priv(vcpu));
+}
+
static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
u64 val;
+ if (pmu_access_el0_disabled(vcpu)) {
+ kvm_forward_trap_to_el1(vcpu);
+ return true;
+ }
+
if (p->is_write) {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -478,6 +514,11 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
+ if (pmu_access_event_counter_el0_disabled(vcpu)) {
+ kvm_forward_trap_to_el1(vcpu);
+ return true;
+ }
+
if (p->is_write)
vcpu_sys_reg(vcpu, r->reg) = p->re
[PATCH v8 17/20] KVM: ARM64: Add PMU overflow interrupt routing
From: Shannon Zhao <shannon.z...@linaro.org>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
interrupt.
On VM entry, if there is counter overflowed, inject the interrupt with
the level set to 1. Otherwise, inject the interrupt with the level set
to 0.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 50 +-
3 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index dda1959..f54264c 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -577,6 +578,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct
kvm_run *run)
* non-preemptible context.
*/
preempt_disable();
+ kvm_pmu_flush_hwstate(vcpu);
kvm_timer_flush_hwstate(vcpu);
kvm_vgic_flush_hwstate(vcpu);
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 7ec7706..136f4e3 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -40,6 +40,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
@@ -59,6 +60,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index fda32cb..e28df0f 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
/**
* kvm_pmu_get_counter_value - get PMU counter value
@@ -161,6 +162,52 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
}
/**
+ * kvm_pmu_flush_hwstate - flush pmu state to cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
+ */
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ u64 overflow;
+
+ if (pmu->irq_num == -1)
+ return;
+
+ if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E))
+ return;
+
+ overflow = kvm_pmu_overflow_status(vcpu);
+ kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num, !!overflow);
+}
+
+static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
+{
+ struct kvm_pmu *pmu;
+ struct kvm_vcpu_arch *vcpu_arch;
+
+ pmc -= pmc->idx;
+ pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
+ vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
+ return container_of(vcpu_arch, struct kvm_vcpu, arch);
+}
+
+/**
+ * When perf event overflows, call kvm_pmu_overflow_set to set overflow status.
+ */
+static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+ struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
+ int idx = pmc->idx;
+
+ kvm_pmu_overflow_set(vcpu, BIT(idx));
+}
+
+/**
* kvm_pmu_software_increment - do software increment
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMSWINC register
@@ -279,7 +326,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data,
/* The initial sample period (overflow count) of an event. */
attr.sample_period = (-counter) & pmc->bitmask;
- event = perf_event_create_kernel_counter(, -1, current, NULL, pmc);
+ event = perf_event_create_kernel_counter(, -1, current,
+kvm_pmu_perf_overflow, pmc);
if (IS_ERR(event)) {
printk_once("kvm: pmu event creation failed %ld\n",
PTR_ERR(e
[PATCH v8 00/20] KVM: ARM64: Add guest PMU support
From: Shannon Zhao <shannon.z...@linaro.org>
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.
Use perf to test this patchset in guest. When using "perf list", it
shows the list of the hardware events and hardware cache events perf
supports. Then use "perf stat -e EVENT" to monitor some event. For
example, use "perf stat -e cycles" to count cpu cycles and
"perf stat -e cache-misses" to count cache misses.
Below are the outputs of "perf stat -r 5 sleep 5" when running in host
and guest.
Host:
Performance counter stats for 'sleep 5' (5 runs):
0.549456 task-clock (msec) #0.000 CPUs utilized
( +- 5.68% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
48 page-faults #0.088 M/sec
( +- 1.40% )
1146243 cycles#2.086 GHz
( +- 5.71% )
stalled-cycles-frontend
stalled-cycles-backend
627195 instructions #0.55 insns per cycle
( +- 15.65% )
branches
9826 branch-misses # 17.883 M/sec
( +- 1.10% )
5.000875516 seconds time elapsed
( +- 0.00% )
Guest:
Performance counter stats for 'sleep 5' (5 runs):
0.640712 task-clock (msec) #0.000 CPUs utilized
( +- 0.41% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
50 page-faults #0.077 M/sec
( +- 1.37% )
1320428 cycles#2.061 GHz
( +- 0.29% )
stalled-cycles-frontend
stalled-cycles-backend
642373 instructions #0.49 insns per cycle
( +- 0.46% )
branches
10399 branch-misses # 16.230 M/sec
( +- 1.57% )
5.001181020 seconds time elapsed
( +- 0.00% )
Have a cycle counter read test like below in guest and host:
static void test(void)
{
unsigned long count, count1, count2;
count1 = read_cycles();
count++;
count2 = read_cycles();
}
Host:
count1: 3049567104
count2: 3049567247
delta: 143
Guest:
count1: 5281420890
count2: 5281421068
delta: 178
The gap between guest and host is very small. One reason for this I
think is that it doesn't count the cycles in EL2 and host since we add
exclude_hv = 1. So the cycles spent to store/restore registers which
happens at EL2 are not included.
This patchset can be fetched from [1] and the relevant QEMU version for
test can be fetched from [2].
The results of 'perf test' can be found from [3][4].
The results of perf_event_tests test suite can be found from [5][6].
Also, I have tested "perf top" in two VMs and host at the same time. It
works well.
Thanks,
Shannon
[1] https://git.linaro.org/people/shannon.zhao/linux-mainline.git
KVM_ARM64_PMU_v8
[2] https://git.linaro.org/people/shannon.zhao/qemu.git virtual_PMU
[3] http://people.linaro.org/~shannon.zhao/PMU/perf-test-host.txt
[4] http://people.linaro.org/~shannon.zhao/PMU/perf-test-guest.txt
[5] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-host.txt
[6] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-guest.txt
Changes since v7:
* Rebase on kvm-arm next
* Fix the handler of PMUSERENR and add a helper to forward trap to guest
EL1
* Fix some small bugs found by Marc
Changes since v6:
* Rebase on v4.4-rc5
* Drop access_pmu_cp15_regs() so that it could use same handler for both
arch64 and arch32. And it could drop the definitions of CP15 register
offsets, also avoid same codes added twice
* Use vcpu_sys_reg() when accessing PMU registers to avoid endian things
* Add handler for PMUSERENR and some checkers for other registers
* Add kvm_arm_pmu_get_attr()
Changes since v5:
* Rebase on new linux kernel mainline
* Remove state duplications and drop PMOVSCLR, PMCNTENCLR, PMINTENCLR,
PMXEVCNTR, PMXEVTYPER
* Add a helper to check if vPMU is already initialized
* remove kvm_vcpu from kvm_pmc
Changes since v4:
* Rebase on new linux kernel mainline
* Drop the reset handler of CP15 registers
* Fix a compile failure on arch ARM due to lack of asm/pmu.h
* Refactor the interrupt injecting flow according to Marc's suggestion
* Check the value of PMSELR register
* Calculate the attr.disabled according to PMCR.E
[PATCH v8 01/20] ARM64: Move PMU register related defines to asm/pmu.h
From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/pmu.h | 67 ++ arch/arm64/kernel/perf_event.c | 36 +-- 2 files changed, 68 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/include/asm/pmu.h diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h new file mode 100644 index 000..4406184 --- /dev/null +++ b/arch/arm64/include/asm/pmu.h @@ -0,0 +1,67 @@ +/* + * PMU support + * + * Copyright (C) 2012 ARM Limited + * Author: Will Deacon <will.dea...@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __ASM_PMU_H +#define __ASM_PMU_H + +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#defineARMV8_PMCR_N_MASK 0x1f +#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#defineARMV8_CNTEN_MASK0x /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#defineARMV8_INTEN_MASK0x /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ +#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#defineARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#defineARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#defineARMV8_EXCLUDE_EL1 (1 << 31) +#defineARMV8_EXCLUDE_EL0 (1 << 30) +#defineARMV8_INCLUDE_EL2 (1 << 27) + +#endif /* __ASM_PMU_H */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 5b1897e..7eca5dc 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -24,6 +24,7 @@ #include #include #include +#include /* * ARMv8 PMUv3 Performance Events handling code. @@ -187,9 +188,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_COUNTER_LAST(cpu_pmu) \ (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#defineARMV8_MAX_COUNTERS 32 -#defineARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -200,38 +198,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#defineARMV8_PMCR_N_MASK 0x1f -#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ -#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXE
[PATCH v8 18/20] KVM: ARM64: Reset PMU state when resetting vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index f34745c..dfbce78 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -120,6 +120,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
/* Reset system registers */
kvm_reset_sys_regs(vcpu);
+ /* Reset PMU */
+ kvm_pmu_vcpu_reset(vcpu);
+
/* Reset timer */
return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 136f4e3..51dd2d1 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -37,6 +37,7 @@ struct kvm_pmu {
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
@@ -57,6 +58,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
return 0;
}
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index e28df0f..e6aac73 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -68,6 +68,23 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu,
struct kvm_pmc *pmc)
}
}
+/**
+ * kvm_pmu_vcpu_reset - reset pmu state for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ kvm_pmu_stop_counter(vcpu, >pmc[i]);
+ pmu->pmc[i].idx = i;
+ pmu->pmc[i].bitmask = 0xUL;
+ }
+}
+
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT;
--
2.0.4
--
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[PATCH v8 03/20] KVM: ARM64: Add offset defines for PMU registers
From: Shannon Zhao <shannon.z...@linaro.org>
We are about to trap and emulate accesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_host.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 6f0241f..6bab7fb 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -115,6 +115,21 @@ enum vcpu_sysreg {
MDSCR_EL1, /* Monitor Debug System Control Register */
MDCCINT_EL1,/* Monitor Debug Comms Channel Interrupt Enable Reg */
+ /* Performance Monitors Registers */
+ PMCR_EL0, /* Control Register */
+ PMOVSSET_EL0, /* Overflow Flag Status Set Register */
+ PMSELR_EL0, /* Event Counter Selection Register */
+ PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
+ PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
+ PMCCNTR_EL0,/* Cycle Counter Register */
+ PMEVTYPER0_EL0, /* Event Type Register (0-30) */
+ PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
+ PMCCFILTR_EL0, /* Cycle Count Filter Register */
+ PMCNTENSET_EL0, /* Count Enable Set Register */
+ PMINTENSET_EL1, /* Interrupt Enable Set Register */
+ PMUSERENR_EL0, /* User Enable Register */
+ PMSWINC_EL0,/* Software Increment Register */
+
/* 32bit specific registers. Keep them at the end of the range */
DACR32_EL2, /* Domain Access Control Register */
IFSR32_EL2, /* Instruction Fault Status Register */
--
2.0.4
--
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[PATCH v8 13/20] KVM: ARM64: Add access handler for PMSWINC register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 18 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 33 +
3 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d61f271dd..92021dc 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -682,6 +682,21 @@ static bool access_pmovs(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 mask;
+
+ if (p->is_write) {
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ kvm_pmu_software_increment(vcpu, p->regval & mask);
+ } else {
+ kvm_inject_undefined(vcpu);
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -892,7 +907,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmovs, NULL, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- trap_raz_wi },
+ access_pmswinc, reset_unknown, PMSWINC_EL0 },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
access_pmselr, reset_unknown, PMSELR_EL0 },
@@ -1231,6 +1246,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 244970b..67d168c 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -40,6 +40,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -57,6 +58,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index c23d57e..409f3c4 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -160,6 +160,35 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
kvm_vcpu_kick(vcpu);
}
+/**
+ * kvm_pmu_software_increment - do software increment
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMSWINC register
+ */
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
+{
+ int i;
+ u64 type, enable, reg;
+
+ if (val == 0)
+ return;
+
+ for (i = 0; i < ARMV8_CYCLE_IDX; i++) {
+ if (!(val & BIT(i)))
+ continue;
+ type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
+ & ARMV8_EVTYPE_EVENT;
+ enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+ if ((type == 0) && (enable & BIT(i))) {
+ reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
+ reg = lower_32_bits(reg);
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
+ if (!reg)
+ kvm_pmu_overflow_set(vcpu, BIT(i));
+ }
+ }
+}
+
static inline bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu,
u64 select_idx)
{
@@ -189,6 +218,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data,
kvm_pmu_stop_counter(vcpu, pmc);
eventsel = data & ARMV8_EVTYPE_EVENT;
+ /* For softw
[PATCH v8 14/20] KVM: ARM64: Add helper to handle PMCR register bits
From: Shannon Zhao <shannon.z...@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 42 ++
3 files changed, 45 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 92021dc..04281f1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -464,6 +464,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
val &= ~ARMV8_PMCR_MASK;
val |= p->regval & ARMV8_PMCR_MASK;
vcpu_sys_reg(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 67d168c..7ec7706 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -41,6 +41,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -59,6 +60,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val)
{}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 409f3c4..fda32cb 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -189,6 +189,48 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64
val)
}
}
+/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc;
+ u64 mask;
+ int i;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (val & ARMV8_PMCR_E) {
+ kvm_pmu_enable_counter(vcpu,
+vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
+ } else {
+ kvm_pmu_disable_counter(vcpu, mask);
+ }
+
+ if (val & ARMV8_PMCR_C) {
+ pmc = >pmc[ARMV8_CYCLE_IDX];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ vcpu_sys_reg(vcpu, PMCCNTR_EL0) = 0;
+ }
+
+ if (val & ARMV8_PMCR_P) {
+ for (i = 0; i < ARMV8_CYCLE_IDX; i++) {
+ pmc = >pmc[i];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = 0;
+ }
+ }
+
+ if (val & ARMV8_PMCR_LC) {
+ pmc = >pmc[ARMV8_CYCLE_IDX];
+ pmc->bitmask = 0xUL;
+ }
+}
+
static inline bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu,
u64 select_idx)
{
--
2.0.4
--
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[PATCH v8 02/20] KVM: ARM64: Define PMU data structure for each vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters.
Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/Kconfig| 7 +++
include/kvm/arm_pmu.h | 42 +++
3 files changed, 51 insertions(+)
create mode 100644 include/kvm/arm_pmu.h
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 689d4c9..6f0241f 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -36,6 +36,7 @@
#include
#include
+#include
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
@@ -211,6 +212,7 @@ struct kvm_vcpu_arch {
/* VGIC state */
struct vgic_cpu vgic_cpu;
struct arch_timer_cpu timer_cpu;
+ struct kvm_pmu pmu;
/*
* Anything that is not used directly from assembly code goes
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index a5272c0..de7450d 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -36,6 +36,7 @@ config KVM
select HAVE_KVM_EVENTFD
select HAVE_KVM_IRQFD
select KVM_ARM_VGIC_V3
+ select KVM_ARM_PMU if HW_PERF_EVENTS
---help---
Support hosting virtualized guest machines.
We don't support KVM with 16K page tables yet, due to the multiple
@@ -48,6 +49,12 @@ config KVM_ARM_HOST
---help---
Provides host support for ARM processors.
+config KVM_ARM_PMU
+ bool
+ ---help---
+ Adds support for a virtual Performance Monitoring Unit (PMU) in
+ virtual machines.
+
source drivers/vhost/Kconfig
endif # VIRTUALIZATION
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
new file mode 100644
index 000..ddcb5b2
--- /dev/null
+++ b/include/kvm/arm_pmu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARM_KVM_PMU_H
+#define __ASM_ARM_KVM_PMU_H
+
+#ifdef CONFIG_KVM_ARM_PMU
+
+#include
+#include
+
+struct kvm_pmc {
+ u8 idx;/* index into the pmu->pmc array */
+ struct perf_event *perf_event;
+ u64 bitmask;
+};
+
+struct kvm_pmu {
+ /* PMU IRQ Number per VCPU */
+ int irq_num;
+ struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
+};
+#else
+struct kvm_pmu {
+};
+#endif
+
+#endif
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[PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device
From: Shannon Zhao <shannon.z...@linaro.org>
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 24 +
arch/arm64/include/uapi/asm/kvm.h | 4 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 2 +
virt/kvm/arm/pmu.c| 128 ++
virt/kvm/kvm_main.c | 4 +
6 files changed, 163 insertions(+)
create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
b/Documentation/virtual/kvm/devices/arm-pmu.txt
new file mode 100644
index 000..dda864e
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
@@ -0,0 +1,24 @@
+ARM Virtual Performance Monitor Unit (vPMU)
+===
+
+Device types supported:
+ KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
+
+Instantiate one PMU instance for per VCPU through this API.
+
+Groups:
+ KVM_DEV_ARM_PMU_GRP_IRQ
+ Attributes:
+The attr field of kvm_device_attr encodes one value:
+bits: | 63 32 | 31 0 |
+values: | reserved | vcpu_index |
+A value describing the PMU overflow interrupt number for the specified
+vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one VM the
+interrupt type must be same for each vcpu. As a PPI, the interrupt number
is
+same for all vcpus, while as a SPI it must be different for each vcpu.
+
+ Errors:
+-ENXIO: Unsupported attribute group
+-EBUSY: The PMU overflow interrupt is already set
+-ENODEV: Getting the PMU overflow interrupt number while it's not set
+-EINVAL: Invalid vcpu_index or PMU overflow interrupt number supplied
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index 2d4ca4b..cbb9022 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -204,6 +204,10 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+/* Device Control API: ARM PMU */
+#define KVM_DEV_ARM_PMU_GRP_IRQ0
+#define KVM_DEV_ARM_PMU_CPUID_MASK 0xULL
+
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index c923350..608dea6 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
extern struct kvm_device_ops kvm_xics_ops;
extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
+extern struct kvm_device_ops kvm_arm_pmu_ops;
#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 03f3618..4ba6fdd 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1032,6 +1032,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
+ KVM_DEV_TYPE_ARM_PMU_V3,
+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
KVM_DEV_TYPE_MAX,
};
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 3ec3cdd..5518308 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -374,3 +375,130 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu
*vcpu, u64 data,
pmc->perf_event = event;
}
+
+static inline bool kvm_arm_pmu_initialized(struct kvm_vcpu *vcpu)
+{
+ return vcpu->arch.pmu.irq_num != -1;
+}
+
+static int kvm_arm_pmu_irq_access(struct kvm *kvm, struct kvm_device_attr
*attr,
+ int *irq, bool is_set)
+{
+ int cpuid;
+ struct kvm_vcpu *vcpu;
+ struct kvm_pmu *pmu;
+
+ cpuid = attr->attr & KVM_DEV_ARM_PMU_CPUID_MASK;
+ if (cpuid >= atomic_read(>online_vcpus))
+ return -EINVAL;
+
+ vcpu = kvm_get_vcpu(kvm, cpuid);
+ if (!vcpu)
+ return -EINVAL;
+
+ pmu = >arch.pmu;
+ if (!is_set) {
+ if (!kvm_arm_pmu_initialized(vcpu))
+ return -ENODEV;
+
+ *irq = pmu->irq_num;
+ } else {
+ if (kvm_arm_pmu_initialized(vcpu))
+ return -EBUSY;
+
+ kvm_debug("Set kvm ARM PMU irq: %d\n", *irq);
+ pmu->irq_num = *irq;
+ }
+
+ return 0;
+}
+
+static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type)
+{
+ int i;
+ struct
[PATCH v8 05/20] KVM: ARM64: Add access handler for PMSELR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c60047e..f9985fc 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -474,6 +474,18 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ else
+ /* return PMSELR.SEL field */
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -673,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -924,7 +936,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
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[PATCH v8 09/20] KVM: ARM64: Add access handler for event counter register
From: Shannon Zhao <shannon.z...@linaro.org>
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When reading these registers, return the sum of register value and the
value perf event counts.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 138 --
1 file changed, 134 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ed2939b..1818947 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -569,6 +569,57 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
return true;
}
+static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 idx, reg, val;
+
+ if (!p->is_aarch32) {
+ if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 2)
+ /* PMXEVCNTR_EL0 */
+ reg = 0;
+ else
+ /* PMEVCNTRn_EL0 or PMCCNTR_EL0 */
+ reg = r->reg;
+ } else {
+ if (r->CRn == 9 && r->CRm == 13) {
+ reg = (r->Op2 & 2) ? 0 : PMCCNTR_EL0;
+ } else {
+ reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+ reg += PMEVCNTR0_EL0;
+ }
+ }
+
+ switch (reg) {
+ case PMEVCNTR0_EL0 ... PMEVCNTR30_EL0:
+ idx = reg - PMEVCNTR0_EL0;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+ break;
+ case PMCCNTR_EL0:
+ idx = ARMV8_CYCLE_IDX;
+ break;
+ default:
+ /* PMXEVCNTR_EL0 */
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+
+ reg = (idx == ARMV8_CYCLE_IDX) ? PMCCNTR_EL0
+: PMEVCNTR0_EL0 + idx;
+ break;
+ }
+
+ val = kvm_pmu_get_counter_value(vcpu, idx);
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, reg) += (s64)p->regval - val;
+ else
+ p->regval = val;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -584,6 +635,13 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVCNTRn_EL0 register */
+#define PMU_PMEVCNTR_EL0(n)\
+ /* PMEVCNTRn_EL0 */ \
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
+
/* Macro to expand the PMEVTYPERn_EL0 register */
#define PMU_PMEVTYPER_EL0(n) \
/* PMEVTYPERn_EL0 */\
@@ -784,13 +842,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
- trap_raz_wi },
+ access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
access_pmu_evtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
- trap_raz_wi },
+ access_pmu_evcntr },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
trap_raz_wi },
@@ -805,6 +863,38 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVCNTRn_EL0 */
+ PMU_PMEVCNTR_EL0(0),
+ PMU_PMEVCNTR_EL0(1),
+ PMU_PMEVCNTR_EL0(2),
+ PMU_PMEVCNTR_EL0(3),
+ PMU_PMEVCNTR_EL0(4),
+ PMU_PMEVCNTR_EL0(5),
+ PMU_PMEVCNTR_EL0(6),
+ PMU_PMEVCNTR_EL0(7),
+ PMU_PMEVCNTR_EL0(8),
+ PMU_PMEVCNTR_EL0(9),
+
[PATCH v8 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f54264c..d2c2cc3 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -266,6 +266,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
kvm_vgic_vcpu_destroy(vcpu);
+ kvm_pmu_vcpu_destroy(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 51dd2d1..bd49cde 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
@@ -59,6 +60,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
return 0;
}
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index e6aac73..3ec3cdd 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -85,6 +85,27 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
}
}
+/**
+ * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ struct kvm_pmc *pmc = >pmc[i];
+
+ if (pmc->perf_event) {
+ perf_event_disable(pmc->perf_event);
+ perf_event_release_kernel(pmc->perf_event);
+ pmc->perf_event = NULL;
+ }
+ }
+}
+
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
{
u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT;
--
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[PATCH v8 12/20] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, the counter and its interrupt
is enabled, kick this vcpu to sync PMU interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 26 +++---
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 30 ++
3 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 24ce4fe..d61f271dd 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -663,6 +663,25 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+const struct sys_reg_desc *r)
+{
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ if (p->is_write) {
+ if (r->CRm & 0x2)
+ /* accessing PMOVSSET_EL0 */
+ kvm_pmu_overflow_set(vcpu, p->regval & mask);
+ else
+ /* accessing PMOVSCLR_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) &= ~(p->regval & mask);
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -870,7 +889,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmcnten, NULL, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- trap_raz_wi },
+ access_pmovs, NULL, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
trap_raz_wi },
@@ -897,7 +916,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- trap_raz_wi },
+ access_pmovs, reset_unknown, PMOVSSET_EL0 },
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -1211,7 +1230,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
- { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
@@ -1221,6 +1240,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 9d2d0c0..244970b 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,7 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx);
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -55,6 +56,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
}
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index bc64043..c23d57e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -130,6 +130,36 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64
val)
}
}
+static inline u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
+{
+ u64 reg;
+
+ reg = vcpu_sys_reg(
[PATCH v8 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
From: Shannon Zhao <shannon.z...@linaro.org>
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw event
type to create a perf_event for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/pmu.h | 3 ++
arch/arm64/kvm/Makefile | 1 +
include/kvm/arm_pmu.h| 11
virt/kvm/arm/pmu.c | 122 +++
4 files changed, 137 insertions(+)
create mode 100644 virt/kvm/arm/pmu.c
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index 4406184..2588f9c 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -21,6 +21,7 @@
#define ARMV8_MAX_COUNTERS 32
#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
+#define ARMV8_CYCLE_IDX (ARMV8_MAX_COUNTERS - 1)
/*
* Per-CPU PMCR: config reg
@@ -31,6 +32,8 @@
#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
+/* Determines which PMCCNTR_EL0 bit generates an overflow */
+#define ARMV8_PMCR_LC (1 << 6)
#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters
supported */
#defineARMV8_PMCR_N_MASK 0x1f
#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index caee9ee..122cff4 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -26,3 +26,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2-emul.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
+kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index ddcb5b2..14bedb0 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -34,9 +34,20 @@ struct kvm_pmu {
int irq_num;
struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
};
+
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
+ u64 select_idx);
#else
struct kvm_pmu {
};
+
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
+{
+ return 0;
+}
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
+ u64 select_idx) {}
#endif
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
new file mode 100644
index 000..9d27999
--- /dev/null
+++ b/virt/kvm/arm/pmu.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * kvm_pmu_get_counter_value - get PMU counter value
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ */
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
+{
+ u64 counter, reg, enabled, running;
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc = >pmc[select_idx];
+
+ reg = (select_idx == ARMV8_CYCLE_IDX)
+ ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
+ counter = vcpu_sys_reg(vcpu, reg);
+
+ /* The real counter value is equal to the value of counter register plus
+* the value perf event counts.
+*/
+ if (pmc->perf_event)
+ counter += perf_event_read_value(pmc->perf_event, ,
+);
+
+ return counter & pmc->bitmask;
+}
+
+/**
+ * kvm_pmu_stop_counter - stop PMU counter
+ * @pmc: The PMU counter pointer
+ *
+ * If this counter has been configured to monitor some event, release it here.
+ */
+static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
+{
+ u64 counter, reg;
+
+ if (pmc->perf_event) {
+ counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
+ reg = (pmc->
[PATCH v8 10/20] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 32 +---
include/kvm/arm_pmu.h | 9 +++
virt/kvm/arm/pmu.c| 63 +++
3 files changed, 100 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1818947..3416881 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -620,6 +620,30 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
return true;
}
+static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 val, mask;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (p->is_write) {
+ val = p->regval & mask;
+ if (r->Op2 & 0x1) {
+ /* accessing PMCNTENSET_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ kvm_pmu_enable_counter(vcpu, val);
+ } else {
+ /* accessing PMCNTENCLR_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ kvm_pmu_disable_counter(vcpu, val);
+ }
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -821,10 +845,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmcr, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmcnten, NULL, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -1166,8 +1190,8 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 14bedb0..9d2d0c0 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -36,6 +36,9 @@ struct kvm_pmu {
};
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
+u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -46,6 +49,12 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx)
{
return 0;
}
+u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
+{
+ return 0;
+}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9d27999..bc64043 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -67,6 +67,69 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu,
struct kvm_pmc *pmc)
}
}
+u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
+{
+ u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT;
+
+ val &= ARMV8_PMCR_N_MASK;
+ return GENMASK(val - 1, 0) | BIT(ARMV8_CYCLE_IDX);
+}
+
+/**
+ * kvm_pmu_enable_counter - enable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENSET register
+ *
+ * Call perf_event_enable to start counting the perf event
+ */
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val
[PATCH v8 11/20] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 3416881..24ce4fe 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -644,6 +644,25 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ if (p->is_write) {
+ if (r->Op2 & 0x1)
+ /* accessing PMINTENSET_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) |= (p->regval & mask);
+ else
+ /* accessing PMINTENCLR_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) &= ~(p->regval & mask);
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -802,10 +821,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMINTENSET_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
- trap_raz_wi },
+ access_pminten, reset_unknown, PMINTENSET_EL1 },
/* PMINTENCLR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
- trap_raz_wi },
+ access_pminten, NULL, PMINTENSET_EL1 },
/* MAIR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1200,8 +1219,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
--
2.0.4
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[PATCH v8 06/20] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f9985fc..2552db1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -486,6 +486,25 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (p->is_write) {
+ kvm_inject_undefined(vcpu);
+ } else {
+ if (!(p->Op2 & 1))
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ p->regval = pmceid;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -688,10 +707,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmceid },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -937,8 +956,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
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[PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register
From: Shannon Zhao <shannon.z...@linaro.org>
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When writing to these registers, create a perf_event for the selected
event type.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 156 +-
1 file changed, 154 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2552db1..ed2939b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
+{
+ u64 pmcr, val;
+
+ pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+ val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
+ if (idx >= val && idx != ARMV8_CYCLE_IDX)
+ return false;
+
+ return true;
+}
+
+static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 idx, reg;
+
+ if (r->CRn == 9) {
+ /* PMXEVTYPER_EL0 */
+ reg = 0;
+ } else {
+ if (!p->is_aarch32) {
+ /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
+ reg = r->reg;
+ } else {
+ if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
+ reg = PMCCFILTR_EL0;
+ } else {
+ reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+ reg += PMEVTYPER0_EL0;
+ }
+ }
+ }
+
+ switch (reg) {
+ case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
+ idx = reg - PMEVTYPER0_EL0;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+ break;
+ case PMCCFILTR_EL0:
+ idx = ARMV8_CYCLE_IDX;
+ break;
+ default:
+ /* PMXEVTYPER_EL0 */
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+
+ reg = (idx == ARMV8_CYCLE_IDX) ? PMCCFILTR_EL0
+: PMEVTYPER0_EL0 + idx;
+ break;
+ }
+
+ if (p->is_write) {
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+ vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -520,6 +584,13 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n) \
+ /* PMEVTYPERn_EL0 */\
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -716,7 +787,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
- trap_raz_wi },
+ access_pmu_evtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
trap_raz_wi },
@@ -734,6 +805,45 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVTYPERn_EL0 */
+ PMU_PMEVTYPER_EL0(0),
+ PMU_PMEVTYPER_EL0(1),
+ PMU_PMEVTYPER_EL0(2),
+ PMU_PMEVTYPER_EL0(3),
+ PMU_PMEVTYPER_EL0(4),
+ PMU_PMEVTYPER_EL0(5),
+ PMU_PMEVTYPER_EL0(6),
+ PMU_PMEVTYPER_EL0(7),
+ PMU_PMEVTYPER_EL0(8),
+ PMU_PMEVTYPER_EL0(
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/17 16:33, Marc Zyngier wrote: > On Thu, 17 Dec 2015 15:22:50 +0800 > Shannon Zhao <zhaoshengl...@huawei.com> wrote: > >> > >> > >> > On 2015/12/17 4:33, Christoffer Dall wrote: >>> > > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: >>>> > >> Hi, >>>> > >> >>>> > >> On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>>>> > >>>>>>>>> But in this case, you're returning an error if it is >>>>>>>>>>> > >>>>>>>>> *not* initialized. >>>>>>>>>>> > >>>>>>>>> I understand that in that case you cannot return an >>>>>>>>>>> > >>>>>>>>> interrupt number (-1 >>>>>>>>>>> > >>>>>>>>> would be weird), but returning -EBUSY feels even more >>>>>>>>>>> > >>>>>>>>> weird. >>>>>>>>>>> > >>>>>>>>> >>>>>>>>>>> > >>>>>>>>> I'd settle for -ENOXIO, or something similar. Anyone >>>>>>>>>>> > >>>>>>>>> having a better idea? >>>>>>>>>>> > >>>>>>>>> >>>>>>> > >>>>> ENXIO or ENODEV would be my choice too, and add that to the >>>>>>> > >>>>> Documentation clearly describing when this error code is used. >>>>>>> > >>>>> >>>>>>> > >>>>> By the way, why do you loop over all VCPUS to set the same >>>>>>> > >>>>> value when >>>>>>> > >>>>> you can't do anything per VCPU anyway? It seems to me it's >>>>>>> > >>>>> either a >>>>>>> > >>>>> per-VM property (that you can store on the VM data structure) >>>>>>> > >>>>> or it's a >>>>>>> > >>>>> true per-VCPU property? >>>>> > >>> This is a per-VCPU property. PMU interrupt could be PPI or SPI. For >>>>> > >>> PPI >>>>> > >>> the interrupt numbers are same for each vcpu, while for SPI they are >>>>> > >>> different, so it needs to set them separately. I planned to support >>>>> > >>> both >>>>> > >>> PPI and SPI. I think I should add support for SPI at this moment >>>>> > >>> and let >>>>> > >>> users (QEMU) to set these interrupts for each one. >>>> > >> >>>> > >> How about below vPMU Documentation? >>>> > >> >>>> > >> ARM Virtual Performance Monitor Unit (vPMU) >>>> > >> === >>>> > >> >>>> > >> Device types supported: >>>> > >> KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3 >>>> > >> >>>> > >> Instantiate one PMU instance for per VCPU through this API. >>>> > >> >>>> > >> Groups: >>>> > >> KVM_DEV_ARM_PMU_GRP_IRQ >>>> > >> Attributes: >>>> > >> The attr field of kvm_device_attr encodes two values: >>>> > >> bits: | 63 32 | 31 0 | >>>> > >> values: | vcpu_index | irq_num | >> > BTW, I change this Attribute to below format and pass vcpu_index through >> > this Attribute while pass irq_num through kvm_device_attr.addr. >> > Is it fine? >> > >> > bits: | 63 32 | 31 0 | >> > values: | reserved | vcpu_index | > Using the .addr field for something that is clearly not an address is > rather odd. Is there any prior usage of that field for something that > is not an address? I see this usage in vgic_attr_regs_access(). But if you prefer previous one, I'll use that. -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/17 17:38, Marc Zyngier wrote: > On 17/12/15 08:41, Shannon Zhao wrote: >> > >> > >> > On 2015/12/17 16:33, Marc Zyngier wrote: >>> >> On Thu, 17 Dec 2015 15:22:50 +0800 >>> >> Shannon Zhao <zhaoshengl...@huawei.com> wrote: >>> >> >>>>> >>>> >>>>> >>>> >>>>> >>>> On 2015/12/17 4:33, Christoffer Dall wrote: >>>>>>> >>>>>> On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: >>>>>>>>> >>>>>>>> Hi, >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> But in this case, you're >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> returning an error if it is >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> *not* initialized. >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> I understand that in that case >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> you cannot return an interrupt >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> number (-1 >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> would be weird), but returning >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> -EBUSY feels even more weird. >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> I'd settle for -ENOXIO, or >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> something similar. Anyone having >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> a better idea? >>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>> >>>>>>>>>>>>>> ENXIO or ENODEV would be my choice too, and add >>>>>>>>>>>>>>> >>>>>>>>>>>>>> that to the >>>>>>>>>>>>>>> >>>>>>>>>>>>>> Documentation clearly describing when this error >>>>>>>>>>>>>>> >>>>>>>>>>>>>> code is used. >>>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>>> >>>>>>>>>>>>>> By the way, why do you loop over all VCPUS to >>>>>>>>>>>>>>> >>>>>>>>>>>>>> set the same value when >>>>>>>>>>>>>>> >>>>>>>>>>>>>> you can't do anything per VCPU anyway? It seems >>>>>>>>>>>>>>> >>>>>>>>>>>>>> to me it's either a >>>>>>>>>>>>>>> >>>>>>>>>>>>>> per-VM property (that you can store on the VM >>>>>>>>>>>>>>> >>>>>>>>>>>>>> data structure) or it's a >>>>>>>>>>>>>>> >>>>>>>>>>>>>> true per-VCPU property? >>>>>>>>>>> >>>>>>>>>> This is a per-VCPU property. PMU interrupt could be PPI >>>>>>>>>>> >>>>>>>>>> or SPI. For PPI >>>>>>>>>>> >>>>>>>>>> the interrupt numbers are same for each vcpu, while for >>>>>>>>>>> >>>>>>>>>> SPI they are >>>>>>>>>>> >>>>>>>>>> different, so it needs to set them separately. I planned >>>>>>>>>>> >>>>>>>>>> to support both >>>>>>>>>>> >>>>>>>>>> PPI and SPI. I think I should add support for SPI at >>>>>>>>>>> >>>>>>>>>> this moment and let >>>>>>>>>>> >>>>>>>>>> users (QEMU) to set these interrupts for each one. >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> How about below vPMU Documentation? >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> ARM Virtual Performance Monitor Unit (vPMU) >>>>>>>>> >>>>>>>> === >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> Device types supported: >>>>>>>>> >>>>>>>> KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor >>>>>>>>> >>>>>>>> Unit v3 >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> Instantiate one PMU instance for per VCPU through this API. >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> Groups: >>>>>>>>> >>>>>>>> KVM_DEV_ARM_PMU_GRP_IRQ >>>>>>>>> >>>>>>>> Attributes: >>>>>>>>> >>>>>>>> The attr field of kvm_device_attr encodes two values: >>>>>>>>> >>>>>>>> bits: | 63 32 | 31 0 | >>>>>>>>> >>>>>>>> values: | vcpu_index | irq_num | >>>>> >>>> BTW, I change this Attribute to below format and pass vcpu_index >>>>> >>>> through >>>>> >>>> this Attribute while pass irq_num through kvm_device_attr.addr. >>>>> >>>> Is it fine? >>>>> >>>> >>>>> >>>> bits: | 63 32 | 31 0 | >>>>> >>>> values: | reserved | vcpu_index | >>> >> Using the .addr field for something that is clearly not an address is >>> >> rather odd. Is there any prior usage of that field for something that >>> >> is not an address? >> > >> > I see this usage in vgic_attr_regs_access(). But if you prefer previous >> > one, I'll use that. > Ah, you're using the .addr field to point to a userspace value, not to > carry the value itself! That'd be fine by me (even if I still prefer the > original one), but I'd like others to chime in (I'm quite bad at > defining userspace stuff...). Another reason I think is that it needs to pass the irq_num to user space when calling get_attr. It could be passed via kvm_device_attr.addr while can't be passed via kvm_device_attr.attr within current framework. Thanks, -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/17 4:33, Christoffer Dall wrote: > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: >> Hi, >> >> On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>> But in this case, you're returning an error if it is *not* >>>>>>>>> initialized. >>>>>>>>> I understand that in that case you cannot return an interrupt number >>>>>>>>> (-1 >>>>>>>>> would be weird), but returning -EBUSY feels even more weird. >>>>>>>>> >>>>>>>>> I'd settle for -ENOXIO, or something similar. Anyone having a better >>>>>>>>> idea? >>>>>>>>> >>>>> ENXIO or ENODEV would be my choice too, and add that to the >>>>> Documentation clearly describing when this error code is used. >>>>> >>>>> By the way, why do you loop over all VCPUS to set the same value when >>>>> you can't do anything per VCPU anyway? It seems to me it's either a >>>>> per-VM property (that you can store on the VM data structure) or it's a >>>>> true per-VCPU property? >>> This is a per-VCPU property. PMU interrupt could be PPI or SPI. For PPI >>> the interrupt numbers are same for each vcpu, while for SPI they are >>> different, so it needs to set them separately. I planned to support both >>> PPI and SPI. I think I should add support for SPI at this moment and let >>> users (QEMU) to set these interrupts for each one. >> >> How about below vPMU Documentation? >> >> ARM Virtual Performance Monitor Unit (vPMU) >> === >> >> Device types supported: >> KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3 >> >> Instantiate one PMU instance for per VCPU through this API. >> >> Groups: >> KVM_DEV_ARM_PMU_GRP_IRQ >> Attributes: >> The attr field of kvm_device_attr encodes two values: >> bits: | 63 32 | 31 0 | >> values: | vcpu_index | irq_num | BTW, I change this Attribute to below format and pass vcpu_index through this Attribute while pass irq_num through kvm_device_attr.addr. Is it fine? bits: | 63 32 | 31 0 | values: | reserved | vcpu_index | >> The irq_num describes the PMU overflow interrupt number for the >> specified >> vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one >> VM the >> interrupt type must be same for each vcpu. > > some formatting snafus that I expect come from pasting the text in an > e-mail client. > >> >> Errors: >> -ENXIO: Getting or setting this attribute is not yet supported > > 'not yet supported' as in something we'll implement later, or as in you > need to call this other function before you can access this state? > Since only when the group is not KVM_DEV_ARM_PMU_GRP_IRQ, it will return -ENXIO. So what about this? "-ENXIO: Unsupported attribute group" Thanks, -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/16 17:04, Marc Zyngier wrote: > On 16/12/15 08:06, Shannon Zhao wrote: >> > Hi, >> > >> > On 2015/12/16 15:31, Shannon Zhao wrote: >>>>>>>>> >>>>>>>> But in this case, you're returning an error if it is *not* >>>>>>>>> >>>>>>>> initialized. >>>>>>>>> >>>>>>>> I understand that in that case you cannot return an >>>>>>>>> >>>>>>>> interrupt number (-1 >>>>>>>>> >>>>>>>> would be weird), but returning -EBUSY feels even more weird. >>>>>>>>> >>>>>>>> >>>>>>>>> >>>>>>>> I'd settle for -ENOXIO, or something similar. Anyone having >>>>>>>>> >>>>>>>> a better idea? >>>>>>>>> >>>>>>>> >>>>> >>>> ENXIO or ENODEV would be my choice too, and add that to the >>>>> >>>> Documentation clearly describing when this error code is used. >>>>> >>>> >>>>> >>>> By the way, why do you loop over all VCPUS to set the same value when >>>>> >>>> you can't do anything per VCPU anyway? It seems to me it's either a >>>>> >>>> per-VM property (that you can store on the VM data structure) or >>>>> >>>> it's a >>>>> >>>> true per-VCPU property? >>> >> This is a per-VCPU property. PMU interrupt could be PPI or SPI. For PPI >>> >> the interrupt numbers are same for each vcpu, while for SPI they are >>> >> different, so it needs to set them separately. I planned to support both >>> >> PPI and SPI. I think I should add support for SPI at this moment and let >>> >> users (QEMU) to set these interrupts for each one. >> > >> > How about below vPMU Documentation? >> > >> > ARM Virtual Performance Monitor Unit (vPMU) >> > === >> > >> > Device types supported: >> > KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3 >> > >> > Instantiate one PMU instance for per VCPU through this API. >> > >> > Groups: >> > KVM_DEV_ARM_PMU_GRP_IRQ >> > Attributes: >> > The attr field of kvm_device_attr encodes two values: >> > bits: | 63 32 | 31 0 | >> > values: | vcpu_index | irq_num | >> > The irq_num describes the PMU overflow interrupt number for the >> > specified >> > vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one >> > VM the >> > interrupt type must be same for each vcpu. >> > >> > Errors: >> > -ENXIO: Getting or setting this attribute is not yet supported >> > -ENODEV: Getting the PMU overflow interrupt number while it's not set >> > -EBUSY: The PMU overflow interrupt is already set >> > -EINVAL: Invalid vcpu_index or irq_num supplied >> > >> > > Let's add at least one comment that forbids two vcpus from getting the > same SPI. This is too common a mistake that we see in actual SoCs, and I > don't want to see it replicated in VMs... Ok, will add. Thanks, -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
Hi, On 2015/12/16 15:31, Shannon Zhao wrote: >>>> >> > But in this case, you're returning an error if it is *not* >>>> >> > initialized. >>>> >> > I understand that in that case you cannot return an interrupt number >>>> >> > (-1 >>>> >> > would be weird), but returning -EBUSY feels even more weird. >>>> >> > >>>> >> > I'd settle for -ENOXIO, or something similar. Anyone having a better >>>> >> > idea? >>>> >> > >> > ENXIO or ENODEV would be my choice too, and add that to the >> > Documentation clearly describing when this error code is used. >> > >> > By the way, why do you loop over all VCPUS to set the same value when >> > you can't do anything per VCPU anyway? It seems to me it's either a >> > per-VM property (that you can store on the VM data structure) or it's a >> > true per-VCPU property? > This is a per-VCPU property. PMU interrupt could be PPI or SPI. For PPI > the interrupt numbers are same for each vcpu, while for SPI they are > different, so it needs to set them separately. I planned to support both > PPI and SPI. I think I should add support for SPI at this moment and let > users (QEMU) to set these interrupts for each one. How about below vPMU Documentation? ARM Virtual Performance Monitor Unit (vPMU) === Device types supported: KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3 Instantiate one PMU instance for per VCPU through this API. Groups: KVM_DEV_ARM_PMU_GRP_IRQ Attributes: The attr field of kvm_device_attr encodes two values: bits: | 63 32 | 31 0 | values: | vcpu_index | irq_num | The irq_num describes the PMU overflow interrupt number for the specified vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one VM the interrupt type must be same for each vcpu. Errors: -ENXIO: Getting or setting this attribute is not yet supported -ENODEV: Getting the PMU overflow interrupt number while it's not set -EBUSY: The PMU overflow interrupt is already set -EINVAL: Invalid vcpu_index or irq_num supplied -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 17/19] KVM: ARM64: Reset PMU state when resetting vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index f34745c..dfbce78 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -120,6 +120,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
/* Reset system registers */
kvm_reset_sys_regs(vcpu);
+ /* Reset PMU */
+ kvm_pmu_vcpu_reset(vcpu);
+
/* Reset timer */
return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 732ccaf..59cb53c 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -35,6 +35,7 @@ struct kvm_pmu {
struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
};
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
@@ -48,6 +49,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
struct kvm_pmu {
};
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
{
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index eff5b19..c62e7f5 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -76,6 +76,23 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu,
struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_vcpu_reset - reset pmu state for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ kvm_pmu_stop_counter(vcpu, >pmc[i]);
+ pmu->pmc[i].idx = i;
+ pmu->pmc[i].bitmask = 0xUL;
+ }
+}
+
+/**
* kvm_pmu_flush_hwstate - flush pmu state to cpu
* @vcpu: The vcpu pointer
*
--
2.0.4
--
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[PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing
From: Shannon Zhao <shannon.z...@linaro.org>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
interrupt.
On VM entry, if there is counter overflowed, inject the interrupt with
the level set to 1. Otherwise, inject the interrupt with the level set
to 0.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 54 ++-
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index e06fd29..cd696ef 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -569,6 +570,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct
kvm_run *run)
* non-preemptible context.
*/
preempt_disable();
+ kvm_pmu_flush_hwstate(vcpu);
kvm_timer_flush_hwstate(vcpu);
kvm_vgic_flush_hwstate(vcpu);
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 25b5f98..732ccaf 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -35,6 +35,7 @@ struct kvm_pmu {
struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
};
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
@@ -47,6 +48,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
struct kvm_pmu {
};
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
{
return 0;
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index e664721..eff5b19 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
/**
* kvm_pmu_get_counter_value - get PMU counter value
@@ -75,6 +76,56 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu,
struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_flush_hwstate - flush pmu state to cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
+ */
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ u64 overflow;
+
+ if (pmu->irq_num == -1)
+ return;
+
+ if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E))
+ return;
+
+ overflow = vcpu_sys_reg(vcpu, PMCNTENSET_EL0)
+ & vcpu_sys_reg(vcpu, PMINTENSET_EL1)
+ & vcpu_sys_reg(vcpu, PMOVSSET_EL0);
+
+ kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num,
+ overflow ? 1 : 0);
+}
+
+static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
+{
+ struct kvm_pmu *pmu;
+ struct kvm_vcpu_arch *vcpu_arch;
+
+ pmc -= pmc->idx;
+ pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
+ vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
+ return container_of(vcpu_arch, struct kvm_vcpu, arch);
+}
+
+/**
+ * When perf event overflows, call kvm_pmu_overflow_set to set overflow status.
+ */
+static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+ struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
+ int idx = pmc->idx;
+
+ kvm_pmu_overflow_set(vcpu, BIT(idx));
+}
+
+/**
* kvm_pmu_enable_counter - enable selected PMU counter
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMCNTENSET register
@@ -258,7 +309,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data,
/* The initial sample period (overflow count) of an event. */
attr.sample_period = (-counter) & pmc->bitmask;
- event = perf_event_create_kernel_counter(, -1, current, NULL, pmc);
+ event = perf_event_create_kernel_counter(, -1, current,
+kvm_pmu_perf_overflow, pmc);
if (IS_ERR(event)) {
printk_once("kvm: pmu event creation failed %ld\n",
PTR_ERR(event));
--
2.0.4
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[PATCH v7 00/19] KVM: ARM64: Add guest PMU support
From: Shannon Zhao <shannon.z...@linaro.org>
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.
Use perf to test this patchset in guest. When using "perf list", it
shows the list of the hardware events and hardware cache events perf
supports. Then use "perf stat -e EVENT" to monitor some event. For
example, use "perf stat -e cycles" to count cpu cycles and
"perf stat -e cache-misses" to count cache misses.
Below are the outputs of "perf stat -r 5 sleep 5" when running in host
and guest.
Host:
Performance counter stats for 'sleep 5' (5 runs):
0.549456 task-clock (msec) #0.000 CPUs utilized
( +- 5.68% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
48 page-faults #0.088 M/sec
( +- 1.40% )
1146243 cycles#2.086 GHz
( +- 5.71% )
stalled-cycles-frontend
stalled-cycles-backend
627195 instructions #0.55 insns per cycle
( +- 15.65% )
branches
9826 branch-misses # 17.883 M/sec
( +- 1.10% )
5.000875516 seconds time elapsed
( +- 0.00% )
Guest:
Performance counter stats for 'sleep 5' (5 runs):
0.640712 task-clock (msec) #0.000 CPUs utilized
( +- 0.41% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
50 page-faults #0.077 M/sec
( +- 1.37% )
1320428 cycles#2.061 GHz
( +- 0.29% )
stalled-cycles-frontend
stalled-cycles-backend
642373 instructions #0.49 insns per cycle
( +- 0.46% )
branches
10399 branch-misses # 16.230 M/sec
( +- 1.57% )
5.001181020 seconds time elapsed
( +- 0.00% )
Have a cycle counter read test like below in guest and host:
static void test(void)
{
unsigned long count, count1, count2;
count1 = read_cycles();
count++;
count2 = read_cycles();
}
Host:
count1: 3049567104
count2: 3049567247
delta: 143
Guest:
count1: 5281420890
count2: 5281421068
delta: 178
The gap between guest and host is very small. One reason for this I
think is that it doesn't count the cycles in EL2 and host since we add
exclude_hv = 1. So the cycles spent to store/restore registers which
happens at EL2 are not included.
This patchset can be fetched from [1] and the relevant QEMU version for
test can be fetched from [2].
The results of 'perf test' can be found from [3][4].
The results of perf_event_tests test suite can be found from [5][6].
Also, I have tested "perf top" in two VMs and host at the same time. It
works well.
Thanks,
Shannon
[1] https://git.linaro.org/people/shannon.zhao/linux-mainline.git
KVM_ARM64_PMU_v7
[2] https://git.linaro.org/people/shannon.zhao/qemu.git virtual_PMU
[3] http://people.linaro.org/~shannon.zhao/PMU/perf-test-host.txt
[4] http://people.linaro.org/~shannon.zhao/PMU/perf-test-guest.txt
[5] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-host.txt
[6] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-guest.txt
Changes since v6:
* Rebase on v4.4-rc5
* Drop access_pmu_cp15_regs() so that it could use same handler for both
arch64 and arch32. And it could drop the definitions of CP15 register
offsets
* Use vcpu_sys_reg() when accessing PMU registers to avoid endian things
* Add handler for PMUSERENR and some checkers for other registers
* Add kvm_arm_pmu_get_attr()
Changes since v5:
* Rebase on new linux kernel mainline
* Remove state duplications and drop PMOVSCLR, PMCNTENCLR, PMINTENCLR,
PMXEVCNTR, PMXEVTYPER
* Add a helper to check if vPMU is already initialized
* remove kvm_vcpu from kvm_pmc
Changes since v4:
* Rebase on new linux kernel mainline
* Drop the reset handler of CP15 registers
* Fix a compile failure on arch ARM due to lack of asm/pmu.h
* Refactor the interrupt injecting flow according to Marc's suggestion
* Check the value of PMSELR register
* Calculate the attr.disabled according to PMCR.E and PMCNTENSET/CLR
* Fix some coding style
* Document the vPMU irq range
Changes since v3:
* Rebase on new linux kernel mainline
* Use ARMV8_MAX_COUNTERS instead of 32
* Reset PMCR.E
[PATCH v7 04/19] KVM: ARM64: Add access handler for PMCR register
From: Shannon Zhao <shannon.z...@linaro.org>
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d2650e8..9a06116 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
@@ -438,6 +439,40 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
}
+static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+ u64 pmcr, val;
+
+ asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
+ /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN
+* except PMCR.E resetting to zero.
+*/
+ val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad))
+ & (~ARMV8_PMCR_E);
+ vcpu_sys_reg(vcpu, r->reg) = val;
+}
+
+static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 val;
+
+ if (p->is_write) {
+ /* Only update writeable bits of PMCR */
+ val = vcpu_sys_reg(vcpu, r->reg);
+ val &= ~ARMV8_PMCR_MASK;
+ val |= p->regval & ARMV8_PMCR_MASK;
+ vcpu_sys_reg(vcpu, r->reg) = val;
+ } else {
+ /* PMCR.P & PMCR.C are RAZ */
+ val = vcpu_sys_reg(vcpu, r->reg)
+ & ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
+ p->regval = val;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -622,7 +657,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMCR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
- trap_raz_wi },
+ access_pmcr, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
trap_raz_wi },
@@ -884,7 +919,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
/* PMU */
- { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
--
2.0.4
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[PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h
From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/pmu.h | 64 ++ arch/arm64/kernel/perf_event.c | 36 +--- 2 files changed, 65 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/include/asm/pmu.h diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h new file mode 100644 index 000..4264ea0 --- /dev/null +++ b/arch/arm64/include/asm/pmu.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2015 Linaro Ltd, Shannon Zhao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __ASM_PMU_H +#define __ASM_PMU_H + +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#defineARMV8_PMCR_N_MASK 0x1f +#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#defineARMV8_CNTEN_MASK0x /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#defineARMV8_INTEN_MASK0x /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ +#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#defineARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#defineARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#defineARMV8_EXCLUDE_EL1 (1 << 31) +#defineARMV8_EXCLUDE_EL0 (1 << 30) +#defineARMV8_INCLUDE_EL2 (1 << 27) + +#endif /* __ASM_PMU_H */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 5b1897e..7eca5dc 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -24,6 +24,7 @@ #include #include #include +#include /* * ARMv8 PMUv3 Performance Events handling code. @@ -187,9 +188,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_COUNTER_LAST(cpu_pmu) \ (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#defineARMV8_MAX_COUNTERS 32 -#defineARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -200,38 +198,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#defineARMV8_PMCR_N_MASK 0x1f -#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ -#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#defineARMV8_EVTYPE_MASK 0xc
[PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 14 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 32
3 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d1926c4..f09e500 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -690,6 +690,17 @@ static bool access_pmovsset(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ kvm_pmu_software_increment(vcpu, p->regval);
+ return true;
+ } else {
+ return read_zero(vcpu, p);
+ }
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -900,7 +911,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmovsset, NULL, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- trap_raz_wi },
+ access_pmswinc, reset_unknown, PMSWINC_EL0 },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
access_pmselr, reset_unknown, PMSELR_EL0 },
@@ -1239,6 +1250,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcntenset },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcntenset },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovsset },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 93aea6a..f5888eb 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,7 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -52,6 +53,7 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx)
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 861471d..01af727 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -150,6 +150,34 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
}
/**
+ * kvm_pmu_software_increment - do software increment
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMSWINC register
+ */
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
+{
+ int i;
+ u64 type, enable, reg;
+
+ if (val == 0)
+ return;
+
+ for (i = 0; i < ARMV8_CYCLE_IDX; i++) {
+ if (!((val >> i) & 0x1))
+ continue;
+ type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
+ & ARMV8_EVTYPE_EVENT;
+ enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+ if ((type == 0) && ((enable >> i) & 0x1)) {
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i)++;
+ reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i);
+ if ((reg & 0x) == 0)
+ kvm_pmu_overflow_set(vcpu, BIT(i));
+ }
+ }
+}
+
+/**
* kvm_pmu_set_counter_event_type - set selected counter to monitor some event
* @vcpu: The vcpu pointer
* @data: The data guest writes to PMXEVTYPER_EL0
@@ -171,6 +199,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u64 data,
kvm_pmu_stop_counter(vcpu, pmc);
eventsel = data & ARMV8_EVTYPE_EVENT;
+ /* For software increment event it does't need to create perf event */
+
[PATCH v7 18/19] KVM: ARM64: Free perf event of PMU when destroying vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index cd696ef..cea2176 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -259,6 +259,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
kvm_vgic_vcpu_destroy(vcpu);
+ kvm_pmu_vcpu_destroy(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 59cb53c..b1b63ac 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -36,6 +36,7 @@ struct kvm_pmu {
};
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
@@ -50,6 +51,7 @@ struct kvm_pmu {
};
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
{
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index c62e7f5..d113ee4 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -93,6 +93,27 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
}
/**
+ * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ struct kvm_pmc *pmc = >pmc[i];
+
+ if (pmc->perf_event) {
+ perf_event_disable(pmc->perf_event);
+ perf_event_release_kernel(pmc->perf_event);
+ pmc->perf_event = NULL;
+ }
+ }
+}
+
+/**
* kvm_pmu_flush_hwstate - flush pmu state to cpu
* @vcpu: The vcpu pointer
*
--
2.0.4
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[PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
ignored.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c21f91b..e043224 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -486,6 +486,24 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (p->is_write)
+ return write_to_read_only(vcpu, p);
+
+ if (!(p->Op2 & 1))
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ p->regval = pmceid;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -688,10 +706,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmceid },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -937,8 +955,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
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[PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f216da7..594e53f 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -648,6 +648,27 @@ static bool access_pmcntenset(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
return true;
}
+static bool access_pmintenset(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ if (p->is_write) {
+ if (r->Op2 & 0x1) {
+ /* accessing PMINTENSET_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) |= (p->regval & mask);
+ } else {
+ /* accessing PMINTENCLR_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) &= mask;
+ vcpu_sys_reg(vcpu, r->reg) &= ~p->regval;
+ }
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -806,10 +827,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMINTENSET_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
- trap_raz_wi },
+ access_pmintenset, reset_unknown, PMINTENSET_EL1 },
/* PMINTENCLR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
- trap_raz_wi },
+ access_pmintenset, NULL, PMINTENSET_EL1 },
/* MAIR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1204,8 +1225,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmintenset },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmintenset },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
--
2.0.4
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[PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 41 +++
include/kvm/arm_pmu.h | 4
virt/kvm/arm/pmu.c| 55 +++
3 files changed, 96 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index dc6bb26..f216da7 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -615,6 +615,39 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
return true;
}
+static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
+{
+ u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMCR_N_SHIFT;
+
+ val &= ARMV8_PMCR_N_MASK;
+ return GENMASK(val - 1, 0) | BIT(ARMV8_CYCLE_IDX);
+}
+
+static bool access_pmcntenset(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 val, mask;
+
+ mask = kvm_pmu_valid_counter_mask(vcpu);
+ if (p->is_write) {
+ val = p->regval & mask;
+ if (r->Op2 & 0x1) {
+ /* accessing PMCNTENSET_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ kvm_pmu_enable_counter(vcpu, val);
+ } else {
+ /* accessing PMCNTENCLR_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) &= mask;
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ kvm_pmu_disable_counter(vcpu, val);
+ }
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -816,10 +849,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmcr, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmcntenset, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmcntenset, NULL, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -1161,8 +1194,8 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcntenset },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcntenset },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 14bedb0..43c4117 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -36,6 +36,8 @@ struct kvm_pmu {
};
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -46,6 +48,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx)
{
return 0;
}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index b107fb8..94bff0e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -75,6 +75,61 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu,
struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_enable_counter - enable selected PMU counter
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCNTENSET register
+ *
+ * Call perf_event_enable to start counting the perf event
+ */
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val)
+{
+ int i;
+
[PATCH v7 03/19] KVM: ARM64: Add offset defines for PMU registers
From: Shannon Zhao <shannon.z...@linaro.org> We are about to trap and emulate accesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/kvm_asm.h | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 5e37710..1aef220 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -48,12 +48,27 @@ #define MDSCR_EL1 22 /* Monitor Debug System Control Register */ #define MDCCINT_EL123 /* Monitor Debug Comms Channel Interrupt Enable Reg */ +/* Performance Monitors Registers */ +#define PMCR_EL0 24 /* Control Register */ +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */ +#define PMSELR_EL0 26 /* Event Counter Selection Register */ +#define PMEVCNTR0_EL0 27 /* Event Counter Register (0-30) */ +#define PMEVCNTR30_EL0 57 +#define PMCCNTR_EL058 /* Cycle Counter Register */ +#define PMEVTYPER0_EL0 59 /* Event Type Register (0-30) */ +#define PMEVTYPER30_EL089 +#define PMCCFILTR_EL0 90 /* Cycle Count Filter Register */ +#define PMCNTENSET_EL0 91 /* Count Enable Set Register */ +#define PMINTENSET_EL1 92 /* Interrupt Enable Set Register */ +#define PMUSERENR_EL0 93 /* User Enable Register */ +#define PMSWINC_EL094 /* Software Increment Register */ + /* 32bit specific registers. Keep them at the end of the range */ -#defineDACR32_EL2 24 /* Domain Access Control Register */ -#defineIFSR32_EL2 25 /* Instruction Fault Status Register */ -#defineFPEXC32_EL2 26 /* Floating-Point Exception Control Register */ -#defineDBGVCR32_EL227 /* Debug Vector Catch Register */ -#defineNR_SYS_REGS 28 +#defineDACR32_EL2 95 /* Domain Access Control Register */ +#defineIFSR32_EL2 96 /* Instruction Fault Status Register */ +#defineFPEXC32_EL2 97 /* Floating-Point Exception Control Register */ +#defineDBGVCR32_EL298 /* Debug Vector Catch Register */ +#defineNR_SYS_REGS 99 /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ -- 2.0.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 28 +---
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 20
3 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 594e53f..d1926c4 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -669,6 +669,27 @@ static bool access_pmintenset(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
return true;
}
+static bool access_pmovsset(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 mask = kvm_pmu_valid_counter_mask(vcpu);
+
+ if (p->is_write) {
+ if (r->CRm & 0x2) {
+ /* accessing PMOVSSET_EL0 */
+ kvm_pmu_overflow_set(vcpu, p->regval & mask);
+ } else {
+ /* accessing PMOVSCLR_EL0 */
+ vcpu_sys_reg(vcpu, r->reg) &= mask;
+ vcpu_sys_reg(vcpu, r->reg) &= ~p->regval;
+ }
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & mask;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -876,7 +897,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmcntenset, NULL, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- trap_raz_wi },
+ access_pmovsset, NULL, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
trap_raz_wi },
@@ -903,7 +924,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- trap_raz_wi },
+ access_pmovsset, reset_unknown, PMOVSSET_EL0 },
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -1217,7 +1238,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcntenset },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcntenset },
- { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovsset },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
@@ -1227,6 +1248,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmintenset },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmintenset },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovsset },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 43c4117..93aea6a 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
#else
@@ -50,6 +51,7 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64
select_idx)
}
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 94bff0e..861471d 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -130,6 +130,26 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64
val)
}
/**
+ * kvm_pmu_overflow_set - set PMU overflow interrupt
+ * @vcpu: The vcpu pointer
+ * @val
[PATCH v7 02/19] KVM: ARM64: Define PMU data structure for each vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters.
Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/Kconfig| 7 +++
include/kvm/arm_pmu.h | 42 +++
3 files changed, 51 insertions(+)
create mode 100644 include/kvm/arm_pmu.h
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index a35ce72..42e15bb 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -37,6 +37,7 @@
#include
#include
+#include
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
@@ -132,6 +133,7 @@ struct kvm_vcpu_arch {
/* VGIC state */
struct vgic_cpu vgic_cpu;
struct arch_timer_cpu timer_cpu;
+ struct kvm_pmu pmu;
/*
* Anything that is not used directly from assembly code goes
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index a5272c0..de7450d 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -36,6 +36,7 @@ config KVM
select HAVE_KVM_EVENTFD
select HAVE_KVM_IRQFD
select KVM_ARM_VGIC_V3
+ select KVM_ARM_PMU if HW_PERF_EVENTS
---help---
Support hosting virtualized guest machines.
We don't support KVM with 16K page tables yet, due to the multiple
@@ -48,6 +49,12 @@ config KVM_ARM_HOST
---help---
Provides host support for ARM processors.
+config KVM_ARM_PMU
+ bool
+ ---help---
+ Adds support for a virtual Performance Monitoring Unit (PMU) in
+ virtual machines.
+
source drivers/vhost/Kconfig
endif # VIRTUALIZATION
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
new file mode 100644
index 000..ddcb5b2
--- /dev/null
+++ b/include/kvm/arm_pmu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARM_KVM_PMU_H
+#define __ASM_ARM_KVM_PMU_H
+
+#ifdef CONFIG_KVM_ARM_PMU
+
+#include
+#include
+
+struct kvm_pmc {
+ u8 idx;/* index into the pmu->pmc array */
+ struct perf_event *perf_event;
+ u64 bitmask;
+};
+
+struct kvm_pmu {
+ /* PMU IRQ Number per VCPU */
+ int irq_num;
+ struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
+};
+#else
+struct kvm_pmu {
+};
+#endif
+
+#endif
--
2.0.4
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[PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9a06116..c21f91b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -473,6 +473,19 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ } else {
+ /* return PMSELR.SEL field */
+ p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -672,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -923,7 +936,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
2.0.4
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[PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
From: Shannon Zhao <shannon.z...@linaro.org>
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw event
type to create a perf_event for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/pmu.h | 3 ++
arch/arm64/kvm/Makefile | 1 +
include/kvm/arm_pmu.h| 11
virt/kvm/arm/pmu.c | 122 +++
4 files changed, 137 insertions(+)
create mode 100644 virt/kvm/arm/pmu.c
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index 4264ea0..714edcc 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -18,6 +18,7 @@
#define ARMV8_MAX_COUNTERS 32
#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
+#define ARMV8_CYCLE_IDX (ARMV8_MAX_COUNTERS - 1)
/*
* Per-CPU PMCR: config reg
@@ -28,6 +29,8 @@
#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
+/* Determines which PMCCNTR_EL0 bit generates an overflow */
+#define ARMV8_PMCR_LC (1 << 6)
#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters
supported */
#defineARMV8_PMCR_N_MASK 0x1f
#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 1949fe5..18d56d8 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -27,3 +27,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
+kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index ddcb5b2..14bedb0 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -34,9 +34,20 @@ struct kvm_pmu {
int irq_num;
struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
};
+
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
+ u64 select_idx);
#else
struct kvm_pmu {
};
+
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
+{
+ return 0;
+}
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
+ u64 select_idx) {}
#endif
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
new file mode 100644
index 000..b107fb8
--- /dev/null
+++ b/virt/kvm/arm/pmu.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * kvm_pmu_get_counter_value - get PMU counter value
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ */
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
+{
+ u64 counter, reg, enabled, running;
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc = >pmc[select_idx];
+
+ reg = (select_idx == ARMV8_CYCLE_IDX)
+ ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
+ counter = vcpu_sys_reg(vcpu, reg);
+
+ /* The real counter value is equal to the value of counter register plus
+* the value perf event counts.
+*/
+ if (pmc->perf_event)
+ counter += perf_event_read_value(pmc->perf_event, ,
+);
+
+ return counter & pmc->bitmask;
+}
+
+static inline bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu,
+ u64 select_idx)
+{
+ return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &&
+ (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx));
+}
+
+/**
+ * kvm_pmu_stop_counter - stop PMU counter
+ * @pmc: The PMU counter pointer
+ *
+ * If this counter has been configured to monitor
[PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register
From: Shannon Zhao <shannon.z...@linaro.org>
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When writing to these registers, create a perf_event for the selected
event type.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 154 +-
1 file changed, 152 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e043224..c52ff15 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -504,6 +504,68 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
return true;
}
+static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
+{
+ u64 pmcr, val;
+
+ pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+ val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
+ if (idx >= val && idx != ARMV8_CYCLE_IDX)
+ return false;
+
+ return true;
+}
+
+static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 idx, reg;
+
+ if (r->CRn == 9) {
+ /* PMXEVTYPER_EL0 */
+ reg = 0;
+ } else {
+ if (!p->is_aarch32) {
+ /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
+ reg = r->reg;
+ } else {
+ if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
+ reg = PMCCFILTR_EL0;
+ } else {
+ reg = ((r->CRm & 3) << 3) & (r->Op2 & 7);
+ reg += PMEVTYPER0_EL0;
+ }
+ }
+ }
+
+ switch (reg) {
+ case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
+ idx = reg - PMEVTYPER0_EL0;
+ break;
+ case PMCCFILTR_EL0:
+ idx = ARMV8_CYCLE_IDX;
+ break;
+ default:
+ /* PMXEVTYPER_EL0 */
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+
+ reg = (idx == ARMV8_CYCLE_IDX) ? PMCCFILTR_EL0
+: PMEVTYPER0_EL0 + idx;
+ break;
+ }
+
+ if (p->is_write) {
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+ vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
+ } else {
+ p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -519,6 +581,13 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n) \
+ /* PMEVTYPERn_EL0 */\
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -715,7 +784,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
- trap_raz_wi },
+ access_pmu_evtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
trap_raz_wi },
@@ -733,6 +802,45 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVTYPERn_EL0 */
+ PMU_PMEVTYPER_EL0(0),
+ PMU_PMEVTYPER_EL0(1),
+ PMU_PMEVTYPER_EL0(2),
+ PMU_PMEVTYPER_EL0(3),
+ PMU_PMEVTYPER_EL0(4),
+ PMU_PMEVTYPER_EL0(5),
+ PMU_PMEVTYPER_EL0(6),
+ PMU_PMEVTYPER_EL0(7),
+ PMU_PMEVTYPER_EL0(8),
+ PMU_PMEVTYPER_EL0(9),
+ PMU_PMEVTYPER_EL0(10),
+ PMU_PMEVTYPER_EL0(11),
+ PMU_PMEVTYPER_E
[PATCH v7 14/19] KVM: ARM64: Add helper to handle PMCR register bits
From: Shannon Zhao <shannon.z...@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 40
3 files changed, 43 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f09e500..b2ccc25 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -463,6 +463,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
val &= ~ARMV8_PMCR_MASK;
val |= p->regval & ARMV8_PMCR_MASK;
vcpu_sys_reg(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
} else {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index f5888eb..25b5f98 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -42,6 +42,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
#else
struct kvm_pmu {
};
@@ -56,6 +57,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
u64 select_idx) {}
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
#endif
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 01af727..e664721 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -130,6 +130,46 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64
val)
}
/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc;
+ int i;
+
+ if (val & ARMV8_PMCR_E) {
+ kvm_pmu_enable_counter(vcpu,
+ vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
+ } else {
+ kvm_pmu_disable_counter(vcpu, 0xUL);
+ }
+
+ if (val & ARMV8_PMCR_C) {
+ pmc = >pmc[ARMV8_CYCLE_IDX];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ vcpu_sys_reg(vcpu, PMCCNTR_EL0) = 0;
+ }
+
+ if (val & ARMV8_PMCR_P) {
+ for (i = 0; i < ARMV8_CYCLE_IDX; i++) {
+ pmc = >pmc[i];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = 0;
+ }
+ }
+
+ if (val & ARMV8_PMCR_LC) {
+ pmc = >pmc[ARMV8_CYCLE_IDX];
+ pmc->bitmask = 0xUL;
+ }
+}
+
+/**
* kvm_pmu_overflow_set - set PMU overflow interrupt
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMOVSSET register
--
2.0.4
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[PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
From: Shannon Zhao <shannon.z...@linaro.org>
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 2 +
virt/kvm/arm/pmu.c| 115 ++
virt/kvm/kvm_main.c | 4 +
6 files changed, 141 insertions(+)
create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
b/Documentation/virtual/kvm/devices/arm-pmu.txt
new file mode 100644
index 000..5121f1f
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
@@ -0,0 +1,16 @@
+ARM Virtual Performance Monitor Unit (vPMU)
+===
+
+Device types supported:
+ KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
+
+Instantiate one PMU instance for per VCPU through this API.
+
+Groups:
+ KVM_DEV_ARM_PMU_GRP_IRQ
+ Attributes:
+A value describing the interrupt number of PMU overflow interrupt. This
+interrupt should be a PPI.
+
+ Errors:
+-EINVAL: Value set is out of the expected range (from 16 to 31)
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index 2d4ca4b..568afa2 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+/* Device Control API: ARM PMU */
+#define KVM_DEV_ARM_PMU_GRP_IRQ0
+
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index c923350..608dea6 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
extern struct kvm_device_ops kvm_xics_ops;
extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
+extern struct kvm_device_ops kvm_arm_pmu_ops;
#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 03f3618..4ba6fdd 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1032,6 +1032,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
+ KVM_DEV_TYPE_ARM_PMU_V3,
+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
KVM_DEV_TYPE_MAX,
};
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index d113ee4..1965d0d 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -357,3 +358,117 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu
*vcpu, u64 data,
pmc->perf_event = event;
}
+
+static inline bool kvm_arm_pmu_initialized(struct kvm_vcpu *vcpu)
+{
+ return vcpu->arch.pmu.irq_num != -1;
+}
+
+static int kvm_arm_pmu_irq_access(struct kvm *kvm, int *irq, bool is_set)
+{
+ int j;
+ struct kvm_vcpu *vcpu;
+
+ kvm_for_each_vcpu(j, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ if (!is_set) {
+ if (!kvm_arm_pmu_initialized(vcpu))
+ return -EBUSY;
+
+ *irq = pmu->irq_num;
+ break;
+ }
+
+ if (kvm_arm_pmu_initialized(vcpu))
+ return -EBUSY;
+
+ kvm_debug("Set kvm ARM PMU irq: %d\n", *irq);
+ pmu->irq_num = *irq;
+ }
+
+ return 0;
+}
+
+static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type)
+{
+ int i;
+ struct kvm_vcpu *vcpu;
+ struct kvm *kvm = dev->kvm;
+
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ memset(pmu, 0, sizeof(*pmu));
+ kvm_pmu_vcpu_reset(vcpu);
+ pmu->irq_num = -1;
+ }
+
+ return 0;
+}
+
+static void kvm_arm_pmu_destroy(struct kvm_device *dev)
+{
+ kfree(dev);
+}
+
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
+ struct kvm_device_attr *attr)
+{
+ switch (attr->group) {
+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
+ int __user *uaddr = (int __user *)(long)attr->addr;
+ int reg;
+
+ if (get_user(reg, uaddr))
+ return -EFAULT;
+
+ i
[PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register
From: Shannon Zhao <shannon.z...@linaro.org>
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.
When reading these registers, return the sum of register value and the
value perf event counts.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 136 --
1 file changed, 132 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c52ff15..dc6bb26 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -566,6 +566,55 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
return true;
}
+static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 idx, reg, val;
+
+ if (!p->is_aarch32) {
+ if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 2)
+ /* PMXEVCNTR_EL0 */
+ reg = 0;
+ else
+ /* PMEVCNTRn_EL0 or PMCCNTR_EL0 */
+ reg = r->reg;
+ } else {
+ if (r->CRn == 9 && r->CRm == 13) {
+ reg = (r->Op2 & 2) ? 0 : PMCCNTR_EL0;
+ } else {
+ reg = ((r->CRm & 3) << 3) & (r->Op2 & 7);
+ reg += PMEVCNTR0_EL0;
+ }
+ }
+
+ switch (reg) {
+ case PMEVCNTR0_EL0 ... PMEVCNTR30_EL0:
+ idx = reg - PMEVCNTR0_EL0;
+ break;
+ case PMCCNTR_EL0:
+ idx = ARMV8_CYCLE_IDX;
+ break;
+ default:
+ /* PMXEVCNTR_EL0 */
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+ if (!pmu_counter_idx_valid(vcpu, idx))
+ return true;
+
+ reg = (idx == ARMV8_CYCLE_IDX) ? PMCCNTR_EL0
+: PMEVCNTR0_EL0 + idx;
+ break;
+ }
+
+ val = kvm_pmu_get_counter_value(vcpu, idx);
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, reg) += (s64)p->regval - val;
+ else
+ p->regval = val;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -581,6 +630,13 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVCNTRn_EL0 register */
+#define PMU_PMEVCNTR_EL0(n)\
+ /* PMEVCNTRn_EL0 */ \
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
+
/* Macro to expand the PMEVTYPERn_EL0 register */
#define PMU_PMEVTYPER_EL0(n) \
/* PMEVTYPERn_EL0 */\
@@ -781,13 +837,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
- trap_raz_wi },
+ access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
access_pmu_evtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
- trap_raz_wi },
+ access_pmu_evcntr },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
trap_raz_wi },
@@ -802,6 +858,38 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVCNTRn_EL0 */
+ PMU_PMEVCNTR_EL0(0),
+ PMU_PMEVCNTR_EL0(1),
+ PMU_PMEVCNTR_EL0(2),
+ PMU_PMEVCNTR_EL0(3),
+ PMU_PMEVCNTR_EL0(4),
+ PMU_PMEVCNTR_EL0(5),
+ PMU_PMEVCNTR_EL0(6),
+ PMU_PMEVCNTR_EL0(7),
+ PMU_PMEVCNTR_EL0(8),
+ PMU_PMEVCNTR_EL0(9),
+ PMU_PMEVCNTR_EL0(10),
+ PMU_PMEVCNTR_EL0(11),
+ PMU_PMEVCNTR_EL0(12),
+
[PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register
From: Shannon Zhao <shannon.z...@linaro.org>
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from EL0.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 124 --
1 file changed, 119 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index b2ccc25..bad3dfd 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -452,12 +452,44 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, r->reg) = val;
}
+static inline bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & 0x1) || vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & 0x3) || vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & 0x5) || vcpu_mode_priv(vcpu));
+}
+
+static inline bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
+{
+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
+
+ return !((reg & 0x9) || vcpu_mode_priv(vcpu));
+}
+
static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
u64 val;
+ bool unaccessible = pmu_access_el0_disabled(vcpu);
if (p->is_write) {
+ if (unaccessible)
+ return ignore_write(vcpu, p);
+
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
val &= ~ARMV8_PMCR_MASK;
@@ -465,6 +497,9 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
vcpu_sys_reg(vcpu, r->reg) = val;
kvm_pmu_handle_pmcr(vcpu, val);
} else {
+ if (unaccessible)
+ return read_zero(vcpu, p);
+
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
& ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
@@ -477,9 +512,17 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
+ bool unaccessible = pmu_access_event_counter_el0_disabled(vcpu);
+
if (p->is_write) {
+ if (unaccessible)
+ return ignore_write(vcpu, p);
+
vcpu_sys_reg(vcpu, r->reg) = p->regval;
} else {
+ if (unaccessible)
+ return read_zero(vcpu, p);
+
/* return PMSELR.SEL field */
p->regval = vcpu_sys_reg(vcpu, r->reg) & ARMV8_COUNTER_MASK;
}
@@ -494,6 +537,8 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
if (p->is_write)
return write_to_read_only(vcpu, p);
+ else if (pmu_access_el0_disabled(vcpu))
+ return read_zero(vcpu, p);
if (!(p->Op2 & 1))
asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
@@ -521,6 +566,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
u64 idx, reg;
+ bool unaccessible = pmu_access_el0_disabled(vcpu);
if (r->CRn == 9) {
/* PMXEVTYPER_EL0 */
@@ -558,9 +604,15 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
}
if (p->is_write) {
+ if (unaccessible)
+ return ignore_write(vcpu, p);
+
kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
} else {
+ if (unaccessible)
+ return read_zero(vcpu, p);
+
p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
}
@@ -572,6 +624,7 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
const struct sys_reg_desc *r)
{
u64 idx, reg, val;
+ bool unaccessible = false;
if (!p->is_aarch32) {
if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 2)
@@ -591,13 +644,22 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
switch (reg) {
case PMEVCNTR0_EL0 ... PMEVCNTR30_EL0
Re: [PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h
On 2015/12/15 19:34, Marc Zyngier wrote: On 15/12/15 08:49, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/pmu.h | 64 ++ arch/arm64/kernel/perf_event.c | 36 +--- 2 files changed, 65 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/include/asm/pmu.h diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h new file mode 100644 index 000..4264ea0 --- /dev/null +++ b/arch/arm64/include/asm/pmu.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2015 Linaro Ltd, Shannon Zhao Erm, not quite. You're simply moving existing code from one file to another. That doesn't change the copyright of said code, which reads: * PMU support * * Copyright (C) 2012 ARM Limited * Author: Will Deacon <will.dea...@arm.com> Please keep this mention in place. Sure, will fix this. Thanks. -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/15 23:33, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao<shannon.z...@linaro.org>
>
>Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
>the kvm_device_ops for it.
>
>Signed-off-by: Shannon Zhao<shannon.z...@linaro.org>
>---
> Documentation/virtual/kvm/devices/arm-pmu.txt | 16
> arch/arm64/include/uapi/asm/kvm.h | 3 +
> include/linux/kvm_host.h | 1 +
> include/uapi/linux/kvm.h | 2 +
> virt/kvm/arm/pmu.c| 115
++
> virt/kvm/kvm_main.c | 4 +
> 6 files changed, 141 insertions(+)
> create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
>
>diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
b/Documentation/virtual/kvm/devices/arm-pmu.txt
>new file mode 100644
>index 000..5121f1f
>--- /dev/null
>+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
>@@ -0,0 +1,16 @@
>+ARM Virtual Performance Monitor Unit (vPMU)
>+===
>+
>+Device types supported:
>+ KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
>+
>+Instantiate one PMU instance for per VCPU through this API.
>+
>+Groups:
>+ KVM_DEV_ARM_PMU_GRP_IRQ
>+ Attributes:
>+A value describing the interrupt number of PMU overflow interrupt. This
>+interrupt should be a PPI.
>+
>+ Errors:
>+-EINVAL: Value set is out of the expected range (from 16 to 31)
>diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
>index 2d4ca4b..568afa2 100644
>--- a/arch/arm64/include/uapi/asm/kvm.h
>+++ b/arch/arm64/include/uapi/asm/kvm.h
>@@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
> #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>
>+/* Device Control API: ARM PMU */
>+#define KVM_DEV_ARM_PMU_GRP_IRQ0
>+
> /* KVM_IRQ_LINE irq field index values */
> #define KVM_ARM_IRQ_TYPE_SHIFT24
> #define KVM_ARM_IRQ_TYPE_MASK 0xff
>diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
>index c923350..608dea6 100644
>--- a/include/linux/kvm_host.h
>+++ b/include/linux/kvm_host.h
>@@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
> extern struct kvm_device_ops kvm_xics_ops;
> extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
> extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
>+extern struct kvm_device_ops kvm_arm_pmu_ops;
>
> #ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
>
>diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
>index 03f3618..4ba6fdd 100644
>--- a/include/uapi/linux/kvm.h
>+++ b/include/uapi/linux/kvm.h
>@@ -1032,6 +1032,8 @@ enum kvm_device_type {
> #define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
>KVM_DEV_TYPE_ARM_VGIC_V3,
> #define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
>+ KVM_DEV_TYPE_ARM_PMU_V3,
>+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
>KVM_DEV_TYPE_MAX,
> };
>
>diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
>index d113ee4..1965d0d 100644
>--- a/virt/kvm/arm/pmu.c
>+++ b/virt/kvm/arm/pmu.c
>@@ -19,6 +19,7 @@
> #include
> #include
> #include
>+#include
> #include
> #include
> #include
>@@ -357,3 +358,117 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu
*vcpu, u64 data,
>
>pmc->perf_event = event;
> }
>+
>+static inline bool kvm_arm_pmu_initialized(struct kvm_vcpu *vcpu)
>+{
>+ return vcpu->arch.pmu.irq_num != -1;
>+}
>+
>+static int kvm_arm_pmu_irq_access(struct kvm *kvm, int *irq, bool is_set)
>+{
>+ int j;
>+ struct kvm_vcpu *vcpu;
>+
>+ kvm_for_each_vcpu(j, vcpu, kvm) {
>+ struct kvm_pmu *pmu = >arch.pmu;
>+
>+ if (!is_set) {
>+ if (!kvm_arm_pmu_initialized(vcpu))
>+ return -EBUSY;
Returning -EBUSY is a bit odd. Maybe -EINVAL? But this seems weird
anyway. Actually, why would you return an error in this case?
While this is a unexpected operation from user space and it's already
initialized and working, so I think it should return an error to user
and tell user that it's already initialized and working (this should
mean "busy" ?).
--
Shannon
--
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Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register
On 2015/12/15 22:58, Marc Zyngier wrote:
On 15/12/15 08:49, Shannon Zhao wrote:
>From: Shannon Zhao<shannon.z...@linaro.org>
>
>The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>
>PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
>accessed from EL0. Add some check helpers to handle the access from EL0.
>
>Signed-off-by: Shannon Zhao<shannon.z...@linaro.org>
>---
> arch/arm64/kvm/sys_regs.c | 124
--
> 1 file changed, 119 insertions(+), 5 deletions(-)
>
>diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>index b2ccc25..bad3dfd 100644
>--- a/arch/arm64/kvm/sys_regs.c
>+++ b/arch/arm64/kvm/sys_regs.c
>@@ -452,12 +452,44 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
>vcpu_sys_reg(vcpu, r->reg) = val;
> }
>
>+static inline bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
>+{
>+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>+
>+ return !((reg & 0x1) || vcpu_mode_priv(vcpu));
>+}
>+
>+static inline bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
>+{
>+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>+
>+ return !((reg & 0x3) || vcpu_mode_priv(vcpu));
>+}
>+
>+static inline bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu
*vcpu)
>+{
>+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>+
>+ return !((reg & 0x5) || vcpu_mode_priv(vcpu));
>+}
>+
>+static inline bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu
*vcpu)
>+{
>+ u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
>+
>+ return !((reg & 0x9) || vcpu_mode_priv(vcpu));
>+}
Please add #defines for the PMUSERNR_EL0 bits.
>+
> static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>const struct sys_reg_desc *r)
> {
>u64 val;
>+ bool unaccessible = pmu_access_el0_disabled(vcpu);
>
>if (p->is_write) {
>+ if (unaccessible)
>+ return ignore_write(vcpu, p);
>+
This is not how this is supposed to work. If EL0 is denied access to the
PMU, you must inject an exception into EL1 for it to handle the fault.
The code should reflect the flow described at D5.11.2 in the ARM ARM.
Does it need to add a helper to inject an exception into EL1 or is there
a existing one?
Thanks,
--
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Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/16 4:47, Christoffer Dall wrote:
> On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote:
>> > On 15/12/15 15:50, Shannon Zhao wrote:
>>> > >
>>> > >
>>> > > On 2015/12/15 23:33, Marc Zyngier wrote:
>>>> > >> On 15/12/15 08:49, Shannon Zhao wrote:
>>>>>> > >>>> From: Shannon Zhao<shannon.z...@linaro.org>
>>>>>> > >>>>
>>>>>> > >>>> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU.
>>>>>> > >>>> Implement
>>>>>> > >>>> the kvm_device_ops for it.
>>>>>> > >>>>
>>>>>> > >>>> Signed-off-by: Shannon Zhao<shannon.z...@linaro.org>
>>>>>> > >>>> ---
>>>>>> > >>>> Documentation/virtual/kvm/devices/arm-pmu.txt | 16
>>>>>> > >>>> arch/arm64/include/uapi/asm/kvm.h | 3 +
>>>>>> > >>>> include/linux/kvm_host.h | 1 +
>>>>>> > >>>> include/uapi/linux/kvm.h | 2 +
>>>>>> > >>>> virt/kvm/arm/pmu.c| 115
>>>>>> > >>>> ++
>>>>>> > >>>> virt/kvm/kvm_main.c | 4 +
>>>>>> > >>>> 6 files changed, 141 insertions(+)
>>>>>> > >>>> create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
>>>>>> > >>>>
>>>>>> > >>>> diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
>>>>>> > >>>> b/Documentation/virtual/kvm/devices/arm-pmu.txt
>>>>>> > >>>> new file mode 100644
>>>>>> > >>>> index 000..5121f1f
>>>>>> > >>>> --- /dev/null
>>>>>> > >>>> +++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
>>>>>> > >>>> @@ -0,0 +1,16 @@
>>>>>> > >>>> +ARM Virtual Performance Monitor Unit (vPMU)
>>>>>> > >>>> +===
>>>>>> > >>>> +
>>>>>> > >>>> +Device types supported:
>>>>>> > >>>> + KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
>>>>>> > >>>> +
>>>>>> > >>>> +Instantiate one PMU instance for per VCPU through this API.
>>>>>> > >>>> +
>>>>>> > >>>> +Groups:
>>>>>> > >>>> + KVM_DEV_ARM_PMU_GRP_IRQ
>>>>>> > >>>> + Attributes:
>>>>>> > >>>> +A value describing the interrupt number of PMU overflow
>>>>>> > >>>> interrupt. This
>>>>>> > >>>> +interrupt should be a PPI.
>>>>>> > >>>> +
>>>>>> > >>>> + Errors:
>>>>>> > >>>> +-EINVAL: Value set is out of the expected range (from 16 to
>>>>>> > >>>> 31)
>>>>>> > >>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h
>>>>>> > >>>> b/arch/arm64/include/uapi/asm/kvm.h
>>>>>> > >>>> index 2d4ca4b..568afa2 100644
>>>>>> > >>>> --- a/arch/arm64/include/uapi/asm/kvm.h
>>>>>> > >>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
>>>>>> > >>>> @@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
>>>>>> > >>>> #define KVM_DEV_ARM_VGIC_GRP_CTRL4
>>>>>> > >>>> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>>>>>> > >>>>
>>>>>> > >>>> +/* Device Control API: ARM PMU */
>>>>>> > >>>> +#define KVM_DEV_ARM_PMU_GRP_IRQ 0
>>>>>> > >>>> +
>>>>>> > >>>> /* KVM_IRQ_LINE irq field index values */
>>>>>> > >>>> #define KVM_ARM_IRQ_TYPE_SHIFT 24
>>>>>> > >>>>
Re: [PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register
Hi Marc,
On 2015/12/9 0:30, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
>> > reset_unknown for its reset handler. Add access handler which emulates
>> > writing and reading PMEVCNTRn or PMCCNTR register. When reading
>> > PMEVCNTRn or PMCCNTR, call perf_event_read_value to get the count value
>> > of the perf event.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 107
>> > +-
>> > 1 file changed, 105 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index c116a1b..f7a73b5 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -525,6 +525,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
>> >
>> >if (p->is_write) {
>> >switch (r->reg) {
>> > + case PMEVCNTR0_EL0 ... PMCCNTR_EL0: {
> Same problem as previously mentioned.
>
>> > + val = kvm_pmu_get_counter_value(vcpu,
>> > + r->reg - PMEVCNTR0_EL0);
>> > + vcpu_sys_reg(vcpu, r->reg) += (s64)p->regval - val;
>> > + break;
>> > + }
If I use a handler to handle these accesses to PMEVCNTRn and PMCCNTR
like below. It converts the register offset c14_PMEVCNTRn and c9_PMCCNTR
to PMEVCNTRn_EL0 and PMCCNTR_EL0, uniformly uses vcpu_sys_reg and
doesn't need to take care the big endian. What do you think about this?
static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
u64 idx, reg, val;
if (p->is_aarch32)
reg = r->reg / 2;
else
reg = r->reg;
switch (reg) {
case PMEVCNTR0_EL0 ... PMEVCNTR30_EL0: {
idx = reg - PMEVCNTR0_EL0;
break;
}
case PMCCNTR_EL0: {
idx = ARMV8_CYCLE_IDX;
break;
}
default:
idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
if (!pmu_counter_idx_valid(vcpu, idx))
return true;
reg = (idx == ARMV8_CYCLE_IDX) ? PMCCNTR_EL0 :
PMEVCNTR0_EL0 + idx;
break;
}
val = kvm_pmu_get_counter_value(vcpu, idx);
if (p->is_write)
vcpu_sys_reg(vcpu, reg) = (s64)p->regval - val;
else
p->regval = val;
return true;
}
Thanks,
--
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Re: [PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register
On 2015/12/10 20:07, Marc Zyngier wrote:
> Hi Shannon,
>
> On 10/12/15 11:36, Shannon Zhao wrote:
>> > Hi Marc,
>> >
>> > On 2015/12/9 0:30, Marc Zyngier wrote:
>>> >> On 08/12/15 12:47, Shannon Zhao wrote:
>>>>> >>>> From: Shannon Zhao <shannon.z...@linaro.org>
>>>>> >>>>
>>>>> >>>> Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
>>>>> >>>> reset_unknown for its reset handler. Add access handler which
>>>>> >>>> emulates
>>>>> >>>> writing and reading PMEVCNTRn or PMCCNTR register. When reading
>>>>> >>>> PMEVCNTRn or PMCCNTR, call perf_event_read_value to get the count
>>>>> >>>> value
>>>>> >>>> of the perf event.
>>>>> >>>>
>>>>> >>>> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>>>>> >>>> ---
>>>>> >>>> arch/arm64/kvm/sys_regs.c | 107
>>>>> >>>> +-
>>>>> >>>> 1 file changed, 105 insertions(+), 2 deletions(-)
>>>>> >>>>
>>>>> >>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>>>> >>>> index c116a1b..f7a73b5 100644
>>>>> >>>> --- a/arch/arm64/kvm/sys_regs.c
>>>>> >>>> +++ b/arch/arm64/kvm/sys_regs.c
>>>>> >>>> @@ -525,6 +525,12 @@ static bool access_pmu_regs(struct kvm_vcpu
>>>>> >>>> *vcpu,
>>>>> >>>>
>>>>> >>>> if (p->is_write) {
>>>>> >>>> switch (r->reg) {
>>>>> >>>> +case PMEVCNTR0_EL0 ... PMCCNTR_EL0: {
>>> >> Same problem as previously mentioned.
>>> >>
>>>>> >>>> +val = kvm_pmu_get_counter_value(vcpu,
>>>>> >>>> +r->reg -
>>>>> >>>> PMEVCNTR0_EL0);
>>>>> >>>> +vcpu_sys_reg(vcpu, r->reg) += (s64)p->regval -
>>>>> >>>> val;
>>>>> >>>> +break;
>>>>> >>>> +}
>> >
>> > If I use a handler to handle these accesses to PMEVCNTRn and PMCCNTR
>> > like below. It converts the register offset c14_PMEVCNTRn and c9_PMCCNTR
>> > to PMEVCNTRn_EL0 and PMCCNTR_EL0, uniformly uses vcpu_sys_reg and
>> > doesn't need to take care the big endian. What do you think about this?
>> >
>> > static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
>> > struct sys_reg_params *p,
>> > const struct sys_reg_desc *r)
>> > {
>> > u64 idx, reg, val;
>> >
>> > if (p->is_aarch32)
>> > reg = r->reg / 2;
> I'd prefer it if you actually decoded the reg itself. Something like:
>
> if (p->is_aarch32) {
> if (r->CRn == 9 && r->CRm == 13)
> reg = (r->Op2 & 1) ? 0 : PMCCNTR_EL0;
> if (r->CRn == 14 && (r->CRm & 0xc) == 8) {
> reg = ((r->CRm & 3) << 2) & (r->Op2 & 7);
> reg += PMEVCNTR0_EL0;
> } else {
> BUG();
> }
> } else {
>
> }
>
> And then you can get rid of the c14_PMVCNTR* and c9_PMCCNTR macros.
> The only slightly ugly thing is this 0 value to represent PMXEVTYPER,
> but that's what we already have with your "default" clause below.
>
Ok, thanks.
>> > else
>> > reg = r->reg;
>> >
>> > switch (reg) {
>> > case PMEVCNTR0_EL0 ... PMEVCNTR30_EL0: {
>> > idx = reg - PMEVCNTR0_EL0;
>> > break;
>> > }
>> > case PMCCNTR_EL0: {
>> > idx = ARMV8_CYCLE_IDX;
>> > break;
>> > }
>> > default:
>> > idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
>> > if (!pmu_counter_idx_valid(vcpu, idx))
>> > return true;
>> > reg = (idx == ARMV8_CYCLE_IDX) ? PMCCNTR_EL0 :
>> > PMEVCNTR0_EL0 + idx;
>> > break;
>> > }
>> >
>> > val = kvm_pmu_get_counter_value(vcpu, idx);
>> > if (p->is_write)
>> > vcpu_sys_reg(vcpu, reg) = (s64)p->regval - val;
> Maybe I don't have my head screwed in the right way, but as long as
> we're only using u64 quantities, why do we need this s64 cast?
>
In case p->regval less than val.
For example, at the first time it writes 0x8001 to
vcpu_sys_reg(vcpu, reg) and start a perf event which counts a value
1. Then we want to start the same perf event with writing 0x8001
to vcpu_sys_reg(vcpu, reg) too. At this time, p->regval(0x8001) is
less than val(0x8001 + 1).
Thanks,
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Re: [PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register
On 2015/12/9 0:42, Marc Zyngier wrote:
>> +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable)
>> > +{
>> > + int i;
>> > + struct kvm_pmu *pmu = >arch.pmu;
>> > + struct kvm_pmc *pmc;
>> > +
>> > + if (!all_enable)
>> > + return;
> You have the vcpu. Can you move the check for PMCR_EL0.E here instead of
> having it in both of the callers?
>
But it still needs to check PMCR_EL0.E in kvm_pmu_handle_pmcr(). When
PMCR_EL0.E == 1, it calls kvm_pmu_enable_counter(), otherwise it calls
kvm_pmu_disable_counter(). So as it checks already, just pass the result
as a parameter.
>> > +
>> > + for_each_set_bit(i, (const unsigned long *), ARMV8_MAX_COUNTERS) {
> Nonononono... If you must have to use a long, use a long. Don't cast it
> to a different type (hint: big endian).
>
>> > + pmc = >pmc[i];
>> > + if (pmc->perf_event) {
>> > + perf_event_enable(pmc->perf_event);
>> > + if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
>> > + kvm_debug("fail to enable perf event\n");
>> > + }
>> > + }
>> > +}
>> > +
>> > +/**
>> > + * kvm_pmu_disable_counter - disable selected PMU counter
>> > + * @vcpu: The vcpu pointer
>> > + * @val: the value guest writes to PMCNTENCLR register
>> > + *
>> > + * Call perf_event_disable to stop counting the perf event
>> > + */
>> > +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val)
>> > +{
>> > + int i;
>> > + struct kvm_pmu *pmu = >arch.pmu;
>> > + struct kvm_pmc *pmc;
>> > +
> Why are enable and disable asymmetric (handling of PMCR.E)?
>
To enable a counter, it needs both the PMCR_EL0.E and the corresponding
bit of PMCNTENSET_EL0 set to 1. But to disable a counter, it only needs
one of them and when PMCR_EL0.E == 0， it disables all the counters.
Thanks,
--
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Re: [PATCH v6 14/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register
On 2015/12/9 0:59, Marc Zyngier wrote: >> > + } >> > + >> > + /* If all overflow bits are cleared, kick the vcpu to clear interrupt >> > + * pending status. >> > + */ >> > + if (val == 0) >> > + kvm_vcpu_kick(vcpu); > Do we really need to do so? This will be dropped on the next entry > anyway, so i don't see the need to kick the vcpu again. Or am I missing > something? > I thought maybe it could not set the interrupt low immediately when all the overflow bits are cleared for some reason, so add a kick to force it to sync the interrupt. But as you said, I'll remove this. Thanks, -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 15/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register
On 2015/12/9 1:03, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.z...@linaro.org>
>> >
>> > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 5 +++--
>> > 1 file changed, 3 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index c830fde..80b66c0 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -880,7 +880,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>> > access_pmu_pmxevcntr },
>> >/* PMUSERENR_EL0 */
>> >{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
>> > -trap_raz_wi },
>> > +access_pmu_regs, reset_unknown, PMUSERENR_EL0 },
> So while the 64bit view of the register resets as unknown, a CPU
> resetting in 32bit mode resets as 0. I suggest you reset it as zero, and
> document that choice. You may have to revisit all the other registers
> that do reset as unknown for 64bit as well.
>
Sure.
BTW, here I didn't handle the bits of PMUSERENR which are used to
permit/forbid accessing some PMU registers from EL0. Does it need to add
the handler? Is there any way to get the exceptional level of the
accessing in hypervisor?
Thanks,
--
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Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers
Hi Marc, On 2015/12/7 22:55, Marc Zyngier wrote: > On 07/12/15 14:31, Shannon Zhao wrote: >> > >> > >> > On 2015/12/7 22:06, Marc Zyngier wrote: >>> >> On 03/12/15 06:11, Shannon Zhao wrote: >>>> >>> From: Shannon Zhao <shannon.z...@linaro.org> >>>> >>> >>>> >>> We are about to trap and emulate acccesses to each PMU register >>> >> >>> >> s/acccesses/accesses/ >>> >> >>>> >>> individually. This adds the context offsets for the AArch64 PMU >>>> >>> registers and their AArch32 counterparts. >>>> >>> >>>> >>> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> >>>> >>> --- >>>> >>> arch/arm64/include/asm/kvm_asm.h | 55 >>>> >>> >>>> >>> 1 file changed, 50 insertions(+), 5 deletions(-) >>>> >>> >>>> >>> diff --git a/arch/arm64/include/asm/kvm_asm.h >>>> >>> b/arch/arm64/include/asm/kvm_asm.h >>>> >>> index 5e37710..4f804c1 100644 >>>> >>> --- a/arch/arm64/include/asm/kvm_asm.h >>>> >>> +++ b/arch/arm64/include/asm/kvm_asm.h >>>> >>> @@ -48,12 +48,34 @@ >>>> >>> #define MDSCR_EL122 /* Monitor Debug System Control >>>> >>> Register */ >>>> >>> #define MDCCINT_EL1 23 /* Monitor Debug Comms Channel >>>> >>> Interrupt Enable Reg */ >>>> >>> >>> >> >>> >> Coming back to this patch, it gives a clear view of where you have state >>> >> duplication. >>> >> >>>> >>> +/* Performance Monitors Registers */ >>>> >>> +#define PMCR_EL0 24 /* Control Register */ >>>> >>> +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */ >>>> >>> +#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register >>>> >>> */ >>> >> >>> >> This should only be a single state. You don't even have to represent it >>> >> in the sysreg array, to be honest. >>> >> Re-think about this. Since there are different operates to SET/CLR registers, maybe it should keep both of them while only storing the state in one of them. To SET: vcpu_sys_reg(vcpu, r->reg) |= val; To CLR: vcpu_sys_reg(vcpu, r->reg) &= ~val; Or keep one of them and within the access handler, according to the operates encoding value to judge whether it's SET or CLR. -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
From: Shannon Zhao <shannon.z...@linaro.org>
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw event
type to create a perf_event for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/pmu.h | 2 +
arch/arm64/kvm/Makefile | 1 +
include/kvm/arm_pmu.h| 13
virt/kvm/arm/pmu.c | 138 +++
4 files changed, 154 insertions(+)
create mode 100644 virt/kvm/arm/pmu.c
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index 4264ea0..e3cb6b3 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -28,6 +28,8 @@
#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
+/* Determines which PMCCNTR_EL0 bit generates an overflow */
+#define ARMV8_PMCR_LC (1 << 6)
#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters
supported */
#defineARMV8_PMCR_N_MASK 0x1f
#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 1949fe5..18d56d8 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -27,3 +27,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
+kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index dea78f8..36bde48 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -37,4 +37,17 @@ struct kvm_pmu {
#endif
};
+#ifdef CONFIG_KVM_ARM_PMU
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+ u32 select_idx);
+#else
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ return 0;
+}
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+ u32 select_idx) {}
+#endif
+
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
new file mode 100644
index 000..15babf1
--- /dev/null
+++ b/virt/kvm/arm/pmu.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * kvm_pmu_get_counter_value - get PMU counter value
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ */
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ u64 counter, enabled, running;
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc = >pmc[select_idx];
+
+ if (!vcpu_mode_is_32bit(vcpu))
+ counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
+ else
+ counter = vcpu_cp15(vcpu, c14_PMEVCNTR0 + select_idx);
+
+ if (pmc->perf_event)
+ counter += perf_event_read_value(pmc->perf_event, ,
+);
+
+ return counter & pmc->bitmask;
+}
+
+static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ if (!vcpu_mode_is_32bit(vcpu))
+ return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &
+ (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) >> select_idx);
+ else
+ return (vcpu_sys_reg(vcpu, c9_PMCR) & ARMV8_PMCR_E) &
+ (vcpu_sys_reg(vcpu, c9_PMCNTENSET) >> select_idx);
+}
+
+static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
+{
+ struct kvm_pmu *pmu;
+ struct kvm_vcpu_arch *vcpu_arch;
+
+ pmc -= pmc->idx;
+ pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
+ vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
+ return container_of
[PATCH v6 11/21] KVM: ARM64: Add access handler for PMXEVCNTR register
From: Shannon Zhao <shannon.z...@linaro.org>
Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which
is selected by PMSELR.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f7a73b5..2304937 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -516,6 +516,46 @@ out:
return true;
}
+static bool access_pmu_pmxevcntr(struct kvm_vcpu *vcpu,
+struct sys_reg_params *p,
+const struct sys_reg_desc *r)
+{
+ u64 pmcr, idx, val;
+
+ if (!vcpu_mode_is_32bit(vcpu)) {
+ pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+ if (!pmu_counter_idx_valid(pmcr, idx))
+ goto out;
+
+ val = kvm_pmu_get_counter_value(vcpu, idx);
+ if (!p->is_write) {
+ p->regval = val;
+ goto out;
+ }
+
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + idx) += (s64)p->regval - val;
+ } else {
+ pmcr = vcpu_cp15(vcpu, c9_PMCR);
+ idx = vcpu_cp15(vcpu, c9_PMSELR) & ARMV8_COUNTER_MASK;
+
+ if (!pmu_counter_idx_valid(pmcr, idx))
+ goto out;
+
+ val = kvm_pmu_get_counter_value(vcpu, idx);
+ if (!p->is_write) {
+ p->regval = val;
+ goto out;
+ }
+
+ vcpu_cp15(vcpu, c14_PMEVCNTR0 + idx) += (s64)p->regval - val;
+ }
+
+out:
+ return true;
+}
+
/* PMU registers accessor. */
static bool access_pmu_regs(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
@@ -804,7 +844,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_pmxevtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
- trap_raz_wi },
+ access_pmu_pmxevcntr },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
trap_raz_wi },
@@ -1192,7 +1232,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_cp15_regs,
NULL, c9_PMCCNTR },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_pmxevtyper },
- { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_pmxevcntr },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
--
2.0.4
--
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[PATCH v6 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the accessing action
specially, it uses default case to emulate writing and reading PMSELR
register.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index beb42f1..d81f7ac 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -690,7 +690,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -981,7 +981,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
+ NULL, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
2.0.4
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[PATCH v6 09/21] KVM: ARM64: Add access handler for PMXEVTYPER register
From: Shannon Zhao <shannon.z...@linaro.org>
Accessing PMXEVTYPER register is mapped to the PMEVTYPERn or
PMCCFILTR which is selected by PMSELR. If the value of PMSELR is valid,
call kvm_pmu_set_counter_event_type to create a perf_event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 55 +--
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2d8bd15..c116a1b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -465,6 +465,57 @@ static void reset_pmceid(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, r->reg) = pmceid;
}
+static bool pmu_counter_idx_valid(u64 pmcr, u64 idx)
+{
+ u64 val;
+
+ val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
+ if (idx >= val && idx != ARMV8_COUNTER_MASK)
+ return false;
+
+ return true;
+}
+
+static bool access_pmu_pmxevtyper(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmcr, idx;
+
+ if (!vcpu_mode_is_32bit(vcpu)) {
+ pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+ idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+ if (!pmu_counter_idx_valid(pmcr, idx))
+ goto out;
+
+ if (!p->is_write) {
+ p->regval = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx);
+ goto out;
+ }
+
+ vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx) = p->regval;
+ } else {
+ pmcr = vcpu_cp15(vcpu, c9_PMCR);
+ idx = vcpu_cp15(vcpu, c9_PMSELR) & ARMV8_COUNTER_MASK;
+
+ if (!pmu_counter_idx_valid(pmcr, idx))
+ goto out;
+
+ if (!p->is_write) {
+ p->regval = vcpu_cp15(vcpu, c14_PMEVTYPER0 + idx);
+ goto out;
+ }
+
+ vcpu_cp15(vcpu, c14_PMEVTYPER0 + idx) = p->regval;
+ }
+
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+
+out:
+ return true;
+}
+
/* PMU registers accessor. */
static bool access_pmu_regs(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
@@ -731,7 +782,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
- trap_raz_wi },
+ access_pmu_pmxevtyper },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
trap_raz_wi },
@@ -1069,7 +1120,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
NULL, c9_PMCEID1 },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_pmxevtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
--
2.0.4
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[PATCH v6 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index cd696ef..cea2176 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -259,6 +259,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
kvm_vgic_vcpu_destroy(vcpu);
+ kvm_pmu_vcpu_destroy(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index e0f5bfe..f7bc4bf 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,7 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -51,6 +52,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 01e8eb2..f8007c7 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -108,6 +108,27 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
}
/**
+ * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ struct kvm_pmc *pmc = >pmc[i];
+
+ if (pmc->perf_event) {
+ perf_event_disable(pmc->perf_event);
+ perf_event_release_kernel(pmc->perf_event);
+ pmc->perf_event = NULL;
+ }
+ }
+}
+
+/**
* kvm_pmu_flush_hwstate - flush pmu state to cpu
* @vcpu: The vcpu pointer
*
--
2.0.4
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[PATCH v6 21/21] KVM: ARM64: Add a new kvm ARM PMU device
From: Shannon Zhao <shannon.z...@linaro.org>
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 2 +
virt/kvm/arm/pmu.c| 93 +++
virt/kvm/kvm_main.c | 4 ++
6 files changed, 119 insertions(+)
create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
b/Documentation/virtual/kvm/devices/arm-pmu.txt
new file mode 100644
index 000..5121f1f
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
@@ -0,0 +1,16 @@
+ARM Virtual Performance Monitor Unit (vPMU)
+===
+
+Device types supported:
+ KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
+
+Instantiate one PMU instance for per VCPU through this API.
+
+Groups:
+ KVM_DEV_ARM_PMU_GRP_IRQ
+ Attributes:
+A value describing the interrupt number of PMU overflow interrupt. This
+interrupt should be a PPI.
+
+ Errors:
+-EINVAL: Value set is out of the expected range (from 16 to 31)
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index 2d4ca4b..568afa2 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+/* Device Control API: ARM PMU */
+#define KVM_DEV_ARM_PMU_GRP_IRQ0
+
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index c923350..608dea6 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
extern struct kvm_device_ops kvm_xics_ops;
extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
+extern struct kvm_device_ops kvm_arm_pmu_ops;
#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 03f3618..4ba6fdd 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1032,6 +1032,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
+ KVM_DEV_TYPE_ARM_PMU_V3,
+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
KVM_DEV_TYPE_MAX,
};
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index f8007c7..a84a4d7 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -19,10 +19,13 @@
#include
#include
#include
+#include
#include
#include
#include
+#include "vgic.h"
+
/**
* kvm_pmu_get_counter_value - get PMU counter value
* @vcpu: The vcpu pointer
@@ -438,3 +441,93 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
pmc->perf_event = event;
}
+
+static inline bool kvm_arm_pmu_initialized(struct kvm_vcpu *vcpu)
+{
+ return vcpu->arch.pmu.irq_num != -1;
+}
+
+static int kvm_arm_pmu_set_irq(struct kvm *kvm, int irq)
+{
+ int j;
+ struct kvm_vcpu *vcpu;
+
+ kvm_for_each_vcpu(j, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ if (!kvm_arm_pmu_initialized(vcpu))
+ kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
+ pmu->irq_num = irq;
+ }
+
+ return 0;
+}
+
+static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type)
+{
+ int i;
+ struct kvm_vcpu *vcpu;
+ struct kvm *kvm = dev->kvm;
+
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ memset(pmu, 0, sizeof(*pmu));
+ kvm_pmu_vcpu_reset(vcpu);
+ pmu->irq_num = -1;
+ }
+
+ return 0;
+}
+
+static void kvm_arm_pmu_destroy(struct kvm_device *dev)
+{
+ kfree(dev);
+}
+
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
+ struct kvm_device_attr *attr)
+{
+ switch (attr->group) {
+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
+ int __user *uaddr = (int __user *)(long)attr->addr;
+ int reg;
+
+ if (get_user(reg, uaddr))
+ return -EFAULT;
+
+ if (reg < VGIC_NR_SGIS || reg >= VGIC_NR_PRIVATE_IRQS)
+ return -EINVAL;
+
+ return kvm_arm_pmu_set_irq(dev->kvm,
[PATCH v6 18/21] KVM: ARM64: Add PMU overflow interrupt routing
From: Shannon Zhao <shannon.z...@linaro.org>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 52 ++-
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index e06fd29..cd696ef 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -569,6 +570,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct
kvm_run *run)
* non-preemptible context.
*/
preempt_disable();
+ kvm_pmu_flush_hwstate(vcpu);
kvm_timer_flush_hwstate(vcpu);
kvm_vgic_flush_hwstate(vcpu);
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index a131f76..c4041008 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
};
#ifdef CONFIG_KVM_ARM_PMU
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
@@ -48,6 +49,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
u32 select_idx);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
return 0;
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9b9c706..ff182d6 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
/**
* kvm_pmu_get_counter_value - get PMU counter value
@@ -90,6 +91,54 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_flush_hwstate - flush pmu state to cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
+ */
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ u32 overflow;
+
+ if (pmu->irq_num == -1)
+ return;
+
+ if (!vcpu_mode_is_32bit(vcpu)) {
+ if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E))
+ return;
+
+ overflow = vcpu_sys_reg(vcpu, PMCNTENSET_EL0)
+ & vcpu_sys_reg(vcpu, PMINTENSET_EL1)
+ & vcpu_sys_reg(vcpu, PMOVSSET_EL0);
+ } else {
+ if (!(vcpu_cp15(vcpu, c9_PMCR) & ARMV8_PMCR_E))
+ return;
+
+ overflow = vcpu_cp15(vcpu, c9_PMCNTENSET)
+ & vcpu_cp15(vcpu, c9_PMINTENSET)
+ & vcpu_cp15(vcpu, c9_PMOVSSET);
+ }
+
+ kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num,
+ overflow ? 1 : 0);
+}
+
+/**
+ * When perf event overflows, call kvm_pmu_overflow_set to set overflow status.
+ */
+static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+ struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
+ int idx = pmc->idx;
+
+ kvm_pmu_overflow_set(vcpu, BIT(idx));
+}
+
+/**
* kvm_pmu_enable_counter - enable selected PMU counter
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMCNTENSET register
@@ -341,7 +390,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
/* The initial sample period (overflow count) of an event. */
attr.sample_period = (-counter) & pmc->bitmask;
- event = perf_event_create_kernel_counter(, -1, current, NULL, pmc);
+ event = perf_event_create_kernel_counter(, -1, current,
+kvm_pmu_perf_overflow, pmc);
if (IS_ERR(event)) {
printk_once("kvm: pmu event creation failed %ld\n",
PTR_ERR(event));
--
2.0.4
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[PATCH v6 16/21] KVM: ARM64: Add reset and access handlers for PMSWINC register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 16 +++-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
3 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 80b66c0..9baa654 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -610,6 +610,10 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
kvm_pmu_overflow_clear(vcpu, p->regval);
break;
}
+ case PMSWINC_EL0: {
+ kvm_pmu_software_increment(vcpu, p->regval);
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -633,6 +637,8 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
p->regval = val;
break;
}
+ case PMSWINC_EL0:
+ return read_zero(vcpu, p);
case PMCR_EL0: {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
@@ -859,7 +865,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMSWINC_EL0 },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
access_pmu_regs, reset_unknown, PMSELR_EL0 },
@@ -1202,6 +1208,10 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
kvm_pmu_overflow_clear(vcpu, p->regval);
break;
}
+ case c9_PMSWINC: {
+ kvm_pmu_software_increment(vcpu, p->regval);
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1225,6 +1235,8 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
p->regval = val;
break;
}
+ case c9_PMSWINC:
+ return read_zero(vcpu, p);
case c9_PMCR: {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_cp15(vcpu, r->reg)
@@ -1291,6 +1303,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMCNTENSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
NULL, c9_PMOVSSET },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmu_cp15_regs,
+ NULL, c9_PMSWINC },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index a76df52..d12450a 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -43,6 +43,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
#else
@@ -54,6 +55,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val)
{}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {}
void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {}
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index ba7d11c..093e211 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -209,6 +209,46 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val)
}
/**
+ * kvm_pmu_software_increment - do software increment
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMSWINC register
+ */
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val)
+{
+ int i;
+ u32 type, enable, reg;
+
+ if (val ==
[PATCH v6 00/21] KVM: ARM64: Add guest PMU support
From: Shannon Zhao <shannon.z...@linaro.org>
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.
Use perf to test this patchset in guest. When using "perf list", it
shows the list of the hardware events and hardware cache events perf
supports. Then use "perf stat -e EVENT" to monitor some event. For
example, use "perf stat -e cycles" to count cpu cycles and
"perf stat -e cache-misses" to count cache misses.
Below are the outputs of "perf stat -r 5 sleep 5" when running in host
and guest.
Host:
Performance counter stats for 'sleep 5' (5 runs):
0.510276 task-clock (msec) #0.000 CPUs utilized
( +- 1.57% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
49 page-faults #0.096 M/sec
( +- 0.77% )
1064117 cycles#2.085 GHz
( +- 1.56% )
stalled-cycles-frontend
stalled-cycles-backend
529051 instructions #0.50 insns per cycle
( +- 0.55% )
branches
9894 branch-misses # 19.390 M/sec
( +- 1.70% )
5.000853900 seconds time elapsed
( +- 0.00% )
Guest:
Performance counter stats for 'sleep 5' (5 runs):
0.642456 task-clock (msec) #0.000 CPUs utilized
( +- 1.81% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
49 page-faults #0.076 M/sec
( +- 1.64% )
1322717 cycles#2.059 GHz
( +- 1.88% )
stalled-cycles-frontend
stalled-cycles-backend
640944 instructions #0.48 insns per cycle
( +- 1.10% )
branches
10665 branch-misses # 16.600 M/sec
( +- 2.23% )
5.001181452 seconds time elapsed
( +- 0.00% )
Have a cycle counter read test like below in guest and host:
static void test(void)
{
unsigned long count, count1, count2;
count1 = read_cycles();
count++;
count2 = read_cycles();
}
Host:
count1: 3046186213
count2: 3046186347
delta: 134
Guest:
count1: 5645797121
count2: 5645797270
delta: 149
The gap between guest and host is very small. One reason for this I
think is that it doesn't count the cycles in EL2 and host since we add
exclude_hv = 1. So the cycles spent to store/restore registers which
happens at EL2 are not included.
This patchset can be fetched from [1] and the relevant QEMU version for
test can be fetched from [2].
The results of 'perf test' can be found from [3][4].
The results of perf_event_tests test suite can be found from [5][6].
Also, I have tested "perf top" in two VMs and host at the same time. It
works well.
Thanks,
Shannon
[1] https://git.linaro.org/people/shannon.zhao/linux-mainline.git
KVM_ARM64_PMU_v6
[2] https://git.linaro.org/people/shannon.zhao/qemu.git virtual_PMU
[3] http://people.linaro.org/~shannon.zhao/PMU/perf-test-host.txt
[4] http://people.linaro.org/~shannon.zhao/PMU/perf-test-guest.txt
[5] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-host.txt
[6] http://people.linaro.org/~shannon.zhao/PMU/perf_event_tests-guest.txt
Changes since v5:
* Rebase on new linux kernel mainline
* Remove state duplications and drop PMOVSCLR, PMCNTENCLR, PMINTENCLR,
PMXEVCNTR, PMXEVTYPER
* Add a helper to check if vPMU is already initialized
* remove kvm_vcpu from kvm_pmc
Changes since v4:
* Rebase on new linux kernel mainline
* Drop the reset handler of CP15 registers
* Fix a compile failure on arch ARM due to lack of asm/pmu.h
* Refactor the interrupt injecting flow according to Marc's suggestion
* Check the value of PMSELR register
* Calculate the attr.disabled according to PMCR.E and PMCNTENSET/CLR
* Fix some coding style
* Document the vPMU irq range
Changes since v3:
* Rebase on new linux kernel mainline
* Use ARMV8_MAX_COUNTERS instead of 32
* Reset PMCR.E to zero.
* Trigger overflow for software increment.
* Optimize PMU interrupt inject logic.
* Add handler for E,C,P bits of PMCR
* Fix the overflow bug found by perf_event_tests
* Run 'perf test', 'perf top' and perf_event_tests test suite
* Add exclude_hv = 1 configuration to not count in EL2
Changes since v2:
* Directly use perf raw event type to create perf_event in K
[PATCH v6 15/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register
From: Shannon Zhao <shannon.z...@linaro.org>
The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c830fde..80b66c0 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -880,7 +880,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_pmxevcntr },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMUSERENR_EL0 },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
@@ -1301,7 +1301,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMCCNTR },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_pmxevtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_pmxevcntr },
- { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmu_cp15_regs,
+ NULL, c9_PMUSERENR, 0 },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs,
NULL, c9_PMINTENSET },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
--
2.0.4
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[PATCH v6 01/21] ARM64: Move PMU register related defines to asm/pmu.h
From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/pmu.h | 64 ++ arch/arm64/kernel/perf_event.c | 36 +--- 2 files changed, 65 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/include/asm/pmu.h diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h new file mode 100644 index 000..4264ea0 --- /dev/null +++ b/arch/arm64/include/asm/pmu.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2015 Linaro Ltd, Shannon Zhao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __ASM_PMU_H +#define __ASM_PMU_H + +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#defineARMV8_PMCR_N_MASK 0x1f +#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#defineARMV8_CNTEN_MASK0x /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#defineARMV8_INTEN_MASK0x /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ +#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#defineARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#defineARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#defineARMV8_EXCLUDE_EL1 (1 << 31) +#defineARMV8_EXCLUDE_EL0 (1 << 30) +#defineARMV8_INCLUDE_EL2 (1 << 27) + +#endif /* __ASM_PMU_H */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 5b1897e..7eca5dc 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -24,6 +24,7 @@ #include #include #include +#include /* * ARMv8 PMUv3 Performance Events handling code. @@ -187,9 +188,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_COUNTER_LAST(cpu_pmu) \ (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#defineARMV8_MAX_COUNTERS 32 -#defineARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -200,38 +198,6 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #defineARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#defineARMV8_PMCR_N_MASK 0x1f -#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#defineARMV8_OVSR_MASK 0x /* Mask for writable bits */ -#defineARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#defineARMV8_EVTYPE_MASK 0xc
[PATCH v6 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
From: Shannon Zhao <shannon.z...@linaro.org>
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E to zero. Add a common access
handler for PMU registers which emulates writing and reading register
and add emulation for PMCR.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 97 ++-
1 file changed, 95 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d2650e8..beb42f1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
@@ -438,6 +439,58 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
}
+static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+ u64 pmcr, val;
+
+ asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
+ /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN
+* except PMCR.E resetting to zero.
+*/
+ val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad))
+ & (~ARMV8_PMCR_E);
+ vcpu_sys_reg(vcpu, r->reg) = val;
+}
+
+/* PMU registers accessor. */
+static bool access_pmu_regs(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 val;
+
+ if (p->is_write) {
+ switch (r->reg) {
+ case PMCR_EL0: {
+ /* Only update writeable bits of PMCR */
+ val = vcpu_sys_reg(vcpu, r->reg);
+ val &= ~ARMV8_PMCR_MASK;
+ val |= p->regval & ARMV8_PMCR_MASK;
+ vcpu_sys_reg(vcpu, r->reg) = val;
+ break;
+ }
+ default:
+ vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ break;
+ }
+ } else {
+ switch (r->reg) {
+ case PMCR_EL0: {
+ /* PMCR.P & PMCR.C are RAZ */
+ val = vcpu_sys_reg(vcpu, r->reg)
+ & ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
+ p->regval = val;
+ break;
+ }
+ default:
+ p->regval = vcpu_sys_reg(vcpu, r->reg);
+ break;
+ }
+ }
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -622,7 +675,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMCR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
trap_raz_wi },
@@ -856,6 +909,45 @@ static const struct sys_reg_desc cp14_64_regs[] = {
{ Op1( 0), CRm( 2), .access = trap_raz_wi },
};
+/* PMU CP15 registers accessor. */
+static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
+struct sys_reg_params *p,
+const struct sys_reg_desc *r)
+{
+ u32 val;
+
+ if (p->is_write) {
+ switch (r->reg) {
+ case c9_PMCR: {
+ /* Only update writeable bits of PMCR */
+ val = vcpu_cp15(vcpu, r->reg);
+ val &= ~ARMV8_PMCR_MASK;
+ val |= p->regval & ARMV8_PMCR_MASK;
+ vcpu_cp15(vcpu, r->reg) = val;
+ break;
+ }
+ default:
+ vcpu_cp15(vcpu, r->reg) = p->regval;
+ break;
+ }
+ } else {
+ switch (r->reg) {
+ case c9_PMCR: {
+ /* PMCR.P & PMCR.C are RAZ */
+ val = vcpu_cp15(vcpu, r->reg)
+ & ~(ARMV8_PMCR_P | ARMV8_PMCR_C);
+ p->regval = val;
+ break;
+ }
+ default:
+ p->regval = vcpu_cp15(vcpu, r->reg);
+ break;
+ }
+ }
+
+ return true;
+}
+
/*
* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
* depending on the way they are accessed (as a 32bit or a 64bit
@@ -884,7 +976,8 @
[PATCH v6 03/21] KVM: ARM64: Add offset defines for PMU registers
From: Shannon Zhao <shannon.z...@linaro.org> We are about to trap and emulate accesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/kvm_asm.h | 45 +++- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 5e37710..fb3a2a0 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -48,12 +48,29 @@ #define MDSCR_EL1 22 /* Monitor Debug System Control Register */ #define MDCCINT_EL123 /* Monitor Debug Comms Channel Interrupt Enable Reg */ +/* Performance Monitors Registers */ +#define PMCR_EL0 24 /* Control Register */ +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */ +#define PMSELR_EL0 26 /* Event Counter Selection Register */ +#define PMCEID0_EL027 /* Common Event Identification Register 0 */ +#define PMCEID1_EL028 /* Common Event Identification Register 1 */ +#define PMEVCNTR0_EL0 29 /* Event Counter Register (0-30) */ +#define PMEVCNTR30_EL0 59 +#define PMCCNTR_EL060 /* Cycle Counter Register */ +#define PMEVTYPER0_EL0 61 /* Event Type Register (0-30) */ +#define PMEVTYPER30_EL091 +#define PMCCFILTR_EL0 92 /* Cycle Count Filter Register */ +#define PMCNTENSET_EL0 93 /* Count Enable Set Register */ +#define PMINTENSET_EL1 94 /* Interrupt Enable Set Register */ +#define PMUSERENR_EL0 95 /* User Enable Register */ +#define PMSWINC_EL096 /* Software Increment Register */ + /* 32bit specific registers. Keep them at the end of the range */ -#defineDACR32_EL2 24 /* Domain Access Control Register */ -#defineIFSR32_EL2 25 /* Instruction Fault Status Register */ -#defineFPEXC32_EL2 26 /* Floating-Point Exception Control Register */ -#defineDBGVCR32_EL227 /* Debug Vector Catch Register */ -#defineNR_SYS_REGS 28 +#defineDACR32_EL2 97 /* Domain Access Control Register */ +#defineIFSR32_EL2 98 /* Instruction Fault Status Register */ +#defineFPEXC32_EL2 99 /* Floating-Point Exception Control Register */ +#defineDBGVCR32_EL2100 /* Debug Vector Catch Register */ +#defineNR_SYS_REGS 101 /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ @@ -75,6 +92,19 @@ #define c6_IFAR(c6_DFAR + 1) /* Instruction Fault Address Register */ #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ #define c7_PAR_high(c7_PAR + 1)/* PAR top 32 bits */ + +/* Performance Monitors*/ +#define c9_PMCR(PMCR_EL0 * 2) +#define c9_PMOVSSET(PMOVSSET_EL0 * 2) +#define c9_PMCCNTR (PMCCNTR_EL0 * 2) +#define c9_PMSELR (PMSELR_EL0 * 2) +#define c9_PMCEID0 (PMCEID0_EL0 * 2) +#define c9_PMCEID1 (PMCEID1_EL0 * 2) +#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2) +#define c9_PMINTENSET (PMINTENSET_EL1 * 2) +#define c9_PMUSERENR (PMUSERENR_EL0 * 2) +#define c9_PMSWINC (PMSWINC_EL0 * 2) + #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ @@ -86,6 +116,11 @@ #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ #define c14_CNTKCTL(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ +/* Performance Monitors*/ +#define c14_PMEVCNTR0 (PMEVCNTR0_EL0 * 2) +#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2) +#define c14_PMCCFILTR (PMCCFILTR_EL0 * 2) + #define cp14_DBGDSCRext(MDSCR_EL1 * 2) #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) -- 2.0.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use
reset_unknown for its reset handler. Add access handler which emulates
writing and reading PMEVCNTRn or PMCCNTR register. When reading
PMEVCNTRn or PMCCNTR, call perf_event_read_value to get the count value
of the perf event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 107 +-
1 file changed, 105 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c116a1b..f7a73b5 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -525,6 +525,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
if (p->is_write) {
switch (r->reg) {
+ case PMEVCNTR0_EL0 ... PMCCNTR_EL0: {
+ val = kvm_pmu_get_counter_value(vcpu,
+ r->reg - PMEVCNTR0_EL0);
+ vcpu_sys_reg(vcpu, r->reg) += (s64)p->regval - val;
+ break;
+ }
case PMEVTYPER0_EL0 ... PMCCFILTR_EL0: {
val = r->reg - PMEVTYPER0_EL0;
kvm_pmu_set_counter_event_type(vcpu, p->regval, val);
@@ -548,6 +554,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
}
} else {
switch (r->reg) {
+ case PMEVCNTR0_EL0 ... PMCCNTR_EL0: {
+ val = kvm_pmu_get_counter_value(vcpu,
+ r->reg - PMEVCNTR0_EL0);
+ p->regval = val;
+ break;
+ }
case PMCR_EL0: {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
@@ -579,6 +591,13 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVCNTRn_EL0 register */
+#define PMU_PMEVCNTR_EL0(n)\
+ /* PMEVCNTRn_EL0 */ \
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVCNTR0_EL0 + n), }
+
/* Macro to expand the PMEVTYPERn_EL0 register */
#define PMU_PMEVTYPER_EL0(n) \
/* PMEVTYPERn_EL0 */\
@@ -779,7 +798,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_pmceid, PMCEID1_EL0 },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCCNTR_EL0 },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
access_pmu_pmxevtyper },
@@ -800,6 +819,38 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVCNTRn_EL0 */
+ PMU_PMEVCNTR_EL0(0),
+ PMU_PMEVCNTR_EL0(1),
+ PMU_PMEVCNTR_EL0(2),
+ PMU_PMEVCNTR_EL0(3),
+ PMU_PMEVCNTR_EL0(4),
+ PMU_PMEVCNTR_EL0(5),
+ PMU_PMEVCNTR_EL0(6),
+ PMU_PMEVCNTR_EL0(7),
+ PMU_PMEVCNTR_EL0(8),
+ PMU_PMEVCNTR_EL0(9),
+ PMU_PMEVCNTR_EL0(10),
+ PMU_PMEVCNTR_EL0(11),
+ PMU_PMEVCNTR_EL0(12),
+ PMU_PMEVCNTR_EL0(13),
+ PMU_PMEVCNTR_EL0(14),
+ PMU_PMEVCNTR_EL0(15),
+ PMU_PMEVCNTR_EL0(16),
+ PMU_PMEVCNTR_EL0(17),
+ PMU_PMEVCNTR_EL0(18),
+ PMU_PMEVCNTR_EL0(19),
+ PMU_PMEVCNTR_EL0(20),
+ PMU_PMEVCNTR_EL0(21),
+ PMU_PMEVCNTR_EL0(22),
+ PMU_PMEVCNTR_EL0(23),
+ PMU_PMEVCNTR_EL0(24),
+ PMU_PMEVCNTR_EL0(25),
+ PMU_PMEVCNTR_EL0(26),
+ PMU_PMEVCNTR_EL0(27),
+ PMU_PMEVCNTR_EL0(28),
+ PMU_PMEVCNTR_EL0(29),
+ PMU_PMEVCNTR_EL0(30),
/* PMEVTYPERn_EL0 */
PMU_PMEVTYPER_EL0(0),
PMU_PMEVTYPER_EL0(1),
@@ -1034,6 +1085,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
if (p->is_write) {
switch (r->reg) {
+ case c14_PMEVCNTR0 ... c9_PMCCNTR: {
+ val = kvm_pmu_get_counter_value(vcpu,
+ r->reg - c14_PMEVCNTR0);
+ vcpu_cp15(vcpu, r->reg) += (s64)p->regval - val;
+ break;
+ }
case c14_PMEVTYP
[PATCH v6 19/21] KVM: ARM64: Reset PMU state when resetting vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When resetting vcpu, it needs to reset the PMU state to initial status.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/reset.c | 3 +++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c | 17 +
3 files changed, 22 insertions(+)
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index f34745c..dfbce78 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -120,6 +120,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
/* Reset system registers */
kvm_reset_sys_regs(vcpu);
+ /* Reset PMU */
+ kvm_pmu_vcpu_reset(vcpu);
+
/* Reset timer */
return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index c4041008..e0f5bfe 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
};
#ifdef CONFIG_KVM_ARM_PMU
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -49,6 +50,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
u32 select_idx);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index ff182d6..01e8eb2 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -91,6 +91,23 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_vcpu_reset - reset pmu state for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ kvm_pmu_stop_counter(>pmc[i]);
+ pmu->pmc[i].idx = i;
+ pmu->pmc[i].bitmask = 0xUL;
+ }
+}
+
+/**
* kvm_pmu_flush_hwstate - flush pmu state to cpu
* @vcpu: The vcpu pointer
*
--
2.0.4
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[PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.
When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 39 +++
include/kvm/arm_pmu.h | 4
virt/kvm/arm/pmu.c| 47 +++
3 files changed, 86 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2304937..a780cb5 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -577,6 +577,21 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) = p->regval;
break;
}
+ case PMCNTENSET_EL0: {
+ val = p->regval;
+ if (r->Op2 == 1) {
+ /* accessing PMCNTENSET_EL0 */
+ kvm_pmu_enable_counter(vcpu, val,
+ vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E);
+ vcpu_sys_reg(vcpu, r->reg) |= val;
+ } else {
+
+ /* accessing PMCNTENCLR_EL0 */
+ kvm_pmu_disable_counter(vcpu, val);
+ vcpu_sys_reg(vcpu, r->reg) &= ~val;
+ }
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -817,10 +832,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
trap_raz_wi },
@@ -1137,6 +1152,20 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, r->reg) = p->regval;
break;
}
+ case c9_PMCNTENSET: {
+ val = p->regval;
+ if (r->Op2 == 1) {
+ /* accessing c9_PMCNTENSET */
+ kvm_pmu_enable_counter(vcpu, val,
+ vcpu_cp15(vcpu, c9_PMCR) & ARMV8_PMCR_E);
+ vcpu_cp15(vcpu, r->reg) |= val;
+ } else {
+ /* accessing c9_PMCNTENCLR */
+ kvm_pmu_disable_counter(vcpu, val);
+ vcpu_cp15(vcpu, r->reg) &= ~val;
+ }
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1220,8 +1249,10 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
NULL, c9_PMCR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs,
+ NULL, c9_PMCNTENSET },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
+ NULL, c9_PMCNTENSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 36bde48..e731656 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,8 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
#else
@@ -46,6 +48,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32
select_idx)
{
return 0;
}
+void kvm_pmu_disable_counter(struct kvm_vcpu *vcp
[PATCH v6 13/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a780cb5..c1dffb2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -592,6 +592,15 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
}
break;
}
+ case PMINTENSET_EL1: {
+ if (r->Op2 == 1)
+ /* accessing PMINTENSET_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) |= p->regval;
+ else
+ /* accessing PMINTENCLR_EL1 */
+ vcpu_sys_reg(vcpu, r->reg) &= ~p->regval;
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -789,10 +798,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMINTENSET_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMINTENSET_EL1 },
/* PMINTENCLR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMINTENSET_EL1 },
/* MAIR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1166,6 +1175,15 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
}
break;
}
+ case c9_PMINTENSET: {
+ if (r->Op2 == 1)
+ /* accessing c9_PMCNTENSET */
+ vcpu_cp15(vcpu, r->reg) |= p->regval;
+ else
+ /* accessing c9_PMCNTENCLR */
+ vcpu_cp15(vcpu, r->reg) &= ~p->regval;
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1265,8 +1283,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_pmxevtyper },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_pmxevcntr },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs,
+ NULL, c9_PMINTENSET },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
+ NULL, c9_PMINTENSET },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
--
2.0.4
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[PATCH v6 17/21] KVM: ARM64: Add helper to handle PMCR register bits
From: Shannon Zhao <shannon.z...@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 51 +++
3 files changed, 55 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9baa654..110b288 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -620,6 +620,7 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
val &= ~ARMV8_PMCR_MASK;
val |= p->regval & ARMV8_PMCR_MASK;
vcpu_sys_reg(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
break;
}
case PMCEID0_EL0:
@@ -1218,6 +1219,7 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
val &= ~ARMV8_PMCR_MASK;
val |= p->regval & ARMV8_PMCR_MASK;
vcpu_cp15(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
break;
}
case c9_PMCEID0:
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index d12450a..a131f76 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -46,6 +46,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
@@ -58,6 +59,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx) {}
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val) {}
#endif
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 093e211..9b9c706 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -151,6 +151,57 @@ static u32 kvm_pmu_valid_counter_mask(struct kvm_vcpu
*vcpu)
}
/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc;
+ u32 enable;
+ int i;
+
+ if (val & ARMV8_PMCR_E) {
+ if (!vcpu_mode_is_32bit(vcpu))
+ enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+ else
+ enable = vcpu_cp15(vcpu, c9_PMCNTENSET);
+
+ kvm_pmu_enable_counter(vcpu, enable, true);
+ } else {
+ kvm_pmu_disable_counter(vcpu, 0xUL);
+ }
+
+ if (val & ARMV8_PMCR_C) {
+ pmc = >pmc[ARMV8_MAX_COUNTERS - 1];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ if (!vcpu_mode_is_32bit(vcpu))
+ vcpu_sys_reg(vcpu, PMCCNTR_EL0) = 0;
+ else
+ vcpu_cp15(vcpu, c9_PMCCNTR) = 0;
+ }
+
+ if (val & ARMV8_PMCR_P) {
+ for (i = 0; i < ARMV8_MAX_COUNTERS - 1; i++) {
+ pmc = >pmc[i];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ if (!vcpu_mode_is_32bit(vcpu))
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = 0;
+ else
+ vcpu_cp15(vcpu, c14_PMEVCNTR0 + i) = 0;
+ }
+ }
+
+ if (val & ARMV8_PMCR_LC) {
+ pmc = >pmc[ARMV8_MAX_COUNTERS - 1];
+ pmc->bitmask = 0xUL;
+ }
+}
+
+/**
* kvm_pmu_overflow_clear - clear PMU overflow interrupt
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMOVSCLR register
--
2.0.4
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[PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters.
Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/Kconfig| 8
include/kvm/arm_pmu.h | 40 +++
3 files changed, 50 insertions(+)
create mode 100644 include/kvm/arm_pmu.h
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index a35ce72..42e15bb 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -37,6 +37,7 @@
#include
#include
+#include
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
@@ -132,6 +133,7 @@ struct kvm_vcpu_arch {
/* VGIC state */
struct vgic_cpu vgic_cpu;
struct arch_timer_cpu timer_cpu;
+ struct kvm_pmu pmu;
/*
* Anything that is not used directly from assembly code goes
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index a5272c0..66da9a2 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -36,6 +36,7 @@ config KVM
select HAVE_KVM_EVENTFD
select HAVE_KVM_IRQFD
select KVM_ARM_VGIC_V3
+ select KVM_ARM_PMU
---help---
Support hosting virtualized guest machines.
We don't support KVM with 16K page tables yet, due to the multiple
@@ -48,6 +49,13 @@ config KVM_ARM_HOST
---help---
Provides host support for ARM processors.
+config KVM_ARM_PMU
+ bool
+ depends on KVM_ARM_HOST && HW_PERF_EVENTS
+ ---help---
+ Adds support for a virtual Performance Monitoring Unit (PMU) in
+ virtual machines.
+
source drivers/vhost/Kconfig
endif # VIRTUALIZATION
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
new file mode 100644
index 000..dea78f8
--- /dev/null
+++ b/include/kvm/arm_pmu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARM_KVM_PMU_H
+#define __ASM_ARM_KVM_PMU_H
+
+#include
+#ifdef CONFIG_KVM_ARM_PMU
+#include
+#endif
+
+struct kvm_pmc {
+ u8 idx;/* index into the pmu->pmc array */
+ struct perf_event *perf_event;
+ u64 bitmask;
+};
+
+struct kvm_pmu {
+#ifdef CONFIG_KVM_ARM_PMU
+ /* PMU IRQ Number per VCPU */
+ int irq_num;
+ struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
+#endif
+};
+
+#endif
--
2.0.4
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[PATCH v6 14/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the current value, clear the PMU
pending interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 27 --
include/kvm/arm_pmu.h | 4 +++
virt/kvm/arm/pmu.c| 72 +++
3 files changed, 100 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c1dffb2..c830fde 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -601,6 +601,15 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) &= ~p->regval;
break;
}
+ case PMOVSSET_EL0: {
+ if (r->CRm == 14)
+ /* accessing PMOVSSET_EL0 */
+ kvm_pmu_overflow_set(vcpu, p->regval);
+ else
+ /* accessing PMOVSCLR_EL0 */
+ kvm_pmu_overflow_clear(vcpu, p->regval);
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -847,7 +856,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
trap_raz_wi },
@@ -874,7 +883,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -1184,6 +1193,15 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, r->reg) &= ~p->regval;
break;
}
+ case c9_PMOVSSET: {
+ if (r->CRm == 14)
+ /* accessing c9_PMOVSSET */
+ kvm_pmu_overflow_set(vcpu, p->regval);
+ else
+ /* accessing c9_PMOVSCLR */
+ kvm_pmu_overflow_clear(vcpu, p->regval);
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1271,7 +1289,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMCNTENSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
NULL, c9_PMCNTENSET },
- { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
+ NULL, c9_PMOVSSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
@@ -1287,6 +1306,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMINTENSET },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
NULL, c9_PMINTENSET },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmu_cp15_regs,
+ NULL, c9_PMOVSSET },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index e731656..a76df52 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -41,6 +41,8 @@ struct kvm_pmu {
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
+void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
#else
@@ -50,6 +52,8 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32
select_idx)
}
void kvm_pmu_disable_counter(struct
[PATCH v6 08/21] KVM: ARM64: Add access handler for PMEVTYPERn and PMCCFILTR register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMEVTYPERn or
PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call
kvm_pmu_set_counter_event_type to create a perf_event for the selected
event type.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 98 +++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1bcb2b7..2d8bd15 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -474,6 +474,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
if (p->is_write) {
switch (r->reg) {
+ case PMEVTYPER0_EL0 ... PMCCFILTR_EL0: {
+ val = r->reg - PMEVTYPER0_EL0;
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, val);
+ vcpu_sys_reg(vcpu, r->reg) = p->regval;
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -522,6 +528,13 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n) \
+ /* PMEVTYPERn_EL0 */\
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -736,6 +749,42 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVTYPERn_EL0 */
+ PMU_PMEVTYPER_EL0(0),
+ PMU_PMEVTYPER_EL0(1),
+ PMU_PMEVTYPER_EL0(2),
+ PMU_PMEVTYPER_EL0(3),
+ PMU_PMEVTYPER_EL0(4),
+ PMU_PMEVTYPER_EL0(5),
+ PMU_PMEVTYPER_EL0(6),
+ PMU_PMEVTYPER_EL0(7),
+ PMU_PMEVTYPER_EL0(8),
+ PMU_PMEVTYPER_EL0(9),
+ PMU_PMEVTYPER_EL0(10),
+ PMU_PMEVTYPER_EL0(11),
+ PMU_PMEVTYPER_EL0(12),
+ PMU_PMEVTYPER_EL0(13),
+ PMU_PMEVTYPER_EL0(14),
+ PMU_PMEVTYPER_EL0(15),
+ PMU_PMEVTYPER_EL0(16),
+ PMU_PMEVTYPER_EL0(17),
+ PMU_PMEVTYPER_EL0(18),
+ PMU_PMEVTYPER_EL0(19),
+ PMU_PMEVTYPER_EL0(20),
+ PMU_PMEVTYPER_EL0(21),
+ PMU_PMEVTYPER_EL0(22),
+ PMU_PMEVTYPER_EL0(23),
+ PMU_PMEVTYPER_EL0(24),
+ PMU_PMEVTYPER_EL0(25),
+ PMU_PMEVTYPER_EL0(26),
+ PMU_PMEVTYPER_EL0(27),
+ PMU_PMEVTYPER_EL0(28),
+ PMU_PMEVTYPER_EL0(29),
+ PMU_PMEVTYPER_EL0(30),
+ /* PMCCFILTR_EL0 */
+ { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b), Op2(0b111),
+ access_pmu_regs, reset_unknown, PMCCFILTR_EL0, },
+
/* DACR32_EL2 */
{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b), Op2(0b000),
NULL, reset_unknown, DACR32_EL2 },
@@ -934,6 +983,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
if (p->is_write) {
switch (r->reg) {
+ case c14_PMEVTYPER0 ... c14_PMCCFILTR: {
+ val = r->reg - c14_PMEVTYPER0;
+ kvm_pmu_set_counter_event_type(vcpu, p->regval, val);
+ vcpu_cp15(vcpu, r->reg) = p->regval;
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -967,6 +1022,13 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
return true;
}
+/* Macro to expand the PMEVTYPERn register */
+#define PMU_PMEVTYPER(n) \
+ /* PMEVTYPERn */\
+ { Op1(0), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_cp15_regs, NULL, (c14_PMEVTYPER0 + n), }
+
/*
* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
* depending on the way they are accessed (as a 32bit or a 64bit
@@ -1022,6 +1084,42 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
+
+ /* PMEVTYPERn */
+ PMU_PMEVTYPER(0),
+ PMU_PMEVTYP
[PATCH v6 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register
From: Shannon Zhao <shannon.z...@linaro.org>
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d81f7ac..1bcb2b7 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -452,6 +452,19 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct
sys_reg_desc *r)
vcpu_sys_reg(vcpu, r->reg) = val;
}
+static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (r->reg == PMCEID0_EL0)
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ /* PMCEID1_EL0 */
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ vcpu_sys_reg(vcpu, r->reg) = pmceid;
+}
+
/* PMU registers accessor. */
static bool access_pmu_regs(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
@@ -469,6 +482,9 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) = val;
break;
}
+ case PMCEID0_EL0:
+ case PMCEID1_EL0:
+ return ignore_write(vcpu, p);
default:
vcpu_sys_reg(vcpu, r->reg) = p->regval;
break;
@@ -693,10 +709,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID0_EL0 },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID1_EL0 },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -926,6 +942,9 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, r->reg) = val;
break;
}
+ case c9_PMCEID0:
+ case c9_PMCEID1:
+ return ignore_write(vcpu, p);
default:
vcpu_cp15(vcpu, r->reg) = p->regval;
break;
@@ -983,8 +1002,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
+ NULL, c9_PMCEID0 },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
+ NULL, c9_PMCEID1 },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
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Re: [PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu
On 2015/12/8 22:10, Marc Zyngier wrote: On 08/12/15 13:53, Will Deacon wrote: On Tue, Dec 08, 2015 at 01:37:14PM +, Marc Zyngier wrote: On 08/12/15 12:47, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters. Since this only supports ARM64 (or PMUv3), add a separate config symbol for it. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Kconfig| 8 include/kvm/arm_pmu.h | 40 +++ 3 files changed, 50 insertions(+) create mode 100644 include/kvm/arm_pmu.h [...] diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index a5272c0..66da9a2 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -36,6 +36,7 @@ config KVM select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD select KVM_ARM_VGIC_V3 + select KVM_ARM_PMU What if HW_PERF_EVENTS is not selected? Also, selecting HW_PERF_EVENTS is not enough, and you probably need PERF_EVENTS as well, So this should probably read: select KVM_ARM_PMU if (HW_PERF_EVENTS && PERF_EVENTS) HW_PERF_EVENTS depends on ARM_PMU which in turn depends on PERF_EVENTS. Yeah, this is the reason why I choose HW_PERF_EVENTS. in which case, let's make it: select KVM_ARM_PMU if HW_PERF_EVENTS Sure, will do. which should give us the minimal chain. I hate the kernel config language! ;-) M. -- Shannon -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
On 2015/12/8 23:43, Marc Zyngier wrote:
> On 08/12/15 12:47, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.z...@linaro.org>
>> +/**
>> + * kvm_pmu_get_counter_value - get PMU counter value
>> + * @vcpu: The vcpu pointer
>> + * @select_idx: The counter index
>> + */
>> +u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
>> +{
>> +u64 counter, enabled, running;
>> +struct kvm_pmu *pmu = >arch.pmu;
>> +struct kvm_pmc *pmc = >pmc[select_idx];
>> +
>> +if (!vcpu_mode_is_32bit(vcpu))
>> +counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
>> +else
>> +counter = vcpu_cp15(vcpu, c14_PMEVCNTR0 + select_idx);
>> +
>> +if (pmc->perf_event)
>> +counter += perf_event_read_value(pmc->perf_event, ,
>> + );
>> +
>> +return counter & pmc->bitmask;
>
> This one confused me for a while. Is it the case that you return
> whatever is in the vcpu view of the counter, plus anything that perf
> itself has counted? If so, I'd appreciate a comment here...
>
Yes, the real counter value is the current counter value plus the value
perf event counts. I'll add a comment.
>> +}
>> +
>> +static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u32
>> select_idx)
>> +{
>> +if (!vcpu_mode_is_32bit(vcpu))
>> +return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &
>> + (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) >> select_idx);
>
> This looks wrong. Shouldn't it be:
>
> return ((vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &&
> (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & (1 << select_idx)));
>
>> +else
>> +return (vcpu_sys_reg(vcpu, c9_PMCR) & ARMV8_PMCR_E) &
>> + (vcpu_sys_reg(vcpu, c9_PMCNTENSET) >> select_idx);
>> +}
>
> Also, I don't really see why we need to check the 32bit version, which
> has the exact same content.
>
>> +
>> +static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
>> +{
>> +struct kvm_pmu *pmu;
>> +struct kvm_vcpu_arch *vcpu_arch;
>> +
>> +pmc -= pmc->idx;
>> +pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
>> +vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
>> +return container_of(vcpu_arch, struct kvm_vcpu, arch);
>> +}
>> +
>> +/**
>> + * kvm_pmu_stop_counter - stop PMU counter
>> + * @pmc: The PMU counter pointer
>> + *
>> + * If this counter has been configured to monitor some event, release it
>> here.
>> + */
>> +static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
>> +{
>> +struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
>> +u64 counter;
>> +
>> +if (pmc->perf_event) {
>> +counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
>> +if (!vcpu_mode_is_32bit(vcpu))
>> +vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + pmc->idx) = counter;
>> +else
>> +vcpu_cp15(vcpu, c14_PMEVCNTR0 + pmc->idx) = counter;
>
> Same thing - we don't need to make a difference between 32 and 64bit.
>
So it's fine to drop all the vcpu_mode_is_32bit(vcpu) check of this
series? The only one we should take care is the PMCCNTR, right?
>> +
>> +perf_event_release_kernel(pmc->perf_event);
>> +pmc->perf_event = NULL;
>> +}
>> +}
>> +
>> +/**
>> + * kvm_pmu_set_counter_event_type - set selected counter to monitor some
>> event
>> + * @vcpu: The vcpu pointer
>> + * @data: The data guest writes to PMXEVTYPER_EL0
>> + * @select_idx: The number of selected counter
>> + *
>> + * When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to
>> count an
>> + * event with given hardware event number. Here we call perf_event API to
>> + * emulate this action and create a kernel perf event for it.
>> + */
>> +void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
>> +u32 select_idx)
>> +{
>> +struct kvm_pmu *pmu = >arch.pmu;
>> +struct kvm_pmc *pmc = >pmc[select_idx];
>> +struct perf_event *event;
>> +struct perf_event_attr attr;
>> +u32 eventsel;
>> +u64 counter;
>> +
>> +kvm_pmu_stop_counter(pmc);
>
> Wait. I didn't realize this before, but you have the vcpu right here.
> Why don't you pass it as a parameter to kvm_pmu_stop_counter and avoid
> the kvm_pmc_to_vcpu thing altogether?
>
Yeah, we could pass vcpu as a parameter for this function. But the
kvm_pmc_to_vcpu helper is also used in kvm_pmu_perf_overflow() and
within kvm_pmu_perf_overflow it needs the pmc->idx, we couldn't pass
vcpu as a parameter, so this helper is necessary for kvm_pmu_perf_overflow.
Thanks,
--
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Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers
On 2015/12/7 22:06, Marc Zyngier wrote: On 03/12/15 06:11, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> We are about to trap and emulate acccesses to each PMU register s/acccesses/accesses/ individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/kvm_asm.h | 55 1 file changed, 50 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 5e37710..4f804c1 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -48,12 +48,34 @@ #define MDSCR_EL1 22 /* Monitor Debug System Control Register */ #define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */ Coming back to this patch, it gives a clear view of where you have state duplication. +/* Performance Monitors Registers */ +#define PMCR_EL0 24 /* Control Register */ +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */ +#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */ This should only be a single state. You don't even have to represent it in the sysreg array, to be honest. Yeah, I could store the state in one of them and drop one of them here. +#define PMSELR_EL0 27 /* Event Counter Selection Register */ +#define PMCEID0_EL028 /* Common Event Identification Register 0 */ +#define PMCEID1_EL029 /* Common Event Identification Register 1 */ +#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */ +#define PMEVCNTR30_EL0 60 +#define PMCCNTR_EL061 /* Cycle Counter Register */ +#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */ +#define PMEVTYPER30_EL092 +#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */ +#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */ +#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */ These "select" registers aren't real ones, but just a way to pick the real register. They should be removed. I think these two could be retained, since it's convenient to handle the guest accessing by using "case PMXEVCNTR_EL0" +#define PMCNTENSET_EL0 96 /* Count Enable Set Register */ +#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */ +#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */ +#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */ Same for these. They are just convenient accessors for the HW register. +#define PMUSERENR_EL0 100 /* User Enable Register */ +#define PMSWINC_EL0101 /* Software Increment Register */ + /* 32bit specific registers. Keep them at the end of the range */ -#defineDACR32_EL2 24 /* Domain Access Control Register */ -#defineIFSR32_EL2 25 /* Instruction Fault Status Register */ -#defineFPEXC32_EL2 26 /* Floating-Point Exception Control Register */ -#defineDBGVCR32_EL227 /* Debug Vector Catch Register */ -#defineNR_SYS_REGS 28 +#defineDACR32_EL2 102 /* Domain Access Control Register */ +#defineIFSR32_EL2 103 /* Instruction Fault Status Register */ +#defineFPEXC32_EL2 104 /* Floating-Point Exception Control Register */ +#defineDBGVCR32_EL2105 /* Debug Vector Catch Register */ +#defineNR_SYS_REGS 106 /* 32bit mapping */ #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ @@ -75,6 +97,24 @@ #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ #define c7_PAR(PAR_EL1 * 2) /* Physical Address Register */ #define c7_PAR_high (c7_PAR + 1)/* PAR top 32 bits */ + +/* Performance Monitors*/ +#define c9_PMCR(PMCR_EL0 * 2) +#define c9_PMOVSSET(PMOVSSET_EL0 * 2) +#define c9_PMOVSCLR(PMOVSCLR_EL0 * 2) +#define c9_PMCCNTR (PMCCNTR_EL0 * 2) +#define c9_PMSELR (PMSELR_EL0 * 2) +#define c9_PMCEID0 (PMCEID0_EL0 * 2) +#define c9_PMCEID1 (PMCEID1_EL0 * 2) +#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2) +#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2) +#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2) +#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2) +#define c9_PMINTENSET (PMINTENSET_EL1 * 2) +#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2) +#define c9_PMUSERENR (PMUSERENR_EL0 * 2) +#define c9_PMSWINC (PMSWINC_EL0 * 2) + #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ @@ -86,6 +126,11 @@ #define c10_AMAIR1(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ #define c14_CNTKCTL (CNTKCTL_EL
Re: [PATCH v5 00/21] KVM: ARM64: Add guest PMU support
Hi Marc,
On 2015/12/7 22:11, Marc Zyngier wrote:
Shannon,
On 03/12/15 06:11, Shannon Zhao wrote:
From: Shannon Zhao <shannon.z...@linaro.org>
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.
Use perf to test this patchset in guest. When using "perf list", it
shows the list of the hardware events and hardware cache events perf
supports. Then use "perf stat -e EVENT" to monitor some event. For
example, use "perf stat -e cycles" to count cpu cycles and
"perf stat -e cache-misses" to count cache misses.
Below are the outputs of "perf stat -r 5 sleep 5" when running in host
and guest.
Host:
Performance counter stats for 'sleep 5' (5 runs):
0.510276 task-clock (msec) #0.000 CPUs utilized
( +- 1.57% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
49 page-faults #0.096 M/sec
( +- 0.77% )
1064117 cycles#2.085 GHz
( +- 1.56% )
stalled-cycles-frontend
stalled-cycles-backend
529051 instructions #0.50 insns per cycle
( +- 0.55% )
branches
9894 branch-misses # 19.390 M/sec
( +- 1.70% )
5.000853900 seconds time elapsed
( +- 0.00% )
Guest:
Performance counter stats for 'sleep 5' (5 runs):
0.642456 task-clock (msec) #0.000 CPUs utilized
( +- 1.81% )
1 context-switches #0.002 M/sec
0 cpu-migrations#0.000 K/sec
49 page-faults #0.076 M/sec
( +- 1.64% )
1322717 cycles#2.059 GHz
( +- 1.88% )
stalled-cycles-frontend
stalled-cycles-backend
640944 instructions #0.48 insns per cycle
( +- 1.10% )
branches
10665 branch-misses # 16.600 M/sec
( +- 2.23% )
5.001181452 seconds time elapsed
( +- 0.00% )
Have a cycle counter read test like below in guest and host:
static void test(void)
{
unsigned long count, count1, count2;
count1 = read_cycles();
count++;
count2 = read_cycles();
}
Host:
count1: 3046186213
count2: 3046186347
delta: 134
Guest:
count1: 5645797121
count2: 5645797270
delta: 149
The gap between guest and host is very small. One reason for this I
think is that it doesn't count the cycles in EL2 and host since we add
exclude_hv = 1. So the cycles spent to store/restore registers which
happens at EL2 are not included.
This patchset can be fetched from [1] and the relevant QEMU version for
test can be fetched from [2].
The results of 'perf test' can be found from [3][4].
The results of perf_event_tests test suite can be found from [5][6].
Also, I have tested "perf top" in two VMs and host at the same time. It
works well.
I've commented on more issues I've found. Hopefully you'll be able to
respin this quickly enough, and end-up with a simpler code base (state
duplication is a bit messy).
Ok, will try my best :)
Another thing I have noticed is that you have dropped the vgic changes
that were configuring the interrupt. It feels like they should be
included, and configure the PPI as a LEVEL interrupt.
The reason why I drop that is in upstream code PPIs are LEVEL interrupt
by default which is changed by the arch_timers patches. So is it
necessary to configure it again?
Also, looking at
your QEMU code, you seem to configure the interrupt as EDGE, which is
now how yor emulated HW behaves.
Sorry, the QEMU code is not updated while the version I use for test
locally configures the interrupt as LEVEL. I will push the newest one
tomorrow.
Looking forward to reviewing the next version.
Thanks,
M.
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Re: [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device
On 2015/12/7 21:56, Marc Zyngier wrote:
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
>+ struct kvm_device_attr *attr)
>+{
>+ switch (attr->group) {
>+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
>+ int __user *uaddr = (int __user *)(long)attr->addr;
>+ int reg;
>+
>+ if (get_user(reg, uaddr))
>+ return -EFAULT;
>+
>+ if (reg < VGIC_NR_SGIS || reg >= VGIC_NR_PRIVATE_IRQS)
>+ return -EINVAL;
>+
>+ return kvm_arm_pmu_set_irq(dev->kvm, reg);
What prevents the IRQ to be changed while the VM is already running?
This should probably be a one-shot thing (change it once, be denied
other changes).
So add a helper like vgic_initialized to check whether vPMU is initialized?
Thanks,
--
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[PATCH v5 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
From: Shannon Zhao <shannon.z...@linaro.org>
When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw event
type to create a perf_event for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/pmu.h | 2 +
arch/arm64/kvm/Makefile | 1 +
include/kvm/arm_pmu.h| 13 +
virt/kvm/arm/pmu.c | 127 +++
4 files changed, 143 insertions(+)
create mode 100644 virt/kvm/arm/pmu.c
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index 4264ea0..e3cb6b3 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -28,6 +28,8 @@
#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
+/* Determines which PMCCNTR_EL0 bit generates an overflow */
+#define ARMV8_PMCR_LC (1 << 6)
#defineARMV8_PMCR_N_SHIFT 11 /* Number of counters
supported */
#defineARMV8_PMCR_N_MASK 0x1f
#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 1949fe5..18d56d8 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -27,3 +27,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o
kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
+kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 0c13470..59d9085 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,4 +38,17 @@ struct kvm_pmu {
#endif
};
+#ifdef CONFIG_KVM_ARM_PMU
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+ u32 select_idx);
+#else
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ return 0;
+}
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+ u32 select_idx) {}
+#endif
+
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
new file mode 100644
index 000..6c50003
--- /dev/null
+++ b/virt/kvm/arm/pmu.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * kvm_pmu_get_counter_value - get PMU counter value
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ */
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ u64 counter, enabled, running;
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc = >pmc[select_idx];
+
+ if (!vcpu_mode_is_32bit(vcpu))
+ counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
+ else
+ counter = vcpu_cp15(vcpu, c14_PMEVCNTR0 + select_idx);
+
+ if (pmc->perf_event)
+ counter += perf_event_read_value(pmc->perf_event, ,
+);
+
+ return counter & pmc->bitmask;
+}
+
+static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+ if (!vcpu_mode_is_32bit(vcpu))
+ return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &
+ (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) >> select_idx);
+ else
+ return (vcpu_sys_reg(vcpu, c9_PMCR) & ARMV8_PMCR_E) &
+ (vcpu_sys_reg(vcpu, c9_PMCNTENSET) >> select_idx);
+}
+
+/**
+ * kvm_pmu_stop_counter - stop PMU counter
+ * @pmc: The PMU counter pointer
+ *
+ * If this counter has been configured to monitor some event, release it here.
+ */
+static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
+{
+ struct kvm_vcpu *vcpu = pmc->vcpu;
+ u64 counter;
+
[PATCH v5 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 1 +
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 21 +
3 files changed, 24 insertions(+)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index cd696ef..cea2176 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -259,6 +259,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
kvm_vgic_vcpu_destroy(vcpu);
+ kvm_pmu_vcpu_destroy(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
}
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index fe8035a..53feebb 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -40,6 +40,7 @@ struct kvm_pmu {
#ifdef CONFIG_KVM_ARM_PMU
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -52,6 +53,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 4014831..bd2fece 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -98,6 +98,27 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
}
/**
+ * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+ int i;
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+ struct kvm_pmc *pmc = >pmc[i];
+
+ if (pmc->perf_event) {
+ perf_event_disable(pmc->perf_event);
+ perf_event_release_kernel(pmc->perf_event);
+ pmc->perf_event = NULL;
+ }
+ }
+}
+
+/**
* kvm_pmu_flush_hwstate - flush pmu state to cpu
* @vcpu: The vcpu pointer
*
--
2.0.4
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[PATCH v5 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register
From: Shannon Zhao <shannon.z...@linaro.org>
Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1f1f6a6..b0a8d88 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -460,6 +460,19 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct
sys_reg_desc *r)
vcpu_sys_reg(vcpu, r->reg) = val;
}
+static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (r->reg == PMCEID0_EL0)
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ /* PMCEID1_EL0 */
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ vcpu_sys_reg(vcpu, r->reg) = pmceid;
+}
+
/* PMU registers accessor. */
static bool access_pmu_regs(struct kvm_vcpu *vcpu,
const struct sys_reg_params *p,
@@ -477,6 +490,9 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) = val;
break;
}
+ case PMCEID0_EL0:
+ case PMCEID1_EL0:
+ return ignore_write(vcpu, p);
default:
vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
break;
@@ -701,10 +717,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID0_EL0 },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID1_EL0 },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -934,6 +950,9 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, r->reg) = val;
break;
}
+ case c9_PMCEID0:
+ case c9_PMCEID1:
+ return ignore_write(vcpu, p);
default:
vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
break;
@@ -991,8 +1010,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
+ NULL, c9_PMCEID0 },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
+ NULL, c9_PMCEID1 },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
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[PATCH v5 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 18 +-
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 44
3 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index eb4fcf9..12f4806 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -567,6 +567,11 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt));
break;
}
+ case PMSWINC_EL0: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_software_increment(vcpu, val);
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -602,6 +607,8 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
*vcpu_reg(vcpu, p->Rt) = val;
break;
}
+ case PMSWINC_EL0:
+ return read_zero(vcpu, p);
case PMCR_EL0: {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_sys_reg(vcpu, r->reg)
@@ -814,7 +821,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMOVSCLR_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMSWINC_EL0 },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
access_pmu_regs, reset_unknown, PMSELR_EL0 },
@@ -1119,6 +1126,11 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt));
break;
}
+ case c9_PMSWINC: {
+ val = *vcpu_reg(vcpu, p->Rt);
+ kvm_pmu_software_increment(vcpu, val);
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1154,6 +1166,8 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
*vcpu_reg(vcpu, p->Rt) = val;
break;
}
+ case c9_PMSWINC:
+ return read_zero(vcpu, p);
case c9_PMCR: {
/* PMCR.P & PMCR.C are RAZ */
val = vcpu_cp15(vcpu, r->reg)
@@ -1206,6 +1220,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
NULL, c9_PMOVSCLR },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmu_cp15_regs,
+ NULL, c9_PMSWINC },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 4f3154c..a54c391 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -44,6 +44,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
#else
@@ -55,6 +56,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val)
{}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {}
void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {}
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx) {}
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 296b4ad..d133909 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -206,6 +206,46 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val)
}
/**
+ * kvm_pmu_software_increment - do software increment
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMSWINC register
+ */
+void kvm_pmu
[PATCH v5 17/21] KVM: ARM64: Add helper to handle PMCR register bits
From: Shannon Zhao <shannon.z...@linaro.org>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 51 +++
3 files changed, 55 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 9320277..405cf70 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -578,6 +578,7 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
val &= ~ARMV8_PMCR_MASK;
val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK;
vcpu_sys_reg(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
break;
}
case PMCEID0_EL0:
@@ -1219,6 +1220,7 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
val &= ~ARMV8_PMCR_MASK;
val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK;
vcpu_cp15(vcpu, r->reg) = val;
+ kvm_pmu_handle_pmcr(vcpu, val);
break;
}
case c9_PMCEID0:
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index a54c391..212a3de 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -47,6 +47,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
@@ -59,6 +60,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx) {}
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val) {}
#endif
#endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index d133909..b81e35e 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -140,6 +140,57 @@ static unsigned long kvm_pmu_valid_counter_mask(struct
kvm_vcpu *vcpu)
}
/**
+ * kvm_pmu_handle_pmcr - handle PMCR register
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMCR register
+ */
+void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ struct kvm_pmc *pmc;
+ u32 enable;
+ int i;
+
+ if (val & ARMV8_PMCR_E) {
+ if (!vcpu_mode_is_32bit(vcpu))
+ enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+ else
+ enable = vcpu_cp15(vcpu, c9_PMCNTENSET);
+
+ kvm_pmu_enable_counter(vcpu, enable, true);
+ } else {
+ kvm_pmu_disable_counter(vcpu, 0xUL);
+ }
+
+ if (val & ARMV8_PMCR_C) {
+ pmc = >pmc[ARMV8_MAX_COUNTERS - 1];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ if (!vcpu_mode_is_32bit(vcpu))
+ vcpu_sys_reg(vcpu, PMCCNTR_EL0) = 0;
+ else
+ vcpu_cp15(vcpu, c9_PMCCNTR) = 0;
+ }
+
+ if (val & ARMV8_PMCR_P) {
+ for (i = 0; i < ARMV8_MAX_COUNTERS - 1; i++) {
+ pmc = >pmc[i];
+ if (pmc->perf_event)
+ local64_set(>perf_event->count, 0);
+ if (!vcpu_mode_is_32bit(vcpu))
+ vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = 0;
+ else
+ vcpu_cp15(vcpu, c14_PMEVCNTR0 + i) = 0;
+ }
+ }
+
+ if (val & ARMV8_PMCR_LC) {
+ pmc = >pmc[ARMV8_MAX_COUNTERS - 1];
+ pmc->bitmask = 0xUL;
+ }
+}
+
+/**
* kvm_pmu_overflow_clear - clear PMU overflow interrupt
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMOVSCLR register
--
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[PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu
From: Shannon Zhao <shannon.z...@linaro.org>
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters.
Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/kvm/Kconfig| 8
include/kvm/arm_pmu.h | 41 +++
3 files changed, 51 insertions(+)
create mode 100644 include/kvm/arm_pmu.h
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index a35ce72..42e15bb 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -37,6 +37,7 @@
#include
#include
+#include
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
@@ -132,6 +133,7 @@ struct kvm_vcpu_arch {
/* VGIC state */
struct vgic_cpu vgic_cpu;
struct arch_timer_cpu timer_cpu;
+ struct kvm_pmu pmu;
/*
* Anything that is not used directly from assembly code goes
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index a5272c0..66da9a2 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -36,6 +36,7 @@ config KVM
select HAVE_KVM_EVENTFD
select HAVE_KVM_IRQFD
select KVM_ARM_VGIC_V3
+ select KVM_ARM_PMU
---help---
Support hosting virtualized guest machines.
We don't support KVM with 16K page tables yet, due to the multiple
@@ -48,6 +49,13 @@ config KVM_ARM_HOST
---help---
Provides host support for ARM processors.
+config KVM_ARM_PMU
+ bool
+ depends on KVM_ARM_HOST && HW_PERF_EVENTS
+ ---help---
+ Adds support for a virtual Performance Monitoring Unit (PMU) in
+ virtual machines.
+
source drivers/vhost/Kconfig
endif # VIRTUALIZATION
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
new file mode 100644
index 000..0c13470
--- /dev/null
+++ b/include/kvm/arm_pmu.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao <shannon.z...@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARM_KVM_PMU_H
+#define __ASM_ARM_KVM_PMU_H
+
+#include
+#ifdef CONFIG_KVM_ARM_PMU
+#include
+#endif
+
+struct kvm_pmc {
+ u8 idx;/* index into the pmu->pmc array */
+ struct perf_event *perf_event;
+ struct kvm_vcpu *vcpu;
+ u64 bitmask;
+};
+
+struct kvm_pmu {
+#ifdef CONFIG_KVM_ARM_PMU
+ /* PMU IRQ Number per VCPU */
+ int irq_num;
+ struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
+#endif
+};
+
+#endif
--
2.0.4
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[PATCH v5 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register
From: Shannon Zhao <shannon.z...@linaro.org>
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, pend PMU interrupt. When the
value writing to PMOVSCLR is equal to the current value, clear the PMU
pending interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 25 +--
include/kvm/arm_pmu.h | 4 +++
virt/kvm/arm/pmu.c| 80 +++
3 files changed, 106 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a4f9177..f5e0732 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -559,6 +559,14 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
break;
}
+ case PMOVSSET_EL0: {
+ kvm_pmu_overflow_set(vcpu, *vcpu_reg(vcpu, p->Rt));
+ break;
+ }
+ case PMOVSCLR_EL0: {
+ kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt));
+ break;
+ }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -803,7 +811,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSCLR_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
trap_raz_wi },
@@ -830,7 +838,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -1103,6 +,14 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val;
break;
}
+ case c9_PMOVSSET: {
+ kvm_pmu_overflow_set(vcpu, *vcpu_reg(vcpu, p->Rt));
+ break;
+ }
+ case c9_PMOVSCLR: {
+ kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt));
+ break;
+ }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1188,7 +1204,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMCNTENSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
NULL, c9_PMCNTENCLR },
- { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
+ NULL, c9_PMOVSCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
NULL, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
@@ -1206,6 +1223,8 @@ static const struct sys_reg_desc cp15_regs[] = {
NULL, c9_PMINTENSET },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
NULL, c9_PMINTENCLR },
+ { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmu_cp15_regs,
+ NULL, c9_PMOVSSET },
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index fff8f15..4f3154c 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -42,6 +42,8 @@ struct kvm_pmu {
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
+void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
#else
@@ -51,6 +53,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu
*vcpu, u32 select_idx)
}
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {}
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {}
+void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {}
+void kvm_pmu_overflow_set(st
[PATCH v5 18/21] KVM: ARM64: Add PMU overflow interrupt routing
From: Shannon Zhao <shannon.z...@linaro.org>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, call
kvm_vcpu_kick() to sync the interrupt.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm/kvm/arm.c| 2 ++
include/kvm/arm_pmu.h | 2 ++
virt/kvm/arm/pmu.c| 52 ++-
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index e06fd29..cd696ef 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -569,6 +570,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct
kvm_run *run)
* non-preemptible context.
*/
preempt_disable();
+ kvm_pmu_flush_hwstate(vcpu);
kvm_timer_flush_hwstate(vcpu);
kvm_vgic_flush_hwstate(vcpu);
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 212a3de..4cb0ade 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,7 @@ struct kvm_pmu {
};
#ifdef CONFIG_KVM_ARM_PMU
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable);
@@ -49,6 +50,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
u32 select_idx);
void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
#else
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
{
return 0;
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index b81e35e..34e7386 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
/**
* kvm_pmu_get_counter_value - get PMU counter value
@@ -79,6 +80,54 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
}
/**
+ * kvm_pmu_flush_hwstate - flush pmu state to cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
+ */
+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+ struct kvm_pmu *pmu = >arch.pmu;
+ u32 overflow;
+
+ if (pmu->irq_num == -1)
+ return;
+
+ if (!vcpu_mode_is_32bit(vcpu)) {
+ if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E))
+ return;
+
+ overflow = vcpu_sys_reg(vcpu, PMCNTENSET_EL0)
+ & vcpu_sys_reg(vcpu, PMINTENSET_EL1)
+ & vcpu_sys_reg(vcpu, PMOVSSET_EL0);
+ } else {
+ if (!(vcpu_cp15(vcpu, c9_PMCR) & ARMV8_PMCR_E))
+ return;
+
+ overflow = vcpu_cp15(vcpu, c9_PMCNTENSET)
+ & vcpu_cp15(vcpu, c9_PMINTENSET)
+ & vcpu_cp15(vcpu, c9_PMOVSSET);
+ }
+
+ kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num,
+ overflow ? 1 : 0);
+}
+
+/**
+ * When perf event overflows, call kvm_pmu_overflow_set to set overflow status.
+ */
+static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+ struct kvm_vcpu *vcpu = pmc->vcpu;
+ int idx = pmc->idx;
+
+ kvm_pmu_overflow_set(vcpu, BIT(idx));
+}
+
+/**
* kvm_pmu_enable_counter - enable selected PMU counter
* @vcpu: The vcpu pointer
* @val: the value guest writes to PMCNTENSET register
@@ -338,7 +387,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
/* The initial sample period (overflow count) of an event. */
attr.sample_period = (-counter) & pmc->bitmask;
- event = perf_event_create_kernel_counter(, -1, current, NULL, pmc);
+ event = perf_event_create_kernel_counter(, -1, current,
+kvm_pmu_perf_overflow, pmc);
if (IS_ERR(event)) {
printk_once("kvm: pmu event creation failed %ld\n",
PTR_ERR(event));
--
2.0.4
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[PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device
From: Shannon Zhao <shannon.z...@linaro.org>
Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
Documentation/virtual/kvm/devices/arm-pmu.txt | 16 +
arch/arm64/include/uapi/asm/kvm.h | 3 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 2 +
virt/kvm/arm/pmu.c| 87 +++
virt/kvm/kvm_main.c | 4 ++
6 files changed, 113 insertions(+)
create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt
diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt
b/Documentation/virtual/kvm/devices/arm-pmu.txt
new file mode 100644
index 000..5121f1f
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
@@ -0,0 +1,16 @@
+ARM Virtual Performance Monitor Unit (vPMU)
+===
+
+Device types supported:
+ KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
+
+Instantiate one PMU instance for per VCPU through this API.
+
+Groups:
+ KVM_DEV_ARM_PMU_GRP_IRQ
+ Attributes:
+A value describing the interrupt number of PMU overflow interrupt. This
+interrupt should be a PPI.
+
+ Errors:
+-EINVAL: Value set is out of the expected range (from 16 to 31)
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index 2d4ca4b..568afa2 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+/* Device Control API: ARM PMU */
+#define KVM_DEV_ARM_PMU_GRP_IRQ0
+
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
#define KVM_ARM_IRQ_TYPE_MASK 0xff
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index c923350..608dea6 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
extern struct kvm_device_ops kvm_xics_ops;
extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
+extern struct kvm_device_ops kvm_arm_pmu_ops;
#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 03f3618..4ba6fdd 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1032,6 +1032,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
+ KVM_DEV_TYPE_ARM_PMU_V3,
+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
KVM_DEV_TYPE_MAX,
};
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index bd2fece..82b90e8 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -19,10 +19,13 @@
#include
#include
#include
+#include
#include
#include
#include
+#include "vgic.h"
+
/**
* kvm_pmu_get_counter_value - get PMU counter value
* @vcpu: The vcpu pointer
@@ -436,3 +439,87 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
u32 data,
pmc->perf_event = event;
}
+
+static int kvm_arm_pmu_set_irq(struct kvm *kvm, int irq)
+{
+ int j;
+ struct kvm_vcpu *vcpu;
+
+ kvm_for_each_vcpu(j, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
+ pmu->irq_num = irq;
+ }
+
+ return 0;
+}
+
+static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type)
+{
+ int i;
+ struct kvm_vcpu *vcpu;
+ struct kvm *kvm = dev->kvm;
+
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ struct kvm_pmu *pmu = >arch.pmu;
+
+ memset(pmu, 0, sizeof(*pmu));
+ kvm_pmu_vcpu_reset(vcpu);
+ pmu->irq_num = -1;
+ }
+
+ return 0;
+}
+
+static void kvm_arm_pmu_destroy(struct kvm_device *dev)
+{
+ kfree(dev);
+}
+
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
+ struct kvm_device_attr *attr)
+{
+ switch (attr->group) {
+ case KVM_DEV_ARM_PMU_GRP_IRQ: {
+ int __user *uaddr = (int __user *)(long)attr->addr;
+ int reg;
+
+ if (get_user(reg, uaddr))
+ return -EFAULT;
+
+ if (reg < VGIC_NR_SGIS || reg >= VGIC_NR_PRIVATE_IRQS)
+ return -EINVAL;
+
+ return kvm_arm_pmu_set_irq(dev->kvm, reg);
+ }
+ }
+
+ return -ENXIO;
+}
+
+static int kvm_arm_pmu_get_attr(struct kvm_device *dev,
+ struct kvm_device_attr *attr)
+{
+ retur
[PATCH v5 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register
From: Shannon Zhao <shannon.z...@linaro.org>
Add access handler which emulates writing and reading PMEVCNTRn and
PMEVTYPERn.
Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 164 ++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 12f4806..9320277 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -640,6 +640,20 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
+/* Macro to expand the PMEVCNTRn_EL0 register */
+#define PMU_PMEVCNTR_EL0(n)\
+ /* PMEVCNTRn_EL0 */ \
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVCNTR0_EL0 + n), }
+
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n) \
+ /* PMEVTYPERn_EL0 */\
+ { Op0(0b11), Op1(0b011), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -854,6 +868,74 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* PMEVCNTRn_EL0 */
+ PMU_PMEVCNTR_EL0(0),
+ PMU_PMEVCNTR_EL0(1),
+ PMU_PMEVCNTR_EL0(2),
+ PMU_PMEVCNTR_EL0(3),
+ PMU_PMEVCNTR_EL0(4),
+ PMU_PMEVCNTR_EL0(5),
+ PMU_PMEVCNTR_EL0(6),
+ PMU_PMEVCNTR_EL0(7),
+ PMU_PMEVCNTR_EL0(8),
+ PMU_PMEVCNTR_EL0(9),
+ PMU_PMEVCNTR_EL0(10),
+ PMU_PMEVCNTR_EL0(11),
+ PMU_PMEVCNTR_EL0(12),
+ PMU_PMEVCNTR_EL0(13),
+ PMU_PMEVCNTR_EL0(14),
+ PMU_PMEVCNTR_EL0(15),
+ PMU_PMEVCNTR_EL0(16),
+ PMU_PMEVCNTR_EL0(17),
+ PMU_PMEVCNTR_EL0(18),
+ PMU_PMEVCNTR_EL0(19),
+ PMU_PMEVCNTR_EL0(20),
+ PMU_PMEVCNTR_EL0(21),
+ PMU_PMEVCNTR_EL0(22),
+ PMU_PMEVCNTR_EL0(23),
+ PMU_PMEVCNTR_EL0(24),
+ PMU_PMEVCNTR_EL0(25),
+ PMU_PMEVCNTR_EL0(26),
+ PMU_PMEVCNTR_EL0(27),
+ PMU_PMEVCNTR_EL0(28),
+ PMU_PMEVCNTR_EL0(29),
+ PMU_PMEVCNTR_EL0(30),
+ /* PMEVTYPERn_EL0 */
+ PMU_PMEVTYPER_EL0(0),
+ PMU_PMEVTYPER_EL0(1),
+ PMU_PMEVTYPER_EL0(2),
+ PMU_PMEVTYPER_EL0(3),
+ PMU_PMEVTYPER_EL0(4),
+ PMU_PMEVTYPER_EL0(5),
+ PMU_PMEVTYPER_EL0(6),
+ PMU_PMEVTYPER_EL0(7),
+ PMU_PMEVTYPER_EL0(8),
+ PMU_PMEVTYPER_EL0(9),
+ PMU_PMEVTYPER_EL0(10),
+ PMU_PMEVTYPER_EL0(11),
+ PMU_PMEVTYPER_EL0(12),
+ PMU_PMEVTYPER_EL0(13),
+ PMU_PMEVTYPER_EL0(14),
+ PMU_PMEVTYPER_EL0(15),
+ PMU_PMEVTYPER_EL0(16),
+ PMU_PMEVTYPER_EL0(17),
+ PMU_PMEVTYPER_EL0(18),
+ PMU_PMEVTYPER_EL0(19),
+ PMU_PMEVTYPER_EL0(20),
+ PMU_PMEVTYPER_EL0(21),
+ PMU_PMEVTYPER_EL0(22),
+ PMU_PMEVTYPER_EL0(23),
+ PMU_PMEVTYPER_EL0(24),
+ PMU_PMEVTYPER_EL0(25),
+ PMU_PMEVTYPER_EL0(26),
+ PMU_PMEVTYPER_EL0(27),
+ PMU_PMEVTYPER_EL0(28),
+ PMU_PMEVTYPER_EL0(29),
+ PMU_PMEVTYPER_EL0(30),
+ /* PMCCFILTR_EL0 */
+ { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b), Op2(0b111),
+ access_pmu_regs, reset_unknown, PMCCFILTR_EL0, },
+
/* DACR32_EL2 */
{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b), Op2(0b000),
NULL, reset_unknown, DACR32_EL2 },
@@ -1184,6 +1266,20 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
return true;
}
+/* Macro to expand the PMEVCNTRn register */
+#define PMU_PMEVCNTR(n)
\
+ /* PMEVCNTRn */ \
+ { Op1(0), CRn(0b1110), \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_cp15_regs, NULL, (c14_PMEVCNTR0 + n), }
+
+/* Macro to expand the PMEVTYPERn register */
+#define PMU_PMEVTYPER(n) \
+ /* PMEVTYPERn */\
+ { Op1(0), CRn(0b1110), \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_cp15_regs, NULL, (c14_
