Re: [Qemu-devel] [PATCH v3 15/39] e1000: convert to memory API
On 08/04/2011 08:06 AM, Avi Kivity wrote:
Reviewed-by: Richard Hendersonr...@twiddle.net
Signed-off-by: Avi Kivitya...@redhat.com
Reviewed-by: Anthony Liguori aligu...@us.ibm.com
Regards,
Anthony Liguori
---
hw/e1000.c | 114 +--
1 files changed, 48 insertions(+), 66 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index 96d84f9..dfc082b 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -82,7 +82,8 @@ typedef struct E1000State_st {
PCIDevice dev;
NICState *nic;
NICConf conf;
-int mmio_index;
+MemoryRegion mmio;
+MemoryRegion io;
uint32_t mac_reg[0x8000];
uint16_t phy_reg[0x20];
@@ -151,14 +152,6 @@ static const char phy_regcap[0x20] = {
};
static void
-ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
- pcibus_t size, int type)
-{
-DBGOUT(IO, e1000_ioport_map addr=0x%04FMT_PCIBUS
-size=0x%08FMT_PCIBUS\n, addr, size);
-}
-
-static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
if (val)
@@ -905,7 +898,8 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr 0x1) 2;
@@ -913,31 +907,15 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
if (index NWRITEOPS macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index NREADOPS macreg_readops[index]) {
-DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04x\n, index2, val);
+DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04PRIx64\n, index2,
val);
} else {
-DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08x\n,
+DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08PRIx64\n,
index2, val);
}
}
-static void
-e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr ~3,
- (val 0x) (8*(addr 3)));
-}
-
-static void
-e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr ~3,
- (val 0xff) (8*(addr 3)));
-}
-
-static uint32_t
-e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t
+e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr 0x1) 2;
@@ -950,20 +928,39 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
-static uint32_t
-e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
+static const MemoryRegionOps e1000_mmio_ops = {
+.read = e1000_mmio_read,
+.write = e1000_mmio_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr ~3))
-(8 * (addr 3))) 0xff;
+E1000State *s = opaque;
+
+(void)s;
+return 0;
}
-static uint32_t
-e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr ~3))
-(8 * (addr 3))) 0x;
+E1000State *s = opaque;
+
+(void)s;
}
+static const MemoryRegionOps e1000_io_ops = {
+.read = e1000_io_read,
+.write = e1000_io_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
@@ -1083,36 +1080,22 @@ static const uint32_t mac_reg_init[] = {
/* PCI interface */
-static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
-e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
-};
-
-static CPUReadMemoryFunc * const e1000_mmio_read[] = {
-e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
-};
-
static void
-e1000_mmio_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+e1000_mmio_setup(E1000State *d)
{
-E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
int i;
const uint32_t excluded_regs[] = {
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
};
-
-DBGOUT(MMIO, e1000_mmio_map addr=0x%08FMT_PCIBUS 0x%08FMT_PCIBUS\n,
- addr, size);
-
-cpu_register_physical_memory(addr, PNPMMIO_SIZE, d-mmio_index);
-
[PATCH v3 15/39] e1000: convert to memory API
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/e1000.c | 114 +--
1 files changed, 48 insertions(+), 66 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index 96d84f9..dfc082b 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -82,7 +82,8 @@ typedef struct E1000State_st {
PCIDevice dev;
NICState *nic;
NICConf conf;
-int mmio_index;
+MemoryRegion mmio;
+MemoryRegion io;
uint32_t mac_reg[0x8000];
uint16_t phy_reg[0x20];
@@ -151,14 +152,6 @@ static const char phy_regcap[0x20] = {
};
static void
-ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
- pcibus_t size, int type)
-{
-DBGOUT(IO, e1000_ioport_map addr=0x%04FMT_PCIBUS
-size=0x%08FMT_PCIBUS\n, addr, size);
-}
-
-static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
if (val)
@@ -905,7 +898,8 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr 0x1) 2;
@@ -913,31 +907,15 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
if (index NWRITEOPS macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index NREADOPS macreg_readops[index]) {
-DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04x\n, index2, val);
+DBGOUT(MMIO, e1000_mmio_writel RO %x: 0x%04PRIx64\n, index2,
val);
} else {
-DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08x\n,
+DBGOUT(UNKNOWN, MMIO unknown write addr=0x%08x,val=0x%08PRIx64\n,
index2, val);
}
}
-static void
-e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr ~3,
- (val 0x) (8*(addr 3)));
-}
-
-static void
-e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-// emulate hw without byte enables: no RMW
-e1000_mmio_writel(opaque, addr ~3,
- (val 0xff) (8*(addr 3)));
-}
-
-static uint32_t
-e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t
+e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr 0x1) 2;
@@ -950,20 +928,39 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
return 0;
}
-static uint32_t
-e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
+static const MemoryRegionOps e1000_mmio_ops = {
+.read = e1000_mmio_read,
+.write = e1000_mmio_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+};
+
+static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr ~3))
-(8 * (addr 3))) 0xff;
+E1000State *s = opaque;
+
+(void)s;
+return 0;
}
-static uint32_t
-e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
+static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
-return ((e1000_mmio_readl(opaque, addr ~3))
-(8 * (addr 3))) 0x;
+E1000State *s = opaque;
+
+(void)s;
}
+static const MemoryRegionOps e1000_io_ops = {
+.read = e1000_io_read,
+.write = e1000_io_write,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
@@ -1083,36 +1080,22 @@ static const uint32_t mac_reg_init[] = {
/* PCI interface */
-static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
-e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
-};
-
-static CPUReadMemoryFunc * const e1000_mmio_read[] = {
-e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
-};
-
static void
-e1000_mmio_map(PCIDevice *pci_dev, int region_num,
-pcibus_t addr, pcibus_t size, int type)
+e1000_mmio_setup(E1000State *d)
{
-E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
int i;
const uint32_t excluded_regs[] = {
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
};
-
-DBGOUT(MMIO, e1000_mmio_map addr=0x%08FMT_PCIBUS 0x%08FMT_PCIBUS\n,
- addr, size);
-
-cpu_register_physical_memory(addr, PNPMMIO_SIZE, d-mmio_index);
-qemu_register_coalesced_mmio(addr, excluded_regs[0]);
-
+memory_region_init_io(d-mmio, e1000_mmio_ops, d, e1000-mmio,
+
