Re: [PATCH 13/38] KVM: PPC: booke: category E.HV (GS-mode) support
+/* + * Host interrupt handlers may have clobbered these guest-readable + * SPRGs, so we need to reload them here with the guest's values. + */ +lwz r3, VCPU_VRSAVE(r4) +lwz r5, VCPU_SHARED_SPRG4(r11) +mtspr SPRN_VRSAVE, r3 +lwz r6, VCPU_SHARED_SPRG5(r11) +mtspr SPRN_SPRG4W, r5 +lwz r7, VCPU_SHARED_SPRG6(r11) +mtspr SPRN_SPRG5W, r6 +lwz r8, VCPU_SHARED_SPRG7(r11) +mtspr SPRN_SPRG6W, r7 +mtspr SPRN_SPRG7W, r8 + That should be here. +/* Load some guest volatiles. */ +PPC_LL r3, VCPU_LR(r4) +PPC_LL r5, VCPU_XER(r4) +PPC_LL r6, VCPU_CTR(r4) +PPC_LL r7, VCPU_CR(r4) +PPC_LL r8, VCPU_PC(r4) +#ifndef CONFIG_64BIT +lwz r9, (VCPU_SHARED_MSR + 4)(r11) +#else +ld r9, (VCPU_SHARED_MSR)(r11) +#endif +PPC_LL r0, VCPU_GPR(r0)(r4) +PPC_LL r1, VCPU_GPR(r1)(r4) +PPC_LL r2, VCPU_GPR(r2)(r4) +PPC_LL r10, VCPU_GPR(r10)(r4) +PPC_LL r11, VCPU_GPR(r11)(r4) +PPC_LL r12, VCPU_GPR(r12)(r4) +PPC_LL r13, VCPU_GPR(r13)(r4) +mtlrr3 +mtxer r5 +mtctr r6 +mtcrr7 +mtsrr0 r8 +mtsrr1 r9 + +#ifdef CONFIG_KVM_EXIT_TIMING +/* save enter time */ +1: +mfspr r6, SPRN_TBRU +mfspr r7, SPRN_TBRL +mfspr r8, SPRN_TBRU +cmpwr8, r6 Is not we should save guest CR after this otherwise this can corrupt it? I think this should be a typo since in our previous kvm implementation, we always did collect kvm exit timing at the above location :) Tiejun Thanks -Bharat +PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4) +bne 1b +PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4) +#endif + +/* Finish loading guest volatiles and jump to guest. */ +PPC_LL r5, VCPU_GPR(r5)(r4) +PPC_LL r6, VCPU_GPR(r6)(r4) +PPC_LL r7, VCPU_GPR(r7)(r4) +PPC_LL r8, VCPU_GPR(r8)(r4) +PPC_LL r9, VCPU_GPR(r9)(r4) + +PPC_LL r3, VCPU_GPR(r3)(r4) +PPC_LL r4, VCPU_GPR(r4)(r4) +rfi -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Restore guest CR after exit timing calculation
No instruction which can change Condition Register (CR) should be executed after Guest CR is loaded. So the guest CR is restored after the Exit Timing in lightweight_exit executes cmpw, which can clobber CR. Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com --- This patch is against e500mc branch. arch/powerpc/kvm/bookehv_interrupts.S | 11 --- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 63fc5f0..6b9389f 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -574,7 +574,6 @@ lightweight_exit: mtlrr3 mtxer r5 mtctr r6 - mtcrr7 mtsrr0 r8 mtsrr1 r9 @@ -582,14 +581,20 @@ lightweight_exit: /* save enter time */ 1: mfspr r6, SPRN_TBRU - mfspr r7, SPRN_TBRL + mfspr r9, SPRN_TBRL mfspr r8, SPRN_TBRU cmpwr8, r6 - PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4) + PPC_STL r9, VCPU_TIMING_LAST_ENTER_TBL(r4) bne 1b PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4) #endif + /* +* Don't execute any instruction which can change CR after +* below instruction. +*/ + mtcrr7 + /* Finish loading guest volatiles and jump to guest. */ PPC_LL r5, VCPU_GPR(r5)(r4) PPC_LL r6, VCPU_GPR(r6)(r4) -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] KVM: PPC: Save/Restore CR over vcpu_run
On PPC, CR2-CR4 are nonvolatile, thus have to be saved across function calls. We didn't respect that for any architecture until Paul spotted it in his patch for Book3S-HV. This patch saves/restores CR for all KVM capable PPC hosts. Signed-off-by: Alexander Graf ag...@suse.de --- arch/powerpc/kvm/book3s_interrupts.S |7 +++ arch/powerpc/kvm/booke_interrupts.S |7 ++- arch/powerpc/kvm/bookehv_interrupts.S |8 +++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S index 0a8515a..3e35383 100644 --- a/arch/powerpc/kvm/book3s_interrupts.S +++ b/arch/powerpc/kvm/book3s_interrupts.S @@ -84,6 +84,10 @@ kvm_start_entry: /* Save non-volatile registers (r14 - r31) */ SAVE_NVGPRS(r1) + /* Save CR */ + mfcrr14 + stw r14, _CCR(r1) + /* Save LR */ PPC_STL r0, _LINK(r1) @@ -165,6 +169,9 @@ kvm_exit_loop: PPC_LL r4, _LINK(r1) mtlrr4 + lwz r14, _CCR(r1) + mtcrr14 + /* Restore non-volatile host registers (r14 - r31) */ REST_NVGPRS(r1) diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S index 10d8ef6..c8c4b87 100644 --- a/arch/powerpc/kvm/booke_interrupts.S +++ b/arch/powerpc/kvm/booke_interrupts.S @@ -34,7 +34,8 @@ /* r2 is special: it holds 'current', and it made nonvolatile in the * kernel with the -ffixed-r2 gcc option. */ #define HOST_R2 12 -#define HOST_NV_GPRS16 +#define HOST_CR 16 +#define HOST_NV_GPRS20 #define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4)) #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + 4) #define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */ @@ -296,8 +297,10 @@ heavyweight_exit: /* Return to kvm_vcpu_run(). */ lwz r4, HOST_STACK_LR(r1) + lwz r5, HOST_CR(r1) addir1, r1, HOST_STACK_SIZE mtlrr4 + mtcrr5 /* r3 still contains the return code from kvmppc_handle_exit(). */ blr @@ -314,6 +317,8 @@ _GLOBAL(__kvmppc_vcpu_run) stw r3, HOST_RUN(r1) mflrr3 stw r3, HOST_STACK_LR(r1) + mfcrr5 + stw r5, HOST_CR(r1) /* Save host non-volatile register state to stack. */ stw r14, HOST_NV_GPR(r14)(r1) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 63fc5f0..3989b5a 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -49,7 +49,8 @@ * kernel with the -ffixed-r2 gcc option. */ #define HOST_R2 (3 * LONGBYTES) -#define HOST_NV_GPRS(4 * LONGBYTES) +#define HOST_CR (4 * LONGBYTES) +#define HOST_NV_GPRS(5 * LONGBYTES) #define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES)) #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES) #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) ~15) /* Align. */ @@ -396,6 +397,7 @@ skip_nv_load: heavyweight_exit: /* Not returning to guest. */ PPC_LL r5, HOST_STACK_LR(r1) + lwz r6, HOST_CR(r1) /* * We already saved guest volatile register state; now save the @@ -442,6 +444,7 @@ heavyweight_exit: /* Return to kvm_vcpu_run(). */ mtlrr5 + mtcrr6 addir1, r1, HOST_STACK_SIZE /* r3 still contains the return code from kvmppc_handle_exit(). */ blr @@ -459,6 +462,9 @@ _GLOBAL(__kvmppc_vcpu_run) mflrr3 PPC_STL r3, HOST_STACK_LR(r1) + mfcrr5 + stw r5, HOST_CR(r1) + /* Save host non-volatile register state to stack. */ PPC_STL r14, HOST_NV_GPR(r14)(r1) PPC_STL r15, HOST_NV_GPR(r15)(r1) -- 1.6.0.2 -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] KVM: PPC: check error return of kvmppc_core_vcpu_create first
On 02/21/2012 05:30 AM, Ben Collins wrote: The result of kvmppc_core_vcpu_create() was being manipulated before it was checked for IS_ERR(). Did not see the bug occur, but caught it when looking through the code. Nice catch, but this has already been fixed by Matt: commit c6f3830e7313eea47b526b597aadc5b18c69ad55 Author: Matt Evans m...@ozlabs.org Date: Tue Dec 6 21:19:42 2011 + KVM: PPC: Fix vcpu_create dereference before validity check. Fix usage of vcpu struct before check that it's actually valid. Signed-off-by: Matt Evans m...@ozlabs.org Signed-off-by: Alexander Graf ag...@suse.de Thanks a lot for sending the patch nevertheless! Alex -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] KVM: PPC: Book3S HV: Save and restore CR in __kvmppc_vcore_entry
On 02/03/2012 11:53 AM, Paul Mackerras wrote: The ABI specifies that CR fields CR2--CR4 are nonvolatile across function calls. Currently __kvmppc_vcore_entry doesn't save and restore the CR, leading to CR2--CR4 getting corrupted with guest values, possibly leading to incorrect behaviour in its caller. This adds instructions to save and restore CR at the points where we save and restore the nonvolatile GPRs. Signed-off-by: Paul Mackerraspau...@samba.org Thanks, applied all to kvm-ppc-next. Please CC kvm@vger when you send patches. Failing to do so might mean the whole pull request gets blocked by Avi when it gets to him, because he doesn't read kvm-ppc@vger. Alex -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] KVM: PPC: Book3s: PR: Add SPAPR H_BULK_REMOVE support
On 01/31/2012 07:25 AM, Matt Evans wrote: SPAPR support includes various in-kernel hypercalls, improving performance by cutting out the exit to userspace. H_BULK_REMOVE is implemented in this patch. Signed-off-by: Matt Evansm...@ozlabs.org Thanks, applied to kvm-ppc-next. Alex -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Emulating lwarx and stwcx instructions in PowerPc BOOKE e500
Hi
I'm working on powerpc booke architecture and my project requires me to remove
read and write privileges on some pages. Due to this any instruction accessing
these pages traps and i'm trying to emulate the behavior of these instructions.
I've emulated lwarx and stwcx instruction but i think stwcx is not working
correctly. The emulation i've written is written below
case OP_31_XOP_LWARX:
{
ulong ret;
ulong addr;
int eh = inst 0x0001 ;
kvm_gva_to_hva(vcpu,ea,addr);
/*lwarx RT RA RB EH*/
if(eh == 0)
__asm__ __volatile__(lwarx %0,0,%1,0; isync:=r (ret) :r (addr));
else
__asm__ __volatile__(lwarx %0,0,%1,1; isync:=r (ret) :r (addr));
kvmppc_set_gpr(vcpu,rt,ret);
}
case OP_31_XOP_STWCX:
{
ulong tmp;
ulong addr;
ulong data;
kvm_gva_to_hva(vcpu,ea,addr);
kvmppc_read_guest(vcpu,ea,data,sizeof(data));
__asm__ __volatile__(stwcx. %1,0,%2; isync
:=r (tmp):r (data),r (addr):memory);
}
Here kvm_gva_to_hva function convrets a guest effective address to host virtual
address .
void kvm_gva_to_hva(struct kvm_vcpu *vcpu, ulong ea,ulong* hva)
{
gfn_t gfn;
gpa_t gpa ;
int gtlb_index;
int offset;
ulong addr;
struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
gtlb_index = kvmppc_mmu_itlb_index(vcpu, ea);
gpa = kvmppc_mmu_xlate(vcpu,gtlb_index, ea);
gfn = gpa PAGE_SHIFT;
addr = (ulong)gfn_to_hva(vcpu_e500-vcpu.kvm, gfn);
offset = offset_in_page(gpa);
*hva = addr + offset;
return;
}
The guest just hangs once it encounters a stwcx instruction. Does anybody have
any idea why this is not working and what's wrong about the emulation code.
Also i'm working on linux-3.0-rc4 kernel .
Thanks in advance
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Re: Emulating lwarx and stwcx instructions in PowerPc BOOKE e500
On 03/05/2012 02:37 PM, Aashish Mittal wrote:
Hi
I'm working on powerpc booke architecture and my project requires me to remove
read and write privileges on some pages. Due to this any instruction accessing
these pages traps and i'm trying to emulate the behavior of these
instructions.
I've emulated lwarx and stwcx instruction but i think stwcx is not working
correctly. The emulation i've written is written below
What is it you're emulating that needs lwarx/stwcx to work?
case OP_31_XOP_LWARX:
{
ulong ret;
ulong addr;
int eh = inst 0x0001 ;
kvm_gva_to_hva(vcpu,ea,addr);
/*lwarx RT RA RB EH*/
if(eh == 0)
__asm__ __volatile__(lwarx %0,0,%1,0; isync:=r (ret) :r (addr));
else
__asm__ __volatile__(lwarx %0,0,%1,1; isync:=r (ret) :r (addr));
kvmppc_set_gpr(vcpu,rt,ret);
}
case OP_31_XOP_STWCX:
{
ulong tmp;
ulong addr;
ulong data;
kvm_gva_to_hva(vcpu,ea,addr);
kvmppc_read_guest(vcpu,ea,data,sizeof(data));
__asm__ __volatile__(stwcx. %1,0,%2; isync
:=r (tmp):r (data),r (addr):memory);
}
Here kvm_gva_to_hva function convrets a guest effective address to host
virtual
address .
void kvm_gva_to_hva(struct kvm_vcpu *vcpu, ulong ea,ulong* hva)
{
gfn_t gfn;
gpa_t gpa ;
int gtlb_index;
int offset;
ulong addr;
struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
gtlb_index = kvmppc_mmu_itlb_index(vcpu, ea);
gpa = kvmppc_mmu_xlate(vcpu,gtlb_index, ea);
gfn = gpa PAGE_SHIFT;
addr = (ulong)gfn_to_hva(vcpu_e500-vcpu.kvm, gfn);
offset = offset_in_page(gpa);
*hva = addr + offset;
return;
}
The guest just hangs once it encounters a stwcx instruction. Does anybody have
any idea why this is not working and what's wrong about the emulation code.
You're losing the reservation somewhere. Any lock or atomic operation
along the emulation path will do this.
Even if this didn't happen by accident, we really don't want to leave a
reservation when we return to the guest -- it could have belonged to a
previously running guest operating on shared memory, for example.
Perhaps we should have a dummy stwcx on KVM guest entry code, similar to
the one on interrupt return?
Also i'm working on linux-3.0-rc4 kernel .
Why are you working on something other than the current code or a stable
release?
-Scott
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Re: [PATCH] KVM: PPC: Save/Restore CR over vcpu_run
On 03/05/2012 10:02 AM, Alexander Graf wrote: @@ -442,6 +444,7 @@ heavyweight_exit: /* Return to kvm_vcpu_run(). */ mtlrr5 + mtcrr6 addir1, r1, HOST_STACK_SIZE /* r3 still contains the return code from kvmppc_handle_exit(). */ blr @@ -459,6 +462,9 @@ _GLOBAL(__kvmppc_vcpu_run) mflrr3 PPC_STL r3, HOST_STACK_LR(r1) + mfcrr5 + stw r5, HOST_CR(r1) If you move the mfcr before the PPC_STL they should be able to run in parallel. Otherwise on e500mc mfcr will wait for PPC_STL to take its 3 cycles and then mfcr will take 5 cyles before the stw of HOST_CR. Alternatively, consider using mcrf/mtocrf three times. Similar issues in booke_interrupts.S (except we can't assume mtocrf exists there), but I'm less worried about that one as it still needs an optimization pass in general. -Scott -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
