kvm: deadlock in kvm_vgic_map_resources
Hello,
While running syzkaller fuzzer I've got the following deadlock.
On commit 9c763584b7c8911106bb77af7e648bef09af9d80.
=
[ INFO: possible recursive locking detected ]
4.9.0-rc6-xc2-00056-g08372dd4b91d-dirty #50 Not tainted
-
syz-executor/20805 is trying to acquire lock:
(
&kvm->lock
){+.+.+.}
, at:
[< inline >] kvm_vgic_dist_destroy
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:271
[] kvm_vgic_destroy+0x34/0x250
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:294
but task is already holding lock:
(&kvm->lock){+.+.+.}, at:
[] kvm_vgic_map_resources+0x2c/0x108
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:343
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
lock(&kvm->lock);
lock(&kvm->lock);
*** DEADLOCK ***
May be due to missing lock nesting notation
2 locks held by syz-executor/20805:
#0:(&vcpu->mutex){+.+.+.}, at:
[] vcpu_load+0x28/0x1d0
arch/arm64/kvm/../../../virt/kvm/kvm_main.c:143
#1:(&kvm->lock){+.+.+.}, at:
[] kvm_vgic_map_resources+0x2c/0x108
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:343
stack backtrace:
CPU: 2 PID: 20805 Comm: syz-executor Not tainted
4.9.0-rc6-xc2-00056-g08372dd4b91d-dirty #50
Hardware name: Hardkernel ODROID-C2 (DT)
Call trace:
[] dump_backtrace+0x0/0x3c8 arch/arm64/kernel/traps.c:69
[] show_stack+0x20/0x30 arch/arm64/kernel/traps.c:219
[< inline >] __dump_stack lib/dump_stack.c:15
[] dump_stack+0x100/0x150 lib/dump_stack.c:51
[< inline >] print_deadlock_bug kernel/locking/lockdep.c:1728
[< inline >] check_deadlock kernel/locking/lockdep.c:1772
[< inline >] validate_chain kernel/locking/lockdep.c:2250
[] __lock_acquire+0x1938/0x3440 kernel/locking/lockdep.c:3335
[] lock_acquire+0xdc/0x1d8 kernel/locking/lockdep.c:3746
[< inline >] __mutex_lock_common kernel/locking/mutex.c:521
[] mutex_lock_nested+0xdc/0x7b8 kernel/locking/mutex.c:621
[< inline >] kvm_vgic_dist_destroy
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:271
[] kvm_vgic_destroy+0x34/0x250
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:294
[] vgic_v2_map_resources+0x218/0x430
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-v2.c:295
[] kvm_vgic_map_resources+0xcc/0x108
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:348
[< inline >] kvm_vcpu_first_run_init
arch/arm64/kvm/../../../arch/arm/kvm/arm.c:505
[] kvm_arch_vcpu_ioctl_run+0xab8/0xce0
arch/arm64/kvm/../../../arch/arm/kvm/arm.c:591
[] kvm_vcpu_ioctl+0x434/0xc08
arch/arm64/kvm/../../../virt/kvm/kvm_main.c:2557
[< inline >] vfs_ioctl fs/ioctl.c:43
[] do_vfs_ioctl+0x128/0xfc0 fs/ioctl.c:679
[< inline >] SYSC_ioctl fs/ioctl.c:694
[] SyS_ioctl+0xa8/0xb8 fs/ioctl.c:685
[] el0_svc_naked+0x24/0x28 arch/arm64/kernel/entry.S:755
INFO: task syz-executor:20805 blocked for more than 120 seconds.
Not tainted 4.9.0-rc6-xc2-00056-g08372dd4b91d-dirty #50
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
syz-executor D 0 20805 1 0x0001
Call trace:
[] __switch_to+0x184/0x258 arch/arm64/kernel/process.c:345
[< inline >] context_switch kernel/sched/core.c:2899
[] __schedule+0x42c/0x1298 kernel/sched/core.c:3402
[] schedule+0xc8/0x260 kernel/sched/core.c:3457
[] schedule_preempt_disabled+0x74/0x110
kernel/sched/core.c:3490
[< inline >] __mutex_lock_common kernel/locking/mutex.c:582
[] mutex_lock_nested+0x318/0x7b8 kernel/locking/mutex.c:621
[< inline >] kvm_vgic_dist_destroy
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:271
[] kvm_vgic_destroy+0x34/0x250
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:294
[] vgic_v2_map_resources+0x218/0x430
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-v2.c:295
[] kvm_vgic_map_resources+0xcc/0x108
arch/arm64/kvm/../../../virt/kvm/arm/vgic/vgic-init.c:348
[< inline >] kvm_vcpu_first_run_init
arch/arm64/kvm/../../../arch/arm/kvm/arm.c:505
[] kvm_arch_vcpu_ioctl_run+0xab8/0xce0
arch/arm64/kvm/../../../arch/arm/kvm/arm.c:591
[] kvm_vcpu_ioctl+0x434/0xc08
arch/arm64/kvm/../../../virt/kvm/kvm_main.c:2557
[< inline >] vfs_ioctl fs/ioctl.c:43
[] do_vfs_ioctl+0x128/0xfc0 fs/ioctl.c:679
[< inline >] SYSC_ioctl fs/ioctl.c:694
[] SyS_ioctl+0xa8/0xb8 fs/ioctl.c:685
[] el0_svc_naked+0x24/0x28 arch/arm64/kernel/entry.S:755
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Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
[finally, some proper bikeshedding] On 11/01/17 18:40, Timur Tabi wrote: > On 01/11/2017 12:37 PM, Mark Rutland wrote: >> The name, as it is, is perfectly descriptive. >> >> Let's not sacrifice legibility over a non-issue. > > I don't want to kick a dead horse or anything, but changing it to > QCOM_FLKR_ERRATUM_1003 would eliminate all the spacing problems without > sacrificing anything. Other than not being able to grep for the core name in the source tree, how do you suggest we pronounce FLKR? Because so far, it rolls off the tongue in an interesting way... Thanks, M. -- Jazz is not dead. It just smells funny... ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: > On 01/11/2017 12:37 PM, Mark Rutland wrote: > >The name, as it is, is perfectly descriptive. > > > >Let's not sacrifice legibility over a non-issue. > > I don't want to kick a dead horse or anything, but changing it to > QCOM_FLKR_ERRATUM_1003 would eliminate all the spacing problems > without sacrificing anything. The CPU is called "Falkor", not "FLKR", and we're not coming up with an ACPI table name... The ARM Ltd. erratum numbers are global to all parts, so we don't include the part name. Is the 1003 erratum number specific to Falkor? If it's global, you could use QCOM_ERRATUM_1003 instead. Otherwise, QCOM_FALKOR_ERRATUM_1003 is preferable. Thanks, Mark. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > On 11/01/17 18:06, Catalin Marinas wrote: > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 32682be..9ee46df 100644 > >> --- a/arch/arm64/mm/proc.S > >> +++ b/arch/arm64/mm/proc.S > >> @@ -23,6 +23,7 @@ > >> #include > >> #include > >> #include > >> +#include > >> #include > >> #include > >> #include > >> @@ -140,6 +141,18 @@ ENDPROC(cpu_do_resume) > >> ENTRY(cpu_do_switch_mm) > >>mmidx1, x1 // get mm->context.id > >>bfi x0, x1, #48, #16// set the ASID > >> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 > >> +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 > >> + mrs x2, ttbr0_el1 > >> + mov x3, #FALKOR_RESERVED_ASID > >> + bfi x2, x3, #48, #16// reserved ASID + old BADDR > >> + msr ttbr0_el1, x2 > >> + isb > >> + bfi x2, x0, #0, #48 // reserved ASID + new BADDR > >> + msr ttbr0_el1, x2 > >> + isb > >> +alternative_else_nop_endif > >> +#endif > >>msr ttbr0_el1, x0 // set TTBR0 > >>isb > >>post_ttbr0_update_workaround > > > > Please move the above hunk to a pre_ttbr0_update_workaround macro for > > consistency with post_ttbr0_update_workaround. > > In which case (and also for consistency), should we add that pre_ttbr0 > macro to entry.S, just before __uaccess_ttbr0_enable? It may not be > needed in the SW pan case, but it is probably worth entertaining the > idea that there may be something to do there... Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0(). Thanks, Mark. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On 01/11/2017 12:37 PM, Mark Rutland wrote: The name, as it is, is perfectly descriptive. Let's not sacrifice legibility over a non-issue. I don't want to kick a dead horse or anything, but changing it to QCOM_FLKR_ERRATUM_1003 would eliminate all the spacing problems without sacrificing anything. -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote: > On 01/11/2017 12:33 PM, Mark Rutland wrote: > >It'll need to affect all lines since the kconfig column needs to expand > >by at least one character to fit QCOM_FALKOR_ERRATUM_1003. > > Or we can make the macro shorter. The name, as it is, is perfectly descriptive. Let's not sacrifice legibility over a non-issue. Thanks, Mark. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On 01/11/2017 12:33 PM, Mark Rutland wrote: It'll need to affect all lines since the kconfig column needs to expand by at least one character to fit QCOM_FALKOR_ERRATUM_1003. Or we can make the macro shorter. -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On Wed, Jan 11, 2017 at 06:06:27PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > -| Implementor| Component | Erratum ID | Kconfig > > | > > +| Implementor | Component | Erratum ID | Kconfig > > | > > +| Qualcomm | Falkor v1 | E1003 | > > QCOM_FALKOR_ERRATUM_1003 | > > Please don't change the "Implementor" column width, there is no point > and it makes the patch harder to read (i.e. this hunk should only have > one line). It'll need to affect all lines since the kconfig column needs to expand by at least one character to fit QCOM_FALKOR_ERRATUM_1003. I beleive the intent here was to keep the table fitting into a width of 80 characters. IMO we should allow the table to expand past 80 chars (everyone reading this file should be able to resize tehir terminal), and only expand the kconfig column. Thanks, Mark. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
On 11/01/17 18:06, Catalin Marinas wrote: > Some minor comments below, nothing fundamental (as long as you say the > new sequence doesn't have the speculative TLB load problem I mentioned > on a previous version). > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: >> diff --git a/Documentation/arm64/silicon-errata.txt >> b/Documentation/arm64/silicon-errata.txt >> index 405da11..7151aed 100644 >> --- a/Documentation/arm64/silicon-errata.txt >> +++ b/Documentation/arm64/silicon-errata.txt >> @@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the >> Linux Kernel and >> will be updated when new workarounds are committed and backported to >> stable kernels. >> >> -| Implementor| Component | Erratum ID | Kconfig >>| >> -++-+-+-+ >> -| ARM| Cortex-A53 | #826319 | ARM64_ERRATUM_826319 >>| >> -| ARM| Cortex-A53 | #827319 | ARM64_ERRATUM_827319 >>| >> -| ARM| Cortex-A53 | #824069 | ARM64_ERRATUM_824069 >>| >> -| ARM| Cortex-A53 | #819472 | ARM64_ERRATUM_819472 >>| >> -| ARM| Cortex-A53 | #845719 | ARM64_ERRATUM_845719 >>| >> -| ARM| Cortex-A53 | #843419 | ARM64_ERRATUM_843419 >>| >> -| ARM| Cortex-A57 | #832075 | ARM64_ERRATUM_832075 >>| >> -| ARM| Cortex-A57 | #852523 | N/A >>| >> -| ARM| Cortex-A57 | #834220 | ARM64_ERRATUM_834220 >>| >> -| ARM| Cortex-A72 | #853709 | N/A >>| >> -| ARM| MMU-500 | #841119,#826419 | N/A >>| >> -|| | | >>| >> -| Cavium | ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 >>| >> -| Cavium | ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 >>| >> -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 >>| >> -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 >>| >> -| Cavium | ThunderX SMMUv2 | #27704 | N/A | >> -|| | | >>| >> -| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585 >>| >> +| Implementor | Component | Erratum ID | Kconfig >>| >> ++---+-+-+--+ >> +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 >>| >> +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 >>| >> +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 >>| >> +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 >>| >> +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 >>| >> +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 >>| >> +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 >>| >> +| ARM | Cortex-A57 | #852523 | N/A >>| >> +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 >>| >> +| ARM | Cortex-A72 | #853709 | N/A >>| >> +| ARM | MMU-500 | #841119,#826419 | N/A >>| >> +| | | | >>| >> +| Cavium| ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 >>| >> +| Cavium| ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 >>| >> +| Cavium| ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 >>| >> +| Cavium| ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 >>| >> +| Cavium| ThunderX SMMUv2 | #27704 | N/A >>| >> +| | | | >>| >> +| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585 >>| >> +| Qualcomm | Falkor v1 | E1003 | >> QCOM_FALKOR_ERRATUM_1003 | > > Please don't change the "Implementor" column width, there is no point > and it makes the patch harder to read (i.e. this hunk should only have > one line). > >> diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c >> index 4c63cb1..5a0a82a 100644 >> --- a/arch/arm64/mm/context.c >> +++ b/arch/arm64/mm/context.c >> @@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu) >> /* Update the list of reserved ASIDs and the ASID bitmap. */ >>
Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003
Some minor comments below, nothing fundamental (as long as you say the new sequence doesn't have the speculative TLB load problem I mentioned on a previous version). On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > diff --git a/Documentation/arm64/silicon-errata.txt > b/Documentation/arm64/silicon-errata.txt > index 405da11..7151aed 100644 > --- a/Documentation/arm64/silicon-errata.txt > +++ b/Documentation/arm64/silicon-errata.txt > @@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the > Linux Kernel and > will be updated when new workarounds are committed and backported to > stable kernels. > > -| Implementor| Component | Erratum ID | Kconfig > | > -++-+-+-+ > -| ARM| Cortex-A53 | #826319 | ARM64_ERRATUM_826319 > | > -| ARM| Cortex-A53 | #827319 | ARM64_ERRATUM_827319 > | > -| ARM| Cortex-A53 | #824069 | ARM64_ERRATUM_824069 > | > -| ARM| Cortex-A53 | #819472 | ARM64_ERRATUM_819472 > | > -| ARM| Cortex-A53 | #845719 | ARM64_ERRATUM_845719 > | > -| ARM| Cortex-A53 | #843419 | ARM64_ERRATUM_843419 > | > -| ARM| Cortex-A57 | #832075 | ARM64_ERRATUM_832075 > | > -| ARM| Cortex-A57 | #852523 | N/A > | > -| ARM| Cortex-A57 | #834220 | ARM64_ERRATUM_834220 > | > -| ARM| Cortex-A72 | #853709 | N/A > | > -| ARM| MMU-500 | #841119,#826419 | N/A > | > -|| | | > | > -| Cavium | ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 > | > -| Cavium | ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 > | > -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 > | > -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 > | > -| Cavium | ThunderX SMMUv2 | #27704 | N/A | > -|| | | > | > -| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585 > | > +| Implementor | Component | Erratum ID | Kconfig > | > ++---+-+-+--+ > +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 > | > +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 > | > +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 > | > +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 > | > +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 > | > +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 > | > +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 > | > +| ARM | Cortex-A57 | #852523 | N/A > | > +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 > | > +| ARM | Cortex-A72 | #853709 | N/A > | > +| ARM | MMU-500 | #841119,#826419 | N/A > | > +| | | | > | > +| Cavium| ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 > | > +| Cavium| ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 > | > +| Cavium| ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 > | > +| Cavium| ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 > | > +| Cavium| ThunderX SMMUv2 | #27704 | N/A > | > +| | | | > | > +| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585 > | > +| Qualcomm | Falkor v1 | E1003 | > QCOM_FALKOR_ERRATUM_1003 | Please don't change the "Implementor" column width, there is no point and it makes the patch harder to read (i.e. this hunk should only have one line). > diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c > index 4c63cb1..5a0a82a 100644 > --- a/arch/arm64/mm/context.c > +++ b/arch/arm64/mm/context.c > @@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu) > /* Update the list of reserved ASIDs and the ASID bitmap. */ > bitmap_clear(asid_map, 0, NUM_USER_ASIDS); > > + /* Reserve ASID for Falkor erratum 1003 */ > + if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) && >
[PATCH] KVM: arm64: Increase number of memslots to 512
From: Linu Cherian Having only 32 memslots is a real constraint for the maximum number of PCI devices that can be assigned to a single guest. Assuming each PCI device/virtual function having two memory BAR regions, we could assign only 15 devices/virtual functions to a guest. So increase KVM_MEM_SLOTS_NUM to 512 as done in other archs like x86 and powerpc. For this, KVM_USER_MEM_SLOTS has been changed to 508. Signed-off-by: Linu Cherian --- arch/arm/kvm/arm.c| 3 +++ arch/arm64/include/asm/kvm_host.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 8f92efa..a19389b 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -221,6 +221,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_MAX_VCPUS: r = KVM_MAX_VCPUS; break; + case KVM_CAP_NR_MEMSLOTS: + r = KVM_USER_MEM_SLOTS; + break; case KVM_CAP_MSI_DEVID: if (!kvm) r = -EINVAL; diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index e505038..88f017d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -30,7 +30,7 @@ #define __KVM_HAVE_ARCH_INTC_INITIALIZED -#define KVM_USER_MEM_SLOTS 32 +#define KVM_USER_MEM_SLOTS 508 #define KVM_PRIVATE_MEM_SLOTS 4 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_HALT_POLL_NS_DEFAULT 50 -- 1.9.1 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[kvm-unit-tests PATCH 2/6] lib/pci: fix BAR format strings
Using %x as a format string is not portable across 32/64 bit builds.
Use explicit PRIx32 format strings like the 64 bit version above.
Signed-off-by: Alex Bennée
---
lib/pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/pci.c b/lib/pci.c
index 6416191..597d8f2 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -67,7 +67,7 @@ bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr,
uint32_t msi_data)
pci_config_writel(addr, offset + PCI_MSI_DATA_32, msi_data);
printf("MSI: dev 0x%x init 32bit address: ", addr);
}
- printf("addr=0x%lx, data=0x%x\n", msi_addr, msi_data);
+ printf("addr=0x%" PRIx64 ", data=0x%" PRIx32 "\n", msi_addr, msi_data);
msi_control |= PCI_MSI_FLAGS_ENABLE;
pci_config_writew(addr, offset + PCI_MSI_FLAGS, msi_control);
@@ -237,7 +237,7 @@ void pci_bar_print(struct pci_dev *dev, int bar_num)
printf("BAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
bar_num, bar_num + 1, start, end);
} else {
- printf("BAR#%d [%02x-%02x ",
+ printf("BAR#%d [%" PRIx32 "-%" PRIx32 " ",
bar_num, (uint32_t)start, (uint32_t)end);
}
--
2.11.0
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[kvm-unit-tests PATCH 5/6] docs: mention modifying env vars in README
I had started adding a series of flags to control the run-time behaviour of the tests but it was pointed out env vars can already do that. Mention them in the README so others can find out to. Signed-off-by: Alex Bennée --- README.md | 8 1 file changed, 8 insertions(+) diff --git a/README.md b/README.md index 9462824..fa3a445 100644 --- a/README.md +++ b/README.md @@ -47,6 +47,14 @@ environment variable: QEMU=/tmp/qemu/x86_64-softmmu/qemu-system-x86_64 ./x86-run ./x86/msr.flat +To force the acceleration mode: + +ACCEL=tcg ./run_tests.sh + +To extend or disable the timeouts: + +TIMEOUT=0 ./run_tests.sh + # Contributing ## Directory structure -- 2.11.0 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[kvm-unit-tests PATCH 6/6] run_tests: allow passing of options to QEMU
This allows additional options to be passed to QEMU. It follows the
convention of passing parameters after a -- to the child process. In
my case I'm using it to toggle MTTCG on an off:
./run_tests.sh -- --accel tcg,thread=multi
Signed-off-by: Alex Bennée
---
v1
- changes from -o to --
- fixed whitespace damage
---
README.md | 6 ++
run_tests.sh | 13 +++--
scripts/functions.bash | 7 ---
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/README.md b/README.md
index fa3a445..1bd6dcb 100644
--- a/README.md
+++ b/README.md
@@ -55,6 +55,12 @@ To extend or disable the timeouts:
TIMEOUT=0 ./run_tests.sh
+Any arguments past the end-of-arguments marker (--) is passed on down
+to the QEMU invocation. This can of course be combined with the other
+modifiers:
+
+ACCEL=tcg ./run_tests.sh -v -- --accel tcg,thread=multi
+
# Contributing
## Directory structure
diff --git a/run_tests.sh b/run_tests.sh
index 254129d..3270fba 100755
--- a/run_tests.sh
+++ b/run_tests.sh
@@ -13,7 +13,7 @@ function usage()
{
cat <> test.log; }
RUNTIME_log_stdout () {
if [ "$PRETTY_PRINT_STACKS" = "yes" ]; then
@@ -59,4 +68,4 @@ RUNTIME_log_stdout () {
config=$TEST_DIR/unittests.cfg
rm -f test.log
printf "BUILD_HEAD=$(cat build-head)\n\n" > test.log
-for_each_unittest $config run
+for_each_unittest $config run "$extra_opts"
diff --git a/scripts/functions.bash b/scripts/functions.bash
index ee9143c..60fbc6a 100644
--- a/scripts/functions.bash
+++ b/scripts/functions.bash
@@ -3,10 +3,11 @@ function for_each_unittest()
{
local unittests="$1"
local cmd="$2"
+ local extra_opts=$3
local testname
local smp
local kernel
- local opts
+ local opts=$extra_opts
local groups
local arch
local check
@@ -21,7 +22,7 @@ function for_each_unittest()
testname=${BASH_REMATCH[1]}
smp=1
kernel=""
- opts=""
+ opts=$extra_opts
groups=""
arch=""
check=""
@@ -32,7 +33,7 @@ function for_each_unittest()
elif [[ $line =~ ^smp\ *=\ *(.*)$ ]]; then
smp=${BASH_REMATCH[1]}
elif [[ $line =~ ^extra_params\ *=\ *(.*)$ ]]; then
- opts=${BASH_REMATCH[1]}
+ opts="$opts ${BASH_REMATCH[1]}"
elif [[ $line =~ ^groups\ *=\ *(.*)$ ]]; then
groups=${BASH_REMATCH[1]}
elif [[ $line =~ ^arch\ *=\ *(.*)$ ]]; then
--
2.11.0
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[kvm-unit-tests PATCH 3/6] docs: move README to README.md and symlink
This allows a slightly nicer formatting of the text when displayed on some repository hosts. We keep a symlink from README for the old-school purists. Signed-off-by: Alex Bennée --- README| 69 + README.md | 81 +++ 2 files changed, 82 insertions(+), 68 deletions(-) mode change 100644 => 12 README create mode 100644 README.md diff --git a/README b/README deleted file mode 100644 index f8f196d..000 --- a/README +++ /dev/null @@ -1,68 +0,0 @@ -Welcome to kvm-unit-tests - -See http://www.linux-kvm.org/page/KVM-unit-tests for a high-level -description of this project, as well as running tests and adding -tests HOWTOs. - -This directory contains sources for a kvm test suite. - -To create the test images do - ./configure - make -in this directory. Test images are created in .//*.flat - -Then use the runner script to detect the correct invocation and -invoke the test, e.g. - ./x86-run ./x86/msr.flat -or - ./run_tests.sh -to run them all. - -To select a specific qemu binary, specify the QEMU= -environment variable, e.g. - QEMU=/tmp/qemu/x86_64-softmmu/qemu-system-x86_64 ./x86-run ./x86/msr.flat - -To create and use standalone tests do - ./configure - make standalone - (send tests/some-test somewhere) - (go to somewhere) - ./some-test - -'make install' will install all tests in PREFIX/share/kvm-unit-tests/tests, -each as a standalone test. - -Directory structure: -.: configure script, top-level Makefile, and run_tests.sh -./scripts: helper scripts for building and running tests -./lib: general architecture neutral services for the tests -./lib/: architecture dependent services for the tests -./: the sources of the tests and the created objects/images - -See /README for architecture specific documentation. - -CONTRIBUTING: -= - -Style -- - -Currently there is a mix of indentation styles so any changes to -existing files should be consistent with the existing style. For new -files: - - - C: please use standard linux-with-tabs - - Shell: use TABs for indentation - -Patches - -Patches are welcome at the KVM mailing list . - -Please prefix messages with: [kvm-unit-tests PATCH] - -You can add the following to .git/config to do this automatically for you: - -[format] - subjectprefix = kvm-unit-tests PATCH - diff --git a/README b/README new file mode 12 index 000..42061c0 --- /dev/null +++ b/README @@ -0,0 +1 @@ +README.md \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 000..5027b62 --- /dev/null +++ b/README.md @@ -0,0 +1,81 @@ +# Welcome to kvm-unit-tests + +See http://www.linux-kvm.org/page/KVM-unit-tests for a high-level +description of this project, as well as running tests and adding +tests HOWTOs. + +# Building the tests + +This directory contains sources for a kvm test suite. + +To create the test images do: + +./configure +make + +in this directory. Test images are created in .//*.flat + +## Standalone tests + +The tests can be built as standalone +To create and use standalone tests do: + +./configure +make standalone +(send tests/some-test somewhere) +(go to somewhere) +./some-test + +'make install' will install all tests in PREFIX/share/kvm-unit-tests/tests, +each as a standalone test. + + +# Running the tests + +Then use the runner script to detect the correct invocation and +invoke the test: + +./x86-run ./x86/msr.flat +or: + +./run_tests.sh + +to run them all. + +To select a specific qemu binary, specify the QEMU= +environment variable: + +QEMU=/tmp/qemu/x86_64-softmmu/qemu-system-x86_64 ./x86-run ./x86/msr.flat + +# Contributing + +## Directory structure + +.: configure script, top-level Makefile, and run_tests.sh +./scripts: helper scripts for building and running tests +./lib: general architecture neutral services for the tests +./lib/: architecture dependent services for the tests +./: the sources of the tests and the created objects/images + +See /README for architecture specific documentation. + +## Style + +Currently there is a mix of indentation styles so any changes to +existing files should be consistent with the existing style. For new +files: + + - C: please use standard linux-with-tabs + - Shell: use TABs for indentation + +## Patches + +Patches are welcome at the KVM mailing list . + +Please prefix messages with: [kvm-unit-tests PATCH] + +You can add the following to .git/config to do this automatically for you: + +[format] +subjectprefix = kvm-unit-tests PATCH + -- 2.11.0 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[kvm-unit-tests PATCH 1/6] libcflat: add PRI(dux)32 format types
So we can have portable formatting of uint32_t types. However there is a catch. Different compilers can use legally subtly different types though so we need to probe the compiler defined intdef.h first. Signed-off-by: Alex Bennée --- Makefile | 1 + configure | 13 + lib/libcflat.h | 9 + 3 files changed, 23 insertions(+) diff --git a/Makefile b/Makefile index a32333b..9822d9a 100644 --- a/Makefile +++ b/Makefile @@ -55,6 +55,7 @@ CFLAGS += $(fomit_frame_pointer) CFLAGS += $(fno_stack_protector) CFLAGS += $(fno_stack_protector_all) CFLAGS += $(wno_frame_address) +CFLAGS += $(if $(U32_LONG_FMT),-D__U32_LONG_FMT__,) CXXFLAGS += $(CFLAGS) diff --git a/configure b/configure index 995c8fa..127868c 100755 --- a/configure +++ b/configure @@ -109,6 +109,18 @@ if [ -f $testdir/run ]; then ln -fs $testdir/run $testdir-run fi +# check if uint32_t needs a long format modifier +cat << EOF > lib_test.c +#include +EOF + +$cross_prefix$cc lib_test.c -E | grep "typedef" | grep "long" | grep "uint32_t" &> /dev/null +exit=$? +if [ $exit -eq 0 ]; then +u32_long=true +fi +rm -f lib_test.c + # check for dependent 32 bit libraries if [ "$arch" != "arm" ]; then cat << EOF > lib_test.c @@ -155,4 +167,5 @@ TEST_DIR=$testdir FIRMWARE=$firmware ENDIAN=$endian PRETTY_PRINT_STACKS=$pretty_print_stacks +U32_LONG_FMT=$u32_long EOF diff --git a/lib/libcflat.h b/lib/libcflat.h index 380395f..e80fc50 100644 --- a/lib/libcflat.h +++ b/lib/libcflat.h @@ -58,12 +58,21 @@ typedef _Bool bool; #define true 1 #if __SIZEOF_LONG__ == 8 +# define __PRI32_PREFIX # define __PRI64_PREFIX "l" # define __PRIPTR_PREFIX "l" #else +#if defined(__U32_LONG_FMT__) +# define __PRI32_PREFIX"l" +#else +# define __PRI32_PREFIX +#endif # define __PRI64_PREFIX "ll" # define __PRIPTR_PREFIX #endif +#define PRId32 __PRI32_PREFIX "d" +#define PRIu32 __PRI32_PREFIX "u" +#define PRIx32 __PRI32_PREFIX "x" #define PRId64 __PRI64_PREFIX "d" #define PRIu64 __PRI64_PREFIX "u" #define PRIx64 __PRI64_PREFIX "x" -- 2.11.0 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[kvm-unit-tests PATCH 0/6] Documentation misc fixes
Hi, I broke these out of my earlier MTTCG test series as they are not strictly related. The libcflat/pci fixes are a result of trying to cross-compile arm32 binaries on my arm64 box with a arm-none-abi compiler. I've also tidied up some documentation (along with a controversial move to Markdown ;-). And finally the run_script now follows the convention of passing arguments after -- to the child process. Alex Bennée (6): libcflat: add PRI(dux)32 format types lib/pci: fix BAR format strings docs: move README to README.md and symlink docs: mention checkpatch in the README docs: mention modifying env vars in README run_tests: allow passing of options to QEMU Makefile | 1 + README | 69 +--- README.md | 96 ++ configure | 13 +++ lib/libcflat.h | 9 + lib/pci.c | 4 +-- run_tests.sh | 13 +-- scripts/functions.bash | 7 ++-- 8 files changed, 137 insertions(+), 75 deletions(-) mode change 100644 => 12 README create mode 100644 README.md -- 2.11.0 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[kvm-unit-tests PATCH 4/6] docs: mention checkpatch in the README
Signed-off-by: Alex Bennée --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 5027b62..9462824 100644 --- a/README.md +++ b/README.md @@ -79,3 +79,4 @@ You can add the following to .git/config to do this automatically for you: [format] subjectprefix = kvm-unit-tests PATCH +Please run the kernel's ./scripts/checkpatch.pl on new patches -- 2.11.0 ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[PATCH v3 2/5] arm64: Work around Falkor erratum 1003
From: Shanker Donthineni On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID will ensure that there are no TLB entries with incorrect ASID after changing the the ASID. Pseudo code: write TTBRx_EL1[ASID] to a reserved value ISB write TTBRx_EL1[BADDR] to a desired value ISB write TTBRx_EL1[ASID] to a desired value ISB EL2 and EL3 code changing the EL1&0 ASID is not subject to this erratum because hardware is prohibited from performing translations from an out-of-context translation regime. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- Documentation/arm64/silicon-errata.txt | 43 +- arch/arm64/Kconfig | 11 + arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/mmu_context.h | 8 ++- arch/arm64/kernel/cpu_errata.c | 7 ++ arch/arm64/mm/context.c| 10 arch/arm64/mm/proc.S | 13 ++ 7 files changed, 72 insertions(+), 23 deletions(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 405da11..7151aed 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -42,24 +42,25 @@ file acts as a registry of software workarounds in the Linux Kernel and will be updated when new workarounds are committed and backported to stable kernels. -| Implementor| Component | Erratum ID | Kconfig | -++-+-+-+ -| ARM| Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | -| ARM| Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | -| ARM| Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | -| ARM| Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | -| ARM| Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | -| ARM| Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | -| ARM| Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | -| ARM| Cortex-A57 | #852523 | N/A | -| ARM| Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | -| ARM| Cortex-A72 | #853709 | N/A | -| ARM| MMU-500 | #841119,#826419 | N/A | -|| | | | -| Cavium | ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 | -| Cavium | ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 | -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | -| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | -| Cavium | ThunderX SMMUv2 | #27704 | N/A| -|| | | | -| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585 | +| Implementor | Component | Erratum ID | Kconfig | ++---+-+-+--+ +| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | +| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 | +| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #852523 | N/A | +| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +| ARM | Cortex-A72 | #853709 | N/A | +| ARM | MMU-500 | #841119,#826419 | N/A | +| | | | | +| Cavium| ThunderX ITS| #22375, #24313 | CAVIUM_ERRATUM_22375 | +| Cavium| ThunderX ITS| #23144 | CAVIUM_ERRATUM_23144 | +| Cavium| ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium| ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | +| Cavium| ThunderX SMMUv2 | #27704 | N/A | +| | | |
[PATCH v3 5/5] arm64: Work around Falkor erratum 1009
During a TLB invalidate sequence targeting the inner shareable
domain, Falkor may prematurely complete the DSB before all loads
and stores using the old translation are observed; instruction
fetches are not subject to the conditions of this erratum.
Signed-off-by: Christopher Covington
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/tlbflush.h | 5 -
arch/arm64/kernel/cpu_errata.c | 7 +++
5 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt
b/Documentation/arm64/silicon-errata.txt
index 7151aed..98bef2a 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -64,3 +64,4 @@ stable kernels.
| | | |
|
| Freescale/NXP | LS2080A/LS1043A | A-008585| FSL_ERRATUM_A008585
|
| Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003
|
+| Qualcomm | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009
|
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 2a80ac9..d13e903 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -490,6 +490,16 @@ config QCOM_FALKOR_ERRATUM_1003
If unsure, say Y.
+config QCOM_FALKOR_ERRATUM_1009
+ bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
+ default y
+ help
+ Falkor CPU may prematurely complete a DSB following a TLBI xxIS
+ invalidate maintenance operations. Repeat the TLBI operation one
+ more time to fix the issue.
+
+ If unsure, say Y.
+
endmenu
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 5aaf7ee..55bcd02 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -36,7 +36,8 @@
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
#define ARM64_HAS_NO_FPSIMD16
#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 17
+#define ARM64_WORKAROUND_REPEAT_TLBI 18
-#define ARM64_NCAPS18
+#define ARM64_NCAPS19
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index f28813c..7313cd3 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -85,7 +85,10 @@
asm (__TLBI_INSTR(op, ##__VA_ARGS__) \
__TLBI_IO(op, ##__VA_ARGS__)); \
asm volatile ( as "\ndsb " #attr "\n"\
- : : : "memory"); } while (0)
+ ALTERNATIVE("nop" "\nnop""\n", \
+ __TLBI_INSTR(op, ##__VA_ARGS__) "\ndsb " #attr "\n", \
+ ARM64_WORKAROUND_REPEAT_TLBI) \
+ __TLBI_IO(op, ##__VA_ARGS__) : "memory"); } while (0)
#define __tlbi_dsb(...)__tlbi_asm_dsb("", ##__VA_ARGS__)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 787b542..e644364 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -137,6 +137,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00),
},
#endif
+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
+ {
+ .desc = "Qualcomm Falkor erratum 1009",
+ .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+ MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00),
+ },
+#endif
{
}
};
--
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[PATCH v3 4/5] arm64: Use __tlbi_dsb() macros in KVM code
Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which
will allow an errata workaround that repeats tlbi dsb sequences to only
change one location. This is not intended to change the generated assembly
and comparing before and after vmlinux objdump shows no functional changes.
Signed-off-by: Christopher Covington
---
arch/arm64/kvm/hyp/tlb.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index 88e2f2b..9669e4b 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64/kvm/hyp/tlb.c
@@ -16,6 +16,7 @@
*/
#include
+#include
void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
{
@@ -30,19 +31,15 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm,
phys_addr_t ipa)
* We could do so much better if we had the VA as well.
* Instead, we invalidate Stage-2 for this IPA, and the
* whole of Stage-1. Weep...
+*
+* We have to ensure completion of the invalidation at Stage-2 with a
+* DSB, since a table walk on another CPU could refill a TLB with a
+* complete (S1 + S2) walk based on the old Stage-2 mapping if the
+* Stage-1 invalidation happened first.
*/
ipa >>= 12;
- asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa));
-
- /*
-* We have to ensure completion of the invalidation at Stage-2,
-* since a table walk on another CPU could refill a TLB with a
-* complete (S1 + S2) walk based on the old Stage-2 mapping if
-* the Stage-1 invalidation happened first.
-*/
- dsb(ish);
- asm volatile("tlbi vmalle1is" : : );
- dsb(ish);
+ __tlbi_dsb(ipas2e1is, ish, ipa);
+ __tlbi_dsb(vmalle1is, ish);
isb();
write_sysreg(0, vttbr_el2);
@@ -57,8 +54,7 @@ void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
write_sysreg(kvm->arch.vttbr, vttbr_el2);
isb();
- asm volatile("tlbi vmalls12e1is" : : );
- dsb(ish);
+ __tlbi_dsb(vmalls12e1is, ish);
isb();
write_sysreg(0, vttbr_el2);
@@ -72,8 +68,7 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu
*vcpu)
write_sysreg(kvm->arch.vttbr, vttbr_el2);
isb();
- asm volatile("tlbi vmalle1" : : );
- dsb(nsh);
+ __tlbi_dsb(vmalle1, nsh);
isb();
write_sysreg(0, vttbr_el2);
@@ -82,7 +77,5 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu
*vcpu)
void __hyp_text __kvm_flush_vm_context(void)
{
dsb(ishst);
- asm volatile("tlbi alle1is \n"
-"ic ialluis ": : );
- dsb(ish);
+ __tlbi_asm_dsb("ic ialluis", alle1is, ish);
}
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[PATCH v3 1/5] arm64: Define Falkor v1 CPU
From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/include/asm/cputype.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 26a68dd..ee60561 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -71,6 +71,7 @@ #define ARM_CPU_IMP_APM0x50 #define ARM_CPU_IMP_CAVIUM 0x43 #define ARM_CPU_IMP_BRCM 0x42 +#define ARM_CPU_IMP_QCOM 0x51 #define ARM_CPU_PART_AEM_V80xD0F #define ARM_CPU_PART_FOUNDATION0xD00 @@ -84,10 +85,13 @@ #define BRCM_CPU_PART_VULCAN 0x516 +#define QCOM_CPU_PART_FALKOR_V10x800 + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #ifndef __ASSEMBLY__ -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros
This refactoring will allow an errata workaround that repeats tlbi dsb
sequences to only change one location. This is not intended to change the
generated assembly and comparison of before and after preprocessor output
of arch/arm64/mm/mmu.c and vmlinux objdump shows no functional changes.
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/tlbflush.h | 104 +-
1 file changed, 69 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index deab523..f28813c 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -25,22 +25,69 @@
#include
/*
- * Raw TLBI operations.
+ * Raw TLBI, DSB operations
*
- * Where necessary, use the __tlbi() macro to avoid asm()
- * boilerplate. Drivers and most kernel code should use the TLB
- * management routines in preference to the macro below.
+ * Where necessary, use __tlbi_*dsb() macros to avoid asm() boilerplate.
+ * Drivers and most kernel code should use the TLB management routines in
+ * preference to the macros below.
*
- * The macro can be used as __tlbi(op) or __tlbi(op, arg), depending
- * on whether a particular TLBI operation takes an argument or
- * not. The macros handles invoking the asm with or without the
- * register argument as appropriate.
+ * The __tlbi_dsb() macro handles invoking the asm without any register
+ * argument, with a single register argument, and with start (included)
+ * and end (excluded) range of register arguments. For example:
+ *
+ * __tlbi_dsb(op, attr)
+ *
+ * tlbi op
+ * dsb attr
+ *
+ * __tlbi_dsb(op, attr, addr)
+ *
+ * mov %[addr], =addr
+ * tlbi op, %[addr]
+ * dsb attr
+ *
+ * __tlbi_range_dsb(op, attr, start, end)
+ *
+ * mov %[arg], =start
+ * mov %[end], =end
+ * for:
+ * tlbi op, %[addr]
+ * add %[addr], %[addr], #(1 << (PAGE_SHIFT - 12))
+ * cmp %[addr], %[end]
+ * b.ne for
+ * dsb attr
*/
-#define __TLBI_0(op, arg) asm ("tlbi " #op)
-#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg))
-#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)
-#define __tlbi(op, ...)__TLBI_N(op, ##__VA_ARGS__, 1, 0)
+#define __TLBI_FOR_0(ig0, ig1, ig2)
+#define __TLBI_INSTR_0(op, ig1, ig2) "tlbi " #op
+#define __TLBI_IO_0(ig0, ig1, ig2) : :
+
+#define __TLBI_FOR_1(ig0, ig1, ig2)
+#define __TLBI_INSTR_1(op, ig0, ig1) "tlbi " #op ", %0"
+#define __TLBI_IO_1(ig0, arg, ig1) : : "r" (arg)
+
+#define __TLBI_FOR_2(ig0, start, ig1) unsigned long addr;\
+ for (addr = start; addr < end; \
+ addr += 1 << (PAGE_SHIFT - 12))
+#define __TLBI_INSTR_2(op, ig0, ig1) "tlbi " #op ", %0"
+#define __TLBI_IO_2(ig0, ig1, ig2) : : "r" (addr)
+
+#define __TLBI_FOR_N(op, a1, a2, n, ...) __TLBI_FOR_##n(op, a1, a2)
+#define __TLBI_INSTR_N(op, a1, a2, n, ...) __TLBI_INSTR_##n(op, a1, a2)
+#define __TLBI_IO_N(op, a1, a2, n, ...)__TLBI_IO_##n(op, a1, a2)
+
+#define __TLBI_FOR(op, ...)__TLBI_FOR_N(op, ##__VA_ARGS__, 2, 1, 0)
+#define __TLBI_INSTR(op, ...) __TLBI_INSTR_N(op, ##__VA_ARGS__, 2, 1,
0)
+#define __TLBI_IO(op, ...) __TLBI_IO_N(op, ##__VA_ARGS__, 2, 1, 0)
+
+#define __tlbi_asm_dsb(as, op, attr, ...) do {\
+ __TLBI_FOR(op, ##__VA_ARGS__) \
+ asm (__TLBI_INSTR(op, ##__VA_ARGS__) \
+ __TLBI_IO(op, ##__VA_ARGS__)); \
+ asm volatile ( as "\ndsb " #attr "\n"\
+ : : : "memory"); } while (0)
+
+#define __tlbi_dsb(...)__tlbi_asm_dsb("", ##__VA_ARGS__)
/*
* TLB Management
@@ -84,16 +131,14 @@
static inline void local_flush_tlb_all(void)
{
dsb(nshst);
- __tlbi(vmalle1);
- dsb(nsh);
+ __tlbi_dsb(vmalle1, nsh);
isb();
}
static inline void flush_tlb_all(void)
{
dsb(ishst);
- __tlbi(vmalle1is);
- dsb(ish);
+ __tlbi_dsb(vmalle1is, ish);
isb();
}
@@ -102,8 +147,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
unsigned long asid = ASID(mm) << 48;
dsb(ishst);
- __tlbi(aside1is, asid);
- dsb(ish);
+ __tlbi_dsb(aside1is, ish, asid);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -112,8 +156,7 @@ static inline void flush_tlb_page(struct vm_area_struct
*vma,
unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48);
dsb(ishst);
- __tlbi(vale1is, addr);
- dsb(ish);
+ __tlbi_dsb(vale1is, ish, addr);
}
/*
@@ -127,7 +170,6 @@ static inline void __flush_tlb_range(struct vm_area_struct
*vma,
bool
Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Hi Christoffer, On 01/04/2017 05:33 AM, Christoffer Dall wrote: > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> From: Shanker Donthineni >> >> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may >> allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being >> updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields >> separately using a reserved ASID will ensure that there are no TLB entries >> with incorrect ASID after changing the the ASID. > > When we restore guest state in KVM, we completely save and restore > TTBRx_EL1 from EL2. Would that be affected by this erratum? Good question, but apparently not. I'll add the following explanation to the v3 commit message. "EL2 and EL3 code changing the EL1&0 ASID is not subject to this erratum because hardware is prohibited from performing translations from an out-of-context translation regime." Thanks, Cov -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
