Re: [PATCH] KVM: arm64: vgic-v3: Restrict SEIS workaround to known broken systems
On 2022-01-22 11:14, Ard Biesheuvel wrote:
On Sat, 22 Jan 2022 at 11:39, Marc Zyngier wrote:
Contrary to what df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3
locally generated SErrors") was asserting, there is at least one other
system out there (Cavium ThunderX2) implementing SEIS, and not in
an obviously broken way.
So instead of imposing the M1 workaround on an innocent bystander,
let's limit it to the two known broken Apple implementations.
Fixes: df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3 locally
generated SErrors")
Reported-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Thanks for the fix.
Tested-by: Ard Biesheuvel
Acked-by: Ard Biesheuvel
Thanks for that.
One nit below.
---
arch/arm64/kvm/hyp/vgic-v3-sr.c | 3 +++
arch/arm64/kvm/vgic/vgic-v3.c | 17 +++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c
b/arch/arm64/kvm/hyp/vgic-v3-sr.c
index 20db2f281cf2..4fb419f7b8b6 100644
--- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
+++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
@@ -983,6 +983,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu
*vcpu, u32 vmcr, int rt)
val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
/* IDbits */
val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
+ /* SEIS */
+ if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK)
+ val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT);
/* A3V */
val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
/* EOImode */
diff --git a/arch/arm64/kvm/vgic/vgic-v3.c
b/arch/arm64/kvm/vgic/vgic-v3.c
index 78cf674c1230..d34a795f730c 100644
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -609,6 +609,18 @@ static int __init early_gicv4_enable(char *buf)
}
early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
+static struct midr_range broken_seis[] = {
Can this be const?
Absolutely. I'll fold that in.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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Re: [PATCH] KVM: arm64: vgic-v3: Restrict SEIS workaround to known broken systems
On Sat, 22 Jan 2022 at 11:39, Marc Zyngier wrote:
>
> Contrary to what df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3
> locally generated SErrors") was asserting, there is at least one other
> system out there (Cavium ThunderX2) implementing SEIS, and not in
> an obviously broken way.
>
> So instead of imposing the M1 workaround on an innocent bystander,
> let's limit it to the two known broken Apple implementations.
>
> Fixes: df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3 locally
> generated SErrors")
> Reported-by: Ard Biesheuvel
> Signed-off-by: Marc Zyngier
Thanks for the fix.
Tested-by: Ard Biesheuvel
Acked-by: Ard Biesheuvel
One nit below.
> ---
> arch/arm64/kvm/hyp/vgic-v3-sr.c | 3 +++
> arch/arm64/kvm/vgic/vgic-v3.c | 17 +++--
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
> index 20db2f281cf2..4fb419f7b8b6 100644
> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
> @@ -983,6 +983,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
> u32 vmcr, int rt)
> val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
> /* IDbits */
> val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
> + /* SEIS */
> + if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK)
> + val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT);
> /* A3V */
> val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
> /* EOImode */
> diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
> index 78cf674c1230..d34a795f730c 100644
> --- a/arch/arm64/kvm/vgic/vgic-v3.c
> +++ b/arch/arm64/kvm/vgic/vgic-v3.c
> @@ -609,6 +609,18 @@ static int __init early_gicv4_enable(char *buf)
> }
> early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
>
> +static struct midr_range broken_seis[] = {
Can this be const?
> + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
> + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
> + {},
> +};
> +
> +static bool vgic_v3_broken_seis(void)
> +{
> + return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
> + is_midr_in_range_list(read_cpuid_id(), broken_seis));
> +}
> +
> /**
> * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
> * @info: pointer to the GIC description
> @@ -676,9 +688,10 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
> group1_trap = true;
> }
>
> - if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) {
> - kvm_info("GICv3 with locally generated SEI\n");
> + if (vgic_v3_broken_seis()) {
> + kvm_info("GICv3 with broken locally generated SEI\n");
>
> + kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
> group0_trap = true;
> group1_trap = true;
> if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
> --
> 2.34.1
>
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[PATCH] KVM: arm64: vgic-v3: Restrict SEIS workaround to known broken systems
Contrary to what df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3
locally generated SErrors") was asserting, there is at least one other
system out there (Cavium ThunderX2) implementing SEIS, and not in
an obviously broken way.
So instead of imposing the M1 workaround on an innocent bystander,
let's limit it to the two known broken Apple implementations.
Fixes: df652bcf1136 ("KVM: arm64: vgic-v3: Work around GICv3 locally generated
SErrors")
Reported-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/vgic-v3-sr.c | 3 +++
arch/arm64/kvm/vgic/vgic-v3.c | 17 +++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
index 20db2f281cf2..4fb419f7b8b6 100644
--- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
+++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
@@ -983,6 +983,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32
vmcr, int rt)
val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
/* IDbits */
val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
+ /* SEIS */
+ if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK)
+ val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT);
/* A3V */
val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
/* EOImode */
diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
index 78cf674c1230..d34a795f730c 100644
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -609,6 +609,18 @@ static int __init early_gicv4_enable(char *buf)
}
early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
+static struct midr_range broken_seis[] = {
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
+ {},
+};
+
+static bool vgic_v3_broken_seis(void)
+{
+ return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
+ is_midr_in_range_list(read_cpuid_id(), broken_seis));
+}
+
/**
* vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
* @info: pointer to the GIC description
@@ -676,9 +688,10 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
group1_trap = true;
}
- if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) {
- kvm_info("GICv3 with locally generated SEI\n");
+ if (vgic_v3_broken_seis()) {
+ kvm_info("GICv3 with broken locally generated SEI\n");
+ kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
group0_trap = true;
group1_trap = true;
if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
--
2.34.1
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