Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function gen8_gpe_context_add_surface() to set surface state on GEN8
On 11/17/2016 11:48 PM, Xiang, Haihao wrote:
-Original Message-
From: Zhao, Yakui
Sent: Thursday, November 17, 2016 9:14 PM
To: Xiang, Haihao
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function
gen8_gpe_context_add_surface() to set surface state on GEN8
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
Signed-off-by: Xiang, Haihao
Can the gen8_gpe_context_add_surface follow the similar logic in
gen9_gpe_context_add_surface?
>2d_surface&& override_offset
I won't use override offset, so I didn't add the support for override offset in
this patch.
Of course I can add it if it is useful to you
Yes. It is useful.
It will be great if it can be added.
>2d&& is_uv
>2d
>adv
>buffer
The 2d_surface&& override_offset is especially useful to add the U/V plane
of I420/YUV surface.
Thanks
---
src/i965_gpe_utils.c | 231
+++
src/i965_gpe_utils.h | 5 ++
2 files changed, 236 insertions(+)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index d1b1941..e7f1c25 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -2206,3 +2206,234 @@
gen8_gpe_reset_binding_table(VADriverContextP ctx, struct
i965_gpe_context *gpe_
dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
}
+
+static void
+gen8_gpe_set_2d_surface_state(struct gen8_surface_state *ss,
+ unsigned int vert_line_stride_offset,
+ unsigned int vert_line_stride,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.vert_line_stride_ofs = vert_line_stride_offset;
+ss->ss0.vert_line_stride = vert_line_stride;
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_2D;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = width - 1;
+ss->ss2.height = height - 1;
+
+ss->ss3.pitch = pitch - 1;
+
+ss->ss5.y_offset = y_offset;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+
+gen8_gpe_set_surface_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_adv_surface_state(struct gen8_surface_state2 *ss,
+ unsigned int v_direction,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_cb_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
+ss->ss1.width = width - 1;
+ss->ss1.height = height - 1;
+
+ss->ss2.surface_format = format;
+ss->ss2.interleave_chroma = 1;
+ss->ss2.pitch = pitch - 1;
+
+ss->ss3.y_offset_for_cb = y_cb_offset;
+
+ss->ss5.surface_object_mocs = cacheability_control;
+
+ss->ss6.base_addr = base_offset;
+
+gen8_gpe_set_surface2_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_buffer2_surface_state(struct gen8_surface_state *ss,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int size,
+ unsigned int pitch,
+ unsigned int base_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_BUFFER;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = (size - 1)& 0x7F;
+ss->ss2.height = ((size - 1)& 0x1FFF80)>> 7;
+
+ss->ss3.depth = ((size - 1)& 0xFE0)>> 21;
+ss->ss3.pitch = pitch - 1;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+}
+
+void
+gen8_gpe_con
Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function gen8_gpe_context_add_surface() to set surface state on GEN8
>-Original Message-
>From: Zhao, Yakui
>Sent: Thursday, November 17, 2016 9:14 PM
>To: Xiang, Haihao
>Cc: libva@lists.freedesktop.org
>Subject: Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function
>gen8_gpe_context_add_surface() to set surface state on GEN8
>
>On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
>> Signed-off-by: Xiang, Haihao
>
>Can the gen8_gpe_context_add_surface follow the similar logic in
>gen9_gpe_context_add_surface?
>>2d_surface && override_offset
I won't use override offset, so I didn't add the support for override offset in
this patch.
Of course I can add it if it is useful to you
>>2d && is_uv
>>2d
>>adv
>>buffer
>
>The 2d_surface && override_offset is especially useful to add the U/V plane
>of I420/YUV surface.
>
>
>Thanks
>
>
>> ---
>> src/i965_gpe_utils.c | 231
>+++
>> src/i965_gpe_utils.h | 5 ++
>> 2 files changed, 236 insertions(+)
>>
>> diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
>> index d1b1941..e7f1c25 100644
>> --- a/src/i965_gpe_utils.c
>> +++ b/src/i965_gpe_utils.c
>> @@ -2206,3 +2206,234 @@
>gen8_gpe_reset_binding_table(VADriverContextP ctx, struct
>i965_gpe_context *gpe_
>>
>> dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
>> }
>> +
>> +static void
>> +gen8_gpe_set_2d_surface_state(struct gen8_surface_state *ss,
>> + unsigned int vert_line_stride_offset,
>> + unsigned int vert_line_stride,
>> + unsigned int cacheability_control,
>> + unsigned int format,
>> + unsigned int tiling,
>> + unsigned int width,
>> + unsigned int height,
>> + unsigned int pitch,
>> + unsigned int base_offset,
>> + unsigned int y_offset)
>> +{
>> +memset(ss, 0, sizeof(*ss));
>> +
>> +ss->ss0.vert_line_stride_ofs = vert_line_stride_offset;
>> +ss->ss0.vert_line_stride = vert_line_stride;
>> +ss->ss0.surface_format = format;
>> +ss->ss0.surface_type = I965_SURFACE_2D;
>> +
>> +ss->ss1.surface_mocs = cacheability_control;
>> +
>> +ss->ss2.width = width - 1;
>> +ss->ss2.height = height - 1;
>> +
>> +ss->ss3.pitch = pitch - 1;
>> +
>> +ss->ss5.y_offset = y_offset;
>> +
>> +ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
>> +ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
>> +ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
>> +ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
>> +
>> +ss->ss8.base_addr = base_offset;
>> +
>> +gen8_gpe_set_surface_tiling(ss, tiling);
>> +}
>> +
>> +static void
>> +gen8_gpe_set_adv_surface_state(struct gen8_surface_state2 *ss,
>> + unsigned int v_direction,
>> + unsigned int cacheability_control,
>> + unsigned int format,
>> + unsigned int tiling,
>> + unsigned int width,
>> + unsigned int height,
>> + unsigned int pitch,
>> + unsigned int base_offset,
>> + unsigned int y_cb_offset)
>> +{
>> +memset(ss, 0, sizeof(*ss));
>> +
>> +ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
>> +ss->ss1.width = width - 1;
>> +ss->ss1.height = height - 1;
>> +
>> +ss->ss2.surface_format = format;
>> +ss->ss2.interleave_chroma = 1;
>> +ss->ss2.pitch = pitch - 1;
>> +
>> +ss->ss3.y_offset_for_cb = y_cb_offset;
>> +
>> +ss->ss5.surface_object_mocs = cacheability_control;
>> +
>> +ss->ss6.base_addr = base_offset;
>> +
>> +gen8_gpe_set_surface2_tiling(ss, tiling);
>> +}
>> +
>> +static void
>> +gen8_gpe_set_buffer2_surface_state(struct gen8_surface_state *ss,
>> + unsigned int cacheability_control,
>> + unsigned int format,
>> + unsigned int size,
>> +
Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function gen8_gpe_context_add_surface() to set surface state on GEN8
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
Signed-off-by: Xiang, Haihao
Can the gen8_gpe_context_add_surface follow the similar logic in
gen9_gpe_context_add_surface?
>2d_surface && override_offset
>2d && is_uv
>2d
>adv
>buffer
The 2d_surface && override_offset is especially useful to add the
U/V plane of I420/YUV surface.
Thanks
---
src/i965_gpe_utils.c | 231 +++
src/i965_gpe_utils.h | 5 ++
2 files changed, 236 insertions(+)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index d1b1941..e7f1c25 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -2206,3 +2206,234 @@ gen8_gpe_reset_binding_table(VADriverContextP ctx,
struct i965_gpe_context *gpe_
dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
}
+
+static void
+gen8_gpe_set_2d_surface_state(struct gen8_surface_state *ss,
+ unsigned int vert_line_stride_offset,
+ unsigned int vert_line_stride,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.vert_line_stride_ofs = vert_line_stride_offset;
+ss->ss0.vert_line_stride = vert_line_stride;
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_2D;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = width - 1;
+ss->ss2.height = height - 1;
+
+ss->ss3.pitch = pitch - 1;
+
+ss->ss5.y_offset = y_offset;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+
+gen8_gpe_set_surface_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_adv_surface_state(struct gen8_surface_state2 *ss,
+ unsigned int v_direction,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_cb_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
+ss->ss1.width = width - 1;
+ss->ss1.height = height - 1;
+
+ss->ss2.surface_format = format;
+ss->ss2.interleave_chroma = 1;
+ss->ss2.pitch = pitch - 1;
+
+ss->ss3.y_offset_for_cb = y_cb_offset;
+
+ss->ss5.surface_object_mocs = cacheability_control;
+
+ss->ss6.base_addr = base_offset;
+
+gen8_gpe_set_surface2_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_buffer2_surface_state(struct gen8_surface_state *ss,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int size,
+ unsigned int pitch,
+ unsigned int base_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_BUFFER;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = (size - 1)& 0x7F;
+ss->ss2.height = ((size - 1)& 0x1FFF80)>> 7;
+
+ss->ss3.depth = ((size - 1)& 0xFE0)>> 21;
+ss->ss3.pitch = pitch - 1;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+}
+
+void
+gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
+ struct i965_gpe_surface *gpe_surface,
+ int index)
+{
+char *buf;
+unsigned int tiling, swizzle, width, height, pitch, tile_alignment,
y_offset = 0;
+unsigned int surface_state_offset =
gpe_context->surface_state_binding_table.surface_state_offset +
+index * SURFACE_STATE_PADDED_SIZE_GEN8;
+unsigned int binding_table_offset =
gpe_context->surface_state_binding_table.binding_table_offset +
+index * 4;
+struct i965_gpe_resource *gpe_resource = gpe_surface->gpe_resource;
+
+dri_bo_get_tiling(gpe_resource->bo,&tiling,&swizzle);
+
+dri_bo_map(gpe_context->surface_sta
[Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function gen8_gpe_context_add_surface() to set surface state on GEN8
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 231 +++
src/i965_gpe_utils.h | 5 ++
2 files changed, 236 insertions(+)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index d1b1941..e7f1c25 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -2206,3 +2206,234 @@ gen8_gpe_reset_binding_table(VADriverContextP ctx,
struct i965_gpe_context *gpe_
dri_bo_unmap(gpe_context->surface_state_binding_table.bo);
}
+
+static void
+gen8_gpe_set_2d_surface_state(struct gen8_surface_state *ss,
+ unsigned int vert_line_stride_offset,
+ unsigned int vert_line_stride,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.vert_line_stride_ofs = vert_line_stride_offset;
+ss->ss0.vert_line_stride = vert_line_stride;
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_2D;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = width - 1;
+ss->ss2.height = height - 1;
+
+ss->ss3.pitch = pitch - 1;
+
+ss->ss5.y_offset = y_offset;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+
+gen8_gpe_set_surface_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_adv_surface_state(struct gen8_surface_state2 *ss,
+ unsigned int v_direction,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int tiling,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ unsigned int base_offset,
+ unsigned int y_cb_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss1.cbcr_pixel_offset_v_direction = v_direction;
+ss->ss1.width = width - 1;
+ss->ss1.height = height - 1;
+
+ss->ss2.surface_format = format;
+ss->ss2.interleave_chroma = 1;
+ss->ss2.pitch = pitch - 1;
+
+ss->ss3.y_offset_for_cb = y_cb_offset;
+
+ss->ss5.surface_object_mocs = cacheability_control;
+
+ss->ss6.base_addr = base_offset;
+
+gen8_gpe_set_surface2_tiling(ss, tiling);
+}
+
+static void
+gen8_gpe_set_buffer2_surface_state(struct gen8_surface_state *ss,
+ unsigned int cacheability_control,
+ unsigned int format,
+ unsigned int size,
+ unsigned int pitch,
+ unsigned int base_offset)
+{
+memset(ss, 0, sizeof(*ss));
+
+ss->ss0.surface_format = format;
+ss->ss0.surface_type = I965_SURFACE_BUFFER;
+
+ss->ss1.surface_mocs = cacheability_control;
+
+ss->ss2.width = (size - 1) & 0x7F;
+ss->ss2.height = ((size - 1) & 0x1FFF80) >> 7;
+
+ss->ss3.depth = ((size - 1) & 0xFE0) >> 21;
+ss->ss3.pitch = pitch - 1;
+
+ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+
+ss->ss8.base_addr = base_offset;
+}
+
+void
+gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
+ struct i965_gpe_surface *gpe_surface,
+ int index)
+{
+char *buf;
+unsigned int tiling, swizzle, width, height, pitch, tile_alignment,
y_offset = 0;
+unsigned int surface_state_offset =
gpe_context->surface_state_binding_table.surface_state_offset +
+index * SURFACE_STATE_PADDED_SIZE_GEN8;
+unsigned int binding_table_offset =
gpe_context->surface_state_binding_table.binding_table_offset +
+index * 4;
+struct i965_gpe_resource *gpe_resource = gpe_surface->gpe_resource;
+
+dri_bo_get_tiling(gpe_resource->bo, &tiling, &swizzle);
+
+dri_bo_map(gpe_context->surface_state_binding_table.bo, 1);
+buf = (char *)gpe_context->surface_state_binding_table.bo->virtual;
+*((unsigned int *)(buf + binding_table_offset)) = surface_state_offset;
+
+if (gpe_surface->is_2d_surface) {
+struct gen8_surface_state *ss = (struct gen8_surface_state *)(buf +
surface_state_offset);
+
+width = gp
