[ACTIVITY] 6 - 10 June 2016
* One day off on Thu [2/10] # Progress # * TCWG-639, non-8-byte-aligned watchpoint is missed on aarch64. [4/10]. It is caused by limited kernel BAS support. RedHat reports this problem and posts a patch. Good to see they start to contribute to aarch64 GDB, but I don't like the patch. Spend much time writing a prototype to prove their patch is not perfect. We agree to fix this problem by extend RSP fortunately. * TCWG-333, [3/10] I follow the way how mips does, and fix some bugs. * TCWG-547, TCWG-518, blocked in upstream review. * Misc, meetings. [1/10] # Plan # * TCWG-333, TCWG-556. * Ping TCWG-547, TCWG-518. -- Yao ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 6 - 10 June 2016
== This Week == * LTO (5/10) a) committed r237207 to fix unresolved test-cases added in r236503 (1/10) b) move increase_alignment pass to regular pass (3/10) - Patch iterations based on suggestions from Honza and Richard - Understanding lto streaming and decl merging code c) TCWG-548 (1/10) - WIP patch * TCWG-319 (1/10) - updated patch submitted upstream: - changing vect_hw_misalign causes regression for vect-align-1.c * Benchmarking (1/10) - Benchmark successfully ran for linaro-gcc-5 submitted by Yvan - Benchmark for fsf-gcc-6 failed both with prebuilt route and letting job build the benchmark * Misc (3/10) - Meetings - Travel to Mumbai for Schengen Visa appointment == Next Week == - Try to get patch committed for increase_alignment - TCWG-319: Look at vect-align-1.c regression - TCWG-548: Complete implementation and validate patch. - ipa-vrp: Experiment with Kugan's patch. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 6-10 June 2016
== Progress == * Validation - disk full on one builder caused problem during the validation of the long series of backports. We'll have to refine the cleanup policy. - switch to docker on-hold until the builders are upgraded * ABE - looked a bit at the gdb/gdbserver issue * Backports - used a script to process the spreadsheet and submitted all the backports that backflip was able to complete in batch mode (a lot!) - fsf-5-branch merge review * GCC - regression reports on trunk, chasing problems that occur in corner case configurations - One of the Neon intrinsics tests I committed recently wrongly executed v8 Neon code on v7 HW: I didn't catch this earlier because of a bug in qemu, promptly fixed by Peter Maydell - neon-testgen.ml removal delayed because other cleanup is desirable before (fixing neon* effective-target tests on-going) - started looking at PR 67591 (ARM v8 Thumb IT blocks deprecated) * Support - started looking at bug 2315 * Misc (conf-calls, meetings, emails, ...) == Next == * Validation: - patch reviews - look at disk management/cleanup * Backports - check validation results * GCC - monitor trunk regressions - fix "check_vect" guard in gcc.dg/vect tests - fix neon* effective-target - hopefully test-neongen.ml removal - pr 67591 - advsimd tests ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 6-10 June 2016
== Progress == TCWG-607 Initial ARM port for LLD committed upstream. Hello World on an ARM with an ARM only gcc libc is possible, but not much else. TCWG-611 Initial Thumb support sent for upstream review. Interworking is possible at the BLX level but full interworking support (veneers/thunks) isn't there yet. With this patch it will be possible to do Hello World with a recent Linaro gcc release. TCWG-634 llvm-mc putting out R_ARM_THM_PC24 for B.W instead of R_ARM_THM_PC19. Simple fix now committed upstream. == Plans == Interworking thunks for lld. The existing thunk design is very simple and only supports one type of thunk per target. For interworking we need at least two (ARM to Thumb) and (Thumb to ARM). I think it might be possible to fit a basic implementation just good enough for ARMv7a to be correct into the existing mechanism, however just one more thunk type will need a more sophisticated design. Current thought is to try and implement the basic design to learn a bit more about the mechanism as it will hopefully not take too long. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 6-10 June 2016
== Progress == * Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10] - This is a follow-up of TCWG-592: when changing the diag handler, some of the tests started to fail, so we had to add an exit-on-error flag to preserve the old behaviour until we can fix the tests. - Patch fixing the MIR tests (PR27770) - committed upstream - Submitted a patch fixing one of the AMDGPU tests (PR27761) - in upstream review - Submitted a patch fixing the ARM test (PR27765) - in upstream review * Use git worktree in llvm helper scripts [TCWG-587] [1/10] - Minor fixes during the review, hopefully we can wrap it up soon * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [3/10] - Investigated uses of isCortexA*, isSwift etc in the ARM backend - Started extracting subtarget features for the easy ones * LLVM ARM 3.8.1 [TCWG-642] [1/10] - Ran the ARM tests for the LLVM 3.8.1 release * Investigate clang-cmake-thumbv7-a15-full-sh failure [TCWG-635] [1/10] - Found patch that was causing problems, started discussion about it on the mailing list == Plan == * Remove exit-on-error flag from CodeGen tests [TCWG-604] - Address any code review comments - After committing the 2 remaining patches, we should be able to remove the flag and wrap this up * ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] - Extract more subtarget features * OOO on Monday ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
