[ACTIVITY] Week 16
o LLVM * Machine outliner: - Re-based on upstream - working on CTMark issue o Misc * BKK19 and EuroLLVM Feedback. * Various meetings and discussions. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
* 3.5 Days EuroLLVM/travel == Progress == o LLVM * Back to benchmarking job o Misc * Various meetings and discussions. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
Progress: - On holiday all week, at ACCU conference. I've put some highlights at the end of the message. - Did some more investigation into TCWG-466 ADRL support in integrated assembler during breaks. -- Not looking good, to do this properly bumps up against a lot of design decisions and restrictions made by the LLVM assembler (designed as compiler target, not to be user friendly). -- There are ways it could be implemented with restrictions, but it is debateable whether it is worth doing at all. -- On the plus side I've got a much better idea of how the assembler works and what restrictions exist on each stage of the journey from a line in the .s file to emission in the object. Will add some comments to the LDR r0, =expr TCWG as well. -- On the negative side the :upper16: and :lower16: operators for MOVT and MOVW don't look to be correct in the presence of addends. Will need to investigate further to see what the scope of the problem is. Plan: - Dump results of TCWG-466 investigation into Jira. - Take a look at and post a comment on Adhemerval's revised TLS patch, even if it is just looks fine in the hope of pushing it forward a bit more. - Catch up with Renato's scripts and documents for LLVM sub-group. - Work out what to do with TCWG-466, if the answer is put it down, find something else to look at. ACCU Highlights/Report: Tough stuff in modern C++ A deep dive into some of the newer areas of C++ such as: - rvalue references and forwarding (universal) references - How to use SFINAE (mostly std::enable_if) to select algorithms optimised for particular template instantiations - Variadic templates. Including all sorts of strange ways to (ab)use expansion of parameter packs. C++ WG21 SG14 Gaming and low-latency study group - A new study group aiming to represent the gaming (primarily), but also embedded and high frequency trading concerns. - Motto seemed to be make sure "Don't pay for what you don't use" is enforced. Most interested in: -- No exceptions configurations -- No RTTI -- More performance out of the STL (see EA STL https://github.com/electronicarts/EASTL) -- Add ring buffers and support for unitialised memory, fixed point numbers, flat-map, standardised simd vector types Using sentinels - An example of how using two sentinels in an implementation of std::partion speeds up the algorithm by saving comparisons. Can speed up quicksort by a few percent Constexpr in C++14 - Example showing how you could build a string to enum map, operating entirely at compile time, and its subsequent negative effects on compile time! Concepts Lite - Concepts missed the C++17 standard, this presentation went into the current Technical Standard (optional) and how concepts would likely be implemented in C++(20?) - Not surprising to see that concepts still missed C++17 as there is only one implementation and one non-trivial use case (ranges) and there are still unresolved questions to be answered. Introduction to Julia - Really a comparison of Julia to the author's favoured language of common lisp. - Was impressed at how "lispy" Julia was whilst retaining high performance. - Liked the mathematical syntax - Didn't like the python like parts that seemed to be added to try and get people to migrate from python, but were non "lispy". ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
== Issues == * Toolchain64 disk full == Progress == * Linaro GCC 4.9 2014.04 (3/10) - Created FSF Linaro 4.9 branch - Testing FSF 4.9.0 RC * Launchpad bugs: (3/10) o LP #1169164 : including signal.h exposes various PSR_MODE #defines - Two possible ways to fix the issue (to be discussed with maintainers) * Misc: o Cbuildv1 baby-sitting (1/10) o Various meetings (1/10). == Next == - Easter Monday off - Continue on LP #1169164 - Linaro GCC 4.9 release (when FSF release will be made) ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
== Progress == TCWG-156 cortex-strings memset (3/10) * Got a full set of benchmarks (for my 2 targets) * Cleaned up code * Sped up small memsets (for A9, A15 results pending) glibc performance bug in lowlevellock.c (1/10 - I'll make a card next week) * Learned to build and test glibc * Understood the bug and worked out how to fix Misc * Meetings/mail (1/10) * Infrastructure/workflow fiddling (1/10) * 2 days holiday == Plan == More TCWG-156 Finish off glibc performance bug Public holidays Friday Monday ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
Summary: * ARM internal training and R/M toolchain related work. * Investigate Linaro toolchain 4.8 build issues. Details: 1. Fix several linaro toolchain 4.8 binary build issues: * nls patch need be updated to add (char *) when assigning the result of xmalloc to a char*. * gcc build pass-2 need build libbacktrace (get patch from crosstool-ng upstream). * gcc build pass-2 build with -j4 fail. Seams build order issue. A workaround is to remove -j4. * Mingw32 confiugre fail due to missing ISL. A workaround is to add --without-isl Plan: * Work with Bero to release 4.8. * Swith to ISL/CLooG for future release. Best Regards! -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
== Issues == * None == Progress == * Libunwind AArch64 support: - Implemented signal frame detection routine. - Resuming with signal is failing, debug ongoing. == Plan == * Libunwind AArch64 support: - Fix and submit upstream ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 16
== Progress == * Further work on glibc memcpy IFUNC patch based on review. * Ported libdwarf to aarch64 and submitted upstream. * Disabled gold build in binutils cbuild job and created a gold job. * Investigated binutils testsuite failure on precise. * On leave Friday. == Issues == * None. == Plan == * Submit a patch for binutils testsuite failure on precise. * Complete work on glibc memcpy iFUNC patch. * Follow up binutils IFUNC patch. * AArch64 IFUNC next... -- Will Newton Toolchain Working Group, Linaro ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week 16
== Progress == * Running around JM/lencode bug - caused by a codegen opt (ICMP fold) that had repercussions only on A9 and A15 code generation - spent three days trying to reduce the case when the problem fixed itself miraculously :( * Planning for the future - Agreeing on short-term plans for Q2 * Buildbot - Working on self-hosting bot - Moved local buildmaster to hackbox * Investigating LLVMLinux - Building Android kernel with LLVM - Investigating breakage in Debug mode == Plans == * Continue self-hosting bot * Try running a CBuild benchmark with LLVM * Start putting up together the infrastructure for release 3.3 * Try to extract useful information from perf database ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[Activity] Week 16
Summary: * Code size benchmark analysis. * Linaro binary toolchain 2012.04 release. Details: 1. Tuning the heuristic to assign register for copies. * Take the CONFLICT_HARD_REGS and HARD_REG_COSTS of copies into account when conflict_costs is NULL in update_conflict_hard_regno_costs, which handles the following case: a = ... ... b = a // a can be assigned with r3 or r5 which have the same min_cost. ... // b is conflicted with r3 or the cost of r3 is very high = b In this case, if a is assigned with r3, b can not be assigned with r3, so the copy b = a can not be optimized. When taking the CONFLICT_HARD_REGS or HARD_REG_COSTS of b into account, we can assign a with r5. 2. Linaro binary toolchain 2012.04 release. * Update gdb/TOOLCHAIN_PKGVERSION/README to 2012.04. * Test workaround localization patch to fix lp:918926. * Local build and tests show the toolchain can find the corresponding .mo file. * But if the host system does not have the corresponding font packages, it will show some mess characters. * gdb does not have gdb.mo. 3. Investigate code size regressions in 4.7. * Loop invariant hoisting might increase register pressure, which leads to much more spilling. Plans: * Finalize Linaro binary toolchain 2012.04 release * Investigate other code size regressions in 4.7. Planed leaves: * Labor Day’s holiday: April 30 and May 1. Best regards! -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
