Re: [RESEND PATCH 2/4] ARM: msm: Re-organize platsmp to make it extensible
On Mon, 12 Aug 2013, Mark Rutland wrote:
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu, map;
+ unsigned int flags = 0;
+
+ for_each_present_cpu(cpu) {
+ map = cpu_logical_map(cpu);
+ if (map ARRAY_SIZE(cold_boot_flags)) {
+ set_cpu_present(cpu, false);
+ __WARN();
+ continue;
+ }
+ flags |= cold_boot_flags[map];
__WARN() can't be used in generic code because it's possible to have
CONFIG_BUG=n, you probably want something like WARN_ON(1) instead.
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[PATCH v4 3/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3/Kconfig|8 +++
drivers/usb/dwc3/Makefile |1 +
drivers/usb/dwc3/dwc3-msm.c | 167 +++
3 files changed, 176 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-msm.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index f969ea2..d845966 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -71,6 +71,14 @@ config USB_DWC3_PCI
One such PCIe-based platform is Synopsys' PCIe HAPS model of
this IP.
+config USB_DWC3_MSM
+ tristate Qualcomm MSM/APQ Platforms
+ default USB_DWC3
+ select USB_MSM_DWC3_PHYS
+ help
+ Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
+ say 'Y' or 'M' if you have one such device.
+
comment Debugging features
config USB_DWC3_DEBUG
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index dd17601..5226681 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -32,3 +32,4 @@ endif
obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o
obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
+obj-$(CONFIG_USB_DWC3_MSM) += dwc3-msm.o
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
new file mode 100644
index 000..361076c
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -0,0 +1,167 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/usb/phy.h
+
+struct dwc3_msm {
+ struct device *dev;
+
+ struct clk *core_clk;
+ struct clk *iface_clk;
+ struct clk *sleep_clk;
+ struct clk *utmi_clk;
+
+ struct regulator*gdsc;
+};
+
+static int dwc3_msm_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev-dev.of_node;
+ struct dwc3_msm *mdwc;
+ struct resource *res;
+ void __iomem *tcsr;
+ int ret = 0;
+
+ mdwc = devm_kzalloc(pdev-dev, sizeof(*mdwc), GFP_KERNEL);
+ if (!mdwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, mdwc);
+ mdwc-dev = pdev-dev;
+
+ mdwc-gdsc = devm_regulator_get(mdwc-dev, gdsc);
+
+ mdwc-core_clk = devm_clk_get(pdev-dev, core);
+ if (IS_ERR(mdwc-core_clk)) {
+ dev_dbg(pdev-dev, failed to get core clock\n);
+ return PTR_ERR(mdwc-core_clk);
+ }
+
+ mdwc-iface_clk = devm_clk_get(pdev-dev, iface);
+ if (IS_ERR(mdwc-iface_clk)) {
+ dev_dbg(pdev-dev, failed to get iface clock\n);
+ return PTR_ERR(mdwc-iface_clk);
+ }
+
+ mdwc-sleep_clk = devm_clk_get(pdev-dev, sleep );
+ if (IS_ERR(mdwc-sleep_clk)) {
+ dev_dbg(pdev-dev, failed to get sleep clock\n);
+ return PTR_ERR(mdwc-sleep_clk);
+ }
+
+ mdwc-utmi_clk = devm_clk_get(pdev-dev, utmi);
+ if (IS_ERR(mdwc-utmi_clk)) {
+ dev_dbg(pdev-dev, failed to get utmi clock\n);
+ return PTR_ERR(mdwc-utmi_clk);
+ }
+
+ if (!IS_ERR(mdwc-gdsc)) {
+ ret = regulator_enable(mdwc-gdsc);
+ if (ret)
+ dev_err(mdwc-dev, cannot enable usb3 gdsc\n);
+ }
+
+ /*
+* DWC3 Core requires its CORE CLK (aka master / bus clk) to
+* run at 125Mhz in SSUSB mode and 60MHZ for HSUSB mode.
+*/
+ clk_set_rate(mdwc-core_clk, 12500);
+ clk_prepare_enable(mdwc-core_clk);
+ clk_prepare_enable(mdwc-iface_clk);
+ clk_prepare_enable(mdwc-sleep_clk);
+ clk_prepare_enable(mdwc-utmi_clk);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ tcsr = devm_ioremap_resource(pdev-dev, res);
+ if (!tcsr) {
+ ret = PTR_ERR(tcsr);
+ goto dis_clks;
+ }
+
+ /*
+* Primary USB port is shared between USB2 and USB3 controllers.
+
[PATCH v4 0/3] DWC3 USB support for Qualcomm platform
From: Ivan T. Ivanov iiva...@mm-sol.com Hi, Here is fourth version of MSM USB3 drivers patches. Changes since v3: * Remove _clk suffix from clock names * Clarify required child node for qcom,dwc3 * Fix comments in functions headers * Use dbg instead err in drivers probe functions. Changes since v2: * Several improvements in devicetree bindings description * Disable regulators in glue layer if there is error during ioremap. Changes since first version: * Split devicetree bindings description file to separate patch * Address comments for device bindings description * Fix typo in 'gdsc' requlator name. These patches add basic support for USB3.0 controllers found on MSM platforms. USB3.0 core is based on Synopsys DesignWare SuperSpeed IP. Generated on top of Felipe 'testing' branch. Ivan T. Ivanov (3): usb: dwc3: msm: Add device tree binding information usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core usb: dwc3: Add Qualcomm DWC3 glue layer driver .../devicetree/bindings/usb/msm-ssusb.txt | 104 ++ drivers/usb/dwc3/Kconfig |8 + drivers/usb/dwc3/Makefile |1 + drivers/usb/dwc3/dwc3-msm.c| 167 + drivers/usb/phy/Kconfig| 11 + drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 + drivers/usb/phy/phy-msm-dwc3-ss.c | 374 8 files changed, 994 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt create mode 100644 drivers/usb/dwc3/dwc3-msm.c create mode 100644 drivers/usb/phy/phy-msm-dwc3-hs.c create mode 100644 drivers/usb/phy/phy-msm-dwc3-ss.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/3] usb: dwc3: msm: Add device tree binding information
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 104
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 000..cacbd3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,104 @@
+MSM SuperSpeed DWC3 USB SoC controller
+
+
+DWC3 Highspeed USB PHY
+==
+Required properities :
+- compatible : sould be qcom,dwc3-hsphy;
+- reg : offset and length of the register set in the memory map
+- clocks : phandles to clock instances of the device tree nodes
+- clock-names :
+ xo : External reference clock 19 MHz
+ sleep_a : Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+supply-name-supply : phandle to the regulator device tree node
+Required supply-name are:
+ v1p8 : 1.8v supply for HSPHY
+ v3p3 : 3.3v supply for HSPHY
+ vbus : vbus supply for host mode
+ vddcx : vdd supply for HS-PHY digital circuit operation
+
+DWC3 Superspeed USB PHY
+===
+Required properities :
+- compatible : sould be qcom,dwc3-ssphy;
+- reg : offset and length of the register set in the memory map
+- clocks : phandles to clock instances of the device tree nodes
+- clock-names :
+ xo : External reference clock 19 MHz
+ ref : Reference clock - used in host mode.
+supply-name-supply : phandle to the regulator device tree node
+Required supply-name are:
+ v1p8 : 1.8v supply for SS-PHY
+ vddcx : vdd supply for SS-PHY digital circuit operation
+
+DWC3 controller wrapper
+===
+Required properties :
+- compatible : should be qcom,dwc3
+- reg : offset and length of the register set in the memory map
+ offset and length of the TCSR register for routing USB
+ signals to either picoPHY0 or picoPHY1.
+- clocks : phandles to clock instances of the device tree nodes
+- clock-names :
+ core : Master/Core clock, have to be = 125 MHz for SS
+ operation and = 60MHz for HS operation
+ iface : System bus AXI clock
+ sleep : Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+ utmi : Generated by HS-PHY. Used to clock the low power
+ parts of thr HS Link layer.
+Optional properties :
+- gdsc-supply : phandle to the globally distributed switch controller
+ regulator node to the USB controller.
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Example device nodes:
+
+ dwc3_hsphy: phy@f92f8800 {
+ compatible = qcom,dwc3-hsphy;
+ reg = 0xf92f8800 0x30;
+
+ clocks = cxo, usb2a_phy_sleep_cxc;
+ clock-names = xo, sleep_a;
+
+ vbus-supply = supply;
+ vddcx-supply = supply;
+ v1p8-supply = supply;
+ v3p3-supply = supply;
+ };
+
+ dwc3_ssphy: phy@f92f8830 {
+ compatible = qcom,dwc3-ssphy;
+ reg = 0xf92f8830 0x30;
+
+ clocks = cxo, usb30_mock_utmi_cxc;
+ clock-names = xo, ref;
+
+ vddcx-supply = supply;
+ v1p8-supply = supply;
+ };
+
+ usb@fd4ab000 {
+ compatible = qcom,dwc3;
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0xfd4ab000 0x4;
+
+ clocks = usb30_master_cxc, sys_noc_usb3_axi_cxc,
+ usb30_sleep_cxc, usb30_mock_utmi_cxc;
+ clock-names = core, iface, sleep, utmi;
+
+ gdsc-supply = supply;
+
+ ranges;
+ dwc3@f920 {
+ compatible = snps,dwc3;
+ reg = 0xf920 0xcd00;
+ interrupts = 0 131 0;
+ usb-phy = dwc3_hsphy, dwc3_ssphy;
+ tx-fifo-resize;
+ };
+ };
--
1.7.9.5
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[PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile |2 +
drivers/usb/phy/phy-msm-dwc3-hs.c | 327
drivers/usb/phy/phy-msm-dwc3-ss.c | 374 +
4 files changed, 714 insertions(+)
create mode 100644 drivers/usb/phy/phy-msm-dwc3-hs.c
create mode 100644 drivers/usb/phy/phy-msm-dwc3-ss.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index d5589f9..c525835 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -214,6 +214,17 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called phy-rcar-usb.
+config USB_MSM_DWC3_PHYS
+ tristate Qualcomm DWC3 USB controller PHY's support
+ depends on (USB || USB_GADGET) ARCH_MSM
+ select USB_PHY
+ help
+ Enable this to support the USB PHY transceivers on MSM chips with
+ DWC3 USB core. It handles PHY initialization, clock management
+ required after resetting the hardware and power management.
+ This driver is required even for peripheral only or host only
+ mode configurations.
+
config USB_ULPI
bool Generic ULPI Transceiver Driver
depends on ARM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 2135e85..8f2dd94 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)+= phy-msm-dwc3-hs.o
+obj-$(CONFIG_USB_MSM_DWC3_PHYS)+= phy-msm-dwc3-ss.o
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-msm-dwc3-hs.c
b/drivers/usb/phy/phy-msm-dwc3-hs.c
new file mode 100644
index 000..840e766
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dwc3-hs.c
@@ -0,0 +1,327 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/usb/phy.h
+
+/**
+ * USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_CTRL_REG (0x04)
+#define QSCRATCH_GENERAL_CFG (0x08)
+#define PHY_CTRL_REG (0x10)
+#define PARAMETER_OVERRIDE_X_REG (0x14)
+#define CHARGING_DET_CTRL_REG (0x18)
+#define CHARGING_DET_OUTPUT_REG(0x1c)
+#define ALT_INTERRUPT_EN_REG (0x20)
+#define PHY_IRQ_STAT_REG (0x24)
+#define CGCTL_REG (0x28)
+
+#define PHY_3P3_VOL_MIN305 /* uV */
+#define PHY_3P3_VOL_MAX330 /* uV */
+#define PHY_3P3_HPM_LOAD 16000 /* uA */
+
+#define PHY_1P8_VOL_MIN180 /* uV */
+#define PHY_1P8_VOL_MAX180 /* uV */
+#define PHY_1P8_HPM_LOAD 19000 /* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO 1 /* uV */
+#define USB_VDDCX_MIN 5 /* uV */
+#define USB_VDDCX_MAX 7 /* uV */
+
+struct msm_dwc3_hs_phy {
+ struct usb_phy phy;
+ void __iomem*base;
+ struct device *dev;
+
+ struct clk *xo_clk;
+ struct clk *sleep_a_clk;
+
+ struct regulator*v3p3;
+ struct regulator*v1p8;
+ struct regulator*vddcx;
+ struct regulator*vbus;
+};
+
+#definephy_to_dwc3_phy(x) container_of((x), struct
msm_dwc3_hs_phy, phy)
+
+
+/**
+ * Write register.
+ *
+ * @base - MSM DWC3 PHY base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ */
+static inline void msm_dwc3_hs_write(void __iomem *base, u32 offset, u32 val)
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi, On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. -- balbi signature.asc Description: Digital signature
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) -- balbi signature.asc Description: Digital signature
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. Regards, Ivan -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. isn't it a memory mapped IP ? doesn't synopsys provide their own set of registers ? -- balbi signature.asc Description: Digital signature
Re: [PATCH 2/4] devicetree: serial: Document msm_serial bindings
On Aug 19, 2013, at 4:39 PM, Stephen Boyd wrote:
The msm serial device bindings were added to the DTS files but
never documented. Let's document them now and also fix things up
so that it's clearer what hardware is supported. Instead of using
hsuart (for high speed uart), let's use uartdm because that
matches the actual name of the hardware. Also, let's add the
version information in case we need to differentiate between
different versions of the hardware in the future.
Cc: David Brown dav...@codeaurora.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
.../devicetree/bindings/serial/msm_serial.txt | 82 ++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/msm_serial.txt
diff --git a/Documentation/devicetree/bindings/serial/msm_serial.txt
b/Documentation/devicetree/bindings/serial/msm_serial.txt
new file mode 100644
index 000..a6efac3
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/msm_serial.txt
@@ -0,0 +1,82 @@
+* MSM Serial UART and UARTDM
+
+There are two MSM serial hardware designs. UARTDM is designed for use with a
+dma engine in high-speed use cases and the non-DM design is for lower speed
use
+cases. The two designs are mostly compatible from a software perspective
except
+the non-DM design can only read and write one character at a time and so the
+register layout differs slightly.
I think you split this into two binding spec docs, one for each type of uart.
+
+UART
+
+Required properties:
+- compatible: Should contain qcom,msm-uart
+- reg: Should contain UART register location and length. The first
first? is there more than one reg region?
+ register shall specify the main control registers
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock.
+- clock-names: Should be core_clk.
+
+Optional properties:
+- dmas: Should contain dma specifiers for transmit and receive
+- dma-names: Should contain tx for transmit and rx for receive
confused, above you say the non-DM doesn't support DMA so, why the optional
props?
+
+Example:
+
+A uart device with dma capabilities.
+
+serial@a9c0 {
+ compatible = qcom,msm-uart;
+ reg = 0xa9c0 0x1000;
+ interrupts = 11;
+ clocks = uart_cxc;
+ clock-names = core_clk;
+ dmas = dma0 0, dma0 1;
+ dma-names = tx, rx;
+};
+
+UARTDM
+--
+Required properties:
+- compatible: Should contain at least qcom,msm-uartdm.
+ A more specific property should be specified as follows
depending
+ on the version:
+ qcom,msm-uartdm-v1.1
+ qcom,msm-uartdm-v1.2
+ qcom,msm-uartdm-v1.3
+ qcom,msm-uartdm-v1.4
+- reg: Should contain UART register locations and lengths. The first
+ register shall specify the main control registers. An optional second
+ register location shall specify the GSBI control region.
Is GSBI region existing tied to particular versions (if so can we say that)
reg-names?
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock and the ahb clock.
nit, ahb in caps?
+- clock-names: Should be core_clk for the core clock and iface_clk for
the
+ahb clock.
+
+Optional properties:
+- dmas: Should contain dma specifiers for transmit and receive channels
+- dma-names: Should contain tx for transmit and rx for receive channels
+
+Examples:
+
+A uartdm v1.4 device with dma capabilities.
+
+serial@f991e000 {
+ compatible = qcom,msm-uartdm-v1.4, qcom,msm-uartdm;
+ reg = 0xf991e000 0x1000;
+ interrupts = 0 108 0x0;
+ clocks = blsp1_uart2_apps_cxc, blsp1_ahb_cxc;
+ clock-names = core_clk, iface_clk;
+ dmas = dma0 0, dma0 1;
+ dma-names = tx, rx;
+};
+
+A uartdm v1.3 device without dma capabilities.
+
+serial@19c4 {
+ compatible = qcom,msm-uartdm-v1.3, qcom,msm-uartdm;
+ reg = 0x19c4 0x1000,
+ 0x19c0 0x1000;
+ interrupts = 0 195 0x0;
+ clocks = gsbi5_uart_cxc, gsbi5_ahb_cxc;
+ clock-names = core_clk, iface_clk;
+};
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Re: [PATCH v3] hwspinlock/msm: Add support for Qualcomm MSM HW Mutex block
On Aug 16, 2013, at 5:55 PM, Stephen Warren wrote: On 08/14/2013 01:09 PM, Kumar Gala wrote: Add driver for Qualcomm MSM Hardware Mutex block that exists on newer MSM SoC (MSM8974, etc). diff --git a/Documentation/devicetree/bindings/hwlock/msm-tcsr-mutex.txt b/Documentation/devicetree/bindings/hwlock/msm-tcsr-mutex.txt +Required properties: +- compatible: should be qcom,tcsr-mutex +- reg: Should contain registers location and length of mutex registers +- reg-names: +mutex-base - string to identify mutex registers +- qcom,num-locks: the number of locks/mutexes supported Doesn't the block support any interrupts? I suppose the interrupts property can be optional though even if it does. No interrupts on the block. Aside from the comments re: reg-names, this binding seems fine. -- - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
Hi, On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote: On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. isn't it a memory mapped IP ? doesn't synopsys provide their own set of registers ? From what I see it is not directly mapped. How QSCRATCH write and reads transactions are translated to DW IP is unclear to me. Ivan -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, 2013-08-20 at 16:01 +0100, Kumar Gala wrote: On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote: On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. isn't it a memory mapped IP ? doesn't synopsys provide their own set of registers ? From what I see it is not directly mapped. How QSCRATCH write and reads transactions are translated to DW IP is unclear to me. I think the question is how does SW access them? I afraid the answer may be: it depends on the SOC. In my past I had to initialize a (SATA) PHY by implementing a software JTAG state machine, as the PHY's registers were not memory mapped *at all*. And the IP itself came from Synopsys, Cadence or yet another EDA company... Paweł -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, 2013-08-20 at 10:01 -0500, Kumar Gala wrote: On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote: On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. isn't it a memory mapped IP ? doesn't synopsys provide their own set of registers ? From what I see it is not directly mapped. How QSCRATCH write and reads transactions are translated to DW IP is unclear to me. I think the question is how does SW access them? USB QSCRATCH Hardware registers don't ask me what is this :-) or like Pawel says: it depends on the SOC . Ivan - k -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC v3] mmc: sdhci-msm: Add support for MSM chipsets
This platform driver adds the support of Secure Digital Host
Controller Interface compliant controller in MSM chipsets.
CC: Asutosh Das asuto...@codeaurora.org
CC: Venkat Gopalakrishnan venk...@codeaurora.org
CC: Sahitya Tummala stumm...@codeaurora.org
CC: Subhash Jadavani subha...@codeaurora.org
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
Changes from v2:
- Added DT bindings for clocks
- Moved voltage regulators data to platform data
- Removed unneeded includes
- Removed obsolete and wrapper functions
- Removed error checking where unnecessary
- Removed redundant _clk suffix from clock names
- Just return instead of goto where possible
- Minor fixes
Changes from v1:
- GPIO references are replaced by pinctrl
- DT parsing is done mostly by mmc_of_parse()
- Use of_match_device() for DT matching
- A few minor changes
.../devicetree/bindings/mmc/sdhci-msm.txt | 71 ++
drivers/mmc/host/Kconfig | 13 +
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/sdhci-msm.c | 687
4 files changed, 772 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
create mode 100644 drivers/mmc/host/sdhci-msm.c
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
new file mode 100644
index 000..ee112da
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -0,0 +1,71 @@
+* Qualcomm SDHCI controller (sdhci-msm)
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-msm driver.
+
+Required properties:
+- compatible: should be qcom,sdhci-msm
+- reg: should contain SDHC, SD Core register map
+- reg-names: indicates various resources passed to driver (via reg proptery)
by name
+ reg-names examples are hc_mem and core_mem
+- interrupts: should contain SDHC interrupts
+- interrupt-names: indicates interrupts passed to driver (via interrupts
property) by name
+ interrupt-names examples are hc_irq and pwr_irq
+- supply-name-supply: phandle to the regulator device tree node
+ supply-name examples are vdd and vdd-io
+- pinctrl-names: Should contain only one value - default.
+- pinctrl-0: Should specify pin control groups used for this controller.
+- clocks: phandles to clock instances of the device tree nodes
+- clock-names:
+ iface: Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
+ core: SDC MMC clock (MCLK) (required)
+ bus: SDCC bus voter clock (optional)
+
+Optional properties:
+- qcom,bus-speed-mode - specifies supported bus speed modes by host
+ The supported bus speed modes are :
+ HS200_1p8v - indicates that host can support HS200 at 1.8v
+ HS200_1p2v - indicates that host can support HS200 at 1.2v
+ DDR_1p8v - indicates that host can support DDR mode at 1.8v
+ DDR_1p2v - indicates that host can support DDR mode at 1.2v
+
+In the following, supply can be vdd (flash core voltage) or vdd-io (I/O
voltage).
+- qcom,supply-always-on - specifies whether supply should be kept on
always.
+- qcom,supply-lpm-sup - specifies whether supply can be kept in low power
mode (lpm).
+- qcom,supply-voltage-level - specifies voltage levels for supply. Should be
+specified in pairs (min, max), units uV.
+- qcom,supply-current-level - specifies load levels for supply in lpm or
high power mode
+ (hpm). Should be specified in pairs (lpm, hpm), units uA.
+
+Example:
+
+ aliases {
+ sdhc1 = sdhc_1;
+ };
+
+ sdhc_1: qcom,sdhc@f9824900 {
+ compatible = qcom,sdhci-msm;
+ reg = 0xf9824900 0x11c, 0xf9824000 0x800;
+ reg-names = hc_mem, core_mem;
+ interrupts = 0 123 0, 0 138 0;
+ interrupt-names = hc_irq, pwr_irq;
+ bus-width = 4;
+ non-removable;
+
+ vdd-supply = pm8941_l21;
+ vdd-io-supply = pm8941_l13;
+ qcom,vdd-voltage-level = 295 295;
+ qcom,vdd-current-level = 9000 80;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = 180 295;
+ qcom,vdd-io-current-level = 6 22000;
+ qcom,bus-speed-mode = HS200_1p8v, DDR_1p8v;
+
+ pinctrl-names = default;
+ pinctrl-0 = sdc1_clk sdc1_cmd sdc1_data;
+
+ clocks = iface, core, bus;
+ clock-names = iface, core, bus;
+
+ };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8a4c066..2b31471 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -322,6 +322,19 @@ config MMC_ATMELMCI
If unsure, say N.
+config MMC_SDHCI_MSM
+ tristate Qualcomm SDHCI Controller Support
+ depends on ARCH_MSM
+ depends on
Re: [PATCH 2/4] devicetree: serial: Document msm_serial bindings
On 08/20/13 07:41, Kumar Gala wrote:
On Aug 19, 2013, at 4:39 PM, Stephen Boyd wrote:
diff --git a/Documentation/devicetree/bindings/serial/msm_serial.txt
b/Documentation/devicetree/bindings/serial/msm_serial.txt
new file mode 100644
index 000..a6efac3
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/msm_serial.txt
@@ -0,0 +1,82 @@
+* MSM Serial UART and UARTDM
+
+There are two MSM serial hardware designs. UARTDM is designed for use with a
+dma engine in high-speed use cases and the non-DM design is for lower speed
use
+cases. The two designs are mostly compatible from a software perspective
except
+the non-DM design can only read and write one character at a time and so the
+register layout differs slightly.
I think you split this into two binding spec docs, one for each type of uart.
Should split into two files? I can do that.
+
+UART
+
+Required properties:
+- compatible: Should contain qcom,msm-uart
+- reg: Should contain UART register location and length. The first
first? is there more than one reg region?
+ register shall specify the main control registers
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock.
+- clock-names: Should be core_clk.
+
+Optional properties:
+- dmas: Should contain dma specifiers for transmit and receive
+- dma-names: Should contain tx for transmit and rx for receive
confused, above you say the non-DM doesn't support DMA so, why the optional
props?
Ah sorry, copy pasta.
+
+Example:
+
+A uart device with dma capabilities.
+
+serial@a9c0 {
+compatible = qcom,msm-uart;
+reg = 0xa9c0 0x1000;
+interrupts = 11;
+clocks = uart_cxc;
+clock-names = core_clk;
+dmas = dma0 0, dma0 1;
+dma-names = tx, rx;
+};
+
+UARTDM
+--
+Required properties:
+- compatible: Should contain at least qcom,msm-uartdm.
+ A more specific property should be specified as follows
depending
+ on the version:
+qcom,msm-uartdm-v1.1
+qcom,msm-uartdm-v1.2
+qcom,msm-uartdm-v1.3
+qcom,msm-uartdm-v1.4
+- reg: Should contain UART register locations and lengths. The first
+ register shall specify the main control registers. An optional second
+ register location shall specify the GSBI control region.
Is GSBI region existing tied to particular versions (if so can we say that)
Not really. GSBI will always be related to v1.3 but not all v1.3
hardware is part of a GSBI.
reg-names?
Optional should be fine? The driver is already handling this without
reg-names.
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock and the ahb clock.
nit, ahb in caps?
Done.
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Re: [PATCH v4 2/3] usb: phy: Add Qualcomm SS-USB and HS-USB drivers for DWC3 core
On Tue, 2013-08-20 at 16:06 +0100, Pawel Moll wrote: On Tue, 2013-08-20 at 16:01 +0100, Kumar Gala wrote: On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote: On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote: Hi, On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote: Hi, On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote: On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-msm-dwc3-hs.c | 327 drivers/usb/phy/phy-msm-dwc3-ss.c | 374 + please rename these PHY drivers, they have nothing to do with DWC3. PHYs don't care about the USB controller. I think they are SNPS DesignWare PHY's, additionally wrapped with Qualcomm logic. I could substitute dwc3 with just dw, which will be more correct. alright, thank you. Let's add Paul to the loop since he might have very good insight in the synopsys PHYs. mental note: if any other platform shows up with Synopsys PHY, ask them to use this driver instead :-) I really doubt that this will bi possible. Control of the PHY's is not directly trough ULPI, UTMI or PIPE3 interfaces, but trough QSCRATCH registers, which of course is highly Qualcomm specific. isn't it a memory mapped IP ? doesn't synopsys provide their own set of registers ? From what I see it is not directly mapped. How QSCRATCH write and reads transactions are translated to DW IP is unclear to me. I think the question is how does SW access them? I afraid the answer may be: it depends on the SOC. In my past I had to initialize a (SATA) PHY by implementing a software JTAG state machine, as the PHY's registers were not memory mapped *at all*. And the IP itself came from Synopsys, Cadence or yet another EDA company... Having said all that... If the PHY's spec at least defined layout of the registers in question and driver was using regmap API to talk to the device (initially regmap-mmio), it has some chances to become universal. The SOCs designed like my one would have to provide a custom regmap implementation. Paweł -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] devicetree: serial: Document msm_serial bindings
On Aug 20, 2013, at 12:00 PM, Stephen Boyd wrote:
On 08/20/13 07:41, Kumar Gala wrote:
On Aug 19, 2013, at 4:39 PM, Stephen Boyd wrote:
diff --git a/Documentation/devicetree/bindings/serial/msm_serial.txt
b/Documentation/devicetree/bindings/serial/msm_serial.txt
new file mode 100644
index 000..a6efac3
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/msm_serial.txt
@@ -0,0 +1,82 @@
+* MSM Serial UART and UARTDM
+
+There are two MSM serial hardware designs. UARTDM is designed for use with
a
+dma engine in high-speed use cases and the non-DM design is for lower
speed use
+cases. The two designs are mostly compatible from a software perspective
except
+the non-DM design can only read and write one character at a time and so
the
+register layout differs slightly.
I think you split this into two binding spec docs, one for each type of uart.
Should split into two files? I can do that.
yes.
+UART
+
+Required properties:
+- compatible: Should contain qcom,msm-uart
+- reg: Should contain UART register location and length. The first
first? is there more than one reg region?
?
+ register shall specify the main control registers
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock.
+- clock-names: Should be core_clk.
+
+Optional properties:
+- dmas: Should contain dma specifiers for transmit and receive
+- dma-names: Should contain tx for transmit and rx for receive
confused, above you say the non-DM doesn't support DMA so, why the optional
props?
Ah sorry, copy pasta.
+
+Example:
+
+A uart device with dma capabilities.
+
+serial@a9c0 {
+ compatible = qcom,msm-uart;
+ reg = 0xa9c0 0x1000;
+ interrupts = 11;
+ clocks = uart_cxc;
+ clock-names = core_clk;
+ dmas = dma0 0, dma0 1;
+ dma-names = tx, rx;
+};
+
+UARTDM
+--
+Required properties:
+- compatible: Should contain at least qcom,msm-uartdm.
+ A more specific property should be specified as follows
depending
+ on the version:
+ qcom,msm-uartdm-v1.1
+ qcom,msm-uartdm-v1.2
+ qcom,msm-uartdm-v1.3
+ qcom,msm-uartdm-v1.4
+- reg: Should contain UART register locations and lengths. The first
+ register shall specify the main control registers. An optional
second
+ register location shall specify the GSBI control region.
Is GSBI region existing tied to particular versions (if so can we say that)
Not really. GSBI will always be related to v1.3 but not all v1.3
hardware is part of a GSBI.
How about adding that into the binding.
reg-names?
Optional should be fine? The driver is already handling this without
reg-names.
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock and the ahb clock.
nit, ahb in caps?
Done.
- k
--
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