Re: [PATCH] usb: phy: msm: Select secondary PHY via TCSR
Hi, On Fri, Apr 04, 2014 at 03:18:11PM -0700, Tim Bird wrote: Select the secondary PHY using the TCSR register, if phy-num=1 in the DTS (or phy_number is set in the platform data). The SOC has 2 PHYs which can be used with the OTG port, and this code allows configuring the correct one. Note: This resolves the problem I was seeing where I couldn't get the USB driver working at all on a dragonboard, from cold boot. This patch depends on patch 5/14 from Ivan's msm USB patch set. It does not use DT for the register address, as there's no evidence that this address changes between SoC versions. Signed-off-by: Tim Bird tim.b...@sonymobile.com doesn't apply: checking file drivers/usb/phy/phy-msm-usb.c Hunk #1 succeeded at 1412 with fuzz 2 (offset -106 lines). Hunk #2 FAILED at 1581. 1 out of 2 hunks FAILED checking file include/linux/usb/msm_hsusb_hw.h -- balbi signature.asc Description: Digital signature
Re: [PATCH 2/4] soc: qcom: Add GSBI driver
On Mon, Apr 21, 2014 at 12:30:42AM -0500, Andy Gross wrote:
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr...@codeaurora.org
[..]
+++ b/drivers/soc/qcom/qcom_gsbi.c
[..]
+#include linux/clk.h
+#include linux/err.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/platform_device.h
+
+#define GSBI_CTRL_REG0x
+#define GSBI_PROTOCOL_SHIFT 4
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
+
+ struct clk *hclk;
+};
+
+static int gsbi_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev-dev.of_node;
+ struct gsbi_dev *gsbi;
+ struct resource *res;
+ u32 mode;
+
+ gsbi = devm_kzalloc(pdev-dev, sizeof(*gsbi), GFP_KERNEL);
+ if (!gsbi)
+ return -ENOMEM;
+
+ gsbi-dev = pdev-dev;
+ platform_set_drvdata(pdev, gsbi);
+
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+ dev_err(gsbi-dev, missing mode configuration\n);
+ return -EINVAL;
+ }
I'm wondering if you should really be a (very simple) pinctrl driver
proper.
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ gsbi-base = devm_ioremap_resource(gsbi-dev, res);
+ if (IS_ERR(gsbi-base))
+ return PTR_ERR(gsbi-base);
+
+ gsbi-hclk = devm_clk_get(gsbi-dev, iface);
+ if (IS_ERR(gsbi-hclk)) {
+ dev_err(gsbi-dev, Could not get core clock\n);
+ return PTR_ERR(gsbi-hclk);
+ }
+ clk_prepare_enable(gsbi-hclk);
+
+ writel_relaxed((mode GSBI_PROTOCOL_SHIFT), gsbi + GSBI_CTRL_REG);
Did you mean: gsbi-base + GSBI_CTRL_REG ?
+
+ /* make sure the gsbi control write is not reordered */
+ wmb();
+
+ return of_platform_populate(pdev-dev.of_node, NULL, NULL, pdev-dev);
+}
+
+static int gsbi_remove(struct platform_device *pdev)
+{
+ struct gsbi_dev *gsbi = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(gsbi-hclk);
+
+ return 0;
+}
+
+static struct of_device_id gsbi_dt_match[] = {
const
--
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hosted by The Linux Foundation
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Re: [PATCH 2/4] soc: qcom: Add GSBI driver
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
snip
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
Old habits die hard. I'll remove.
snip
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+ dev_err(gsbi-dev, missing mode configuration\n);
+ return -EINVAL;
+ }
I'm wondering if you should really be a (very simple) pinctrl driver
proper.
Perhaps. But how would i reconcile more than one device node that uses the same
GSBI? One could still trounce the other unless I only allow one setting of the
GSBI.
snip
+ clk_prepare_enable(gsbi-hclk);
+
+ writel_relaxed((mode GSBI_PROTOCOL_SHIFT), gsbi + GSBI_CTRL_REG);
Did you mean: gsbi-base + GSBI_CTRL_REG ?
Ouch, how did this get munged. I'll fix this on resend.
snip
+
+static struct of_device_id gsbi_dt_match[] = {
const
Will fix.
--
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[PATCH RFC 00/12] Add Qualcomm SD Card Controller support.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch series adds Qualcomm SD Card Controller support in pl180 mmci driver. QCom SDCC is basically a pl180, but bit more customized, some of the register layouts and offsets are different to the ones mentioned in pl180 datasheet. The plan is to totally remove the standalone SDCC driver drivers/mmc/host/msm_sdcc.* and start using generic mmci driver for all Qualcomm parts, as we get chance to test on other Qcom boards. To start using the existing mmci driver, a fake amba id for Qualcomm is added in patches: ARM: amba: Add Qualcomm vendor ID. mmc: mmci: Add Qualcomm Id to amba id table. Second change is, adding a 3 clock cycle delay for register writes on QCOM SDCC registers, which is done in patches: mmc: mmci: Add register read/write wrappers. mmc: mmci: Add write delay to variant structure. mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write Third change was to accommodate DATCTRL and MMCICLK register layout changes in Qcom SDCC. Which is done in patches: mmc: mmci: Add Qcom datactrl register variant mmc: mmci: Add Qcom variations to MCICommand register. mmc: mmci: Qcom fix MCICLK register settings. mmc: mmci: Add clock support for Qualcomm. Fourth major change was to add qcom specfic pio read function, the need for this is because the way MCIFIFOCNT register behaved in QCOM SDCC is very different to the one in pl180. This change is done in patch: mmc: mmci: Add Qcom specific pio_read function. Last some Qcom unrelated changes to support Qcom are done in patches: mmc: mmci: use NSEC_PER_SEC macro mmc: mmci: move ST specific register extensions access under condition. This patches are tested in PIO mode on IFC8064 board with both eMMC and external SD card. I would appreciate any feedback/suggestions on the overall approach. Thanks, srini Srinivas Kandagatla (12): ARM: amba: Add Qualcomm vendor ID. mmc: mmci: Add Qualcomm Id to amba id table mmc: mmci: Add Qcom datactrl register variant mmc: mmci: Add register read/write wrappers. mmc: mmci: use NSEC_PER_SEC macro mmc: mmci: Add write delay to variant structure. mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write mmc: mmci: move ST specific register extensions access under condition. mmc: mmci: Qcom fix MCICLK register settings. mmc: mmci: Add clock support for Qualcomm. mmc: mmci: Add Qcom variations to MCICommand register. mmc: mmci: Add Qcom specific pio_read function. drivers/mmc/host/mmci.c | 239 +- drivers/mmc/host/mmci.h | 28 ++ include/linux/amba/bus.h |1 + 3 files changed, 202 insertions(+), 66 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC 03/12] mmc: mmci: Add Qcom datactrl register variant
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 391e8d4..19d6b6f 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -58,6 +58,8 @@ static unsigned int fmax = 515633;
* @sdio: variant supports SDIO
* @st_clkdiv: true if using a ST-specific clock divider algorithm
* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl
register
+ * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
+ * register
* @pwrreg_powerup: power up value for MMCIPOWER register
* @signal_direction: input/out direction of bus signals can be indicated
* @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
@@ -73,6 +75,7 @@ struct variant_data {
boolsdio;
boolst_clkdiv;
boolblksz_datactrl16;
+ boolblksz_datactrl4;
u32 pwrreg_powerup;
boolsignal_direction;
boolpwrreg_clkgate;
@@ -162,6 +165,7 @@ static struct variant_data variant_qcom = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
+ .blksz_datactrl4= true,
.datalength_bits= 24,
.blksz_datactrl4= true,
.pwrreg_powerup = MCI_PWR_UP,
@@ -760,6 +764,8 @@ static void mmci_start_data(struct mmci_host *host, struct
mmc_data *data)
if (variant-blksz_datactrl16)
datactrl = MCI_DPSM_ENABLE | (data-blksz 16);
+ else if (variant-blksz_datactrl4)
+ datactrl = MCI_DPSM_ENABLE | (data-blksz 4);
else
datactrl = MCI_DPSM_ENABLE | blksz_bits 4;
--
1.7.9.5
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[PATCH RFC 06/12] mmc: mmci: Add write delay to variant structure.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds write delay parameter required after each write to controller
registers on some of the SOCs like Qualcomm ones. The delay parameter will
provide information on how many clock cycle delay required after each write.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4f8d0ba..86bf330 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -55,6 +55,8 @@ static unsigned int fmax = 515633;
* is asserted (likewise for RX)
* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
* is asserted (likewise for RX)
+ * @reg_write_delay: delay in number of clock cycles required after each write
+ * to controller registers.
* @sdio: variant supports SDIO
* @st_clkdiv: true if using a ST-specific clock divider algorithm
* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl
register
@@ -72,6 +74,7 @@ struct variant_data {
unsigned intdatalength_bits;
unsigned intfifosize;
unsigned intfifohalfsize;
+ unsigned intreg_write_delay;
boolsdio;
boolst_clkdiv;
boolblksz_datactrl16;
@@ -178,7 +181,12 @@ static inline u32 mmci_readl(struct mmci_host *host, u32
off)
static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off)
{
+ struct variant_data *var = host-variant;
+
writel(data, host-base + off);
+
+ if (var-reg_write_delay host-mclk)
+ udelay(1 + ((var-reg_write_delay * USEC_PER_SEC)/host-mclk));
}
static int mmci_card_busy(struct mmc_host *mmc)
--
1.7.9.5
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[PATCH RFC 04/12] mmc: mmci: Add register read/write wrappers.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller registers.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 114 +--
1 file changed, 61 insertions(+), 53 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 19d6b6f..36db31e 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -171,6 +171,16 @@ static struct variant_data variant_qcom = {
.pwrreg_powerup = MCI_PWR_UP,
};
+static inline u32 mmci_readl(struct mmci_host *host, u32 off)
+{
+ return readl(host-base + off);
+}
+
+static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off)
+{
+ writel(data, host-base + off);
+}
+
static int mmci_card_busy(struct mmc_host *mmc)
{
struct mmci_host *host = mmc_priv(mmc);
@@ -180,7 +190,7 @@ static int mmci_card_busy(struct mmc_host *mmc)
pm_runtime_get_sync(mmc_dev(mmc));
spin_lock_irqsave(host-lock, flags);
- if (readl(host-base + MMCISTATUS) MCI_ST_CARDBUSY)
+ if (mmci_readl(host, MMCISTATUS) MCI_ST_CARDBUSY)
busy = 1;
spin_unlock_irqrestore(host-lock, flags);
@@ -230,7 +240,7 @@ static void mmci_write_clkreg(struct mmci_host *host, u32
clk)
{
if (host-clk_reg != clk) {
host-clk_reg = clk;
- writel(clk, host-base + MMCICLOCK);
+ mmci_writel(host, clk, MMCICLOCK);
}
}
@@ -241,7 +251,7 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32
pwr)
{
if (host-pwr_reg != pwr) {
host-pwr_reg = pwr;
- writel(pwr, host-base + MMCIPOWER);
+ mmci_writel(host, pwr, MMCIPOWER);
}
}
@@ -255,7 +265,7 @@ static void mmci_write_datactrlreg(struct mmci_host *host,
u32 datactrl)
if (host-datactrl_reg != datactrl) {
host-datactrl_reg = datactrl;
- writel(datactrl, host-base + MMCIDATACTRL);
+ mmci_writel(host, datactrl, MMCIDATACTRL);
}
}
@@ -321,7 +331,7 @@ static void mmci_set_clkreg(struct mmci_host *host,
unsigned int desired)
static void
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
{
- writel(0, host-base + MMCICOMMAND);
+ mmci_writel(host, 0, MMCICOMMAND);
BUG_ON(host-data);
@@ -336,18 +346,16 @@ mmci_request_end(struct mmci_host *host, struct
mmc_request *mrq)
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
- void __iomem *base = host-base;
-
if (host-singleirq) {
- unsigned int mask0 = readl(base + MMCIMASK0);
+ unsigned int mask0 = mmci_readl(host, MMCIMASK0);
mask0 = ~MCI_IRQ1MASK;
mask0 |= mask;
- writel(mask0, base + MMCIMASK0);
+ mmci_writel(host, mask0, MMCIMASK0);
}
- writel(mask, base + MMCIMASK1);
+ mmci_writel(host, mask, MMCIMASK1);
}
static void mmci_stop_data(struct mmci_host *host)
@@ -498,7 +506,7 @@ static void mmci_dma_finalize(struct mmci_host *host,
struct mmc_data *data)
/* Wait up to 1ms for the DMA to complete */
for (i = 0; ; i++) {
- status = readl(host-base + MMCISTATUS);
+ status = mmci_readl(host, MMCISTATUS);
if (!(status MCI_RXDATAAVLBLMASK) || i = 100)
break;
udelay(10);
@@ -637,8 +645,8 @@ static int mmci_dma_start_data(struct mmci_host *host,
unsigned int datactrl)
* to fire next DMA request. When that happens, MMCI will
* call mmci_data_end()
*/
- writel(readl(host-base + MMCIMASK0) | MCI_DATAENDMASK,
- host-base + MMCIMASK0);
+ mmci_writel(host, mmci_readl(host, MMCIMASK0) | MCI_DATAENDMASK,
+ MMCIMASK0);
return 0;
}
@@ -756,8 +764,8 @@ static void mmci_start_data(struct mmci_host *host, struct
mmc_data *data)
timeout = data-timeout_clks + (unsigned int)clks;
base = host-base;
- writel(timeout, base + MMCIDATATIMER);
- writel(host-size, base + MMCIDATALENGTH);
+ mmci_writel(host, timeout, MMCIDATATIMER);
+ mmci_writel(host, host-size, MMCIDATALENGTH);
blksz_bits = ffs(data-blksz) - 1;
BUG_ON(1 blksz_bits != data-blksz);
@@ -831,20 +839,19 @@ static void mmci_start_data(struct mmci_host *host,
struct mmc_data *data)
}
mmci_write_datactrlreg(host, datactrl);
- writel(readl(base + MMCIMASK0) ~MCI_DATAENDMASK, base + MMCIMASK0);
+ mmci_writel(host, mmci_readl(host, MMCIMASK0) ~MCI_DATAENDMASK,
+ MMCIMASK0);
[PATCH RFC 10/12] mmc: mmci: Add clock support for Qualcomm.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of support is very much similar to bypass mode but there is no such thing
called bypass mode in MCICLK register of Qcom SD card controller. By default
the clock is directly driven by the clk controller.
This patch adds clock support for Qualcomm SDCC in the driver. This bit of
code is conditioned on hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f465eb5..2cd3a8f 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -291,7 +291,18 @@ static void mmci_set_clkreg(struct mmci_host *host,
unsigned int desired)
host-cclk = 0;
if (desired) {
- if (desired = host-mclk) {
+ if (desired != host-mclk
+ host-hw_designer == AMBA_VENDOR_QCOM) {
+ /* Qcom MCLKCLK register does not define bypass bits */
+ int rc = clk_set_rate(host-clk, desired);
+ if (rc 0) {
+ dev_err(mmc_dev(host-mmc),
+ Error setting clock rate (%d)\n, rc);
+ } else {
+ host-mclk = clk_get_rate(host-clk);
+ host-cclk = host-mclk;
+ }
+ } else if (desired = host-mclk) {
clk = MCI_CLK_BYPASS;
if (variant-st_clkdiv)
clk |= MCI_ST_UX500_NEG_EDGE;
@@ -1612,7 +1623,8 @@ static int mmci_probe(struct amba_device *dev,
* of course.
*/
if (plat-f_max)
- mmc-f_max = min(host-mclk, plat-f_max);
+ mmc-f_max = (host-hw_designer == AMBA_VENDOR_QCOM) ?
+ plat-f_max : min(host-mclk, plat-f_max);
else
mmc-f_max = min(host-mclk, fmax);
dev_dbg(mmc_dev(mmc), clocking block at %u Hz\n, mmc-f_max);
--
1.7.9.5
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[PATCH RFC 12/12] mmc: mmci: Add Qcom specific pio_read function.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With the existing logic and
the MCIFIFOCNT behaviour, mmci_pio_read will loop forever, as the FIFOCNT
register will always return transfer size before reading the FIFO.
This patch implements qcom_pio_read function so as existing mmci_pio_read is
not suitable for Qcom SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 8fcd8ef..585888e 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1047,6 +1047,29 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command
*cmd,
}
}
+static int mmci_qcom_pio_read(struct mmci_host *host, char *buffer,
+unsigned int remain)
+{
+ uint32_t*ptr = (uint32_t *) buffer;
+ int count = 0;
+ struct variant_data *variant = host-variant;
+ int fifo_size = variant-fifosize;
+
+ if (remain % 4)
+ remain = ((remain 2) + 1) 2;
+
+ while (readl(host-base + MMCISTATUS) MCI_RXDATAAVLBL) {
+ *ptr = readl(host-base + MMCIFIFO + (count % fifo_size));
+ ptr++;
+ count += sizeof(uint32_t);
+
+ remain -= sizeof(uint32_t);
+ if (remain == 0)
+ break;
+ }
+ return count;
+}
+
static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int
remain)
{
void __iomem *base = host-base;
@@ -1168,8 +1191,12 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
remain = sg_miter-length;
len = 0;
- if (status MCI_RXACTIVE)
- len = mmci_pio_read(host, buffer, remain);
+ if (status MCI_RXACTIVE) {
+ if (host-hw_designer == AMBA_VENDOR_QCOM)
+ len = mmci_qcom_pio_read(host, buffer, remain);
+ else
+ len = mmci_pio_read(host, buffer, remain);
+ }
if (status MCI_TXACTIVE)
len = mmci_pio_write(host, buffer, remain, status);
--
1.7.9.5
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[PATCH RFC 09/12] mmc: mmci: Qcom fix MCICLK register settings.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch adds new setup and makes it specific to Qcom hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 36 ++--
drivers/mmc/host/mmci.h | 21 +
2 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 179abfb..f465eb5 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -327,13 +327,37 @@ static void mmci_set_clkreg(struct mmci_host *host,
unsigned int desired)
/* Set actual clock for debug */
host-mmc-actual_clock = host-cclk;
- if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_4)
- clk |= MCI_4BIT_BUS;
- if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_8)
- clk |= MCI_ST_8BIT_BUS;
+ if (host-hw_designer == AMBA_VENDOR_QCOM) {
+ clk |= MCI_CLK_QCOM_FLOWENA;
+ clk |= (MCI_CLK_QCOM_SEL_FEEDBACK_CLK
+ MCI_CLK_QCOM_SEL_IN_SHIFT); /* feedback clk */
+ if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_8)
+ clk |= MCI_CLK_QCOM_WIDEBUS_8;
+ else if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_4)
+ clk |= MCI_CLK_QCOM_WIDEBUS_4;
+ else
+ clk |= MCI_CLK_QCOM_WIDEBUS_1;
+
+ if (host-mmc-ios.timing == MMC_TIMING_UHS_DDR50) {
+ /* clear SELECT_IN field */
+ clk = ~(MCI_CLK_QCOM_SEL_MASK
+ MCI_CLK_QCOM_SEL_IN_SHIFT);
+ /* set DDR timing mode */
+ clk |= (MCI_CLK_QCOM_SEL_DDR_MODE
+ MCI_CLK_QCOM_SEL_IN_SHIFT);
+ }
+ clk |= (MCI_CLK_SDC4_MCLK_SEL_MCLK
+ MCI_CLK_SDC4_MCLK_SEL_SHIFT);
- if (host-mmc-ios.timing == MMC_TIMING_UHS_DDR50)
- clk |= MCI_ST_UX500_NEG_EDGE;
+ } else {
+ if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_4)
+ clk |= MCI_4BIT_BUS;
+ if (host-mmc-ios.bus_width == MMC_BUS_WIDTH_8)
+ clk |= MCI_ST_8BIT_BUS;
+
+ if (host-mmc-ios.timing == MMC_TIMING_UHS_DDR50)
+ clk |= MCI_ST_UX500_NEG_EDGE;
+ }
mmci_write_clkreg(host, clk);
}
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 58b1b88..0a6de1c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -31,6 +31,27 @@
/* Modified PL180 on Versatile Express platform */
#define MCI_ARM_HWFCEN (1 12)
+/* Modified on Qualcomm Integrations */
+#define MCI_CLK_QCOM_WIDEBUS_1 (0 10)
+#define MCI_CLK_QCOM_WIDEBUS_4 (2 10)
+#define MCI_CLK_QCOM_WIDEBUS_8 (3 10)
+#define MCI_CLK_QCOM_FLOWENA (1 12)
+#define MCI_CLK_QCOM_INVERTOUT (1 13)
+
+/* select in latch data and command */
+#define MCI_CLK_QCOM_SEL_IN_SHIFT (14)
+#define MCI_CLK_QCOM_SEL_MASK (0x3)
+#define MCI_CLK_QCOM_SEL_RISING_EDGE (1)
+#define MCI_CLK_QCOM_SEL_FEEDBACK_CLK (2)
+#define MCI_CLK_QCOM_SEL_DDR_MODE (3)
+
+/* mclk selection */
+#define MCI_CLK_SDC4_MCLK_SEL_SHIFT(23)
+#define MCI_CLK_SDC4_MCLK_SEL_MASK (0x3)
+#define MCI_CLK_SDC4_MCLK_SEL_FB_CLK (1)
+#define MCI_CLK_SDC4_MCLK_SEL_MCLK (2)
+
+
#define MMCIARGUMENT 0x008
#define MMCICOMMAND0x00c
#define MCI_CPSM_RESPONSE (1 6)
--
1.7.9.5
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[PATCH RFC 11/12] mmc: mmci: Add Qcom variations to MCICommand register.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org Some bits which control Command Path State Machine (CPSM) are new in Qcom integration, so this patch adds support to those bits. Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org --- drivers/mmc/host/mmci.c |4 drivers/mmc/host/mmci.h |7 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 2cd3a8f..8fcd8ef 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -910,6 +910,10 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) if (/*interrupt*/0) c |= MCI_CPSM_INTERRUPT; + if (host-hw_designer == AMBA_VENDOR_QCOM + mmc_cmd_type(cmd) == MMC_CMD_ADTC) + c |= MCI_CSPM_QCOM_DATCMD; + host-cmd = cmd; mmci_writel(host, cmd-arg, MMCIARGUMENT); diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 0a6de1c..2ba0834 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -64,6 +64,13 @@ #define MCI_ST_ENCMD_COMPL (1 12) #define MCI_ST_NIEN(1 13) #define MCI_ST_CE_ATACMD (1 14) +/* Modified on Qualcomm Integrations */ +#define MCI_CSPM_QCOM_DATCMD (1 12) +#define MCI_CSPM_QCOM_MCIABORT (1 13) +#define MCI_CSPM_QCOM_CCSENABLE(1 14) +#define MCI_CSPM_QCOM_CCSDISABLE (1 15) +#define MCI_CSPM_QCOM_AUTO_CMD19 (1 16) +#define MCI_CSPM_QCOM_AUTO_CMD21 (1 21) #define MMCIRESPCMD0x010 #define MMCIRESPONSE0 0x014 -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RFC 05/12] mmc: mmci: use NSEC_PER_SEC macro
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org This patch replaces a constant used in calculating timeout with a proper macro. This is make code more readable. Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org --- drivers/mmc/host/mmci.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 36db31e..4f8d0ba 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -759,7 +759,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) data-bytes_xfered = 0; clks = (unsigned long long)data-timeout_ns * host-cclk; - do_div(clks, 10UL); + do_div(clks, NSEC_PER_SEC); timeout = data-timeout_clks + (unsigned int)clks; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 10/12] mmc: mmci: Add clock support for Qualcomm.
On 04/21/14 14:49, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of support is very much similar to bypass mode but there is no such thing
called bypass mode in MCICLK register of Qcom SD card controller. By default
the clock is directly driven by the clk controller.
This patch adds clock support for Qualcomm SDCC in the driver. This bit of
code is conditioned on hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index f465eb5..2cd3a8f 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -291,7 +291,18 @@ static void mmci_set_clkreg(struct mmci_host *host,
unsigned int desired)
host-cclk = 0;
if (desired) {
- if (desired = host-mclk) {
+ if (desired != host-mclk
+ host-hw_designer == AMBA_VENDOR_QCOM) {
+ /* Qcom MCLKCLK register does not define bypass bits */
+ int rc = clk_set_rate(host-clk, desired);
Please turn on lockdep (PROVE_LOCKING) and sleeping while atomic checks
(DEBUG_ATOMIC_SLEEP). You cannot call clk_set_rate() in atomic context.
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