Re: [PATCH] pinctrl: msm: Add more MSM8X74 pin definitions
On Fri, May 2, 2014 at 6:44 AM, Andy Gross agr...@codeaurora.org wrote: This patch adds pin definitiones for the MSM8x74 TLMM. New definitions include: BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins. Signed-off-by: Andy Gross agr...@codeaurora.org This patch does not apply on top of the pin control devel branch, can you please rebase it on my tree, branch devel? https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/ Also keep Björn on CC so he can check/Ack this. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] mfd: pm8x41: add support for Qualcomm 8x41 PMICs
Hi,
On Thu, 2014-04-24 at 13:18 -0500, Josh Cartwright wrote:
On Wed, Apr 23, 2014 at 04:36:22PM -0700, Courtney Cavin wrote:
On Wed, Apr 23, 2014 at 11:46:26PM +0200, Josh Cartwright wrote:
On Tue, Apr 22, 2014 at 05:31:49PM -0700, Courtney Cavin wrote:
[..]
snip
$ git grep spmi-slave-container arch/arm/boot/dts
arch/arm/boot/dts/qcom/msm-pm8019.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8019.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8110.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8110.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8226.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8226.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8841.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8841.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8916.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8916.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8941.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8941.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pma8084.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pma8084.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmd9635.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmd9635.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmi8962.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmi8962.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmiplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmiplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmplutonium.dtsi:
spmi-slave-container;
[..]
+static const struct of_device_id pm8x41_id_table[] = {
+ { .compatible = qcom,pm8841, },
+ { .compatible = qcom,pm8941, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, pm8x41_id_table);
I'm thinking we should probably have a generic compatible entry as well,
qcom,pmic-qpnp or similar. We should still specify in the binding
that PMIC slaves specify a version-specific string as well as the
generic string. That is, a slave should have:
compatible = qcom,pm8841, qcom,pmic-qpnp;
...in case we would ever need to differentiate in the future.
(I recall that in a previous version I had done this, but I don't
remember why I had changed it..)
I gave this some thought but came to the conclusion that there is no
benefit of adding a generic compatible to a new binding. Please clarify
a use-case where this would be ... useful.
Having a generic compatible entry allows for easily supporting new PMICs
without having to add yet another vacuous entry in the ID table. In
this case I think it's perfectly acceptable given that this driver isn't
really defining a programming model for a specific device, but rather
acting much more like a bus.
Requiring a specific PMIC listed before a generic one allows us an
escape hatch in the future if for some reason we need to add a quirk for
a specific PMIC.
Is there a conclusion on this issue? I am voting for generic name :-)
qcom,pm-qpnp.
Further complication is that several sub function drivers expect to
runtime detect the exact version of the controller (qcom, qpnp-iadc,
qcom, qpnp-vadc, qcom, qpnp-linear-charger). This is realized by the
exported function of the driver qcom, qpnp-revid. Would it be good
idea to merge qpnp-revid and qcom,pm-qpnp driver?
Regards,
Ivan
Josh
[1]: git://codeaurora.org/quic/la/kernel/msm-3.10#msm-3.10
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Re: [PATCH] i2c: qup: Fix pm_runtime_get_sync usage
On Fri, May 2, 2014 at 6:54 PM, Andy Gross agr...@codeaurora.org wrote: [...] @@ -479,7 +479,7 @@ static int qup_i2c_xfer(struct i2c_adapter *adap, int ret, idx; ret = pm_runtime_get_sync(qup-dev); - if (ret) + if (ret 0) goto out; Sorry about that, thought I tested that path properly. Wolfram, please pick this up as soon as possible as it renders the driver useless if one enables pm runtime. Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com Regards, Bjorn -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pinctrl: msm: Add more MSM8X74 pin definitions
On Fri, May 09, 2014 at 10:37:00AM +0200, Linus Walleij wrote: On Fri, May 2, 2014 at 6:44 AM, Andy Gross agr...@codeaurora.org wrote: This patch adds pin definitiones for the MSM8x74 TLMM. New definitions include: BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins. Signed-off-by: Andy Gross agr...@codeaurora.org This patch does not apply on top of the pin control devel branch, can you please rebase it on my tree, branch devel? https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/ Sure thing. -- sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v2] pinctrl: msm: Add more MSM8X74 pin definitions
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,msm8974-pinctrl.txt | 22 +-
drivers/pinctrl/pinctrl-msm8x74.c | 675
2 files changed, 557 insertions(+), 140 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
index 9fb89e3..9c292ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -50,7 +50,27 @@ Valid values for pins are:
Supports bias and drive-strength
Valid values for function are:
- blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus
+ cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
+ blsp_uim1, blsp_uart1, blsp_uart1_flow, blsp_i2c1, blsp_spi1,
+ blsp_uim2, blsp_uart2, blsp_uart2_flow, blsp_i2c2, blsp_spi2,
+ blsp_uim3, blsp_uart3, blsp_uart3_flow, blsp_i2c3, blsp_spi3,
+ blsp_uim4, blsp_uart4, blsp_uart4_flow, blsp_i2c4, blsp_spi4,
+ blsp_uim5, blsp_uart5, blsp_uart5_flow, blsp_i2c5, blsp_spi5,
+ blsp_uim6, blsp_uart6, blsp_uart6_flow, blsp_i2c6, blsp_spi6,
+ blsp_uim7, blsp_uart7, blsp_uart7_flow, blsp_i2c7, blsp_spi7,
+ blsp_uim8, blsp_uart8, blsp_uart8_flow, blsp_i2c8, blsp_spi8,
+ blsp_uim9, blsp_uart9, blsp_uart9_flow, blsp_i2c9, blsp_spi9,
+ blsp_uim10, blsp_uart10, blsp_uart10_flow, blsp_i2c10, blsp_spi10,
+ blsp_uim11, blsp_uart11, blsp_uart11_flow, blsp_i2c11, blsp_spi11,
+ blsp_uim12, blsp_uart12, blsp_uart12_flow, blsp_i2c12, blsp_spi12,
+ blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
+ blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
+ sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
+ cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
+ cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
+ hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
+ gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
spkr_mi2s,
+ ter_mi2s, sec_mi2s, slimbus
(Note that this is not yet the complete list of functions)
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c
b/drivers/pinctrl/pinctrl-msm8x74.c
index 57766d5..67d1c2c 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -402,169 +402,566 @@ static const unsigned int sdc2_data_pins[] = { 151 };
* the pingroup table below.
*/
enum msm8x74_functions {
+ MSM_MUX_cci_i2c0,
+ MSM_MUX_cci_i2c1,
+ MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
+ MSM_MUX_blsp_i2c3,
+ MSM_MUX_blsp_i2c4,
+ MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_i2c6,
+ MSM_MUX_blsp_i2c7,
+ MSM_MUX_blsp_i2c8,
+ MSM_MUX_blsp_i2c9,
+ MSM_MUX_blsp_i2c10,
MSM_MUX_blsp_i2c11,
+ MSM_MUX_blsp_i2c12,
MSM_MUX_blsp_spi1,
+ MSM_MUX_blsp_spi1_cs1,
+ MSM_MUX_blsp_spi1_cs2,
+ MSM_MUX_blsp_spi1_cs3,
+ MSM_MUX_blsp_spi2,
+ MSM_MUX_blsp_spi2_cs1,
+ MSM_MUX_blsp_spi2_cs2,
+ MSM_MUX_blsp_spi2_cs3,
+ MSM_MUX_blsp_spi3,
+ MSM_MUX_blsp_spi4,
+ MSM_MUX_blsp_spi5,
+ MSM_MUX_blsp_spi6,
+ MSM_MUX_blsp_spi7,
MSM_MUX_blsp_spi8,
+ MSM_MUX_blsp_spi9,
+ MSM_MUX_blsp_spi10,
+ MSM_MUX_blsp_spi10_cs1,
+ MSM_MUX_blsp_spi10_cs2,
+ MSM_MUX_blsp_spi10_cs3,
+ MSM_MUX_blsp_spi11,
+ MSM_MUX_blsp_spi12,
+ MSM_MUX_blsp_uart1,
+ MSM_MUX_blsp_uart1_flow,
MSM_MUX_blsp_uart2,
+ MSM_MUX_blsp_uart2_flow,
+ MSM_MUX_blsp_uart3,
+ MSM_MUX_blsp_uart3_flow,
+ MSM_MUX_blsp_uart4,
+ MSM_MUX_blsp_uart4_flow,
+ MSM_MUX_blsp_uart5,
+ MSM_MUX_blsp_uart5_flow,
+ MSM_MUX_blsp_uart6,
+ MSM_MUX_blsp_uart6_flow,
+ MSM_MUX_blsp_uart7,
+ MSM_MUX_blsp_uart7_flow,
MSM_MUX_blsp_uart8,
+ MSM_MUX_blsp_uart8_flow,
+ MSM_MUX_blsp_uart9,
+ MSM_MUX_blsp_uart9_flow,
+ MSM_MUX_blsp_uart10,
+ MSM_MUX_blsp_uart10_flow,
+ MSM_MUX_blsp_uart11,
+ MSM_MUX_blsp_uart11_flow,
+ MSM_MUX_blsp_uart12,
+ MSM_MUX_blsp_uart12_flow,
+ MSM_MUX_blsp_uim1,
+ MSM_MUX_blsp_uim2,
+ MSM_MUX_blsp_uim3,
+ MSM_MUX_blsp_uim4,
+ MSM_MUX_blsp_uim5,
+ MSM_MUX_blsp_uim6,
+ MSM_MUX_blsp_uim7,
+ MSM_MUX_blsp_uim8,
+ MSM_MUX_blsp_uim9,
+ MSM_MUX_blsp_uim10,
+ MSM_MUX_blsp_uim11,
+ MSM_MUX_blsp_uim12,
+ MSM_MUX_uim1,
+ MSM_MUX_uim2,
+ MSM_MUX_uim_batt_alarm,
+ MSM_MUX_sdc3,
+ MSM_MUX_sdc4,
[PATCH] pinctrl: qcom: ipq8064: Fix naming convention
Drop underscore in spdif_groups to match all other groups.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/pinctrl/pinctrl-ipq8064.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c
b/drivers/pinctrl/pinctrl-ipq8064.c
index 54aba9f..acafea4 100644
--- a/drivers/pinctrl/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/pinctrl-ipq8064.c
@@ -366,7 +366,7 @@ static const char * const sdc1_groups[] = {
};
static const char * const spdif_groups[] = {
- gpio_10, gpio_48,
+ gpio10, gpio48,
};
static const char * const nand_groups[] = {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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Re: [PATCH v1 00/11] Add Qualcomm SD Card Controller support.
Thanks Bjorn for testing it on msm8960 SOC. On 09/05/14 10:56, Bjorn Andersson wrote: On Tue, Apr 29, 2014 at 1:18 AM, srinivas.kandaga...@linaro.org wrote: [...] This patch series adds Qualcomm SD Card Controller support in pl180 mmci driver. QCom SDCC is basically a pl180, but bit more customized, some of the register layouts and offsets are different to the ones mentioned in pl180 datasheet. The plan is to totally remove the standalone SDCC driver drivers/mmc/host/msm_sdcc.* and start using generic mmci driver for all Qualcomm parts, as we get chance to test on other Qcom boards. Hi Srinivas, I think your series looks good, so I pulled it into my tree and combined with some input from [1] I got this up and running on Sony Xperia T (msm8960 based). I do get below prints in dmesg during probe, mount and some initial accesses; but the code seems to retry the operations and things work out nicely. Great.. Could I add your Ack on these series? [ 193.556540] mmcblk0: response CRC error sending r/w cmd command, card status 0xb00 I could not reproduce this issue with APQ8064 based IFC6410 board. I will keep testing on other boards as on when they are available. Am hoping that we could get this support for v3.16 PS. please send the patch enabling AMBA to Kumar as well. Sure I will send this patch to Kumar. [1] https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/commitdiff/14ea2f1dc5bb719dbfb943e2c700ac166a8c125a Regards, Bjorn thanks, srini -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] clk: qcom: add clocks necessary for apq8064 sdcc
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91..9bd3238 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2876,6 +2876,16 @@ static struct clk_regmap *gcc_apq8064_clks[] = {
[GSBI7_QUP_SRC] = gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = gsbi7_qup_clk.clkr,
[GSBI7_H_CLK] = gsbi7_h_clk.clkr,
+ [SDC1_SRC] = sdc1_src.clkr,
+ [SDC1_CLK] = sdc1_clk.clkr,
+ [SDC2_SRC] = sdc2_src.clkr,
+ [SDC2_CLK] = sdc2_clk.clkr,
+ [SDC3_SRC] = sdc3_src.clkr,
+ [SDC3_CLK] = sdc3_clk.clkr,
+ [SDC4_SRC] = sdc4_src.clkr,
+ [SDC4_CLK] = sdc4_clk.clkr,
+ [SDC5_SRC] = sdc5_src.clkr,
+ [SDC5_CLK] = sdc5_clk.clkr,
};
static const struct regmap_config gcc_msm8960_regmap_config = {
--
1.9.1
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[PATCH] ARM: DT: apq8064: Add sdcc support via mcci driver.
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to SD card controller using generic pl180 mmci driver.
This patch also adds temporary fixed regulator to get it going till the actual
regulator is mainlined.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 ++
arch/arm/boot/dts/qcom-apq8064.dtsi| 50 ++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index c5fda40..ea386bd 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -4,9 +4,25 @@
model = Qualcomm APQ8064/IFC6410;
compatible = qcom,apq8064-ifc6410, qcom,apq8064;
+ aliases {
+ sdcc1 = sdcc1;
+ sdcc3 = sdcc3;
+ };
+
soc {
serial@1664 {
status = ok;
};
+ amba {
+ /* eMMC */
+ sdcc1: sdcc@1240 {
+ status = okay;
+ };
+
+ /* External micro SD card */
+ sdcc3: sdcc@1218 {
+ status = okay;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 60b89e5..640fb1d 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,6 +2,7 @@
/include/ skeleton.dtsi
+#include dt-bindings/interrupt-controller/arm-gic.h
#include dt-bindings/clock/qcom,gcc-msm8960.h
/ {
@@ -147,5 +148,54 @@
#clock-cells = 1;
#reset-cells = 1;
};
+
+ /* Temporary fixed regulator */
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = regulator-fixed;
+ regulator-name = SDCC Power;
+ regulator-min-microvolt = 270;
+ regulator-max-microvolt = 270;
+ regulator-always-on;
+ };
+
+ amba {
+ compatible = arm,amba-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ sdcc1: sdcc@1240 {
+ status = disabled;
+ compatible = arm,pl18x, arm,primecell;
+ arm,primecell-periphid = 0x00051180;
+ reg = 0x1240 0x8000;
+ interrupts = GIC_SPI 104
IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = cmd_irq;
+ clocks = gcc SDC1_CLK, gcc
SDC1_H_CLK;
+ clock-names = mclk, apb_pclk;
+ bus-width = 8;
+ max-frequency = 9600;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = vsdcc_fixed;
+ };
+
+ sdcc3: sdcc@1218 {
+ compatible = arm,pl18x, arm,primecell;
+ arm,primecell-periphid = 0x00051180;
+ status = disabled;
+ reg = 0x1218 0x8000;
+ interrupts = GIC_SPI 102
IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = cmd_irq;
+ clocks = gcc SDC3_CLK, gcc
SDC3_H_CLK;
+ clock-names = mclk, apb_pclk;
+ bus-width = 4;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = 19200;
+ no-1-8-v;
+ vmmc-supply = vsdcc_fixed;
+ };
+ };
};
};
--
1.9.1
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Re: [PATCH] pinctrl: qcom: ipq8064: Fix naming convention
On Fri, May 09, 2014 at 01:08:25PM -0500, Kumar Gala wrote: Drop underscore in spdif_groups to match all other groups. Signed-off-by: Kumar Gala ga...@codeaurora.org Reviewed-by: Andy Gross agr...@codeaurora.org snip -- sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: qcom: add clocks necessary for apq8064 sdcc
On May 9, 2014, at 11:48 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91..9bd3238 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2876,6 +2876,16 @@ static struct clk_regmap *gcc_apq8064_clks[] = {
[GSBI7_QUP_SRC] = gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = gsbi7_qup_clk.clkr,
[GSBI7_H_CLK] = gsbi7_h_clk.clkr,
+ [SDC1_SRC] = sdc1_src.clkr,
+ [SDC1_CLK] = sdc1_clk.clkr,
+ [SDC2_SRC] = sdc2_src.clkr,
+ [SDC2_CLK] = sdc2_clk.clkr,
+ [SDC3_SRC] = sdc3_src.clkr,
+ [SDC3_CLK] = sdc3_clk.clkr,
+ [SDC4_SRC] = sdc4_src.clkr,
+ [SDC4_CLK] = sdc4_clk.clkr,
+ [SDC5_SRC] = sdc5_src.clkr,
+ [SDC5_CLK] = sdc5_clk.clkr,
};
There are only 4 SDCs on APQ8064
- k
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Re: [PATCH] clk: qcom: add clocks necessary for apq8064 sdcc
On 09/05/14 12:21, Kumar Gala wrote: There are only 4 SDCs on APQ8064 You are right.. Will fix it in next version. thanks, srini -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] clk: qcom: add clocks necessary for apq8064 sdcc
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91..c47a758 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2876,6 +2876,14 @@ static struct clk_regmap *gcc_apq8064_clks[] = {
[GSBI7_QUP_SRC] = gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = gsbi7_qup_clk.clkr,
[GSBI7_H_CLK] = gsbi7_h_clk.clkr,
+ [SDC1_SRC] = sdc1_src.clkr,
+ [SDC1_CLK] = sdc1_clk.clkr,
+ [SDC2_SRC] = sdc2_src.clkr,
+ [SDC2_CLK] = sdc2_clk.clkr,
+ [SDC3_SRC] = sdc3_src.clkr,
+ [SDC3_CLK] = sdc3_clk.clkr,
+ [SDC4_SRC] = sdc4_src.clkr,
+ [SDC4_CLK] = sdc4_clk.clkr,
};
static const struct regmap_config gcc_msm8960_regmap_config = {
--
1.9.1
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Re: [PATCH 1/2] mfd: pm8x41: add support for Qualcomm 8x41 PMICs
On Fri, May 09, 2014 at 02:45:30PM +0200, Ivan T. Ivanov wrote: [...] I'm thinking we should probably have a generic compatible entry as well, qcom,pmic-qpnp or similar. We should still specify in the binding that PMIC slaves specify a version-specific string as well as the generic string. That is, a slave should have: compatible = qcom,pm8841, qcom,pmic-qpnp; ...in case we would ever need to differentiate in the future. (I recall that in a previous version I had done this, but I don't remember why I had changed it..) I gave this some thought but came to the conclusion that there is no benefit of adding a generic compatible to a new binding. Please clarify a use-case where this would be ... useful. Having a generic compatible entry allows for easily supporting new PMICs without having to add yet another vacuous entry in the ID table. In this case I think it's perfectly acceptable given that this driver isn't really defining a programming model for a specific device, but rather acting much more like a bus. Requiring a specific PMIC listed before a generic one allows us an escape hatch in the future if for some reason we need to add a quirk for a specific PMIC. Is there a conclusion on this issue? I am voting for generic name :-) qcom,pm-qpnp. Josh and I have discussed this offline, and I think we have come to the conclusion that this should be a generic driver with only a generic binding. The current proposed name is spmi-ext, as there is specific functional relation to Qualcomm, PMICs or QPNP. Further, the binding documentation should be specific to pm8[89]41 as 'mfd/pm8x41.txt', and should contain the compatibles: - qcom,pm8941, spmi-ext - qcom,pm8841, spmi-ext This naming has been discussed to death, so a few more shed color suggestions can't possibly hurt. Further complication is that several sub function drivers expect to runtime detect the exact version of the controller (qcom, qpnp-iadc, qcom, qpnp-vadc, qcom, qpnp-linear-charger). This is realized by the exported function of the driver qcom, qpnp-revid. Would it be good idea to merge qpnp-revid and qcom,pm-qpnp driver? Each block within the PMICs have--undocumented--version registers, so a global version number is not particularly useful. A good example of this is the ADC code [1], as you mentioned. -Courtney [1] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/thermal/qpnp-adc-tm.c#n469 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Patch v2] pinctrl: msm: Add more MSM8X74 pin definitions
On Fri 09 May 10:52 PDT 2014, Andy Gross wrote:
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other
assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
Awesome stuff, only have some minor comments.
+ MSM_MUX_blsp_uart1,
+ MSM_MUX_blsp_uart1_flow,
[...]
+static const char * const blsp_uim1_groups[] = { gpio0, gpio1 };
+static const char * const blsp_uart1_flow_groups[] = { gpio2, gpio3 };
You don't need to separate uart and flow control into two different functions
here. If you have gpio0-gpio3 in a group named uart1 both of the following
snippets are valid:
uart1 {
pins = gpio0, gpio1;
function = uart1;
};
uart1 {
pins = gpio0, gpio1, gpio2, gpio3;
function = uart1;
};
This is how I had to handle gsbis in family a, where a gsbi is pairs of pins
with different configurations.
[...]
+static const char * const hdmi_cec_groups[] = { gpio31 };
+static const char * const hdmi_ddc_groups[] = { gpio32, gpio33 };
+static const char * const hdmi_hpd_groups[] = { gpio34 };
As with the uart vs uart_flow you could group these as hdmi, but maybe not as
useful.
[...]
+ PINGROUP(35, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(37, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(38, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(39, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(40, NA, sdc3, NA, NA, NA, NA, NA),
+ PINGROUP(41, NA, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
+ PINGROUP(42, NA, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
+ PINGROUP(43, NA, blsp_spi7, blsp_uart7_flow, blsp_i2c7, NA, NA, NA),
+ PINGROUP(44, NA, blsp_spi7, blsp_uart7_flow, blsp_i2c7, NA, NA, NA),
I was expecting wcnss, bt and fm as function 1 for pins 35-44. Adding those and
I think we have everything we use in our devices.
[...]
+ PINGROUP(72, NA, spkr_mi2s, NA, NA, NA, NA, NA),
spkr_mi2s is function 1 for pin 72.
Regards,
Bjorn
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Re: [PATCH v2] clk: qcom: add clocks necessary for apq8064 sdcc
On May 9, 2014, at 12:34 PM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91..c47a758 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2876,6 +2876,14 @@ static struct clk_regmap *gcc_apq8064_clks[] = {
[GSBI7_QUP_SRC] = gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = gsbi7_qup_clk.clkr,
[GSBI7_H_CLK] = gsbi7_h_clk.clkr,
+ [SDC1_SRC] = sdc1_src.clkr,
+ [SDC1_CLK] = sdc1_clk.clkr,
+ [SDC2_SRC] = sdc2_src.clkr,
+ [SDC2_CLK] = sdc2_clk.clkr,
+ [SDC3_SRC] = sdc3_src.clkr,
+ [SDC3_CLK] = sdc3_clk.clkr,
+ [SDC4_SRC] = sdc4_src.clkr,
+ [SDC4_CLK] = sdc4_clk.clkr,
};
Reviewed-by: Kumar Gala ga...@codeaurora.org
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
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