Re: [PATCH v3 4/4] pinctrl: qcom: Add support for reset for apq8064
On Fri, Aug 29, 2014 at 4:30 PM, Pramod Gurav pramod.gu...@smartplayin.com wrote: This patch adds support for reset functions to reboot the boards with soc apq8064. CC: Linus Walleij linus.wall...@linaro.org CC: Bjorn Andersson bjorn.anders...@sonymobile.com CC: Ivan T. Ivanov iiva...@mm-sol.com CC: Stephen Boyd sb...@codeaurora.org CC: Andy Gross agr...@codeaurora.org Signed-off-by: Pramod Gurav pramod.gu...@smartplayin.com OK patch applied with Björn's ACK. A bit dirty to have this in this driver, but who cares. Does the APQ8064 accompanying PMIC also have the ability to completely shut the system down? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/4] pinctrl: qcom: Add APQ8084 pinctrl support
This set of patches adds pinctrl support for the Qualcomm APQ8084 platform. The first patch adds the pin definitions. The second patch contains the devicetree binding documentation. The third patch adds the DT node. The last patch makes the INTR_TARGET_PROC_APPS value configurable and defines it for each existing SoC. Tested on IFC6540 board. Changes since v2: - Fixed some incorrect bits and offsets. (suggested by Bjorn Andersson) - Updated binding documentation to follow the format of msm8960. (suggested by Bjorn Andersson) - Added fourth patch, which removes the hardcoded INTR_TARGET_PROC_APPS value and makes it configurable. Also we keep the current value for existing SoCs. (suggested by Bjorn Andersson) Changes since v1: - Updated the total number of pins (suggested by Bjorn Andersson) - Added the missing pin info (provided by Andy Gross) - Updated groups and functions to be consistent with other pinctrls. (suggested by Andy Gross) - Removed unused functions, qdss and test pins. (suggested by Andy Gross) - Updated the documentation with the possible functions. Georgi Djakov (4): pinctrl: qcom: Add APQ8084 pinctrl support dt: Document Qualcomm APQ8084 pinctrl binding ARM: dts: qcom: Add TLMM DT node for APQ8084 pinctrl: qcom: Make the target processor value configurable .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 +++ arch/arm/boot/dts/qcom-apq8084.dtsi| 10 + drivers/pinctrl/qcom/Kconfig |8 + drivers/pinctrl/qcom/Makefile |1 + drivers/pinctrl/qcom/pinctrl-apq8064.c |2 + drivers/pinctrl/qcom/pinctrl-apq8084.c | 1245 drivers/pinctrl/qcom/pinctrl-ipq8064.c |2 + drivers/pinctrl/qcom/pinctrl-msm.c |4 +- drivers/pinctrl/qcom/pinctrl-msm.h |3 + drivers/pinctrl/qcom/pinctrl-msm8960.c |2 + drivers/pinctrl/qcom/pinctrl-msm8x74.c |2 + 11 files changed, 1455 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8084.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/4] pinctrl: qcom: Add APQ8084 pinctrl support
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
drivers/pinctrl/qcom/Kconfig |8 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-apq8084.c | 1243
3 files changed, 1252 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8084.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d160a71..81275af 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -15,6 +15,14 @@ config PINCTRL_APQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
+config PINCTRL_APQ8084
+ tristate Qualcomm APQ8084 pin controller driver
+ depends on GPIOLIB OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
+
config PINCTRL_IPQ8064
tristate Qualcomm IPQ8064 pin controller driver
depends on GPIOLIB OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 2a02602..ba8519f 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -1,6 +1,7 @@
# Qualcomm pin control drivers
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
+obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c
b/drivers/pinctrl/qcom/pinctrl-apq8084.c
new file mode 100644
index 000..5362959
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -0,0 +1,1243 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-msm.h
+
+static const struct pinctrl_pin_desc apq8084_pins[] = {
+ PINCTRL_PIN(0, GPIO_0),
+ PINCTRL_PIN(1, GPIO_1),
+ PINCTRL_PIN(2, GPIO_2),
+ PINCTRL_PIN(3, GPIO_3),
+ PINCTRL_PIN(4, GPIO_4),
+ PINCTRL_PIN(5, GPIO_5),
+ PINCTRL_PIN(6, GPIO_6),
+ PINCTRL_PIN(7, GPIO_7),
+ PINCTRL_PIN(8, GPIO_8),
+ PINCTRL_PIN(9, GPIO_9),
+ PINCTRL_PIN(10, GPIO_10),
+ PINCTRL_PIN(11, GPIO_11),
+ PINCTRL_PIN(12, GPIO_12),
+ PINCTRL_PIN(13, GPIO_13),
+ PINCTRL_PIN(14, GPIO_14),
+ PINCTRL_PIN(15, GPIO_15),
+ PINCTRL_PIN(16, GPIO_16),
+ PINCTRL_PIN(17, GPIO_17),
+ PINCTRL_PIN(18, GPIO_18),
+ PINCTRL_PIN(19, GPIO_19),
+ PINCTRL_PIN(20, GPIO_20),
+ PINCTRL_PIN(21, GPIO_21),
+ PINCTRL_PIN(22, GPIO_22),
+ PINCTRL_PIN(23, GPIO_23),
+ PINCTRL_PIN(24, GPIO_24),
+ PINCTRL_PIN(25, GPIO_25),
+ PINCTRL_PIN(26, GPIO_26),
+ PINCTRL_PIN(27, GPIO_27),
+ PINCTRL_PIN(28, GPIO_28),
+ PINCTRL_PIN(29, GPIO_29),
+ PINCTRL_PIN(30, GPIO_30),
+ PINCTRL_PIN(31, GPIO_31),
+ PINCTRL_PIN(32, GPIO_32),
+ PINCTRL_PIN(33, GPIO_33),
+ PINCTRL_PIN(34, GPIO_34),
+ PINCTRL_PIN(35, GPIO_35),
+ PINCTRL_PIN(36, GPIO_36),
+ PINCTRL_PIN(37, GPIO_37),
+ PINCTRL_PIN(38, GPIO_38),
+ PINCTRL_PIN(39, GPIO_39),
+ PINCTRL_PIN(40, GPIO_40),
+ PINCTRL_PIN(41, GPIO_41),
+ PINCTRL_PIN(42, GPIO_42),
+ PINCTRL_PIN(43, GPIO_43),
+ PINCTRL_PIN(44, GPIO_44),
+ PINCTRL_PIN(45, GPIO_45),
+ PINCTRL_PIN(46, GPIO_46),
+ PINCTRL_PIN(47, GPIO_47),
+ PINCTRL_PIN(48, GPIO_48),
+ PINCTRL_PIN(49, GPIO_49),
+ PINCTRL_PIN(50, GPIO_50),
+ PINCTRL_PIN(51, GPIO_51),
+ PINCTRL_PIN(52, GPIO_52),
+ PINCTRL_PIN(53, GPIO_53),
+ PINCTRL_PIN(54, GPIO_54),
+ PINCTRL_PIN(55, GPIO_55),
+ PINCTRL_PIN(56, GPIO_56),
+ PINCTRL_PIN(57, GPIO_57),
+ PINCTRL_PIN(58, GPIO_58),
+ PINCTRL_PIN(59, GPIO_59),
+ PINCTRL_PIN(60, GPIO_60),
+ PINCTRL_PIN(61, GPIO_61),
+ PINCTRL_PIN(62, GPIO_62),
+ PINCTRL_PIN(63, GPIO_63),
+ PINCTRL_PIN(64, GPIO_64),
+ PINCTRL_PIN(65, GPIO_65),
+ PINCTRL_PIN(66, GPIO_66),
+ PINCTRL_PIN(67,
[PATCH v3 4/4] pinctrl: qcom: Make the target processor value configurable
Currently the value used for specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to use the current value, and only for APQ8084 we use the new value.
Suggested-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
drivers/pinctrl/qcom/pinctrl-apq8064.c |2 ++
drivers/pinctrl/qcom/pinctrl-apq8084.c |2 ++
drivers/pinctrl/qcom/pinctrl-ipq8064.c |2 ++
drivers/pinctrl/qcom/pinctrl-msm.c |4 +---
drivers/pinctrl/qcom/pinctrl-msm.h |3 +++
drivers/pinctrl/qcom/pinctrl-msm8960.c |2 ++
drivers/pinctrl/qcom/pinctrl-msm8x74.c |2 ++
7 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c
b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index feb6f15..f877aed 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c
b/drivers/pinctrl/qcom/pinctrl-apq8084.c
index 5362959..138cbf6 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -371,6 +371,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.intr_status_bit = 0, \
.intr_ack_high = 0, \
.intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -396,6 +397,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index 767cf11..81f49a9 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 2738108..592c6fc 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -649,8 +649,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
spin_unlock_irqrestore(pctrl-lock, flags);
}
-#define INTR_TARGET_PROC_APPS4
-
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -674,7 +672,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d,
unsigned int type)
[PATCH v2 0/3] ARM: dts: qcom: Add initial IFC6540 board support
Add basic support for the IFC6540 single-board computer boards, that are based on the APQ8084 SoC. The first patch adds the initial device tree. The second enables the serial console. The third adds the SDHC nodes and enables the eMMC. Should go through the qcom/arm-soc tree. Changes since v1: - This time add linux-arm-msm list to the CC. - Include a third patch for enabling the eMMC. Georgi Djakov (3): ARM: dts: qcom: Add initial IFC6540 board device tree ARM: dts: qcom: Enable serial port on IFC6540 boards ARM: dts: qcom: Add SDHC nodes for APQ8084 platform arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 23 +++ arch/arm/boot/dts/qcom-apq8084.dtsi| 23 +++ 3 files changed, 47 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/3] ARM: dts: qcom: Add SDHC nodes for APQ8084 platform
Enable support for the two SD host controllers on the APQ8084 platform
by adding the required nodes to the DT files.
On the IFC6540 board, the first controller is connected to the onboard
eMMC and the second is connected to a micro-SD card slot.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 11 +++
arch/arm/boot/dts/qcom-apq8084.dtsi| 23 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index e41cb8a..c9ff108 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -8,5 +8,16 @@
serial@f995e000 {
status = okay;
};
+
+ sdhci@f9824900 {
+ bus-width = 8;
+ non-removable;
+ status = okay;
+ };
+
+ sdhci@f98a4900 {
+ cd-gpios = tlmm 122 GPIO_ACTIVE_LOW;
+ bus-width = 4;
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 21d01e5..1f130bc 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -3,6 +3,7 @@
#include skeleton.dtsi
#include dt-bindings/clock/qcom,gcc-apq8084.h
+#include dt-bindings/gpio/gpio.h
/ {
model = Qualcomm APQ 8084;
@@ -203,5 +204,27 @@
clock-names = core, iface;
status = disabled;
};
+
+ sdhci@f9824900 {
+ compatible = qcom,sdhci-msm-v4;
+ reg = 0xf9824900 0x11c, 0xf9824000 0x800;
+ reg-names = hc_mem, core_mem;
+ interrupts = 0 123 0, 0 138 0;
+ interrupt-names = hc_irq, pwr_irq;
+ clocks = gcc GCC_SDCC1_APPS_CLK, gcc
GCC_SDCC1_AHB_CLK;
+ clock-names = core, iface;
+ status = disabled;
+ };
+
+ sdhci@f98a4900 {
+ compatible = qcom,sdhci-msm-v4;
+ reg = 0xf98a4900 0x11c, 0xf98a4000 0x800;
+ reg-names = hc_mem, core_mem;
+ interrupts = 0 125 0, 0 221 0;
+ interrupt-names = hc_irq, pwr_irq;
+ clocks = gcc GCC_SDCC2_APPS_CLK, gcc
GCC_SDCC2_AHB_CLK;
+ clock-names = core, iface;
+ status = disabled;
+ };
};
};
--
1.7.9.5
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[PATCH v2 2/3] ARM: dts: qcom: Enable serial port on IFC6540 boards
Enable the serial port on the IFC6540 boards.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index 4603e91..e41cb8a 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm APQ8084/IFC6540;
compatible = qcom,apq8084-ifc6540, qcom,apq8084;
+
+ soc {
+ serial@f995e000 {
+ status = okay;
+ };
+ };
};
--
1.7.9.5
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[PATCH v2 1/3] ARM: dts: qcom: Add initial IFC6540 board device tree
Add initial device tree for the IFC6540 Snapdragon 805 pico-itx
single-board computer.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts |6 ++
2 files changed, 7 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b022972..df8453a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -345,6 +345,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-ifc6410.dtb \
qcom-apq8074-dragonboard.dtb \
+ qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
new file mode 100644
index 000..4603e91
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -0,0 +1,6 @@
+#include qcom-apq8084.dtsi
+
+/ {
+ model = Qualcomm APQ8084/IFC6540;
+ compatible = qcom,apq8084-ifc6540, qcom,apq8084;
+};
--
1.7.9.5
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[PATCH] RFC: add function for localbus address
Hi Grant,
I came down to this. Could you review? Is that
implementation closer to the suggestion made by you.
---
drivers/of/address.c | 49
drivers/of/platform.c | 20 ++---
include/linux/of_address.h | 19 +
3 files changed, 84 insertions(+), 4 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index e371825..86c2166 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -601,6 +601,32 @@ const __be32 *of_get_address(struct device_node *dev, int
index, u64 *size,
}
EXPORT_SYMBOL(of_get_address);
+const __be32 *of_get_localbus_address(struct device_node *np, int index,
+ u64 *size)
+{
+ struct device_node *root, *parent;
+ const __be32 *ranges, *prop = NULL;
+
+ parent = of_get_parent(np);
+ if (!parent)
+ return NULL;
+
+ root = of_find_node_by_path(/);
+
+ if (parent == root) {
+ of_node_put(parent);
+ return NULL;
+ }
+
+ ranges = of_get_property(parent, ranges, NULL);
+ of_node_put(parent);
+
+ if (!ranges)
+ prop = of_get_address(np, index, size, NULL);
+
+ return prop;
+}
+
unsigned long __weak pci_address_to_pio(phys_addr_t address)
{
if (address IO_SPACE_LIMIT)
@@ -665,6 +691,29 @@ int of_address_to_resource(struct device_node *dev, int
index,
}
EXPORT_SYMBOL_GPL(of_address_to_resource);
+int of_localbus_address_to_resource(struct device_node *dev, int index,
+ struct resource *r)
+{
+ const char *name = NULL;
+ const __be32 *addrp;
+ u64 size;
+
+ addrp = of_get_localbus_address(dev, index, size);
+ if (!addrp)
+ return -EINVAL;
+
+ of_property_read_string_index(dev, reg-names, index, name);
+
+ memset(r, 0, sizeof(*r));
+ r-start = be32_to_cpup(addrp);
+ r-end = r-start + size - 1;
+ r-flags = IORESOURCE_REG;
+ r-name = name ? name : dev-full_name;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(of_localbus_address_to_resource);
+
struct device_node *of_find_matching_node_by_address(struct device_node *from,
const struct of_device_id *matches,
u64 base_address)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 0197725..36dcbd7 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -106,8 +106,9 @@ struct platform_device *of_device_alloc(struct device_node
*np,
struct device *parent)
{
struct platform_device *dev;
- int rc, i, num_reg = 0, num_irq;
+ int rc, i, num_reg = 0, num_localbus_reg = 0, num_irq;
struct resource *res, temp_res;
+ int num_resources;
dev = platform_device_alloc(, -1);
if (!dev)
@@ -116,22 +117,33 @@ struct platform_device *of_device_alloc(struct
device_node *np,
/* count the io and irq resources */
while (of_address_to_resource(np, num_reg, temp_res) == 0)
num_reg++;
+
+ while (of_localbus_address_to_resource(np,
+ num_localbus_reg, temp_res) == 0)
+ num_localbus_reg++;
+
num_irq = of_irq_count(np);
+ num_resources = num_reg + num_localbus_reg + num_irq;
+
/* Populate the resource table */
- if (num_irq || num_reg) {
- res = kzalloc(sizeof(*res) * (num_irq + num_reg), GFP_KERNEL);
+ if (num_resources) {
+ res = kzalloc(sizeof(*res) * num_resources, GFP_KERNEL);
if (!res) {
platform_device_put(dev);
return NULL;
}
- dev-num_resources = num_reg + num_irq;
+ dev-num_resources = num_resources;
dev-resource = res;
for (i = 0; i num_reg; i++, res++) {
rc = of_address_to_resource(np, i, res);
WARN_ON(rc);
}
+ for (i = 0; i num_localbus_reg; i++, res++) {
+ rc = of_localbus_address_to_resource(np, i, res);
+ WARN_ON(rc);
+ }
if (of_irq_to_resource_table(np, res, num_irq) != num_irq)
pr_debug(not all legacy IRQ resources mapped for %s\n,
np-name);
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index fb7b722..10112ea 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -42,6 +42,8 @@ extern u64 of_translate_dma_address(struct device_node *dev,
extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
extern int of_address_to_resource(struct device_node *dev, int index,
struct resource *r);
Re: [PATCH v2 0/3] ARM: dts: qcom: Add initial IFC6540 board support
On Sep 2, 2014, at 10:40 AM, Georgi Djakov gdja...@mm-sol.com wrote: Add basic support for the IFC6540 single-board computer boards, that are based on the APQ8084 SoC. The first patch adds the initial device tree. The second enables the serial console. The third adds the SDHC nodes and enables the eMMC. Should go through the qcom/arm-soc tree. Changes since v1: - This time add linux-arm-msm list to the CC. - Include a third patch for enabling the eMMC. Georgi Djakov (3): ARM: dts: qcom: Add initial IFC6540 board device tree ARM: dts: qcom: Enable serial port on IFC6540 boards ARM: dts: qcom: Add SDHC nodes for APQ8084 platform arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 23 +++ arch/arm/boot/dts/qcom-apq8084.dtsi| 23 +++ 3 files changed, 47 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts -- 1.7.9.5 Thanks, there is really no reason for these to be 3 patches, can you squash them down into one. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/4] pinctrl: qcom: Add APQ8084 pinctrl support
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote: This patchset adds pinctrl support for the Qualcomm APQ8084 platform. Reviewed-by: Andy Gross agr...@codeaurora.org Signed-off-by: Georgi Djakov gdja...@mm-sol.com I was expecting patch 4 to come before this, so that this commit would be complete. But I'm fine with this. Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/4] dt: Document Qualcomm APQ8084 pinctrl binding
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote: Define a new binding for the Qualcomm TLMM (Top-Level Mode Mux) based pin controller inside the APQ8084. Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com Don't remember giving you this... But, with the s/sdc3/sdc2 below I think it looks good; so with that change you have my Acked-by Regards, Bjorn Signed-off-by: Georgi Djakov gdja...@mm-sol.com --- .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 179 1 file changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt new file mode 100644 index 000..9d95700 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt @@ -0,0 +1,179 @@ +Qualcomm APQ8084 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8960 platform. + +- compatible: + Usage: required + Value type: string + Definition: must be qcom,apq8084-pinctrl + +- reg: + Usage: required + Value type: prop-encoded-array + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: prop-encoded-array + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: none + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/interrupt-controller/irq.h + +- gpio-controller: + Usage: required + Value type: none + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: u32 + Definition: must be 2. Specifying the pin number and flags, as defined + in dt-bindings/gpio/gpio.h + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase pin configuration node. + +The pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: string-array + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio146, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc3_clk, + sdc3_cmd, + sdc3_data These are supposed to be sdc2. + +- function: + Usage: required + Value type: string + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, + blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, + blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, +
Re: [PATCH v3 4/4] pinctrl: qcom: Make the target processor value configurable
On Tue 02 Sep 06:13 PDT 2014, Georgi Djakov wrote:
Currently the value used for specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to use the current value, and only for APQ8084 we use the new value.
Suggested-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Looks good.
Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
drivers/pinctrl/qcom/pinctrl-apq8064.c |2 ++
drivers/pinctrl/qcom/pinctrl-apq8084.c |2 ++
drivers/pinctrl/qcom/pinctrl-ipq8064.c |2 ++
drivers/pinctrl/qcom/pinctrl-msm.c |4 +---
drivers/pinctrl/qcom/pinctrl-msm.h |3 +++
drivers/pinctrl/qcom/pinctrl-msm8960.c |2 ++
drivers/pinctrl/qcom/pinctrl-msm8x74.c |2 ++
7 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c
b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index feb6f15..f877aed 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c
b/drivers/pinctrl/qcom/pinctrl-apq8084.c
index 5362959..138cbf6 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -371,6 +371,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.intr_status_bit = 0, \
.intr_ack_high = 0, \
.intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -396,6 +397,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index 767cf11..81f49a9 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2,\
@@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1,\
.intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 2738108..592c6fc 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -649,8 +649,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
spin_unlock_irqrestore(pctrl-lock, flags);
}
-#define INTR_TARGET_PROC_APPS4
-
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc =
Re: [PATCH v3 4/4] pinctrl: qcom: Add support for reset for apq8064
On Tue 02 Sep 05:36 PDT 2014, Linus Walleij wrote: A bit dirty to have this in this driver, but who cares. Indeed, but we figured the taint was small enough to justify not creating cross-references to a separate driver. Does the APQ8064 accompanying PMIC also have the ability to completely shut the system down? Upon flipping pshold the PMIC will perform either a reset or a shutdown of the system. Per Stephen's suggestion we can hook the control of this up with a reboot_notifier in a pmic driver, hence saving ourselves of a reference to (or from) the PMIC here. Regards, Bjorn -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] hwspinlock/msm: Add support for Qualcomm MSM HW Mutex block
On 8/29/2014 5:14 PM, Bjorn Andersson wrote:
From: Kumar Gala ga...@codeaurora.org
Add driver for Qualcomm MSM Hardware Mutex block that exists on
newer Qualcomm SoCs.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Eric Holmberg eholm...@codeaurora.org
Cc: Courtney Cavin courtney.ca...@sonymobile.com
Signed-off-by: Kumar Gala ga...@codeaurora.org
[bjorn: added pm_runtime calls, from Courtney,
added sfpb-mutex compatible,
updated DT binding documentation formatting]
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
[...]
diff --git a/drivers/hwspinlock/msm_hwspinlock.c
b/drivers/hwspinlock/msm_hwspinlock.c
new file mode 100644
index 000..9ddd020
--- /dev/null
+++ b/drivers/hwspinlock/msm_hwspinlock.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
Should the copyright range be updated to include your changes which I
presume were authored in 2014?
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/err.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/device.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/hwspinlock.h
+#include linux/io.h
Could these be put in alphabetical order? I vaguely recall a few
maintainers expressing this preference to avoid merge issues.
+
+#include hwspinlock_internal.h
+
+#define SPINLOCK_ID_APPS_PROC 1
+#define BASE_ID0
[...]
+static int msm_hwspinlock_probe(struct platform_device *pdev)
+{
+ int ret, i, stride;
+ size_t array_size;
+ u32 num_locks;
+ struct hwspinlock_device *bank;
+ struct hwspinlock *hwlock;
+ struct resource *res;
+ void __iomem *iobase;
+ struct device_node *node = pdev-dev.of_node;
+ const struct of_device_id *match;
+
+ match = of_match_device(msm_hwspinlock_of_match, pdev-dev);
+ if (!match)
+ return -EINVAL;
This seems redundant. It is my understanding that probe will only be
called for a matching device. What are we attempting to accomplish here?
+
+ ret = of_property_read_u32(node, qcom,num-locks, num_locks);
+ if (ret || num_locks == 0)
+ return -ENODEV;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, mutex-base);
+ iobase = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(iobase))
+ return PTR_ERR(iobase);
+
+ array_size = num_locks * sizeof(*hwlock);
+ bank = devm_kzalloc(pdev-dev, sizeof(*bank) + array_size, GFP_KERNEL);
+ if (!bank)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, bank);
+
+ stride = (int)match-data;
+ for (i = 0, hwlock = bank-lock[0]; i num_locks; i++, hwlock++)
+ hwlock-priv = iobase + i * stride;
I am not a fan of this method for determining the stride. We already
have 0x4 and 0x80 in this driver, and will soon need 0x1000 for some of
the current chips (still listed as TCSR too). The stride is completely
up to our hardware designers, and it seems like encoding stride in this
manner will require constant updates and maintenance. I prefer
calculating stride by dividing the reg size by num_locks since that will
automatically adjust for whatever the hardware designers decide to use
next month. If you wanted to, with the reg size calculation, you could
remove the qcom,sfpb-mutex since there is no functional difference
other than stride. What are your thoughts?
+
+ pm_runtime_enable(pdev-dev);
+
+ ret = hwspin_lock_register(bank, pdev-dev, msm_hwspinlock_ops,
+ BASE_ID, num_locks);
+ if (ret)
+ pm_runtime_disable(pdev-dev);
+
+ return ret;
+}
[...]
Jeffrey Hugo
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation.
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Re: [PATCH v2] hwspinlock/msm: Add support for Qualcomm MSM HW Mutex block
On Tue 02 Sep 10:28 PDT 2014, Jeffrey Hugo wrote:
diff --git a/drivers/hwspinlock/msm_hwspinlock.c
b/drivers/hwspinlock/msm_hwspinlock.c
[..]
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
Should the copyright range be updated to include your changes which I
presume were authored in 2014?
That would be expected by people on my side, will update.
[..]
+
+#include linux/err.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/device.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/hwspinlock.h
+#include linux/io.h
Could these be put in alphabetical order? I vaguely recall a few
maintainers expressing this preference to avoid merge issues.
I think we can clean some of them out at least, will have a look.
[..]
+static int msm_hwspinlock_probe(struct platform_device *pdev)
+{
[..]
+ match = of_match_device(msm_hwspinlock_of_match, pdev-dev);
+ if (!match)
+ return -EINVAL;
This seems redundant. It is my understanding that probe will only be
called for a matching device. What are we attempting to accomplish here?
Yeah, if anything it would catch static bugs.
And with the modification below I'll just drop it.
[..]
+ stride = (int)match-data;
+ for (i = 0, hwlock = bank-lock[0]; i num_locks; i++, hwlock++)
+ hwlock-priv = iobase + i * stride;
I am not a fan of this method for determining the stride. We already
have 0x4 and 0x80 in this driver, and will soon need 0x1000 for some of
the current chips (still listed as TCSR too). The stride is completely
up to our hardware designers, and it seems like encoding stride in this
manner will require constant updates and maintenance. I prefer
calculating stride by dividing the reg size by num_locks since that will
automatically adjust for whatever the hardware designers decide to use
next month. If you wanted to, with the reg size calculation, you could
remove the qcom,sfpb-mutex since there is no functional difference
other than stride. What are your thoughts?
I was thinking about this before and with your addition of tcsr having
different strides on different platforms we could either make the compatibles
more specifc (e.g. include platform name) or encode the stride in some other
way.
As you say there's no real technical difference in how we interact with the
current sfpb and tcsr mutex registers, so I would say making the compatibles
more specifc doesn't add any value.
I'll update this and follow your recommendation.
When we started hacking on this we found it very confusing that the caf driver
for tcsr is called sfpb, so I will keep both compatibles for clarity...
Thanks for your input!
Regards,
Bjorn
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[PATCH] msm: scm: Move scm-boot files to drivers/soc and include/soc
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c| 2 +-
drivers/soc/qcom/Makefile | 2 +-
{arch/arm/mach-qcom = drivers/soc/qcom}/scm-boot.c | 4 ++--
{arch/arm/mach-qcom = include/soc/qcom}/scm-boot.h | 0
5 files changed, 4 insertions(+), 5 deletions(-)
rename {arch/arm/mach-qcom = drivers/soc/qcom}/scm-boot.c (97%)
rename {arch/arm/mach-qcom = include/soc/qcom}/scm-boot.h (100%)
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
index db41e8c..e324375 100644
--- a/arch/arm/mach-qcom/Makefile
+++ b/arch/arm/mach-qcom/Makefile
@@ -1,3 +1,2 @@
obj-y := board.o
obj-$(CONFIG_SMP) += platsmp.o
-obj-$(CONFIG_QCOM_SCM) += scm-boot.o
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index d690856..a692bcb 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -20,7 +20,7 @@
#include asm/smp_plat.h
-#include scm-boot.h
+#include soc/qcom/scm-boot.h
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL0x35a0
#define SCSS_CPU1CORE_RESET0x2d80
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index a39446d..70d52ed 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_QCOM_GSBI)+= qcom_gsbi.o
CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
-obj-$(CONFIG_QCOM_SCM) += scm.o
+obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
diff --git a/arch/arm/mach-qcom/scm-boot.c b/drivers/soc/qcom/scm-boot.c
similarity index 97%
rename from arch/arm/mach-qcom/scm-boot.c
rename to drivers/soc/qcom/scm-boot.c
index 5add20e..60ff7b4 100644
--- a/arch/arm/mach-qcom/scm-boot.c
+++ b/drivers/soc/qcom/scm-boot.c
@@ -17,9 +17,9 @@
#include linux/module.h
#include linux/slab.h
-#include soc/qcom/scm.h
-#include scm-boot.h
+#include soc/qcom/scm.h
+#include soc/qcom/scm-boot.h
/*
* Set the cold/warm boot address for one of the CPU cores.
diff --git a/arch/arm/mach-qcom/scm-boot.h b/include/soc/qcom/scm-boot.h
similarity index 100%
rename from arch/arm/mach-qcom/scm-boot.h
rename to include/soc/qcom/scm-boot.h
--
1.9.1
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[PATCH v3] hwspinlock: qcom: Add support for Qualcomm HW Mutex block
From: Kumar Gala ga...@codeaurora.org
Add driver for Qualcomm Hardware Mutex block that exists on newer
Qualcomm SoCs.
Cc: Jeffrey Hugo jh...@codeaurora.org
Cc: Eric Holmberg eholm...@codeaurora.org
Cc: Courtney Cavin courtney.ca...@sonymobile.com
Signed-off-by: Kumar Gala ga...@codeaurora.org
[bjorn: added pm_runtime calls, from Courtney,
added sfpb-mutex compatible,
updated DT binding documentation formatting,
based stride on resource size instead of hardcoded values,
replaced msm prefix with qcom,
cleaned up includes]
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
We need this driver to add support for the shared memory manager, so I'm
reviving Kumars patch from a year ago, with some additional sprinkles on top.
Changes since v2:
- MODULE_DEVICE_TABLE
- Changed prefix to qcom
- Cleaned up includes
- Rely on reg and num-locks to figure out stride, instead of of_match data
Changes since v1:
- Added the pm_runtime calls needed to be able to boot a kernel with
pm_runtime and this driver, patch from Courtney.
- Added sfpb-mutex compatible, for re-use of the driver in family A platforms.
- Updated formatting of DT binding documentation, while adding the extra
compatible.
- Dropped Stephen Boyds Reviewed-by due to these changes.
.../devicetree/bindings/hwlock/qcom-hwspinlock.txt | 35 +
drivers/hwspinlock/Kconfig | 11 ++
drivers/hwspinlock/Makefile|1 +
drivers/hwspinlock/qcom_hwspinlock.c | 147
4 files changed, 194 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt
create mode 100644 drivers/hwspinlock/qcom_hwspinlock.c
diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt
b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt
new file mode 100644
index 000..27c7c80
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt
@@ -0,0 +1,35 @@
+Qualcomm Hardware Mutex Block:
+
+The hardware block provides mutexes utilized between different processors
+on the SoC as part of the communication protocol used by these processors.
+
+- compatible:
+ Usage: required
+ Value type: string
+ Definition: must be one of:
+ qcom,sfpb-mutex,
+ qcom,tcsr-mutex
+
+- reg:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: base address and size of the mutex registers
+
+- reg-names:
+ Usage: required
+ Value type: string
+ Definition: must be mutex-base
+
+- qcom,num-locks:
+ Usage: required
+ Value type: u32
+ Definition: the number of locks/mutex available in this block
+
+Example:
+
+ hwlock@fd484000 {
+ compatible = qcom,tcsr-mutex;
+ reg = 0xfd484000 0x1000;
+ reg-names = mutex-base;
+ qcom,num-locks = 32;
+ };
diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
index 3612cb5..af4c7e6 100644
--- a/drivers/hwspinlock/Kconfig
+++ b/drivers/hwspinlock/Kconfig
@@ -8,6 +8,17 @@ config HWSPINLOCK
menu Hardware Spinlock drivers
+config HWSPINLOCK_QCOM
+ tristate Qualcomm Hardware Spinlock device
+ depends on ARCH_QCOM
+ select HWSPINLOCK
+ help
+ Say y here to support the Qualcomm Hardware Mutex functionality, which
+ provides a synchronisation mechanism for the various processors on
+ the SoC.
+
+ If unsure, say N.
+
config HWSPINLOCK_OMAP
tristate OMAP Hardware Spinlock device
depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX ||
SOC_AM43XX
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
index 93eb64b..f3bff48 100644
--- a/drivers/hwspinlock/Makefile
+++ b/drivers/hwspinlock/Makefile
@@ -3,5 +3,6 @@
#
obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o
+obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o
obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o
obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock/qcom_hwspinlock.c
new file mode 100644
index 000..a9e5fa4
--- /dev/null
+++ b/drivers/hwspinlock/qcom_hwspinlock.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, Sony Mobile Communications AB
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
Re: [PATCH] clk: qcom: Fix sdc 144kHz frequency entry
On 09/02/14 14:44, Mike Turquette wrote: Quoting Stephen Boyd (2014-08-29 12:49:26) The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable. Cc: Kumar Gala ga...@codeaurora.org Cc: Andy Gross agr...@codeaurora.org Fixes: 24d8fba44af3 clk: qcom: Add support for IPQ8064's global clock controller (GCC) Signed-off-by: Stephen Boyd sb...@codeaurora.org Do you need this pulled into a 3.17-rc? Yes that would be helpful since this fixes a driver introduced into 3.17. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3] hwspinlock: qcom: Add support for Qualcomm HW Mutex block
On 9/2/2014 2:04 PM, Bjorn Andersson wrote: From: Kumar Gala ga...@codeaurora.org Add driver for Qualcomm Hardware Mutex block that exists on newer Qualcomm SoCs. Cc: Jeffrey Hugo jh...@codeaurora.org Cc: Eric Holmberg eholm...@codeaurora.org Cc: Courtney Cavin courtney.ca...@sonymobile.com Signed-off-by: Kumar Gala ga...@codeaurora.org [bjorn: added pm_runtime calls, from Courtney, added sfpb-mutex compatible, updated DT binding documentation formatting, based stride on resource size instead of hardcoded values, replaced msm prefix with qcom, cleaned up includes] Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com --- snip For what its worth, this looks good to me. Jeffrey Hugo -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] mmc: sdhci-msm: Make tuning block table endian agnostic
If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that assumes the CPU is little-endian.
Change the table to be an array of bytes instead of 32-bit words
so we can use memcmp() without needing to byte-swap every word
depending on the endianess of the CPU.
Cc: Asutosh Das asuto...@codeaurora.org
Cc: Venkat Gopalakrishnan venk...@codeaurora.org
Cc: Georgi Djakov gdja...@mm-sol.com
Fixes: 415b5a75da43 mmc: sdhci-msm: Add platform_execute_tuning implementation
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/mmc/host/sdhci-msm.c | 42 +++---
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 40573a58486a..5aabffc15ae8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -47,22 +47,34 @@
#define CMUX_SHIFT_PHASE_SHIFT 24
#define CMUX_SHIFT_PHASE_MASK (7 CMUX_SHIFT_PHASE_SHIFT)
-static const u32 tuning_block_64[] = {
- 0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe,
- 0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777,
- 0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff,
- 0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7
+static const u8 tuning_block_64[] = {
+ 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+ 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+ 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+ 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+ 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+ 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+ 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+ 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
};
-static const u32 tuning_block_128[] = {
- 0xff00, 0x, 0x, 0x33cc,
- 0xcccc, 0x, 0xeeff, 0xffff,
- 0xffdd, 0x, 0xbbff, 0xbbff,
- 0xffbb, 0xff77, 0x77ff, 0xffeeddbb,
- 0x00ff, 0x00ff, 0xcc00, 0xcc33,
- 0x, 0xffcc, 0xffee, 0x,
- 0xddff, 0xddff, 0xffdd, 0xffbb,
- 0x, 0x77ff, 0xffff, 0xeeddbb77
+static const u8 tuning_block_128[] = {
+ 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
+ 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
+ 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
+ 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
+ 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
+ 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
+ 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
+ 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
+ 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
+ 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
+ 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
+ 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
+ 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
+ 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
+ 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
+ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
};
struct sdhci_msm_host {
@@ -359,7 +371,7 @@ static int sdhci_msm_execute_tuning(struct sdhci_host
*host, u32 opcode)
{
int tuning_seq_cnt = 3;
u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
- const u32 *tuning_block_pattern = tuning_block_64;
+ const u8 *tuning_block_pattern = tuning_block_64;
int size = sizeof(tuning_block_64); /* Pattern size in bytes */
int rc;
struct mmc_host *mmc = host-mmc;
--
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hosted by The Linux Foundation
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