Re: [Patch v9 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Hi, On Saturday 13 September 2014 12:58 AM, Andy Gross wrote: This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some Qualcomm platforms. This driver uses the generic PHY framework and will interact with the DWC3 controller. Do you have dt documentation for this driver? Signed-off-by: Andy Gross agr...@codeaurora.org --- drivers/phy/Kconfig | 11 + drivers/phy/Makefile|1 + drivers/phy/phy-qcom-dwc3.c | 483 +++ 3 files changed, 495 insertions(+) create mode 100644 drivers/phy/phy-qcom-dwc3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0dd7427..5d56161 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -230,4 +230,15 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_QCOM_DWC3 + tristate QCOM DWC3 USB PHY support + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help + This option enables support for the Synopsis PHYs present inside the + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS + PHY controllers. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 95c69ed..aa16f30 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c new file mode 100644 index 000..2c7b316 --- /dev/null +++ b/drivers/phy/phy-qcom-dwc3.c @@ -0,0 +1,483 @@ +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/module.h +#include linux/of.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/delay.h + +/** + * USB QSCRATCH Hardware registers + */ +#define QSCRATCH_GENERAL_CFG (0x08) +#define HSUSB_PHY_CTRL_REG (0x10) + +/* PHY_CTRL_REG */ +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) +#define HSUSB_CTRL_USB2_SUSPEND BIT(23) +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) alignment went wrong here.. +#define HSUSB_CTRL_USE_CLKCORE BIT(18) +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) +#define HSUSB_CTRL_COMMONONN BIT(11) +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) +#define HSUSB_CTRL_CLAMP_EN BIT(7) +#define HSUSB_CTRL_RETENABLENBIT(1) +#define HSUSB_CTRL_POR BIT(0) + +/* QSCRATCH_GENERAL_CFG */ +#define HSUSB_GCFG_XHCI_REV BIT(2) + +/** + * USB QSCRATCH Hardware registers + */ +#define SSUSB_PHY_CTRL_REG (0x00) +#define SSUSB_PHY_PARAM_CTRL_1 (0x04) +#define SSUSB_PHY_PARAM_CTRL_2 (0x08) +#define CR_PROTOCOL_DATA_IN_REG (0x0c) +#define CR_PROTOCOL_DATA_OUT_REG (0x10) +#define CR_PROTOCOL_CAP_ADDR_REG (0x14) +#define CR_PROTOCOL_CAP_DATA_REG (0x18) +#define CR_PROTOCOL_READ_REG (0x1c) +#define CR_PROTOCOL_WRITE_REG(0x20) + +/* PHY_CTRL_REG */ +#define SSUSB_CTRL_REF_USE_PAD BIT(28) +#define SSUSB_CTRL_TEST_POWERDOWNBIT(27) +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) +#define SSUSB_CTRL_SS_PHY_EN BIT(8) +#define SSUSB_CTRL_SS_PHY_RESET BIT(7) + +/* SSPHY control registers */ +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane) + +/* RX OVRD IN HI bits */ +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) +#define RX_OVRD_IN_HI_RX_RX_RESETBIT(12) +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT8 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
Re: [PATCH v4 1/1] iommu/arm-smmu: Do not access non-existing S2CR registers
On 8/28/2014 3:55 AM, Will Deacon wrote: On Tue, Aug 26, 2014 at 11:37:30AM +0100, Will Deacon wrote: On Sat, Aug 23, 2014 at 01:12:32AM +0100, Olav Haugan wrote: The number of S2CR registers is not properly set when stream matching is not supported. Fix this and add check that we do not try to access outside of the number of S2CR regisrers. Sorry for the bother, but could you base this on either iommu/devel or iommu/staging please? Now that the merge window is well and truly over, I moved those branches forward, so you needn't worry about iommu/pci anymore (which, as you pointed out, contains a bunch of WIP patches which should hold-up useful fixes like this one). Actually, it looks like this was eaten by our sorry excuse for an email service. I've managed to apply a version from the archive, thanks. Thanks Will. Sorry for the late reply. I have been OoO. Thanks, Olav -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] iio: vadc: Qualcomm SPMI PMIC voltage ADC driver
On 13/09/14 00:27, Hartmut Knaack wrote: Stanimir Varbanov schrieb, Am 11.09.2014 17:13: The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has 15bits resolution and register space inside PMIC accessible across SPMI bus. The vadc driver registers itself through IIO interface. Looks already pretty good. Things you should consider in regard of common coding style are to use the variable name ret instead of rc, since it is used in almost all adc drivers and thus makes reviewing a bit easier. Besides that, you seem to use unsigned as well as unsigned int, so to be consistent, please stick to one of them. Other comments in line. A few additional comments from me. My biggest question is whether you are actually making life difficult for yourself by having vadc_channels and vadc-channels (don't like the similar naming btw!) in different orders. I think you can move the ordering into the device tree reading code rather than doing it in lots of other places. Hence rather than an order based on the device tree description, put the data into a fixed ofer in vadc-channels. Entirely possible I'm missing something though :) Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile |1 + drivers/iio/adc/qcom-spmi-vadc.c | 999 + include/dt-bindings/iio/qcom,spmi-pmic-vadc.h | 119 +++ 4 files changed, 1130 insertions(+), 0 deletions(-) create mode 100644 drivers/iio/adc/qcom-spmi-vadc.c create mode 100644 include/dt-bindings/iio/qcom,spmi-pmic-vadc.h diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 11b048a..08700d4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -206,6 +206,17 @@ config NAU7802 To compile this driver as a module, choose M here: the module will be called nau7802. +config QCOM_SPMI_VADC +tristate Qualcomm SPMI PMIC voltage ADC +depends on SPMI +help + Say yes here if you want support for the Qualcomm SPMI PMIC voltage ADC. + + The driver supports reading the HKADC, XOADC through the ADC AMUX arbiter. + The VADC includes support for the conversion sequencer. The driver + supports reading the ADC through the AMUX channels for external pull-ups + simultaneously. + config TI_ADC081C tristate Texas Instruments ADC081C021/027 depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index ad81b51..d5d18f4 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o obj-$(CONFIG_MCP3422) += mcp3422.o obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o obj-$(CONFIG_NAU7802) += nau7802.o +obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c new file mode 100644 index 000..e30eb04 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-vadc.c @@ -0,0 +1,999 @@ +/* + * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/bitops.h +#include linux/completion.h +#include linux/delay.h +#include linux/err.h +#include linux/iio/iio.h +#include linux/interrupt.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/platform_device.h +#include linux/regmap.h +#include linux/slab.h +#include linux/log2.h + +#include dt-bindings/iio/qcom,spmi-pmic-vadc.h + +/* VADC register and bit definition */ +#define VADC_REVISION2 0x1 +#define VADC_REVISION2_SUPPORTED_VADC 1 + +#define VADC_PERPH_TYPE 0x4 +#define VADC_PERPH_TYPE_ADC 8 + +#define VADC_PERPH_SUBTYPE 0x5 +#define VADC_PERPH_SUBTYPE_VADC 1 + +#define VADC_STATUS10x8 +#define VADC_STATUS1_OP_MODE4 +#define VADC_STATUS1_REQ_STSBIT(1) +#define VADC_STATUS1_EOCBIT(0) +#define VADC_STATUS1_REQ_STS_EOC_MASK 0x3 + +#define VADC_MODE_CTL 0x40 +#define VADC_OP_MODE_SHIFT
Re: [PATCH v2 2/2] DT: iio: vadc: document dt binding
On 13/09/14 00:35, Hartmut Knaack wrote:
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
Document DT binding for Qualcomm SPMI PMIC voltage ADC
driver.
Still one typo left.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 123
1 files changed, 123 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
new file mode 100644
index 000..5abb491
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
@@ -0,0 +1,123 @@
+Qualcomm's SPMI PMIC voltage ADC
+
+SPMI PMIC voltage ADC (VADC) provides interface to clients to read
+voltage. A 15 bit ADC is used for voltage measurements. There are multiple
+peripherals to the VADC and the scope of the driver is to provide interface
+for the USR peripheral of the VADC.
+
+VADC node:
+
+- compatible:
+Usage: required
+Value type: string
+Definition: Should contain qcom,spmi-vadc.
+
+- reg:
+Usage: required
+Value type: u32
+Definition: Base address in the SPMI PMIC register map.
+
+- address-cells:
+Usage: required
+Value type: u32
+Definition: Must be one.
+
+- size-cells:
+Usage: required
+Value type: u32
+Definition: Must be zero.
+
+- interrupts:
+Usage: required
+Value type: prop-encoded-array
+Definition: End of convertion interrupt number.
Typo: conversion
+
+- qcom,poll-eoc:
+Usage: optional
+Value type: empty
+Definition: Use polling instead of interrupt for end of conversion
+completion.
+
+Channel node properties:
+
+- reg:
+Usage: required
+Value type: u32
+Definition: AMUX channel number.
+See include/dt-bindings/iio/qcom,spmi-pmic-vadc.h
+
+- qcom,decimation:
+Usage: optional
+Value type: u32
+Definition: Sampling rate to use for the individual channel measurement.
+Quicker measurements can be made by reducing decimation ratio.
+Valid values are 512, 1024, 2048, 4096.
+If property is not found, default value of 512 will be used.
+
+- qcom,pre-scaling:
+Usage: optional
+Value type: u32 array
+Definition: Used for scaling the channel input signal before the signal
is
+fed to VADC. The configuration for this node is to know the
+pre-determined ratio and use it for post scaling. Select one
from
+the following options.
+1 1, 1 3, 1 4, 1 6, 1 20, 1 8, 10 81, 1 10
+If property is not found default value depending of chip will
be used.
+
+- qcom,ratiometric:
+Usage: optional
+Value type: empty
+Definition: Channel calibration type. If this property is specified
+VADC will use the VDD reference(1.8V) and GND for channel
+calibration. If property is not found, channel will be
+calibrated with 625mV and 1.25V reference channels.
+
+- qcom,hw-settle-time:
+Usage: optional
+Value type: u32
+Definition: Time between AMUX getting configured and the ADC starting
+conversion. Delay = 100us * (value) for value 11, and
+2ms * (value - 10) otherwise.
+Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
+900 us and 1, 2, 4, 6, 8, 10 ms
+If property is not found, channel will use 0us.
+
+- qcom,avg-samples:
+Usage: optional
+Value type: u32
+Definition: Number of samples to be used for measurement.
+Fast averaging provides the option to obtain a single
measurement
+from the ADC that is an average of multiple samples. The value
+selected is 2^(value).
+Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
+If property is not found, 1 sample will be used.
+
+NOTE: At least one channel node is required.
Why? As far as I can see it will register all the channels anyway. If that is
not the intent
you need to build the iio_chan_spec array rather than using a static one.
I'm fine with it providing channels with sensible defaults if they aren't
overridden, but then
it should work fine with no channel nodes.
Jonathan
+
+Example:
+/* VADC node */
+pmic_vadc: vadc@3100 {
+compatible = qcom,spmi-vadc;
+reg = 0x3100 0x100;
+interrupts = 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING;
+#address-cells = 1;
+#size-cells = 0;
+#io-channel-cells = 1;
+io-channel-ranges;
+
+/* Channel node */
+usb_id_nopull {
+reg = VADC_LR_MUX10_USB_ID;
+
Re: [PATCH V3 01/16] scsi: support well known logical units
On Thu, Sep 11, 2014 at 05:41:18PM -0700, Subhash Jadavani wrote: UFS device has supports 4 different well known logical units: REPORT_LUNS (address: 01h), UFS Device (address: 50h), RPMB (address: 44h) and BOOT (address: 30h). UFS device's power management needs to be controlled by POWER CONDITION field of SSU (START STOP UNIT) command. But this power condition field will take effect only when its sent to UFS device well known logical unit (address: 50h) hence we require the scsi_device instance to represent this logical unit in order for the UFS host driver to send the SSU command for power management. We also require the scsi_device instance for RPMB (Replay Protected Memory Block) LU so user space process can control this LU. If those are the only LUs you specificly need I'd suggest you just manually call scsi_add_device from your driver for those instead of listing them in REPORT_LUNS and making them part of the normal LUN scan. One advantage of the well known LUNs is that you always know where in the LUN namespace they are :) -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Patch v9 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Hi,
On Sat, Sep 13, 2014 at 12:16:01PM +0530, Kishon Vijay Abraham I wrote:
On Saturday 13 September 2014 12:58 AM, Andy Gross wrote:
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Do you have dt documentation for this driver?
see patch 1
+static inline void qcom_dwc3_phy_write_readback(
+ struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
+ const u32 mask, u32 val)
+{
+ u32 write_val, tmp = readl(phy_dwc3-base + offset);
+
+ tmp = ~mask; /* retain other bits */
+ write_val = tmp | val;
+
+ writel(write_val, phy_dwc3-base + offset);
+
+ /* Read back to see if val was written */
Does it fail sometime? I'm not sure if this should be present in the
driver since this looks more of a debug code.
this was mentioned before. Silicon bug.
+ writel_relaxed(data | SSUSB_CTRL_SS_PHY_RESET,
+ phy_dwc3-base + SSUSB_PHY_CTRL_REG);
+ usleep_range(2000, 2200);
use msleep here..
why ? usleep_range() gives the scheduler oportunity to group timers.
--
balbi
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