Re: [PATCH 4/4] drm/msm: add OCMEM driver

2015-09-28 Thread Stephen Boyd 
On 09/28, Rob Clark wrote:
> On Mon, Sep 28, 2015 at 6:10 PM, Stephen Boyd  wrote:
> > On 09/28, Rob Clark wrote:
> >> diff --git a/drivers/gpu/drm/msm/ocmem/ocmem.c 
> >> b/drivers/gpu/drm/msm/ocmem/ocmem.c
> >> new file mode 100644
> >> index 000..d3cdd64
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/msm/ocmem/ocmem.c
> >> @@ -0,0 +1,396 @@
> >> +/*
> >> + * Copyright (C) 2015 Red Hat
> >> + * Author: Rob Clark 
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify it
> >> + * under the terms of the GNU General Public License version 2 as 
> >> published by
> >> + * the Free Software Foundation.
> >> + *
> >> + * This program is distributed in the hope that it will be useful, but 
> >> WITHOUT
> >> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> >> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
> >> for
> >> + * more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License 
> >> along with
> >> + * this program.  If not, see .
> >> + */
> >> +
> >> +#include 
> >> +#include 
> >
> > What is this include for?
> 
> needed for qcom_scm.h, although I guess I could just add the missing
> #includes in qcom_scm.h instead..

Ok, we should fix that in scm header files. It probably needs a
forward declare of struct cpumask and it should be struct cpumask
* instead of cpumask_t *.

> 
> >> +#include 
> >> +
> >> +#include "msm_drv.h"
> >> +#include "ocmem.h"
> >> +#include "ocmem.xml.h"
> >> +
[..]
> >> +
> >> +static void update_ocmem(struct ocmem *ocmem)
> >> +{
> >> + uint32_t region_mode_ctrl = 0x0;
> >> + unsigned pos = 0;
> >> + unsigned i = 0;
> >> +
> >> + if (!qcom_scm_ocmem_lock_available()) {
> >> + for (i = 0; i < ocmem->config->num_regions; i++) {
> >> + struct ocmem_region *region = &ocmem->regions[i];
> >> + pos = i << 2;
> >> + if (region->mode == THIN_MODE)
> >> + region_mode_ctrl |= BIT(pos);
> >> + }
> >> + dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", 
> >> region_mode_ctrl);
> >> + ocmem_write(ocmem, REG_OCMEM_REGION_MODE_CTL, 
> >> region_mode_ctrl);
> >> + /* Barrier to commit the region mode */
> >> + mb();
> >
> > msm_writel() already has a barrier, so now we have a double
> > barrier?
> 
> hmm, msm_writel() doesn't have any more barrier than writel().. so I
> kept the mb() from downstream..

Yes writel() already has a barrier. Downstream is using
writel_relaxed() instead of writel() in ocmem_write() and then
adding the barrier explicitly after ocmem_write() in the right
places.

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Re: [PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Rob Clark 
On Mon, Sep 28, 2015 at 6:35 PM, Stephen Boyd  wrote:
> On 09/28, Bjorn Andersson wrote:
>> On Mon 28 Sep 14:08 PDT 2015, Rob Clark wrote:
>>
>> > On Mon, Sep 28, 2015 at 4:51 PM, Stephen Boyd  wrote:
>> > > On 09/28, Rob Clark wrote:
>> > >> +bool qcom_scm_ocmem_secure_available(void)
>> > >> +{
>> > >> + int ret = qcom_scm_clk_enable();
>> > >
>> > > I doubt we need to enable clocks to figure out if a call is
>> > > available. Please drop clk stuff here.
>> >
>> > hmm, hdcp did, but pas didn't..  otoh it looks like the call to
>> > __qcom_scm_pas_supported() *should* be wrapped in clk enable/disable..
>> >
>> > And __qcom_scm_is_call_available() does call qcom_scm_call().  Which
>> > is, I assume, what needs the clk's..  so not entirely sure if *all*
>> > the clk enable/disable stuff should be stripped out, or if missing clk
>> > stuff should be added in qcom_scm_pas_supported()..
>> >
>>
>> The scm clocks here are the crypto engine clocks, they are not needed to
>> check if TZ implements PAS for a given processor or not.
>>
>> But it could be argued that this is simply an assumption I make of the
>> black box we're calling into...
>
> Let's not make assumptions. They're not needed to check if it has
> support for something.
>
>>
>> >
>> > >> +
>> > >> + if (ret)
>> > >> + goto clk_err;
>> > >> +
>> > >> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
>> > >> + QCOM_SCM_OCMEM_SECURE_CFG);
>> > >> +
>> > >> + qcom_scm_clk_disable();
>> > >> +
>> > >> +clk_err:
>> > >> + return (ret > 0) ? true : false;
>> > >> +}
>> > >> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
>> > >> +
>> [..]
>> > >> +int qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
>> > >> +{
>> > >> + int ret = qcom_scm_clk_enable();
>> > >> +
>> > >> + if (ret)
>> > >> + return ret;
>> > >> +
>> > >> + ret = __qcom_scm_ocmem_unlock(id, offset, size);
>> > >> + qcom_scm_clk_disable();
>> > >> +
>> > >> + return ret;
>> > >> +}
>> > >> +EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
>> > >
>> > > I don't think we need any clocks for lock/unlock/cfg either. The
>> > > scm clocks are some crypto clocks that the secure side isn't able
>> > > to enable and we don't have a device in DT for them. In the ocmem
>> > > case, we should rely on the ocmem device to get the clocks and
>> > > turn them on before calling any scm APIs that may require those
>> > > clocks.
>> >
>> > Hmm, if that is true then we should probably drop the clks for hdcp
>> > fxns too, and maybe add a comment somewhere since it isn't really
>> > clear what the clks are for (and when it is unclear, folks will just
>> > cargo-cult what the existing fxns are doing).  As-is it is hard to
>> > tell what is required and what is luck..
>> >
>>
>> I would expect hdcp to use the crypto engines in some way and we don't
>> want people to feel that they should add the random clocks here, so
>> commenting them is probably the way to go.
>
> Yes HDCP uses crypto for something so those clock calls should
> stay. If the clocks were used by a HDCP device then it would be
> like the ocmem case, but it isn't.
>
>>
>> > >> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
>> > >> index 46d41e4..a934457 100644
>> > >> --- a/include/linux/qcom_scm.h
>> > >> +++ b/include/linux/qcom_scm.h
>> > >> @@ -23,10 +23,20 @@ struct qcom_scm_hdcp_req {
>> > >>   u32 val;
>> > >>  };
>> > >>
>> > >> +extern bool qcom_scm_is_available(void);
>> > >
>> > > Is this used? Looks like noise.
>> >
>> > perhaps should be split out into a separate patch..  but I am using
>> > this, and it seems like a good idea to avoid null ptr deref's of
>> > __scm.  Probably some of the scm callers should call this first..
>> > either that or we should make other scm entry points behave better if
>> > __scm is null..
>> >
>>
>> This is part of Andy's platformication, didn't he export it properly?
>> I use it as well from the remoteproc.
>
> Do we probe defer ocmem if scm isn't ready? Maybe we should name
> it qcom_scm_is_probed() and have it return -EPROBE_DEFER if it
> isn't probed and 0 if it is probed. Then drivers just call that
> function and return the error if there is one. I'd rather not
> litter scm_*() APIs with checks to see if the driver has probed
> yet. Just let those crash the system. Of course, this probably
> doesn't matter because we don't need to do any clock stuff here
> anyway.

currently, we just skip the scm calls.. which is maybe not the right
thing.  With the various kconfig options in downstream driver, I can't
say I'm really sure if there are any cases where we would skip scm
completely and do everything from kernel..

That said, I'm not a huge fan of 'crash the system' approach in
general.. it's kinda nice if the system can at least boot far enough
to tell what went wrong, especially on devices without serial ports
(or jtag, etc).

If I can assume there should always be scm, then

Re: [PATCH 4/4] drm/msm: add OCMEM driver

2015-09-28 Thread Rob Clark 
On Mon, Sep 28, 2015 at 6:10 PM, Stephen Boyd  wrote:
> On 09/28, Rob Clark wrote:
>> @@ -322,10 +319,8 @@ static void a3xx_destroy(struct msm_gpu *gpu)
>>
>>   adreno_gpu_cleanup(adreno_gpu);
>>
>> -#ifdef CONFIG_MSM_OCMEM
>>   if (a3xx_gpu->ocmem_base)
>
> Is this supposed to be ocmem_base or ocmem_hdl? Perhaps this
> check could be put inside the ocmem_free() itself so that the
> caller doesn't have to care.

yeah, should be ocmem_hdl

I would kind of prefer to keep the check for null in the caller, just
to simplify backports to 3.10 kernel (since otherwise the API matches
downstream).. Although I guess downstream checks for null and spits
out error msg and returns -EINVAL, so maybe that is enough..

>>   ocmem_free(OCMEM_GRAPHICS, a3xx_gpu->ocmem_hdl);
>> -#endif
>>
>>   kfree(a3xx_gpu);
>>  }
>> @@ -289,10 +288,8 @@ static void a4xx_destroy(struct msm_gpu *gpu)
>>
>>   adreno_gpu_cleanup(adreno_gpu);
>>
>> -#ifdef CONFIG_MSM_OCMEM
>> - if (a4xx_gpu->ocmem_base)
>> + if (a4xx_gpu->ocmem_hdl)
>
> This one changed, so a3xx above seems highly suspicious.
>
>>   ocmem_free(OCMEM_GRAPHICS, a4xx_gpu->ocmem_hdl);
>> -#endif
>>
>>   kfree(a4xx_gpu);
>>  }
>> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
>> index 2bbe85a..f042ba8 100644
>> --- a/drivers/gpu/drm/msm/msm_gpu.h
>> +++ b/drivers/gpu/drm/msm/msm_gpu.h
>> @@ -172,4 +172,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
>>  void __init adreno_register(void);
>>  void __exit adreno_unregister(void);
>>
>> +void __init ocmem_register(void);
>> +void __exit ocmem_unregister(void);
>
> __init and __exit in header files is useless
>
>> +
>>  #endif /* __MSM_GPU_H__ */
>> diff --git a/drivers/gpu/drm/msm/ocmem/ocmem.c 
>> b/drivers/gpu/drm/msm/ocmem/ocmem.c
>> new file mode 100644
>> index 000..d3cdd64
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/ocmem/ocmem.c
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright (C) 2015 Red Hat
>> + * Author: Rob Clark 
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License version 2 as published 
>> by
>> + * the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but 
>> WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along 
>> with
>> + * this program.  If not, see .
>> + */
>> +
>> +#include 
>> +#include 
>
> What is this include for?

needed for qcom_scm.h, although I guess I could just add the missing
#includes in qcom_scm.h instead..

>> +#include 
>> +
>> +#include "msm_drv.h"
>> +#include "ocmem.h"
>> +#include "ocmem.xml.h"
>> +
>> +enum region_mode {
>> + WIDE_MODE = 0x0,
>> + THIN_MODE,
>> + MODE_DEFAULT = WIDE_MODE,
>> +};
>> +
>> +enum ocmem_tz_client {
>> + TZ_UNUSED = 0x0,
>> + TZ_GRAPHICS,
>> + TZ_VIDEO,
>> + TZ_LP_AUDIO,
>> + TZ_SENSORS,
>> + TZ_OTHER_OS,
>> + TZ_DEBUG,
>> +};
>> +
>> +struct ocmem_region {
>> + unsigned psgsc_ctrl;
>> + bool interleaved;
>> + enum region_mode mode;
>> + unsigned int num_macros;
>> + enum ocmem_macro_state macro_state[4];
>> + unsigned long macro_size;
>> + unsigned long region_size;
>> +};
>> +
>> +struct ocmem_config {
>> + uint8_t  num_regions;
>> + uint32_t macro_size;
>> +};
>> +
>> +struct ocmem {
>> + struct device *dev;
>> + const struct ocmem_config *config;
>> + struct resource *ocmem_mem;
>> + struct clk *core_clk;
>> + struct clk *iface_clk;
>> + void __iomem *mmio;
>> +
>> + unsigned num_ports;
>
> Is this used after probe?

not currently.. downstream was saving it off in pdata but on closer
look it doesn't seem to use it after probe either..

>> + unsigned num_macros;
>> + bool interleaved;
>
> Is this used after probe?

again, cargo culted from downstream, but it looks like we can drop..

>> +
>> + struct ocmem_region *regions;
>> +};
>> +
>> +struct ocmem *ocmem;
>
> static?
>
>> +
>> +static bool ocmem_exists(void);
>> +
>> +static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
>> +{
>> + msm_writel(data, ocmem->mmio + reg);
>> +}
>> +
>> +static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg)
>> +{
>> + return msm_readl(ocmem->mmio + reg);
>> +}
>> +
>> +static int ocmem_clk_enable(struct ocmem *ocmem)
>> +{
>> + int ret;
>> +
>> + ret = clk_prepare_enable(ocmem->core_clk);
>> + if (ret)
>> + return ret;
>> +
>> + if (ocmem->iface_clk) {
>> + ret = clk_prepare_enable(ocmem->iface_clk);
>
> clk_prepare_enable() on NULL does nothing so it should be safe to
> drop the if.
>
>> + if (ret)
>> +

Re: [PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Stephen Boyd 
On 09/28, Bjorn Andersson wrote:
> On Mon 28 Sep 14:08 PDT 2015, Rob Clark wrote:
> 
> > On Mon, Sep 28, 2015 at 4:51 PM, Stephen Boyd  wrote:
> > > On 09/28, Rob Clark wrote:
> > >> +bool qcom_scm_ocmem_secure_available(void)
> > >> +{
> > >> + int ret = qcom_scm_clk_enable();
> > >
> > > I doubt we need to enable clocks to figure out if a call is
> > > available. Please drop clk stuff here.
> > 
> > hmm, hdcp did, but pas didn't..  otoh it looks like the call to
> > __qcom_scm_pas_supported() *should* be wrapped in clk enable/disable..
> > 
> > And __qcom_scm_is_call_available() does call qcom_scm_call().  Which
> > is, I assume, what needs the clk's..  so not entirely sure if *all*
> > the clk enable/disable stuff should be stripped out, or if missing clk
> > stuff should be added in qcom_scm_pas_supported()..
> > 
> 
> The scm clocks here are the crypto engine clocks, they are not needed to
> check if TZ implements PAS for a given processor or not.
> 
> But it could be argued that this is simply an assumption I make of the
> black box we're calling into...

Let's not make assumptions. They're not needed to check if it has
support for something.

> 
> > 
> > >> +
> > >> + if (ret)
> > >> + goto clk_err;
> > >> +
> > >> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
> > >> + QCOM_SCM_OCMEM_SECURE_CFG);
> > >> +
> > >> + qcom_scm_clk_disable();
> > >> +
> > >> +clk_err:
> > >> + return (ret > 0) ? true : false;
> > >> +}
> > >> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
> > >> +
> [..]
> > >> +int qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
> > >> +{
> > >> + int ret = qcom_scm_clk_enable();
> > >> +
> > >> + if (ret)
> > >> + return ret;
> > >> +
> > >> + ret = __qcom_scm_ocmem_unlock(id, offset, size);
> > >> + qcom_scm_clk_disable();
> > >> +
> > >> + return ret;
> > >> +}
> > >> +EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
> > >
> > > I don't think we need any clocks for lock/unlock/cfg either. The
> > > scm clocks are some crypto clocks that the secure side isn't able
> > > to enable and we don't have a device in DT for them. In the ocmem
> > > case, we should rely on the ocmem device to get the clocks and
> > > turn them on before calling any scm APIs that may require those
> > > clocks.
> > 
> > Hmm, if that is true then we should probably drop the clks for hdcp
> > fxns too, and maybe add a comment somewhere since it isn't really
> > clear what the clks are for (and when it is unclear, folks will just
> > cargo-cult what the existing fxns are doing).  As-is it is hard to
> > tell what is required and what is luck..
> > 
> 
> I would expect hdcp to use the crypto engines in some way and we don't
> want people to feel that they should add the random clocks here, so
> commenting them is probably the way to go.

Yes HDCP uses crypto for something so those clock calls should
stay. If the clocks were used by a HDCP device then it would be
like the ocmem case, but it isn't.

> 
> > >> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
> > >> index 46d41e4..a934457 100644
> > >> --- a/include/linux/qcom_scm.h
> > >> +++ b/include/linux/qcom_scm.h
> > >> @@ -23,10 +23,20 @@ struct qcom_scm_hdcp_req {
> > >>   u32 val;
> > >>  };
> > >>
> > >> +extern bool qcom_scm_is_available(void);
> > >
> > > Is this used? Looks like noise.
> > 
> > perhaps should be split out into a separate patch..  but I am using
> > this, and it seems like a good idea to avoid null ptr deref's of
> > __scm.  Probably some of the scm callers should call this first..
> > either that or we should make other scm entry points behave better if
> > __scm is null..
> > 
> 
> This is part of Andy's platformication, didn't he export it properly?
> I use it as well from the remoteproc.

Do we probe defer ocmem if scm isn't ready? Maybe we should name
it qcom_scm_is_probed() and have it return -EPROBE_DEFER if it
isn't probed and 0 if it is probed. Then drivers just call that
function and return the error if there is one. I'd rather not
litter scm_*() APIs with checks to see if the driver has probed
yet. Just let those crash the system. Of course, this probably
doesn't matter because we don't need to do any clock stuff here
anyway.

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Re: [PATCH 4/4] drm/msm: add OCMEM driver

2015-09-28 Thread Stephen Boyd 
On 09/28, Rob Clark wrote:
> @@ -322,10 +319,8 @@ static void a3xx_destroy(struct msm_gpu *gpu)
>  
>   adreno_gpu_cleanup(adreno_gpu);
>  
> -#ifdef CONFIG_MSM_OCMEM
>   if (a3xx_gpu->ocmem_base)

Is this supposed to be ocmem_base or ocmem_hdl? Perhaps this
check could be put inside the ocmem_free() itself so that the
caller doesn't have to care.

>   ocmem_free(OCMEM_GRAPHICS, a3xx_gpu->ocmem_hdl);
> -#endif
>  
>   kfree(a3xx_gpu);
>  }
> @@ -289,10 +288,8 @@ static void a4xx_destroy(struct msm_gpu *gpu)
>  
>   adreno_gpu_cleanup(adreno_gpu);
>  
> -#ifdef CONFIG_MSM_OCMEM
> - if (a4xx_gpu->ocmem_base)
> + if (a4xx_gpu->ocmem_hdl)

This one changed, so a3xx above seems highly suspicious.

>   ocmem_free(OCMEM_GRAPHICS, a4xx_gpu->ocmem_hdl);
> -#endif
>  
>   kfree(a4xx_gpu);
>  }
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 2bbe85a..f042ba8 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -172,4 +172,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
>  void __init adreno_register(void);
>  void __exit adreno_unregister(void);
>  
> +void __init ocmem_register(void);
> +void __exit ocmem_unregister(void);

__init and __exit in header files is useless

> +
>  #endif /* __MSM_GPU_H__ */
> diff --git a/drivers/gpu/drm/msm/ocmem/ocmem.c 
> b/drivers/gpu/drm/msm/ocmem/ocmem.c
> new file mode 100644
> index 000..d3cdd64
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/ocmem/ocmem.c
> @@ -0,0 +1,396 @@
> +/*
> + * Copyright (C) 2015 Red Hat
> + * Author: Rob Clark 
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published 
> by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but 
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include 
> +#include 

What is this include for?

> +#include 
> +
> +#include "msm_drv.h"
> +#include "ocmem.h"
> +#include "ocmem.xml.h"
> +
> +enum region_mode {
> + WIDE_MODE = 0x0,
> + THIN_MODE,
> + MODE_DEFAULT = WIDE_MODE,
> +};
> +
> +enum ocmem_tz_client {
> + TZ_UNUSED = 0x0,
> + TZ_GRAPHICS,
> + TZ_VIDEO,
> + TZ_LP_AUDIO,
> + TZ_SENSORS,
> + TZ_OTHER_OS,
> + TZ_DEBUG,
> +};
> +
> +struct ocmem_region {
> + unsigned psgsc_ctrl;
> + bool interleaved;
> + enum region_mode mode;
> + unsigned int num_macros;
> + enum ocmem_macro_state macro_state[4];
> + unsigned long macro_size;
> + unsigned long region_size;
> +};
> +
> +struct ocmem_config {
> + uint8_t  num_regions;
> + uint32_t macro_size;
> +};
> +
> +struct ocmem {
> + struct device *dev;
> + const struct ocmem_config *config;
> + struct resource *ocmem_mem;
> + struct clk *core_clk;
> + struct clk *iface_clk;
> + void __iomem *mmio;
> +
> + unsigned num_ports;

Is this used after probe?

> + unsigned num_macros;
> + bool interleaved;

Is this used after probe?

> +
> + struct ocmem_region *regions;
> +};
> +
> +struct ocmem *ocmem;

static?

> +
> +static bool ocmem_exists(void);
> +
> +static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
> +{
> + msm_writel(data, ocmem->mmio + reg);
> +}
> +
> +static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg)
> +{
> + return msm_readl(ocmem->mmio + reg);
> +}
> +
> +static int ocmem_clk_enable(struct ocmem *ocmem)
> +{
> + int ret;
> +
> + ret = clk_prepare_enable(ocmem->core_clk);
> + if (ret)
> + return ret;
> +
> + if (ocmem->iface_clk) {
> + ret = clk_prepare_enable(ocmem->iface_clk);

clk_prepare_enable() on NULL does nothing so it should be safe to
drop the if.

> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void update_ocmem(struct ocmem *ocmem)
> +{
> + uint32_t region_mode_ctrl = 0x0;
> + unsigned pos = 0;
> + unsigned i = 0;
> +
> + if (!qcom_scm_ocmem_lock_available()) {
> + for (i = 0; i < ocmem->config->num_regions; i++) {
> + struct ocmem_region *region = &ocmem->regions[i];
> + pos = i << 2;
> + if (region->mode == THIN_MODE)
> + region_mode_ctrl |= BIT(pos);
> + }
> + dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", 
> region_mode_ctrl);
> + ocmem_write(ocmem, REG_OCMEM_REGION_MODE_CTL, region_mode_ctrl);
> + /* Barrier to commit the region mode

Re: [PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Bjorn Andersson 
On Mon 28 Sep 14:08 PDT 2015, Rob Clark wrote:

> On Mon, Sep 28, 2015 at 4:51 PM, Stephen Boyd  wrote:
> > On 09/28, Rob Clark wrote:
> >> Add interfaces needed for configuring OCMEM.
> >>
> >> Signed-off-by: Rob Clark 
> >> ---
> >>  drivers/firmware/qcom_scm-32.c |  57 ++
> >>  drivers/firmware/qcom_scm-64.c |  16 +++
> >>  drivers/firmware/qcom_scm.c| 106 
> >> +
> >>  drivers/firmware/qcom_scm.h|  13 +
> >>  include/linux/qcom_scm.h   |  10 
> >>  5 files changed, 202 insertions(+)
> >>
> >> diff --git a/drivers/firmware/qcom_scm-32.c 
> >> b/drivers/firmware/qcom_scm-32.c
[..]
> >> +bool qcom_scm_ocmem_secure_available(void)
> >> +{
> >> + int ret = qcom_scm_clk_enable();
> >
> > I doubt we need to enable clocks to figure out if a call is
> > available. Please drop clk stuff here.
> 
> hmm, hdcp did, but pas didn't..  otoh it looks like the call to
> __qcom_scm_pas_supported() *should* be wrapped in clk enable/disable..
> 
> And __qcom_scm_is_call_available() does call qcom_scm_call().  Which
> is, I assume, what needs the clk's..  so not entirely sure if *all*
> the clk enable/disable stuff should be stripped out, or if missing clk
> stuff should be added in qcom_scm_pas_supported()..
> 

The scm clocks here are the crypto engine clocks, they are not needed to
check if TZ implements PAS for a given processor or not.

But it could be argued that this is simply an assumption I make of the
black box we're calling into...

> 
> >> +
> >> + if (ret)
> >> + goto clk_err;
> >> +
> >> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
> >> + QCOM_SCM_OCMEM_SECURE_CFG);
> >> +
> >> + qcom_scm_clk_disable();
> >> +
> >> +clk_err:
> >> + return (ret > 0) ? true : false;
> >> +}
> >> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
> >> +
[..]
> >> +int qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
> >> +{
> >> + int ret = qcom_scm_clk_enable();
> >> +
> >> + if (ret)
> >> + return ret;
> >> +
> >> + ret = __qcom_scm_ocmem_unlock(id, offset, size);
> >> + qcom_scm_clk_disable();
> >> +
> >> + return ret;
> >> +}
> >> +EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
> >
> > I don't think we need any clocks for lock/unlock/cfg either. The
> > scm clocks are some crypto clocks that the secure side isn't able
> > to enable and we don't have a device in DT for them. In the ocmem
> > case, we should rely on the ocmem device to get the clocks and
> > turn them on before calling any scm APIs that may require those
> > clocks.
> 
> Hmm, if that is true then we should probably drop the clks for hdcp
> fxns too, and maybe add a comment somewhere since it isn't really
> clear what the clks are for (and when it is unclear, folks will just
> cargo-cult what the existing fxns are doing).  As-is it is hard to
> tell what is required and what is luck..
> 

I would expect hdcp to use the crypto engines in some way and we don't
want people to feel that they should add the random clocks here, so
commenting them is probably the way to go.

> >> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
> >> index 46d41e4..a934457 100644
> >> --- a/include/linux/qcom_scm.h
> >> +++ b/include/linux/qcom_scm.h
> >> @@ -23,10 +23,20 @@ struct qcom_scm_hdcp_req {
> >>   u32 val;
> >>  };
> >>
> >> +extern bool qcom_scm_is_available(void);
> >
> > Is this used? Looks like noise.
> 
> perhaps should be split out into a separate patch..  but I am using
> this, and it seems like a good idea to avoid null ptr deref's of
> __scm.  Probably some of the scm callers should call this first..
> either that or we should make other scm entry points behave better if
> __scm is null..
> 

This is part of Andy's platformication, didn't he export it properly?
I use it as well from the remoteproc.

Regards,
Bjorn
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Re: [PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Rob Clark 
On Mon, Sep 28, 2015 at 4:51 PM, Stephen Boyd  wrote:
> On 09/28, Rob Clark wrote:
>> Add interfaces needed for configuring OCMEM.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  drivers/firmware/qcom_scm-32.c |  57 ++
>>  drivers/firmware/qcom_scm-64.c |  16 +++
>>  drivers/firmware/qcom_scm.c| 106 
>> +
>>  drivers/firmware/qcom_scm.h|  13 +
>>  include/linux/qcom_scm.h   |  10 
>>  5 files changed, 202 insertions(+)
>>
>> diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
>> index e9c306b..656d8fe 100644
>> --- a/drivers/firmware/qcom_scm-32.c
>> +++ b/drivers/firmware/qcom_scm-32.c
>> @@ -500,6 +500,63 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, 
>> u32 req_cnt, u32 *resp)
>>   req, req_cnt * sizeof(*req), resp, sizeof(*resp));
>>  }
>>
>> +int __qcom_scm_ocmem_secure_cfg(unsigned sec_id)
>> +{
>> + int ret, scm_ret = 0;
>> + struct msm_scm_sec_cfg {
>> + unsigned int id;
>> + unsigned int spare;
>
>
> __le32 for both
>
>> + } cfg;
>> +
>> + cfg.id = sec_id;
>> +
>> +
>
> nitpick: drop double space
>
>> + ret = qcom_scm_call(QCOM_SCM_OCMEM_SECURE_SVC, 
>> QCOM_SCM_OCMEM_SECURE_CFG,
>> + &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
>> +
>> + if (ret || scm_ret) {
>> + pr_err("ocmem: Failed to enable secure programming\n");
>
> Maybe the caller should print something if they care instead of
> burying it down here.
>
>> + return ret ? ret : -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
>> + uint32_t mode)
>
> Please use u32 here instead of uint32_t. uint32_t is not for
> kernel code.
>
>> +{
>> + struct ocmem_tz_lock {
>> + u32 id;
>> + u32 offset;
>> + u32 size;
>> + u32 mode;
>
> All __le32
>
>> + } request;
>> +
>> + request.id = id;
>> + request.offset = offset;
>> + request.size = size;
>> + request.mode = mode;
>
> And then do the cpu_to_le32() stuff here.
>
>> +
>> + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
>> + &request, sizeof(request), NULL, 0);
>> +}
>> +
>> +int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
>
> u32
>
>> +{
>> + struct ocmem_tz_unlock {
>> + u32 id;
>> + u32 offset;
>> + u32 size;
>
> __le32
>
>> + } request;
>> +
>> + request.id = id;
>> + request.offset = offset;
>> + request.size = size;
>> +
>> + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
>> + &request, sizeof(request), NULL, 0);
>> +}
>> +
>>  bool __qcom_scm_pas_supported(u32 peripheral)
>>  {
>>   __le32 out;
>> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
>> index 118df0a..59b1007 100644
>> --- a/drivers/firmware/qcom_scm.c
>> +++ b/drivers/firmware/qcom_scm.c
>> @@ -154,6 +154,112 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, 
>> u32 req_cnt, u32 *resp)
>>  EXPORT_SYMBOL(qcom_scm_hdcp_req);
>>
>>  /**
>> + * qcom_scm_ocmem_secure_available() - Check if secure environment supports
>> + * OCMEM.
>> + *
>> + * Return true if OCMEM secure interface is supported, false if not.
>> + */
>> +bool qcom_scm_ocmem_secure_available(void)
>> +{
>> + int ret = qcom_scm_clk_enable();
>
> I doubt we need to enable clocks to figure out if a call is
> available. Please drop clk stuff here.

hmm, hdcp did, but pas didn't..  otoh it looks like the call to
__qcom_scm_pas_supported() *should* be wrapped in clk enable/disable..

And __qcom_scm_is_call_available() does call qcom_scm_call().  Which
is, I assume, what needs the clk's..  so not entirely sure if *all*
the clk enable/disable stuff should be stripped out, or if missing clk
stuff should be added in qcom_scm_pas_supported()..


>> +
>> + if (ret)
>> + goto clk_err;
>> +
>> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
>> + QCOM_SCM_OCMEM_SECURE_CFG);
>> +
>> + qcom_scm_clk_disable();
>> +
>> +clk_err:
>> + return (ret > 0) ? true : false;
>> +}
>> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
>> +
>> +/**
>> + * qcom_scm_ocmem_secure_cfg() - call OCMEM secure cfg interface
>> + */
>> +int qcom_scm_ocmem_secure_cfg(unsigned sec_id)
>> +{
>> + int ret = qcom_scm_clk_enable();
>> +
>> + if (ret)
>> + return ret;
>> +
>> + ret = __qcom_scm_ocmem_secure_cfg(sec_id);
>> + qcom_scm_clk_disable();
>> +
>> + return ret;
>> +}
>> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_cfg);
>> +
>> +/**
>> + * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface 
>> available
>> + */
>> +bool qcom_scm_ocmem_lock_available(void)
>> +{
>> + int ret = qcom_scm_clk_enable();
>
> No need for clocks?

Re: [PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Stephen Boyd 
On 09/28, Rob Clark wrote:
> Add interfaces needed for configuring OCMEM.
> 
> Signed-off-by: Rob Clark 
> ---
>  drivers/firmware/qcom_scm-32.c |  57 ++
>  drivers/firmware/qcom_scm-64.c |  16 +++
>  drivers/firmware/qcom_scm.c| 106 
> +
>  drivers/firmware/qcom_scm.h|  13 +
>  include/linux/qcom_scm.h   |  10 
>  5 files changed, 202 insertions(+)
> 
> diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
> index e9c306b..656d8fe 100644
> --- a/drivers/firmware/qcom_scm-32.c
> +++ b/drivers/firmware/qcom_scm-32.c
> @@ -500,6 +500,63 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, 
> u32 req_cnt, u32 *resp)
>   req, req_cnt * sizeof(*req), resp, sizeof(*resp));
>  }
>  
> +int __qcom_scm_ocmem_secure_cfg(unsigned sec_id)
> +{
> + int ret, scm_ret = 0;
> + struct msm_scm_sec_cfg {
> + unsigned int id;
> + unsigned int spare;


__le32 for both

> + } cfg;
> +
> + cfg.id = sec_id;
> +
> +

nitpick: drop double space

> + ret = qcom_scm_call(QCOM_SCM_OCMEM_SECURE_SVC, 
> QCOM_SCM_OCMEM_SECURE_CFG,
> + &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
> +
> + if (ret || scm_ret) {
> + pr_err("ocmem: Failed to enable secure programming\n");

Maybe the caller should print something if they care instead of
burying it down here.

> + return ret ? ret : -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
> + uint32_t mode)

Please use u32 here instead of uint32_t. uint32_t is not for
kernel code.

> +{
> + struct ocmem_tz_lock {
> + u32 id;
> + u32 offset;
> + u32 size;
> + u32 mode;

All __le32

> + } request;
> +
> + request.id = id;
> + request.offset = offset;
> + request.size = size;
> + request.mode = mode;

And then do the cpu_to_le32() stuff here.

> +
> + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
> + &request, sizeof(request), NULL, 0);
> +}
> +
> +int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)

u32

> +{
> + struct ocmem_tz_unlock {
> + u32 id;
> + u32 offset;
> + u32 size;

__le32

> + } request;
> +
> + request.id = id;
> + request.offset = offset;
> + request.size = size;
> +
> + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
> + &request, sizeof(request), NULL, 0);
> +}
> +
>  bool __qcom_scm_pas_supported(u32 peripheral)
>  {
>   __le32 out;
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 118df0a..59b1007 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -154,6 +154,112 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, 
> u32 req_cnt, u32 *resp)
>  EXPORT_SYMBOL(qcom_scm_hdcp_req);
>  
>  /**
> + * qcom_scm_ocmem_secure_available() - Check if secure environment supports
> + * OCMEM.
> + *
> + * Return true if OCMEM secure interface is supported, false if not.
> + */
> +bool qcom_scm_ocmem_secure_available(void)
> +{
> + int ret = qcom_scm_clk_enable();

I doubt we need to enable clocks to figure out if a call is
available. Please drop clk stuff here.

> +
> + if (ret)
> + goto clk_err;
> +
> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
> + QCOM_SCM_OCMEM_SECURE_CFG);
> +
> + qcom_scm_clk_disable();
> +
> +clk_err:
> + return (ret > 0) ? true : false;
> +}
> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
> +
> +/**
> + * qcom_scm_ocmem_secure_cfg() - call OCMEM secure cfg interface
> + */
> +int qcom_scm_ocmem_secure_cfg(unsigned sec_id)
> +{
> + int ret = qcom_scm_clk_enable();
> +
> + if (ret)
> + return ret;
> +
> + ret = __qcom_scm_ocmem_secure_cfg(sec_id);
> + qcom_scm_clk_disable();
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(qcom_scm_ocmem_secure_cfg);
> +
> +/**
> + * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
> + */
> +bool qcom_scm_ocmem_lock_available(void)
> +{
> + int ret = qcom_scm_clk_enable();

No need for clocks?

> +
> + if (ret)
> + goto clk_err;
> +
> + ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
> + QCOM_SCM_OCMEM_LOCK_CMD);
> +
> + qcom_scm_clk_disable();
> +
> +clk_err:
> + return (ret > 0) ? true : false;
> +}
> +EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
> +
> +/**
> + * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
> + * region to the specified initiator
> + *
> + * @id: tz initiator id
> + * @offset: OCMEM offset
> + * @size:   OCMEM size
> + * @mode:   access mode (WIDE/NARROW)
> + */
> +int qcom_scm_ocmem_lock(uint32_t id, uint32_t off

[PATCH 1/4] qcom-scm: add ocmem support

2015-09-28 Thread Rob Clark 
Add interfaces needed for configuring OCMEM.

Signed-off-by: Rob Clark 
---
 drivers/firmware/qcom_scm-32.c |  57 ++
 drivers/firmware/qcom_scm-64.c |  16 +++
 drivers/firmware/qcom_scm.c| 106 +
 drivers/firmware/qcom_scm.h|  13 +
 include/linux/qcom_scm.h   |  10 
 5 files changed, 202 insertions(+)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index e9c306b..656d8fe 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -500,6 +500,63 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 
req_cnt, u32 *resp)
req, req_cnt * sizeof(*req), resp, sizeof(*resp));
 }
 
+int __qcom_scm_ocmem_secure_cfg(unsigned sec_id)
+{
+   int ret, scm_ret = 0;
+   struct msm_scm_sec_cfg {
+   unsigned int id;
+   unsigned int spare;
+   } cfg;
+
+   cfg.id = sec_id;
+
+
+   ret = qcom_scm_call(QCOM_SCM_OCMEM_SECURE_SVC, 
QCOM_SCM_OCMEM_SECURE_CFG,
+   &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
+
+   if (ret || scm_ret) {
+   pr_err("ocmem: Failed to enable secure programming\n");
+   return ret ? ret : -EINVAL;
+   }
+
+   return 0;
+}
+
+int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
+   uint32_t mode)
+{
+   struct ocmem_tz_lock {
+   u32 id;
+   u32 offset;
+   u32 size;
+   u32 mode;
+   } request;
+
+   request.id = id;
+   request.offset = offset;
+   request.size = size;
+   request.mode = mode;
+
+   return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
+   &request, sizeof(request), NULL, 0);
+}
+
+int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
+{
+   struct ocmem_tz_unlock {
+   u32 id;
+   u32 offset;
+   u32 size;
+   } request;
+
+   request.id = id;
+   request.offset = offset;
+   request.size = size;
+
+   return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
+   &request, sizeof(request), NULL, 0);
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
__le32 out;
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index e64fd92..ef5c59e 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -62,6 +62,22 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 
req_cnt, u32 *resp)
return -ENOTSUPP;
 }
 
+int __qcom_scm_ocmem_secure_cfg(unsigned sec_id)
+{
+   return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
+   uint32_t mode)
+{
+   return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
+{
+   return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
return false;
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 118df0a..59b1007 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -154,6 +154,112 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 
req_cnt, u32 *resp)
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
 
 /**
+ * qcom_scm_ocmem_secure_available() - Check if secure environment supports
+ * OCMEM.
+ *
+ * Return true if OCMEM secure interface is supported, false if not.
+ */
+bool qcom_scm_ocmem_secure_available(void)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   goto clk_err;
+
+   ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SECURE_SVC,
+   QCOM_SCM_OCMEM_SECURE_CFG);
+
+   qcom_scm_clk_disable();
+
+clk_err:
+   return (ret > 0) ? true : false;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_secure_available);
+
+/**
+ * qcom_scm_ocmem_secure_cfg() - call OCMEM secure cfg interface
+ */
+int qcom_scm_ocmem_secure_cfg(unsigned sec_id)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   return ret;
+
+   ret = __qcom_scm_ocmem_secure_cfg(sec_id);
+   qcom_scm_clk_disable();
+
+   return ret;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_secure_cfg);
+
+/**
+ * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
+ */
+bool qcom_scm_ocmem_lock_available(void)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   goto clk_err;
+
+   ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
+   QCOM_SCM_OCMEM_LOCK_CMD);
+
+   qcom_scm_clk_disable();
+
+clk_err:
+   return (ret > 0) ? true : false;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
+
+/**
+ * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
+ * region to the specified initiator
+ *
+ * @id: tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ * @mode:   access m

[PATCH 3/4] drm/msm: update generated headers

2015-09-28 Thread Rob Clark 
Update generated headers to pull in OCMEM register definitions.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a2xx.xml.h  |   9 +-
 drivers/gpu/drm/msm/adreno/a3xx.xml.h  |  27 --
 drivers/gpu/drm/msm/adreno/a4xx.xml.h  |  15 ++--
 drivers/gpu/drm/msm/adreno/adreno_common.xml.h |  13 ++-
 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h|   9 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h  |   4 +-
 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h  |   4 +-
 drivers/gpu/drm/msm/dsi/sfpb.xml.h |   4 +-
 drivers/gpu/drm/msm/edp/edp.xml.h  |   4 +-
 drivers/gpu/drm/msm/hdmi/hdmi.xml.h|   4 +-
 drivers/gpu/drm/msm/hdmi/qfprom.xml.h  |   4 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h|   4 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h|  82 +-
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h   |  11 ++-
 drivers/gpu/drm/msm/ocmem/ocmem.xml.h  | 113 +
 15 files changed, 267 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.xml.h

diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h 
b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 0261f0d..9e2aceb 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
364 bytes, from 2015-05-20 20:03:07)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
398 bytes, from 2015-09-24 17:25:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1453 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32901 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10551 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10755 bytes, from 2015-09-14 20:46:55)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
14968 bytes, from 2015-05-20 20:12:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67120 bytes, from 2015-08-14 23:22:03)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63785 bytes, from 2015-08-14 18:27:06)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67771 bytes, from 2015-09-14 20:46:55)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63970 bytes, from 2015-09-14 20:50:12)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml (   
1773 bytes, from 2015-09-24 17:30:00)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h 
b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index 48d1337..97dc1c6 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
364 bytes, from 2015-05-20 20:03:07)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
398 bytes, from 2015-09-24 17:25:31)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1453 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32901 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10551 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10755 bytes, from 2015-09-14 20:46:55)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
14968 bytes, from 2015-05-20 20:12:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67120 bytes, from 2015-08-14 23:22:03)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63785 bytes, from 2015-08-14 18:27:06)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67771 bytes, from 2015-09-14 20:46:55)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63970 bytes, from 2015-09-14 20:50:12)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml (   
1773 bytes, from 2015-09-24 17:30:00)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -280,6 +281,8 @@ enum a3xx_rb_blend_opcode {
 enum a3xx_intp_mode {
SMOOTH = 0,
FLAT = 1,
+   ZERO = 2,
+   ONE = 3,
 };
 
 enum a3xx_repl_mode

[PATCH 4/4] drm/msm: add OCMEM driver

2015-09-28 Thread Rob Clark 
For now, since the GPU is the only upstream consumer, just stuff this
into drm/msm.  Eventually if we have other consumers, we'll have to
split this out and make the allocation less hard coded.  But I'll punt
on that until I better understand the non-gpu uses-cases (and whether
the allocation *really* needs to be as complicated as it is in the
downstream driver).

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile  |   3 +-
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c |  17 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c |  19 +-
 drivers/gpu/drm/msm/msm_drv.c |   2 +
 drivers/gpu/drm/msm/msm_gpu.h |   3 +
 drivers/gpu/drm/msm/ocmem/ocmem.c | 396 ++
 drivers/gpu/drm/msm/ocmem/ocmem.h |  46 
 7 files changed, 459 insertions(+), 27 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.c
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 0a543eb..8ddf6fa 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -48,7 +48,8 @@ msm-y := \
msm_iommu.o \
msm_perf.o \
msm_rd.o \
-   msm_ringbuffer.o
+   msm_ringbuffer.o \
+   ocmem/ocmem.o
 
 msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
 msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index ca29688..29bbb80 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -17,10 +17,7 @@
  * this program.  If not, see .
  */
 
-#ifdef CONFIG_MSM_OCMEM
-#  include 
-#endif
-
+#include "ocmem/ocmem.h"
 #include "a3xx_gpu.h"
 
 #define A3XX_INT0_MASK \
@@ -322,10 +319,8 @@ static void a3xx_destroy(struct msm_gpu *gpu)
 
adreno_gpu_cleanup(adreno_gpu);
 
-#ifdef CONFIG_MSM_OCMEM
if (a3xx_gpu->ocmem_base)
ocmem_free(OCMEM_GRAPHICS, a3xx_gpu->ocmem_hdl);
-#endif
 
kfree(a3xx_gpu);
 }
@@ -539,6 +534,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+   struct ocmem_buf *ocmem_hdl;
int ret;
 
if (!pdev) {
@@ -569,18 +565,13 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
goto fail;
 
/* if needed, allocate gmem: */
-   if (adreno_is_a330(adreno_gpu)) {
-#ifdef CONFIG_MSM_OCMEM
-   /* TODO this is different/missing upstream: */
-   struct ocmem_buf *ocmem_hdl =
-   ocmem_allocate(OCMEM_GRAPHICS, 
adreno_gpu->gmem);
-
+   ocmem_hdl = ocmem_allocate(OCMEM_GRAPHICS, adreno_gpu->gmem);
+   if (!IS_ERR(ocmem_hdl)) {
a3xx_gpu->ocmem_hdl = ocmem_hdl;
a3xx_gpu->ocmem_base = ocmem_hdl->addr;
adreno_gpu->gmem = ocmem_hdl->len;
DBG("using %dK of OCMEM at 0x%08x", adreno_gpu->gmem / 1024,
a3xx_gpu->ocmem_base);
-#endif
}
 
if (!gpu->mmu) {
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index a53f1be..17f084d 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -10,10 +10,9 @@
  * GNU General Public License for more details.
  *
  */
+
+#include "ocmem/ocmem.h"
 #include "a4xx_gpu.h"
-#ifdef CONFIG_MSM_OCMEM
-#  include 
-#endif
 
 #define A4XX_INT0_MASK \
(A4XX_INT0_RBBM_AHB_ERROR |\
@@ -289,10 +288,8 @@ static void a4xx_destroy(struct msm_gpu *gpu)
 
adreno_gpu_cleanup(adreno_gpu);
 
-#ifdef CONFIG_MSM_OCMEM
-   if (a4xx_gpu->ocmem_base)
+   if (a4xx_gpu->ocmem_hdl)
ocmem_free(OCMEM_GRAPHICS, a4xx_gpu->ocmem_hdl);
-#endif
 
kfree(a4xx_gpu);
 }
@@ -538,6 +535,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+   struct ocmem_buf *ocmem_hdl;
int ret;
 
if (!pdev) {
@@ -568,18 +566,13 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
goto fail;
 
/* if needed, allocate gmem: */
-   if (adreno_is_a4xx(adreno_gpu)) {
-#ifdef CONFIG_MSM_OCMEM
-   /* TODO this is different/missing upstream: */
-   struct ocmem_buf *ocmem_hdl =
-   ocmem_allocate(OCMEM_GRAPHICS, 
adreno_gpu->gmem);
-
+   ocmem_hdl = ocmem_allocate(OCMEM_GRAPHICS, adreno_gpu->gmem);
+   if (!IS_ERR(ocmem_hdl)) {
a4xx_gpu->ocmem_hdl = ocmem_hdl;
a4xx_gpu->ocmem_base = ocmem_hdl->addr;
adreno_gpu->gmem = ocmem_hdl->len;
DBG("using %dK of OCMEM at 0x%08x", adreno_gpu->gmem / 1024,

[PATCH 0/4] Add OCMEM support

2015-09-28 Thread Rob Clark 
For devices such as 8x74 and 8084, which have a separate OCMEM block
used by the GPU (and some other devices), rather than an internal GMEM
block inside the GPU, we need a driver to power up and configure OCMEM
in order to get the GPU working.

This patchset implements a vastly simplified version of the downstream
vendor kernel's OCMEM driver.  Currently it is just enough to enable
the GPU.  But we can worry about other OCMEM users when they have up-
stream drivers.

The first patch adds support for the necessary scm interfaces, for the
parts of the OCMEM configuration that must be done from secure mode.
The second patch can be dropped, as so far this doesn't seem needed for
the GPU (I'm just sending the patch now so it can be found later if it
turns out to be needed).

The remaining two patches add the OCMEM driver inside drm/msm.  If we
eventually have other upstream OCMEM users, this would need to be split
out.  But that should not effect DT bindings, etc, so that is something
that can easily be done later when the need arises.

Rob Clark (4):
  qcom-scm: add ocmem support
  WIP: qcom-scm: add ocmem dump support
  drm/msm: update generated headers
  drm/msm: add OCMEM driver

 drivers/firmware/qcom_scm-32.c |  89 ++
 drivers/firmware/qcom_scm-64.c |  26 ++
 drivers/firmware/qcom_scm.c| 160 ++
 drivers/firmware/qcom_scm.h|  17 ++
 drivers/gpu/drm/msm/Makefile   |   3 +-
 drivers/gpu/drm/msm/adreno/a2xx.xml.h  |   9 +-
 drivers/gpu/drm/msm/adreno/a3xx.xml.h  |  27 +-
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c  |  17 +-
 drivers/gpu/drm/msm/adreno/a4xx.xml.h  |  15 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c  |  19 +-
 drivers/gpu/drm/msm/adreno/adreno_common.xml.h |  13 +-
 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h|   9 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h  |   4 +-
 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h  |   4 +-
 drivers/gpu/drm/msm/dsi/sfpb.xml.h |   4 +-
 drivers/gpu/drm/msm/edp/edp.xml.h  |   4 +-
 drivers/gpu/drm/msm/hdmi/hdmi.xml.h|   4 +-
 drivers/gpu/drm/msm/hdmi/qfprom.xml.h  |   4 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h|   4 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h|  82 -
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h   |  11 +-
 drivers/gpu/drm/msm/msm_drv.c  |   2 +
 drivers/gpu/drm/msm/msm_gpu.h  |   3 +
 drivers/gpu/drm/msm/ocmem/ocmem.c  | 396 +
 drivers/gpu/drm/msm/ocmem/ocmem.h  |  46 +++
 drivers/gpu/drm/msm/ocmem/ocmem.xml.h  | 113 +++
 include/linux/qcom_scm.h   |  14 +
 27 files changed, 1032 insertions(+), 67 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.c
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.h
 create mode 100644 drivers/gpu/drm/msm/ocmem/ocmem.xml.h

-- 
2.4.3

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[PATCH 2/4] WIP: qcom-scm: add ocmem dump support

2015-09-28 Thread Rob Clark 
Seems so far not to be required, at least for gpu.  Just stuffing it in
a patch since I wrote the code and someone might want to resurrect this
at some later time.

Signed-off-by: Rob Clark 
---
 drivers/firmware/qcom_scm-32.c | 32 +
 drivers/firmware/qcom_scm-64.c | 10 
 drivers/firmware/qcom_scm.c| 54 ++
 drivers/firmware/qcom_scm.h|  4 
 include/linux/qcom_scm.h   |  4 
 5 files changed, 104 insertions(+)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 656d8fe..287041a 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -557,6 +557,38 @@ int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, 
uint32_t size)
&request, sizeof(request), NULL, 0);
 }
 
+int __qcom_scm_ocmem_enable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   struct ocmem_tz_en_dump {
+   u32 id;
+   u32 offset;
+   u32 size;
+   } request;
+
+   request.id = id;
+   request.offset = offset;
+   request.size = size;
+
+   return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_ENABLE_DUMP_CMD,
+   &request, sizeof(request), NULL, 0);
+}
+
+int __qcom_scm_ocmem_disable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   struct ocmem_tz_dis_dump {
+   u32 id;
+   u32 offset;
+   u32 size;
+   } request;
+
+   request.id = id;
+   request.offset = offset;
+   request.size = size;
+
+   return qcom_scm_call(QCOM_SCM_OCMEM_SVC, 
QCOM_SCM_OCMEM_DISABLE_DUMP_CMD,
+   &request, sizeof(request), NULL, 0);
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
__le32 out;
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index ef5c59e..fc02828 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -78,6 +78,16 @@ int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, 
uint32_t size)
return -ENOTSUPP;
 }
 
+int __qcom_scm_ocmem_enable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_disable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
return false;
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 59b1007..b15b0d8 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -260,6 +260,60 @@ int qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, 
uint32_t size)
 EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
 
 /**
+ *
+ */
+bool qcom_scm_ocmem_dump_available(void)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   goto clk_err;
+
+   ret = __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
+   QCOM_SCM_OCMEM_ENABLE_DUMP_CMD);
+
+   qcom_scm_clk_disable();
+
+clk_err:
+   return (ret > 0) ? true : false;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_dump_available);
+
+/**
+ *
+ */
+int qcom_scm_ocmem_enable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   return ret;
+
+   ret = __qcom_scm_ocmem_enable_dump(id, offset, size);
+   qcom_scm_clk_disable();
+
+   return ret;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_enable_dump);
+
+/**
+ *
+ */
+int qcom_scm_ocmem_disable_dump(uint32_t id, uint32_t offset, uint32_t size)
+{
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   return ret;
+
+   ret = __qcom_scm_ocmem_disable_dump(id, offset, size);
+   qcom_scm_clk_disable();
+
+   return ret;
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_disable_dump);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *   available for the given peripherial
  * @peripheral:peripheral id
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index e01656f3..a090236 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -44,10 +44,14 @@ extern int __qcom_scm_ocmem_secure_cfg(unsigned sec_id);
 #define QCOM_SCM_OCMEM_SVC 0xf
 #define QCOM_SCM_OCMEM_LOCK_CMD0x1
 #define QCOM_SCM_OCMEM_UNLOCK_CMD  0x2
+#define QCOM_SCM_OCMEM_ENABLE_DUMP_CMD 0x3
+#define QCOM_SCM_OCMEM_DISABLE_DUMP_CMD0x4
 
 extern int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
uint32_t mode);
 extern int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t 
size);
+extern int __qcom_scm_ocmem_enable_dump(uint32_t id, uint32_t offset, uint32_t 
size);
+extern int __qcom_scm_ocmem_disable_dump(uint32_t id, uint32_t offset, 
uint32_t size);
 
 #define QCOM_SCM_SVC_PIL   0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD0x

Re: [PATCH v2 0/5] Support CPR on MSM8916

2015-09-28 Thread Stephen Boyd 
On 09/26, Rafael J. Wysocki wrote:
> On Friday, September 18, 2015 05:52:04 PM Stephen Boyd wrote:
> > This patch series adds support for CPR on MSM8916. The first
> > patch exposes a corner voting API to the CPR driver so that we can
> > change the corner for the MX regulator. If possible I would
> > like to make this patch prettier, but I don't have any great
> > ideas right now. The next patch adds support to adjust voltages in the OPP
> > layer, and then hooks that up to cpufreq-dt so that we can adjust
> > the voltage in response to what CPR tells us to do. I've also thrown
> > in a patch to make RCU lockdep warnings go away, but I'm not sure if it's
> > right. There's still work to do.
> > 
> > The final patch adds the CPR driver. This still has some rough edges. With
> > the OPPv2 bindings I'm thinking of moving the frequency tables into DT
> > and adding a custom vendor property to describe which fuse corner to use for
> > each frequency.
> > 
> > Once you have these patches in place along with a CPU clock driver you
> > can eanble enable cpufreq-dt and add the cpufreq-dt device (maybe the
> > CPR driver should add the cpufreq-dt device?) and you'll see interrupts
> > for CPR and OPP voltage adjustments triggering CPUfreq to modify voltages.
> > 
> > Andy Gross (1):
> >   regulator: smd: Add floor and corner operations
> > 
> > Stephen Boyd (4):
> >   PM / OPP: Support adjusting OPP voltages at runtime
> >   OPP: Allow notifiers to call dev_pm_opp_get_{voltage,freq} RCU-free
> >   cpufreq-dt: Handle OPP voltage adjust events
> >   power: avs: Add support for CPR (Core Power Reduction)
> 
> From the responses so far I gather there will be a v3?
> 

Yes. Definitely.

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Re: [PATCH 0/7] tty: serial: msm: Add DMA support and fix bit definitions

2015-09-28 Thread Ivan T. Ivanov 

On Fri, 2015-09-25 at 00:27 +0100, Srinivas Kandagatla wrote:
> Hi Ivan,
> On 12/09/15 14:02, Ivan T. Ivanov wrote:
> > Hi,
> > 
> > Following patches add DMA support for UARTDM type of hardware.
> > 
> > Changes have been tested on UARTDM v1.3(APQ8064) and v1.4(APQ8016).
> > 
> > Patches from Gurav were published long ago here[1], I just addressed
> > remaining comments and coding style issues.
> > 
> > Any comments are welcome.
> Looks like Magic Sysrq is broken with this patches.


Will check it shortly.

Thanks,
Ivan
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