Re: [PATCH 5/5] clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver

2015-11-18 Thread Stephen Boyd 
On 11/17, Stephen Boyd wrote:
> +static struct clk_alpha_pll mmpll0_early = {
> + .offset = 0x0,
> + .vco_table = mmpll_p_vco,
> + .num_vco = ARRAY_SIZE(mmpll_p_vco),
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = _alpha_pll_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv mmpll0 = {
> + .offset = 0x0,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0",
> + .parent_names = (const char *[]){ "mmpll0_early" },
> + .num_parents = 1,
> + .ops = _alpha_pll_postdiv_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll mmpll1_early = {
> + .offset = 0x30,
> + .vco_table = mmpll_p_vco,
> + .num_vco = ARRAY_SIZE(mmpll_p_vco),
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = _alpha_pll_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv mmpll1 = {
> + .offset = 0x30,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1",
> + .parent_names = (const char *[]){ "mmpll1_early" },
> + .num_parents = 1,
> + .ops = _alpha_pll_postdiv_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};

These are missing the .enable_reg and .enable_mask members to do
the proper FSM voting. I'll add that in v2.

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[PATCH 5/5] clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver

2015-11-17 Thread Stephen Boyd 
Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.

Signed-off-by: Stephen Boyd 
---
 .../devicetree/bindings/clock/qcom,mmcc.txt|1 +
 drivers/clk/qcom/Kconfig   |9 +
 drivers/clk/qcom/Makefile  |1 +
 drivers/clk/qcom/mmcc-msm8996.c| 3209 
 include/dt-bindings/clock/qcom,mmcc-msm8996.h  |  285 ++
 5 files changed, 3505 insertions(+)
 create mode 100644 drivers/clk/qcom/mmcc-msm8996.c
 create mode 100644 include/dt-bindings/clock/qcom,mmcc-msm8996.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt 
b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 34e7614d5074..8b0f7841af8d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -9,6 +9,7 @@ Required properties :
"qcom,mmcc-msm8660"
"qcom,mmcc-msm8960"
"qcom,mmcc-msm8974"
+   "qcom,mmcc-msm8996"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index fb2b499c647d..b552eceec2be 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -114,3 +114,12 @@ config MSM_GCC_8996
  Support for the global clock controller on msm8996 devices.
  Say Y if you want to use peripheral devices such as UART, SPI,
  i2c, USB, UFS, SD/eMMC, PCIe, etc.
+
+config MSM_MMCC_8996
+   tristate "MSM8996 Multimedia Clock Controller"
+   select MSM_GCC_8996
+   depends on COMMON_CLK_QCOM
+   help
+ Support for the multimedia clock controller on msm8996 devices.
+ Say Y if you want to support multimedia devices such as display,
+ graphics, video encode/decode, camera, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 42dca6799414..dc4280b85db1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
+obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
new file mode 100644
index ..b2329096cd7c
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -0,0 +1,3209 @@
+/*x
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+   P_XO,
+   P_MMPLL0,
+   P_GPLL0,
+   P_GPLL0_DIV,
+   P_MMPLL1,
+   P_MMPLL9,
+   P_MMPLL2,
+   P_MMPLL8,
+   P_MMPLL3,
+   P_DSI0PLL,
+   P_DSI1PLL,
+   P_MMPLL5,
+   P_HDMIPLL,
+   P_DSI0PLL_BYTE,
+   P_DSI1PLL_BYTE,
+   P_MMPLL4,
+};
+
+static const struct parent_map mmss_xo_hdmi_map[] = {
+   { P_XO, 0 },
+   { P_HDMIPLL, 1 }
+};
+
+static const char * const mmss_xo_hdmi[] = {
+   "xo",
+   "hdmipll"
+};
+
+static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
+   { P_XO, 0 },
+   { P_DSI0PLL, 1 },
+   { P_DSI1PLL, 2 }
+};
+
+static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
+   "xo",
+   "dsi0pll",
+   "dsi1pll"
+};
+
+static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
+   { P_XO, 0 },
+   { P_GPLL0, 5 },
+   { P_GPLL0_DIV, 6 }
+};
+
+static const char * const mmss_xo_gpll0_gpll0_div[] = {
+   "xo",
+   "gpll0",
+   "gpll0_div"
+};
+
+static const struct parent_map mmss_xo_dsibyte_map[] = {
+   { P_XO, 0 },
+   { P_DSI0PLL_BYTE, 1 },
+   { P_DSI1PLL_BYTE, 2 }
+};
+
+static const char * const mmss_xo_dsibyte[] = {
+   "xo",
+   "dsi0pllbyte",
+   "dsi1pllbyte"
+};
+
+static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
+   { P_XO, 0 },
+   { P_MMPLL0, 1 },
+