From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile|2 +
drivers/usb/phy/phy-msm-dw-hs.c | 327 ++
drivers/usb/phy/phy-msm-dw-ss.c | 374 +++
4 files changed, 714 insertions(+)
create mode 100644 drivers/usb/phy/phy-msm-dw-hs.c
create mode 100644 drivers/usb/phy/phy-msm-dw-ss.c
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index d5589f9..bbb2d0e 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -214,6 +214,17 @@ config USB_RCAR_PHY
To compile this driver as a module, choose M here: the
module will be called phy-rcar-usb.
+config USB_MSM_DW_PHYS
+ tristate Qualcomm USB controller DW PHY's wrappers support
+ depends on (USB || USB_GADGET) ARCH_MSM
+ select USB_PHY
+ help
+ Enable this to support the DW USB PHY transceivers on MSM chips
+ with DWC3 USB core. It handles PHY initialization, clock
+ management required after resetting the hardware and power
+ management. This driver is required even for peripheral only or
+ host only mode configurations.
+
config USB_ULPI
bool Generic ULPI Transceiver Driver
depends on ARM
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 2135e85..4813eb5 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
obj-$(CONFIG_USB_GPIO_VBUS)+= phy-gpio-vbus-usb.o
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
+obj-$(CONFIG_USB_MSM_DW_PHYS) += phy-msm-dw-hs.o
+obj-$(CONFIG_USB_MSM_DW_PHYS) += phy-msm-dw-ss.o
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o
diff --git a/drivers/usb/phy/phy-msm-dw-hs.c b/drivers/usb/phy/phy-msm-dw-hs.c
new file mode 100644
index 000..52994d2
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-dw-hs.c
@@ -0,0 +1,327 @@
+/* Copyright (c) 2013, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/usb/phy.h
+
+/**
+ * USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_CTRL_REG (0x04)
+#define QSCRATCH_GENERAL_CFG (0x08)
+#define PHY_CTRL_REG (0x10)
+#define PARAMETER_OVERRIDE_X_REG (0x14)
+#define CHARGING_DET_CTRL_REG (0x18)
+#define CHARGING_DET_OUTPUT_REG(0x1c)
+#define ALT_INTERRUPT_EN_REG (0x20)
+#define PHY_IRQ_STAT_REG (0x24)
+#define CGCTL_REG (0x28)
+
+#define PHY_3P3_VOL_MIN305 /* uV */
+#define PHY_3P3_VOL_MAX330 /* uV */
+#define PHY_3P3_HPM_LOAD 16000 /* uA */
+
+#define PHY_1P8_VOL_MIN180 /* uV */
+#define PHY_1P8_VOL_MAX180 /* uV */
+#define PHY_1P8_HPM_LOAD 19000 /* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO 1 /* uV */
+#define USB_VDDCX_MIN 5 /* uV */
+#define USB_VDDCX_MAX 7 /* uV */
+
+struct msm_dw_hs_phy {
+ struct usb_phy phy;
+ void __iomem*base;
+ struct device *dev;
+
+ struct clk *xo_clk;
+ struct clk *sleep_a_clk;
+
+ struct regulator*v3p3;
+ struct regulator*v1p8;
+ struct regulator*vddcx;
+ struct regulator*vbus;
+};
+
+#definephy_to_dw_phy(x)container_of((x), struct msm_dw_hs_phy,
phy)
+
+
+/**
+ * Write register.
+ *
+ * @base - MSM DWC3 PHY base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ */
+static inline void msm_dw_hs_write(void __iomem *base, u32 offset, u32 val)
+{
+ iowrite32(val, base +
