RE: [Patch v7 2/3] usb: phy: Add Qualcomm DWC3 HS/SS PHY drivers
Hi, On Mon, Jun 30, 2014 at 9:33 PM, Andy Gross agr...@codeaurora.org wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver . [snip] . +#include linux/usb/phy.h + +/** + * USB QSCRATCH Hardware registers + */ unused define, can you please remove it +#define QSCRATCH_CTRL_REG (0x04) +#define QSCRATCH_GENERAL_CFG (0x08) +#define PHY_CTRL_REG (0x10) +#define PARAMETER_OVERRIDE_X_REG (0x14) ditto +#define CHARGING_DET_CTRL_REG (0x18) ditto +#define CHARGING_DET_OUTPUT_REG(0x1c) ditto +#define ALT_INTERRUPT_EN_REG (0x20) ditto +#define PHY_IRQ_STAT_REG (0x24) ditto +#define CGCTL_REG (0x28) + +#define PHY_3P3_VOL_MIN305 /* uV */ +#define PHY_3P3_VOL_MAX330 /* uV */ +#define PHY_3P3_HPM_LOAD 16000 /* uA */ + . [snip] . +MODULE_ALIAS(platform:qcom-dwc3-ssphy); +MODULE_LICENSE(GPL v2); +MODULE_DESCRIPTION(DesignWare USB3 QCOM SSPHY driver); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ Regards, Kiran Padwal -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Patch v7 2/3] usb: phy: Add Qualcomm DWC3 HS/SS PHY drivers
On Thu, Jul 17, 2014 at 06:30:24AM -0400, kiran.pad...@smartplayin.com wrote: Hi, On Mon, Jun 30, 2014 at 9:33 PM, Andy Gross agr...@codeaurora.org wrote: From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver . [snip] . I'll remove all the unused/unnecessary defines in the next version. Thanks! -- sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v7 2/3] usb: phy: Add Qualcomm DWC3 HS/SS PHY drivers
From: Ivan T. Ivanov iiva...@mm-sol.com These drivers handles control and configuration of the HS and SS USB PHY transceivers. They are part of the driver which manage Synopsys DesignWare USB3 controller stack inside Qualcomm SoC's. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com Signed-off-by: Andy Gross agr...@codeaurora.org --- drivers/usb/phy/Kconfig | 11 ++ drivers/usb/phy/Makefile |2 + drivers/usb/phy/phy-qcom-hsusb.c | 348 ++ drivers/usb/phy/phy-qcom-ssusb.c | 385 ++ 4 files changed, 746 insertions(+) create mode 100644 drivers/usb/phy/phy-qcom-hsusb.c create mode 100644 drivers/usb/phy/phy-qcom-ssusb.c diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index e253fa0..5580c2f 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -229,4 +229,15 @@ config USB_ULPI_VIEWPORT Provides read/write operations to the ULPI phy register set for controllers with a viewport register (e.g. Chipidea/ARC controllers). +config USB_QCOM_DWC3_PHY + tristate Qualcomm USB controller DWC3 PHY wrappers support + depends on (USB || USB_GADGET) ARCH_QCOM + select USB_PHY + help + Enable this to support the DWC3 USB PHY transceivers on QCOM chips + with DWC3 USB core. It handles PHY initialization, clock + management required after resetting the hardware and power + management. This driver is required even for peripheral only or + host only mode configurations. + endmenu diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 24a9133..ef09c9c 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -29,3 +29,5 @@ obj-$(CONFIG_USB_RCAR_GEN2_PHY) += phy-rcar-gen2-usb.o obj-$(CONFIG_USB_ULPI) += phy-ulpi.o obj-$(CONFIG_USB_ULPI_VIEWPORT)+= phy-ulpi-viewport.o obj-$(CONFIG_KEYSTONE_USB_PHY) += phy-keystone.o +obj-$(CONFIG_USB_QCOM_DWC3_PHY)+= phy-qcom-hsusb.o +obj-$(CONFIG_USB_QCOM_DWC3_PHY)+= phy-qcom-ssusb.o diff --git a/drivers/usb/phy/phy-qcom-hsusb.c b/drivers/usb/phy/phy-qcom-hsusb.c new file mode 100644 index 000..7a44b13 --- /dev/null +++ b/drivers/usb/phy/phy-qcom-hsusb.c @@ -0,0 +1,348 @@ +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include linux/clk.h +#include linux/err.h +#include linux/io.h +#include linux/module.h +#include linux/of.h +#include linux/platform_device.h +#include linux/regulator/consumer.h +#include linux/usb/phy.h + +/** + * USB QSCRATCH Hardware registers + */ +#define QSCRATCH_CTRL_REG (0x04) +#define QSCRATCH_GENERAL_CFG (0x08) +#define PHY_CTRL_REG (0x10) +#define PARAMETER_OVERRIDE_X_REG (0x14) +#define CHARGING_DET_CTRL_REG (0x18) +#define CHARGING_DET_OUTPUT_REG(0x1c) +#define ALT_INTERRUPT_EN_REG (0x20) +#define PHY_IRQ_STAT_REG (0x24) +#define CGCTL_REG (0x28) + +#define PHY_3P3_VOL_MIN305 /* uV */ +#define PHY_3P3_VOL_MAX330 /* uV */ +#define PHY_3P3_HPM_LOAD 16000 /* uA */ + +#define PHY_1P8_VOL_MIN180 /* uV */ +#define PHY_1P8_VOL_MAX180 /* uV */ +#define PHY_1P8_HPM_LOAD 19000 /* uA */ + +/* TODO: these are suspicious */ +#define USB_VDDCX_NO 1 /* index */ +#define USB_VDDCX_MIN 5 /* index */ +#define USB_VDDCX_MAX 7 /* index */ + +/* PHY_CTRL_REG */ +#define HSUSB_CTRL_DMSEHV_CLAMPBIT(24) +#define HSUSB_CTRL_USB2_SUSPENDBIT(23) +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) +#defineHSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) +#define HSUSB_CTRL_USE_CLKCORE BIT(18) +#define HSUSB_CTRL_DPSEHV_CLAMPBIT(17) +#define HSUSB_CTRL_COMMONONN BIT(11) +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) +#define HSUSB_CTRL_OTGSESSVLD_CLAMPBIT(8) +#define HSUSB_CTRL_CLAMP_ENBIT(7) +#define HSUSB_CTRL_RETENABLEN BIT(1) +#define HSYSB_CTRL_POR BIT(0) + + +/* QSCRATCH_GENERAL_CFG */ +#define HSUSB_GCFG_XHCI_REVBIT(2) + +struct
Re: [Patch v7 2/3] usb: phy: Add Qualcomm DWC3 HS/SS PHY drivers
Hi,
first of all, since this is a brand new PHY driver, could you guys use
the generic phy framework instead ? (drivers/phy)
On Mon, Jun 30, 2014 at 11:03:52AM -0500, Andy Gross wrote:
diff --git a/drivers/usb/phy/phy-qcom-hsusb.c
b/drivers/usb/phy/phy-qcom-hsusb.c
new file mode 100644
index 000..7a44b13
--- /dev/null
+++ b/drivers/usb/phy/phy-qcom-hsusb.c
@@ -0,0 +1,348 @@
+/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/usb/phy.h
+
+/**
+ * USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_CTRL_REG(0x04)
+#define QSCRATCH_GENERAL_CFG (0x08)
+#define PHY_CTRL_REG (0x10)
+#define PARAMETER_OVERRIDE_X_REG (0x14)
+#define CHARGING_DET_CTRL_REG(0x18)
+#define CHARGING_DET_OUTPUT_REG (0x1c)
+#define ALT_INTERRUPT_EN_REG (0x20)
+#define PHY_IRQ_STAT_REG (0x24)
+#define CGCTL_REG(0x28)
+
+#define PHY_3P3_VOL_MIN 305 /* uV */
+#define PHY_3P3_VOL_MAX 330 /* uV */
+#define PHY_3P3_HPM_LOAD 16000 /* uA */
+
+#define PHY_1P8_VOL_MIN 180 /* uV */
+#define PHY_1P8_VOL_MAX 180 /* uV */
+#define PHY_1P8_HPM_LOAD 19000 /* uA */
+
+/* TODO: these are suspicious */
+#define USB_VDDCX_NO 1 /* index */
+#define USB_VDDCX_MIN5 /* index */
+#define USB_VDDCX_MAX7 /* index */
+
+/* PHY_CTRL_REG */
+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
+#define HSUSB_CTRL_COMMONONN BIT(11)
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
+#define HSUSB_CTRL_CLAMP_EN BIT(7)
+#define HSUSB_CTRL_RETENABLENBIT(1)
+#define HSYSB_CTRL_POR BIT(0)
+
+
+/* QSCRATCH_GENERAL_CFG */
+#define HSUSB_GCFG_XHCI_REV BIT(2)
+
+struct qcom_dwc3_hs_phy {
+ struct usb_phy phy;
+ void __iomem*base;
+ struct device *dev;
+
+ struct clk *xo_clk;
+ struct clk *utmi_clk;
+
+ struct regulator*v3p3;
+ struct regulator*v1p8;
+ struct regulator*vddcx;
+ struct regulator*vbus;
+};
+
+#define phy_to_dw_phy(x)container_of((x), struct
qcom_dwc3_hs_phy, phy)
+
+/**
+ * Write register.
+ *
+ * @base - QCOM DWC3 PHY base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ */
+static inline void qcom_dwc3_hs_write(void __iomem *base, u32 offset, u32
val)
+{
+ writel(val, base + offset);
+}
+
+/**
+ * Write register and read back masked value to confirm it is written
+ *
+ * @base - QCOM DWC3 PHY base virtual address.
+ * @offset - register offset.
+ * @mask - register bitmask specifying what should be updated
+ * @val - value to write.
+ */
+static inline void qcom_dwc3_hs_write_readback(void __iomem *base, u32
offset,
+ const u32 mask, u32 val)
+{
+ u32 write_val, tmp = readl(base + offset);
+
+ tmp = ~mask; /* retain other bits */
+ write_val = tmp | val;
+
+ writel(write_val, base + offset);
+
+ /* Read back to see if val was written */
+ tmp = readl(base + offset);
+ tmp = mask;/* clear other bits */
+
+ if (tmp != val)
+ pr_err(write: %x to QSCRATCH: %x FAILED\n, val, offset);
really nit-picking - and I'm not even sure I care - but passing a dev
pointer to use dev_err() here might be a good idea.
+}
+
+static void qcom_dwc3_hs_phy_shutdown(struct usb_phy *x)
+{
+ struct qcom_dwc3_hs_phy *phy = phy_to_dw_phy(x);
+ int ret;
+
+ ret = regulator_set_voltage(phy-v3p3, 0,
