Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
Hi Georgi,
On 02/24/2015 09:19 PM, Georgi Djakov wrote:
On 02/24/2015 06:49 AM, Archit Taneja wrote:
Hi,
[..]
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+{ .src = P_DSI0_PHYPLL_DSI },
+{ }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+.cmd_rcgr = 0x4d084,
This should be 0x4d000. Same reason as above.
+.mnd_width = 8,
+.hid_width = 5,
+.parent_map = gcc_xo_gpll0_dsiphy_map,
+.freq_tbl = ftbl_gcc_mdss_pclk,
+.clkr.hw.init = (struct clk_init_data){
+.name = pclk0_clk_src,
+.parent_names = gcc_xo_gpll0_dsiphy,
+.num_parents = 1,
+.ops = clk_rcg2_ops,
+},
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
+F(1920, P_XO, 1, 0,0),
+{ }
+};
+
+static struct clk_rcg2 vsync_clk_src = {
+.cmd_rcgr = 0x4d02c,
+.hid_width = 5,
+.parent_map = gcc_xo_gpll0a_map,
+.freq_tbl = ftbl_gcc_mdss_vsync_clk,
+.clkr.hw.init = (struct clk_init_data){
+.name = vsync_clk_src,
+.parent_names = gcc_xo_gpll0a,
+.num_parents = 2,
+.ops = clk_rcg2_ops,
+},
+};
+
I think we can update the clk ops for pclk0_clk_src and byte0_clk_src to
clk_pixel_ops and clk_byte_ops respectively too. The set_rate functions
in these ops have been modified to make it run with DSI PLL.
An Ack by Stephen for this change would be nice, though.
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
On 02/24/2015 06:49 AM, Archit Taneja wrote:
Hi,
[..]
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+{ .src = P_DSI0_PHYPLL_DSI },
+{ }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+.cmd_rcgr = 0x4d084,
This should be 0x4d000. Same reason as above.
+.mnd_width = 8,
+.hid_width = 5,
+.parent_map = gcc_xo_gpll0_dsiphy_map,
+.freq_tbl = ftbl_gcc_mdss_pclk,
+.clkr.hw.init = (struct clk_init_data){
+.name = pclk0_clk_src,
+.parent_names = gcc_xo_gpll0_dsiphy,
+.num_parents = 1,
+.ops = clk_rcg2_ops,
+},
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
+F(1920, P_XO, 1, 0,0),
+{ }
+};
+
+static struct clk_rcg2 vsync_clk_src = {
+.cmd_rcgr = 0x4d02c,
+.hid_width = 5,
+.parent_map = gcc_xo_gpll0a_map,
+.freq_tbl = ftbl_gcc_mdss_vsync_clk,
+.clkr.hw.init = (struct clk_init_data){
+.name = vsync_clk_src,
+.parent_names = gcc_xo_gpll0a,
+.num_parents = 2,
+.ops = clk_rcg2_ops,
+},
+};
+
mdss clocks look fine otherwise.
Thanks,
Archit
Hi Archit,
Thanks for taking a look. I have fixed these and also a few more.
BR,
Georgi
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
On 02/24/2015 12:46 AM, Stephen Boyd wrote:
On 02/06/15 10:58, Georgi Djakov wrote:
[...]
[..]
+
+/* Vote for GPLL0 to turn on */
+regmap_read(regmap, 0x45000, val);
+val |= BIT(0);
+regmap_write(regmap, 0x45000, val);
Hm.. I guess this is for the CPU to stay on, otherwise GPLL0 might turn
off? But if we expose this register and the bit as gpll0_vote then we're
going to turn it off once the last user turns off GPLL0. So I'm not sure
how to handle this, but it certainly seems like we can just remove this
bit of code and not be any worse off than we are right now. We need to
figure out some way to make this work though.
Ok, agree.
Here's the problem. GPLL0 is used by the CPU running this code. It's
also used by random other clocks in the system. If the code for the CPU
clock is not compiled in (i.e. clock-a53.c or whatever we call it), then
it is very possible that we'll disable the last clock that's using the
PLL according to what software knows, that will in turn disable the PLL
and then the CPU will die.
Of course, it's very possible that we'll never actually turn GPLL0 off
because it's used for quite a few clocks in the system. So the chances
of running into this problem are almost entirely theoretical.
Yes, I am investigating this scenario. Thanks for your comment.
+
+return qcom_cc_really_probe(pdev, gcc_msm8916_desc, regmap);
+}
+
+static int gcc_msm8916_remove(struct platform_device *pdev)
+{
+qcom_cc_remove(pdev);
+return 0;
+}
+
+static struct platform_driver gcc_msm8916_driver = {
+.probe = gcc_msm8916_probe,
+.remove = gcc_msm8916_remove,
+.driver = {
+.name = gcc-msm8916,
We need owner = THIS_MODULE here because the platform_driver_module
macro isn't being used.
But below i use the platform_driver_register macro and therefore it seems
not needed.
+.of_match_table = gcc_msm8916_match_table,
+},
+};
+
+static int __init gcc_msm8916_init(void)
+{
+return platform_driver_register(gcc_msm8916_driver);
+}
+core_initcall(gcc_msm8916_init);
+
+static void __exit gcc_msm8916_exit(void)
+{
+platform_driver_unregister(gcc_msm8916_driver);
+}
+module_exit(gcc_msm8916_exit);
Thank you for taking a look at this preliminary stuff. I'll send in the
next few days updated and tested version.
BR,
Georgi
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
On 02/24, Georgi Djakov wrote:
On 02/24/2015 12:46 AM, Stephen Boyd wrote:
On 02/06/15 10:58, Georgi Djakov wrote:
+
+ return qcom_cc_really_probe(pdev, gcc_msm8916_desc, regmap);
+}
+
+static int gcc_msm8916_remove(struct platform_device *pdev)
+{
+ qcom_cc_remove(pdev);
+ return 0;
+}
+
+static struct platform_driver gcc_msm8916_driver = {
+ .probe = gcc_msm8916_probe,
+ .remove = gcc_msm8916_remove,
+ .driver = {
+ .name = gcc-msm8916,
We need owner = THIS_MODULE here because the platform_driver_module
macro isn't being used.
But below i use the platform_driver_register macro and therefore it seems
not needed.
Ah ok, sorry for the confusion.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support
Hi,
On 02/07/2015 12:28 AM, Georgi Djakov wrote:
This is preliminary and not fully tested patch which adds
support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe
and control their clocks and resets.
Signed-off-by: Georgi Djakov georgi.dja...@linaro.org
snip
+
+static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
+ { .src = P_DSI0_PHYPLL_BYTE },
+ { }
+};
+
+static struct clk_rcg2 byte0_clk_src = {
+ .cmd_rcgr = 0x4d094,
This should be 0x4d044. The one above corresponds to the byte0_cbcr
register.
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0a_dsibyte_map,
+ .freq_tbl = ftbl_gcc_mdss_byte0_clk,
+ .clkr.hw.init = (struct clk_init_data){
+ .name = byte0_clk_src,
+ .parent_names = gcc_xo_gpll0a_dsibyte,
+ .num_parents = 2,
+ .ops = clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
+ F(1920, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 esc0_clk_src = {
+ .cmd_rcgr = 0x4d05c,
+ .hid_width = 5,
+ .parent_map = gcc_xo_dsibyte_map,
+ .freq_tbl = ftbl_gcc_mdss_esc0_clk,
+ .clkr.hw.init = (struct clk_init_data){
+ .name = esc0_clk_src,
+ .parent_names = gcc_xo_dsibyte,
+ .num_parents = 2,
+ .ops = clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
+ F(5000, P_GPLL0, 16, 0, 0),
+ F(8000, P_GPLL0, 10, 0, 0),
+ F(1, P_GPLL0, 8, 0, 0),
+ F(16000, P_GPLL0, 5, 0, 0),
+ F(17778, P_GPLL0, 4.5, 0, 0),
+ F(2, P_GPLL0, 4, 0, 0),
+ F(26667, P_GPLL0, 3, 0, 0),
+ F(32000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 mdp_clk_src = {
+ .cmd_rcgr = 0x4d014,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_dsiphy_map,
+ .freq_tbl = ftbl_gcc_mdss_mdp_clk,
+ .clkr.hw.init = (struct clk_init_data){
+ .name = mdp_clk_src,
+ .parent_names = gcc_xo_gpll0_dsiphy,
+ .num_parents = 1,
+ .ops = clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+ { .src = P_DSI0_PHYPLL_DSI },
+ { }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+ .cmd_rcgr = 0x4d084,
This should be 0x4d000. Same reason as above.
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_dsiphy_map,
+ .freq_tbl = ftbl_gcc_mdss_pclk,
+ .clkr.hw.init = (struct clk_init_data){
+ .name = pclk0_clk_src,
+ .parent_names = gcc_xo_gpll0_dsiphy,
+ .num_parents = 1,
+ .ops = clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
+ F(1920, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 vsync_clk_src = {
+ .cmd_rcgr = 0x4d02c,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0a_map,
+ .freq_tbl = ftbl_gcc_mdss_vsync_clk,
+ .clkr.hw.init = (struct clk_init_data){
+ .name = vsync_clk_src,
+ .parent_names = gcc_xo_gpll0a,
+ .num_parents = 2,
+ .ops = clk_rcg2_ops,
+ },
+};
+
mdss clocks look fine otherwise.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line unsubscribe linux-arm-msm in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
