Re: [PATCH 3/3] hwrng: mxc-fsl - add support for Freescale RNGC

[Uwe Kleine-König]

Hello Fabio,

On Mon, Feb 29, 2016 at 08:54:19PM -0300, Fabio Estevam wrote:
> On Mon, Feb 29, 2016 at 6:38 PM, Uwe Kleine-König
>  wrote:
> > On Mon, Feb 29, 2016 at 06:16:50PM -0300, Fabio Estevam wrote:
> >> On Mon, Feb 29, 2016 at 12:52 PM, Steffen Trumtrar
> >>  wrote:
> >>
> >> > +   ret = clk_prepare_enable(rngc->clk);
> >> > +   if (ret)
> >> > +   return ret;
> >> > +
> >> > +   rngc->irq = platform_get_irq(pdev, 0);
> >> > +   if (!rngc->irq) {
> >> > +   dev_err(>dev, "FSL RNGC couldn't get irq\n");
> >> > +   clk_disable_unprepare(rngc->clk);
> >> > +
> >> > +   return ret;
> >>
> >> You are returning the wrong error code here:
> >>
> >> Better do like this:
> >>
> >>rngc->irq = platform_get_irq(pdev, 0);
> >>if (rngc->irq < 0) {
> >
> > rngc->irq is unsigned, so this is never true.
> >
> >>dev_err(>dev, "FSL RNGC couldn't get irq\n");
> >>clk_disable_unprepare(rngc->clk);
> >>return rngc->irq;
> >>}
> >
> > So here comes my better approach:
> 
> As irq is only used inside probe it can be removed from struct mxc_rngc.

Good idea.

> Or maybe like this:
> 
>  ret = platform_get_irq(pdev, 0);
>  if (ret < 0) {
>  dev_err(>dev, "FSL RNGC couldn't get irq\n");
>  clk_disable_unprepare(rngc->clk);
>  return ret;
>  }

Some people think platform_get_irq returning 0 should be handled as
error.

Best regards
Uwe

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Re: crypto regression in 4.1.18: Check that kernel supports aes-cbc-essiv:sha256 cipher

[Greg KH]

On Tue, Mar 01, 2016 at 01:32:05AM +, Eric Wheeler wrote:
> Hello all,
> 
> We updated from 4.1.17 to 4.1.18 (same .config) and now get the following 
> error when trying to open a LUKS volume.  We've reverted to 4.1.17 and it 
> still works, so except that I'm not sure which commit caused the problem, 
> it is likely one of the recent commits:
> 
> When we `cryptsetup luksOpen` the volume we get this:
> 
>   Check that kernel supports aes-cbc-essiv:sha256 cipher (check syslog for 
> more info).  
> 
> Note that I do not see any dm-crypto commits so I don't think its a 
> dm-crypto issue. 
> 
> I'm happy to test, but can someone who knows the crypto stack suggest 
> which of these patches I should focus on for testing? These are the 
> commits in 4.1.18 that could be relevant:

There are some pending crypto backports to resolve this that hopefully
will show up in the next release, whenever Sasha gets to it.

thanks,

greg k-h
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crypto regression in 4.1.18: Check that kernel supports aes-cbc-essiv:sha256 cipher

[Eric Wheeler]

Hello all,

We updated from 4.1.17 to 4.1.18 (same .config) and now get the following 
error when trying to open a LUKS volume.  We've reverted to 4.1.17 and it 
still works, so except that I'm not sure which commit caused the problem, 
it is likely one of the recent commits:

When we `cryptsetup luksOpen` the volume we get this:

  Check that kernel supports aes-cbc-essiv:sha256 cipher (check syslog for more 
info).  

Note that I do not see any dm-crypto commits so I don't think its a 
dm-crypto issue. 

I'm happy to test, but can someone who knows the crypto stack suggest 
which of these patches I should focus on for testing? These are the 
commits in 4.1.18 that could be relevant:


bd92b10 crypto: algif_hash - wait for crypto_ahash_init() to complete
73f876a crypto: shash - Fix has_key setting
a9c56fd crypto: algif_skcipher - sendmsg SG marking is off by one
5d545a7 crypto: crc32c - Fix crc32c soft dependency
3a1e81a crypto: algif_hash - Fix race condition in hash_check_key
8515819 crypto: af_alg - Forbid bind(2) when nokey child sockets are present
279792e crypto: algif_hash - Remove custom release parent function
99214a2 crypto: af_alg - Allow af_af_alg_release_parent to be called on nokey 
path
e1ed9a4 crypto: algif_hash - Require setkey before accept(2)
c409087 crypto: hash - Add crypto_ahash_has_setkey
92d76b5 crypto: af_alg - Add nokey compatibility path
fa988b3 crypto: af_alg - Fix socket double-free when accept fails
0571ba5 crypto: af_alg - Disallow bind/setkey/... after accept(2)

Thank you for your help!

(My CONFIG_CRYPTO options are below, just in case that helps.)

-Eric

# CONFIG_CRYPTO_SKEIN is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_FIPS=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=m
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_MCRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ABLK_HELPER=y
CONFIG_CRYPTO_GLUE_HELPER_X86=y
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32C_INTEL=m
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_CRC32_PCLMUL=m
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_SSSE3=m
CONFIG_CRYPTO_SHA256_SSSE3=m
CONFIG_CRYPTO_SHA512_SSSE3=m
CONFIG_CRYPTO_SHA1_MB=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_X86_64=y
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_BLOWFISH_X86_64=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAMELLIA_X86_64=m
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST5_AVX_X86_64=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_CAST6_AVX_X86_64=m
CONFIG_CRYPTO_DES=m
# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SALSA20_X86_64=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
CONFIG_CRYPTO_TWOFISH_X86_64=m
CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_ZLIB=m
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=m
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
# CONFIG_CRYPTO_USER_API_RNG is not set
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_PADLOCK=m
CONFIG_CRYPTO_DEV_PADLOCK_AES=m
CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
# CONFIG_CRYPTO_DEV_CCP is not set
CONFIG_CRYPTO_DEV_QAT=m
CONFIG_CRYPTO_DEV_QAT_DH895xCC=m



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Re: [PATCH 3/3] hwrng: mxc-fsl - add support for Freescale RNGC

[Uwe Kleine-König]

On Mon, Feb 29, 2016 at 06:16:50PM -0300, Fabio Estevam wrote:
> On Mon, Feb 29, 2016 at 12:52 PM, Steffen Trumtrar
>  wrote:
> 
> > +   ret = clk_prepare_enable(rngc->clk);
> > +   if (ret)
> > +   return ret;
> > +
> > +   rngc->irq = platform_get_irq(pdev, 0);
> > +   if (!rngc->irq) {
> > +   dev_err(>dev, "FSL RNGC couldn't get irq\n");
> > +   clk_disable_unprepare(rngc->clk);
> > +
> > +   return ret;
> 
> You are returning the wrong error code here:
> 
> Better do like this:
> 
>rngc->irq = platform_get_irq(pdev, 0);
>if (rngc->irq < 0) {

rngc->irq is unsigned, so this is never true.

>dev_err(>dev, "FSL RNGC couldn't get irq\n");
>clk_disable_unprepare(rngc->clk);
>return rngc->irq;
>}

So here comes my better approach:

ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
if (ret == 0)
ret = -EINVAL;
dev_err(>dev, "FSL RNGC couldn't get irq\n");
clk_disable_unprepare(rngc->clk);

return ret;
}

rngc->irq = ret;

Best regards
Uwe

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Re: [PATCH 3/3] hwrng: mxc-fsl - add support for Freescale RNGC

[Fabio Estevam]

On Mon, Feb 29, 2016 at 12:52 PM, Steffen Trumtrar
 wrote:

> +   ret = clk_prepare_enable(rngc->clk);
> +   if (ret)
> +   return ret;
> +
> +   rngc->irq = platform_get_irq(pdev, 0);
> +   if (!rngc->irq) {
> +   dev_err(>dev, "FSL RNGC couldn't get irq\n");
> +   clk_disable_unprepare(rngc->clk);
> +
> +   return ret;

You are returning the wrong error code here:

Better do like this:

   rngc->irq = platform_get_irq(pdev, 0);
   if (rngc->irq < 0) {
   dev_err(>dev, "FSL RNGC couldn't get irq\n");
   clk_disable_unprepare(rngc->clk);
   return rngc->irq;
   }
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Re: [PATCH] crypto/async_pq: use __free_page() instead of put_page()

[Dan Williams]

On Mon, Feb 29, 2016 at 1:33 AM, Arnd Bergmann  wrote:
> The addition of tracepoints to the page reference tracking had an
> unfortunate side-effect in at least one driver that calls put_page
> from its exit function, resulting in a link error:
>
> `.exit.text' referenced in section `__jump_table' of crypto/built-in.o: 
> defined in discarded section `.exit.text' of crypto/built-in.o
>
> From a cursory look at that this driver, it seems that it may be
> doing the wrong thing here anyway, as the page gets allocated
> using 'alloc_page()', and should be freed using '__free_page()'
> rather than 'put_page()'.
>
> With this patch, I no longer get any other build errors from the
> page_ref patch, so hopefully we can assume that it's always wrong
> to call any of those functions from __exit code, and that no other
> driver does it.
>
> Fixes: 0f80830dd044 ("mm/page_ref: add tracepoint to track down page 
> reference manipulation")
> Signed-off-by: Arnd Bergmann 

Acked-by: Dan Williams 

Vinod, will you take this one?
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[PATCH 3/3] hwrng: mxc-fsl - add support for Freescale RNGC

[Steffen Trumtrar]

The driver is ported from Freescales Linux git and can be
found in the

vendor/freescale/imx_2.6.35_maintain

branch.

According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
The i.MX2x actually has an RNGB, which has no driver implementation
in Freescales kernel. However as it turns out, the driver for the RNGC
works fine on the (at least) i.MX25. So, they seem to be somewhat
compatible.

Signed-off-by: Steffen Trumtrar 
---
 drivers/char/hw_random/Kconfig|  13 ++
 drivers/char/hw_random/Makefile   |   1 +
 drivers/char/hw_random/mxc-rngc.c | 400 ++
 3 files changed, 414 insertions(+)
 create mode 100644 drivers/char/hw_random/mxc-rngc.c

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index dbf22719462f..9d6b5c42255b 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -255,6 +255,19 @@ config HW_RANDOM_MXC_RNGA
 
  If unsure, say Y.
 
+config HW_RANDOM_MXC_RNGC
+   tristate "Freescale i.MX RNGC Random Number Generator"
+   depends on ARCH_MXC
+   default HW_RANDOM
+   ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on some Freescale i.MX processors.
+
+ To compile this driver as a module, choose M here: the
+ module will be called mxc-rngc.
+
+ If unsure, say Y.
+
 config HW_RANDOM_NOMADIK
tristate "ST-Ericsson Nomadik Random Number Generator support"
depends on ARCH_NOMADIK
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 5ad397635128..008463bcf662 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
 obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
 obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
 obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
+obj-$(CONFIG_HW_RANDOM_MXC_RNGC) += mxc-rngc.o
 obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
 obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
 obj-$(CONFIG_HW_RANDOM_PPC4XX) += ppc4xx-rng.o
diff --git a/drivers/char/hw_random/mxc-rngc.c 
b/drivers/char/hw_random/mxc-rngc.c
new file mode 100644
index ..e31d306dcacd
--- /dev/null
+++ b/drivers/char/hw_random/mxc-rngc.c
@@ -0,0 +1,400 @@
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
+ * (c) Copyright 2003 Red Hat Inc 
+ *
+ * derived from
+ *
+ * Hardware driver for the AMD 768 Random Number Generator (RNG)
+ * (c) Copyright 2001 Red Hat Inc 
+ *
+ * derived from
+ *
+ * Hardware driver for Intel i810 Random Number Generator (RNG)
+ * Copyright 2000,2001 Jeff Garzik 
+ * Copyright 2000,2001 Philipp Rumpf 
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RNGC_VERSION_MAJOR3 3
+
+#define RNGC_VERSION_ID0x
+#define RNGC_COMMAND   0x0004
+#define RNGC_CONTROL   0x0008
+#define RNGC_STATUS0x000C
+#define RNGC_ERROR 0x0010
+#define RNGC_FIFO  0x0014
+#define RNGC_VERIF_CTRL0x0020
+#define RNGC_OSC_CTRL_COUNT0x0028
+#define RNGC_OSC_COUNT 0x002C
+#define RNGC_OSC_COUNT_STATUS  0x0030
+
+#define RNGC_VERID_ZEROS_MASK  0x0f00
+#define RNGC_VERID_RNG_TYPE_MASK   0xf000
+#define RNGC_VERID_RNG_TYPE_SHIFT  28
+#define RNGC_VERID_CHIP_VERSION_MASK   0x00ff
+#define RNGC_VERID_CHIP_VERSION_SHIFT  16
+#define RNGC_VERID_VERSION_MAJOR_MASK  0xff00
+#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
+#define RNGC_VERID_VERSION_MINOR_MASK  0x00ff
+#define RNGC_VERID_VERSION_MINOR_SHIFT 0
+
+#define RNGC_CMD_ZEROS_MASK0xff8c
+#define RNGC_CMD_SW_RST0x0040
+#define RNGC_CMD_CLR_ERR   0x0020
+#define RNGC_CMD_CLR_INT   0x0010
+#define RNGC_CMD_SEED  

[PATCH 1/3] Documentation: devicetree: add Freescale RNGC binding

[Steffen Trumtrar]

Add binding documentation for the Freescale RNGC found on
some i.MX2/3/5 SoCs.

Signed-off-by: Steffen Trumtrar 
---
 Documentation/devicetree/bindings/rng/mxc_rngc.txt | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rng/mxc_rngc.txt

diff --git a/Documentation/devicetree/bindings/rng/mxc_rngc.txt 
b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
new file mode 100644
index ..e147a6dde40a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
@@ -0,0 +1,16 @@
+Freescale RNGC (Random Number Generator Version C)
+
+Required properties:
+- compatible : Should be "fsl,imx25-rng"
+- reg : Offset and length of the register set of this block
+- interrupts : the interrupt number for the RNG block
+- clocks: should contain the RNG clk source
+
+Example:
+
+rng@53fb {
+   compatible = "fsl,imx25-rng";
+   reg = <0x53fb 0x4000>;
+   interrupts = <22>;
+   clocks = < 109>;
+};
-- 
2.7.0

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[PATCH 2/3] ARM: i.MX25: add RNGC node to dtsi

[Steffen Trumtrar]

Add a devicetree entry for the Random Number Generator Version C (RNGC).

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/boot/dts/imx25.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index cde329e9b9e3..ec44ed125057 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -397,6 +397,15 @@
interrupts = <41>;
};
 
+   rng: rng@53fb {
+   compatible = "fsl,imx25-rng";
+   reg = <0x53fb 0x4000>;
+   clocks = < 109>;
+   clock-names = "ipg";
+   interrupts = <22>;
+   interrupt-names = "rng";
+   };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
-- 
2.7.0

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Re: [PATCH] PKCS#7: fix unitialized boolean 'want'

[David Howells]

Colin King  wrote:

> The boolean want is not initialized and hence garbage. The default should
> be false (later it is only set to true on tne sinfo->authattrs check).
> 
> Found with static analysis using CoverityScan
> 
> Signed-off-by: Colin Ian King 

Applied.
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[PATCH v2 3/3] crypto: add basic driver for the MXC SCC

[Steffen Trumtrar]

According to the Freescale GPL driver code, there are two different
Security Controller (SCC) versions: SCC and SCC2.

The SCC is found on older i.MX SoCs, e.g. the i.MX25. This is the
version implemented and tested here.

As there is no publicly available documentation for this IP core,
all information about this unit is gathered from the GPL'ed driver
from Freescale.

Signed-off-by: Steffen Trumtrar 
---
Changes since v1:
  - minor code cleanups (double newlines, unnecessary parentesis, ...)
  - mxc_scc_ablkcipher_next: complete request with error before
mutex_unlock

 drivers/crypto/Kconfig   |   9 +
 drivers/crypto/Makefile  |   1 +
 drivers/crypto/mxc-scc.c | 746 +++
 3 files changed, 756 insertions(+)
 create mode 100644 drivers/crypto/mxc-scc.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 07d494276aad..ece3e231ee4d 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -339,6 +339,15 @@ config CRYPTO_DEV_SAHARA
  This option enables support for the SAHARA HW crypto accelerator
  found in some Freescale i.MX chips.
 
+config CRYPTO_DEV_MXC_SCC
+   tristate "Support for Freescale Security Controller (SCC)"
+   depends on ARCH_MXC && OF
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_DES
+   help
+ This option enables support for the Security Controller (SCC)
+ found in Freescale i.MX25 chips.
+
 config CRYPTO_DEV_S5P
tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
depends on ARCH_S5PV210 || ARCH_EXYNOS
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 713de9d11148..3c6432dd09d9 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
 obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
 obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
+obj-$(CONFIG_CRYPTO_DEV_MXC_SCC) += mxc-scc.o
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
 obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
diff --git a/drivers/crypto/mxc-scc.c b/drivers/crypto/mxc-scc.c
new file mode 100644
index ..8f27f8720413
--- /dev/null
+++ b/drivers/crypto/mxc-scc.c
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2016 Pengutronix, Steffen Trumtrar 
+ *
+ * The driver is based on information gathered from
+ * drivers/mxc/security/mxc_scc.c which can be found in
+ * the Freescale linux-2.6-imx.git in the imx_2.6.35_maintain branch.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/* Secure Memory (SCM) registers */
+#define SCC_SCM_RED_START  0x
+#define SCC_SCM_BLACK_START0x0004
+#define SCC_SCM_LENGTH 0x0008
+#define SCC_SCM_CTRL   0x000C
+#define SCC_SCM_STATUS 0x0010
+#define SCC_SCM_ERROR_STATUS   0x0014
+#define SCC_SCM_INTR_CTRL  0x0018
+#define SCC_SCM_CFG0x001C
+#define SCC_SCM_INIT_VECTOR_0  0x0020
+#define SCC_SCM_INIT_VECTOR_1  0x0024
+#define SCC_SCM_RED_MEMORY 0x0400
+#define SCC_SCM_BLACK_MEMORY   0x0800
+
+/* Security Monitor (SMN) Registers */
+#define SCC_SMN_STATUS 0x1000
+#define SCC_SMN_COMMAND0x1004
+#define SCC_SMN_SEQ_START  0x1008
+#define SCC_SMN_SEQ_END0x100C
+#define SCC_SMN_SEQ_CHECK  0x1010
+#define SCC_SMN_BIT_COUNT  0x1014
+#define SCC_SMN_BITBANK_INC_SIZE   0x1018
+#define SCC_SMN_BITBANK_DECREMENT  0x101C
+#define SCC_SMN_COMPARE_SIZE   0x1020
+#define SCC_SMN_PLAINTEXT_CHECK0x1024
+#define SCC_SMN_CIPHERTEXT_CHECK   0x1028
+#define SCC_SMN_TIMER_IV   0x102C
+#define SCC_SMN_TIMER_CONTROL  0x1030
+#define SCC_SMN_DEBUG_DETECT_STAT  0x1034
+#define SCC_SMN_TIMER  0x1038
+
+#define SCC_SCM_CTRL_START_CIPHER  BIT(2)
+#define SCC_SCM_CTRL_CBC_MODE  BIT(1)
+#define SCC_SCM_CTRL_DECRYPT_MODE  BIT(0)
+
+#define SCC_SCM_STATUS_LEN_ERR BIT(12)
+#define SCC_SCM_STATUS_SMN_UNBLOCKED   BIT(11)
+#define SCC_SCM_STATUS_CIPHERING_DONE  BIT(10)
+#define SCC_SCM_STATUS_ZEROIZING_DONE  BIT(9)
+#define SCC_SCM_STATUS_INTR_STATUS BIT(8)
+#define SCC_SCM_STATUS_SEC_KEY BIT(7)

[PATCH v2 2/3] ARM: i.MX25: add scc module to dtsi

[Steffen Trumtrar]

Add the Security Controller (SCC) module to the dtsi.

Signed-off-by: Steffen Trumtrar 
---
 arch/arm/boot/dts/imx25.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index cde329e9b9e3..73118aba4cc4 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -397,6 +397,15 @@
interrupts = <41>;
};
 
+   scc: crypto@53fac000 {
+   compatible = "fsl,imx25-scc";
+   reg = <0x53fac000 0x4000>;
+   clocks = < 111>;
+   clock-names = "ipg";
+   interrupts = <49>, <50>;
+   interrupt-names = "scm", "smn";
+   };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
-- 
2.7.0

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[PATCH v2 1/3] Documentation: devicetree: add Freescale SCC bindings

[Steffen Trumtrar]

Add documentation for the Freescale Security Controller (SCC)
found on i.MX25 SoCs.

Signed-off-by: Steffen Trumtrar 
Acked-by: Rob Herring 
---
Changes since v1:
  - add clocks to required properties
  - add Acked-by

 .../devicetree/bindings/crypto/fsl-imx-scc.txt  | 21 +
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt

diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt 
b/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt
new file mode 100644
index ..7aad448e8a36
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt
@@ -0,0 +1,21 @@
+Freescale Security Controller (SCC)
+
+Required properties:
+- compatible : Should be "fsl,imx25-scc".
+- reg : Should contain register location and length.
+- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
+- interrupt-names : Should specify the names "scm" and "smn" for the
+   SCM IRQ and SMN IRQ.
+- clocks: Should contain the clock driving the SCC core.
+- clock-names: Should be set to "ipg".
+
+Example:
+
+   scc: crypto@53fac000 {
+   compatible = "fsl,imx25-scc";
+   reg = <0x53fac000 0x4000>;
+   clocks = < 111>;
+   clock-names = "ipg";
+   interrupts = <49>, <50>;
+   interrupt-names = "scm", "smn";
+   };
-- 
2.7.0

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[PATCH] crypto/async_pq: use __free_page() instead of put_page()

[Arnd Bergmann]

The addition of tracepoints to the page reference tracking had an
unfortunate side-effect in at least one driver that calls put_page
from its exit function, resulting in a link error:

`.exit.text' referenced in section `__jump_table' of crypto/built-in.o: defined 
in discarded section `.exit.text' of crypto/built-in.o

>From a cursory look at that this driver, it seems that it may be
doing the wrong thing here anyway, as the page gets allocated
using 'alloc_page()', and should be freed using '__free_page()'
rather than 'put_page()'.

With this patch, I no longer get any other build errors from the
page_ref patch, so hopefully we can assume that it's always wrong
to call any of those functions from __exit code, and that no other
driver does it.

Fixes: 0f80830dd044 ("mm/page_ref: add tracepoint to track down page reference 
manipulation")
Signed-off-by: Arnd Bergmann 
---
 crypto/async_tx/async_pq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crypto/async_tx/async_pq.c b/crypto/async_tx/async_pq.c
index c0748bbd4c08..08b3ac68952b 100644
--- a/crypto/async_tx/async_pq.c
+++ b/crypto/async_tx/async_pq.c
@@ -444,7 +444,7 @@ static int __init async_pq_init(void)
 
 static void __exit async_pq_exit(void)
 {
-   put_page(pq_scribble_page);
+   __free_page(pq_scribble_page);
 }
 
 module_init(async_pq_init);
-- 
2.7.0

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Re: [PATCH] [RFC] mm/page_ref, crypto/async_pq: don't put_page from __exit

[Arnd Bergmann]

On Monday 29 February 2016 16:40:02 Joonsoo Kim wrote:
> 
> Hello, Arnd.
> 
> I think that we can avoid this error by using __free_page().
> It would not be inlined so calling it would have no problem.
> 
> Could you test it, please?

Yes, I suspect the driver should have done that anyway, new patch
under way.

Arnd
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Re: [PATCH 0/3] KEYS: Use crypto rsa pkcs1pad module for software public keys

[David Howells]

Herbert Xu  wrote:

> David Howells  wrote:
> > 
> > Here's a set of patches that change the software public key asymmetric key
> > subtype to use the RSA pkcs1pad module in the crypto layer.  I've merged
> > together mine and Tadeusz's patches.
> > 
> > I have not included Tadeusz's original three patches that converted to
> > using the raw rsa module in this set, but they're prerequisites for this.
> 
> Looks OK to me.  Where do you want these patches to go?

Can I turn that into an Reviewed-by?  I'll take them through my tree and
James's tree.

David
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