[PATCH] crypto: x86/aes - Don't use %rbp as temporary register

[Eric Biggers]

From: Eric Biggers 

When using the "aes-asm" implementation of AES (*not* the AES-NI
implementation) on an x86_64, v4.12-rc1 kernel with lockdep enabled, the
following warning was reported, along with a long unwinder dump:

WARNING: kernel stack regs at c9643558 in kworker/u4:2:155 has 
bad 'bp' value 001c

The problem is that aes_enc_block() and aes_dec_block() use %rbp as a
temporary register, which breaks stack traces if an interrupt occurs.

Fix this by replacing %rbp with %r9, which was being used to hold the
saved value of %rbp.  This required rearranging the AES round macro
slightly since %r9d cannot be used as the target of a move from %ah-%dh.

Performance is essentially unchanged --- actually about 0.2% faster than
before.  Interestingly, I also measured aes-generic as being nearly 7%
faster than aes-asm, so perhaps aes-asm has outlived its usefulness...

Signed-off-by: Eric Biggers 
---
 arch/x86/crypto/aes-x86_64-asm_64.S | 47 +
 1 file changed, 22 insertions(+), 25 deletions(-)

diff --git a/arch/x86/crypto/aes-x86_64-asm_64.S 
b/arch/x86/crypto/aes-x86_64-asm_64.S
index 910565547163..8739cf7795de 100644
--- a/arch/x86/crypto/aes-x86_64-asm_64.S
+++ b/arch/x86/crypto/aes-x86_64-asm_64.S
@@ -42,17 +42,15 @@
 #define R5E%esi
 #define R6 %rdi
 #define R6E%edi
-#define R7 %rbp
-#define R7E%ebp
+#define R7 %r9 /* don't use %rbp; it breaks stack traces */
+#define R7E%r9d
 #define R8 %r8
-#define R9 %r9
 #define R10%r10
 #define R11%r11
 
-#define prologue(FUNC,KEY,B128,B192,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11) \
+#define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
ENTRY(FUNC);\
movqr1,r2;  \
-   movqr3,r4;  \
leaqKEY+48(r8),r9;  \
movqr10,r11;\
movl(r7),r5 ## E;   \
@@ -70,9 +68,8 @@
je  B192;   \
leaq32(r9),r9;
 
-#define epilogue(FUNC,r1,r2,r3,r4,r5,r6,r7,r8,r9) \
+#define epilogue(FUNC,r1,r2,r5,r6,r7,r8,r9) \
movqr1,r2;  \
-   movqr3,r4;  \
movlr5 ## E,(r9);   \
movlr6 ## E,4(r9);  \
movlr7 ## E,8(r9);  \
@@ -88,12 +85,12 @@
movlTAB(,r6,4),r6 ## E; \
roll$16,r2 ## E;\
shrl$16,r4 ## E;\
-   movzbl  r4 ## H,r7 ## E;\
-   movzbl  r4 ## L,r4 ## E;\
+   movzbl  r4 ## L,r7 ## E;\
+   movzbl  r4 ## H,r4 ## E;\
xorlOFFSET(r8),ra ## E; \
xorlOFFSET+4(r8),rb ## E;   \
-   xorlTAB+3072(,r7,4),r5 ## E;\
-   xorlTAB+2048(,r4,4),r6 ## E;\
+   xorlTAB+3072(,r4,4),r5 ## E;\
+   xorlTAB+2048(,r7,4),r6 ## E;\
movzbl  r1 ## L,r7 ## E;\
movzbl  r1 ## H,r4 ## E;\
movlTAB+1024(,r4,4),r4 ## E;\
@@ -101,19 +98,19 @@
roll$16,r1 ## E;\
shrl$16,r3 ## E;\
xorlTAB(,r7,4),r5 ## E; \
-   movzbl  r3 ## H,r7 ## E;\
-   movzbl  r3 ## L,r3 ## E;\
-   xorlTAB+3072(,r7,4),r4 ## E;\
-   xorlTAB+2048(,r3,4),r5 ## E;\
-   movzbl  r1 ## H,r7 ## E;\
-   movzbl  r1 ## L,r3 ## E;\
+   movzbl  r3 ## L,r7 ## E;\
+   movzbl  r3 ## H,r3 ## E;\
+   xorlTAB+3072(,r3,4),r4 ## E;\
+   xorlTAB+2048(,r7,4),r5 ## E;\
+   movzbl  r1 ## L,r7 ## E;\
+   movzbl  r1 ## H,r3 ## E;\
shrl$16,r1 ## E;\
-   xorlTAB+3072(,r7,4),r6 ## E;\
-   movlTAB+2048(,r3,4),r3 ## E;\
-   movzbl  r1 ## H,r7 ## E;\
-   movzbl  r1 ## L,r1 ## E;\
-   xorlTAB+1024(,r7,4),r6 ## E;\
-   xorlTAB(,r1,4),r3 ## E; \
+   xorlTAB+3072(,r3,4),r6 ## E;\
+   movlTAB+2048(,r7,4),r3 ## E;\
+   movzbl  r1 ## L,r7 ## E;\
+   movzbl  r1 ## H,r1 ## E;\
+   xorlTAB+1024(,r1,4),r6 ## E;\
+   xorlTAB(,r7,4),r3 ## E; \
movzbl  r2 ## H,r1 ## E;\
movzbl  r2 ## L,r7 ## E;\
shrl$16,r2 ## E;\
@@ -131,9 +128,9 @@
movlr4 ## E,r2 ## E;
 
 #define entry(FUNC,KEY,B128,B192) \
-   prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
+   prologue(FUNC,KEY,B128,B192,R2,R8,R1,R3,R4,R6,R10,R5,R11)
 
-#define return(FUNC) epilogue(FUNC,R8,R2,R9,R7,R5,R6,R3,R4,R11)
+#define return(FUNC) epilogue(FUNC,R8,R2,R5,R6,R3,R4,R11)
 
 #define encrypt_round(TAB,OFFSET) \
round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
-- 
2.13.0

Re: [PATCH 4/4] crypto: Documentation: fix none signal safe sample

[Eric Biggers]

On Thu, May 11, 2017 at 02:53:45PM +0300, Gilad Ben-Yossef wrote:
> The sample code was showing use of wait_for_completion_interruptible()
> for waiting for an async. crypto op to finish. However, if a signal
> arrived it would free the buffers used even while crypto HW might
> still DMA from/into the buffers.
> 
> Resolve this by using wait_for_completion() instead.
> 
> Reported-by: Eric Biggers 
> Signed-off-by: Gilad Ben-Yossef 
> ---
>  Documentation/crypto/api-samples.rst | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/crypto/api-samples.rst 
> b/Documentation/crypto/api-samples.rst
> index d021fd9..944f08b 100644
> --- a/Documentation/crypto/api-samples.rst
> +++ b/Documentation/crypto/api-samples.rst
> @@ -48,7 +48,7 @@ Code Example For Symmetric Key Cipher Operation
>  break;
>  case -EINPROGRESS:
>  case -EBUSY:
> -rc = wait_for_completion_interruptible(
> +rc = wait_for_completion(
>  >result.completion);
>  if (!rc && !sk->result.err) {
>  reinit_completion(>result.completion);
> -- 
> 2.1.4
> 

Same issue here: wait_for_completion() doesn't return a value.

Eric

Re: [PATCH 2/4] crypto: drbg wait for crypto op not signal safe

[Eric Biggers]

Hi Gilad,

On Thu, May 11, 2017 at 02:53:43PM +0300, Gilad Ben-Yossef wrote:
> drbg_kcapi_sym_ctr() was using wait_for_completion_interruptible() to
> wait for completion of async crypto op but if a signal occurs it
> may return before DMA ops of HW crypto provider finish, thus
> corrupting the output buffer.
> 
> Resolve this by using wait_for_completion() instead.
> 
> Reported-by: Eric Biggers 
> Signed-off-by: Gilad Ben-Yossef 
> CC: sta...@vger.kernel.org
> ---
>  crypto/drbg.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/crypto/drbg.c b/crypto/drbg.c
> index fa749f4..fa9054d 100644
> --- a/crypto/drbg.c
> +++ b/crypto/drbg.c
> @@ -1767,8 +1767,7 @@ static int drbg_kcapi_sym_ctr(struct drbg_state *drbg,
>   break;
>   case -EINPROGRESS:
>   case -EBUSY:
> - ret = wait_for_completion_interruptible(
> - >ctr_completion);
> + ret = wait_for_completion(>ctr_completion);
>   if (!ret && !drbg->ctr_async_err) {
>   reinit_completion(>ctr_completion);
>   break;
> -- 

wait_for_completion() doesn't return a value.  This was fixed in the next patch,
but it should be done in this patch.

Eric

[PATCH] crypto: stm32 - Add CRC32 support for STM32F4XX

[Cosar Dindar]

This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F4XX series devices.

As an hardware limitation polynomial and key setting are not supported
as they are fixed as 0x4C11DB7 (poly) and 0x (key).

CRC32C Castagnoli algorithm is not supported also.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.

Signed-off-by: Cosar Dindar 
---
 .../devicetree/bindings/crypto/st,stm32-crc.txt|  4 +-
 arch/arm/boot/dts/stm32429i-eval.dts   |  4 ++
 arch/arm/boot/dts/stm32f429-disco.dts  |  4 ++
 arch/arm/boot/dts/stm32f429.dtsi   |  7 +++
 arch/arm/boot/dts/stm32f469-disco.dts  |  4 ++
 drivers/crypto/stm32/stm32_crc32.c | 68 ++
 6 files changed, 79 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
index 3ba92a5..7b30f1e 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -1,7 +1,7 @@
 * STMicroelectronics STM32 CRC
 
 Required properties:
-- compatible: Should be "st,stm32f7-crc".
+- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
 - reg: The address and length of the peripheral registers space
 - clocks: The input clock of the CRC instance
 
@@ -10,7 +10,7 @@ Optional properties: none
 Example:
 
 crc: crc@40023000 {
-   compatible = "st,stm32f7-crc";
+   compatible = "st,stm32f7-crc", "st,stm32f4-crc";
reg = <0x40023000 0x400>;
clocks = < 0 12>;
 };
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index b633114..360fb19 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -141,6 +141,10 @@
clock-frequency = <2500>;
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index 191fa50..ae47cde 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -102,6 +102,10 @@
clock-frequency = <800>;
 };
 
+ {
+   status = "okay";
+};
+
  {
assigned-clocks = < 1 CLK_RTC>;
assigned-clock-parents = < 1 CLK_LSI>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..18343de 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -766,6 +766,13 @@
};
};
 
+   crc: crc@40023000 {
+   compatible = "st,stm32f4-crc";
+   reg = <0x40023000 0x400>;
+   clocks = < 0 STM32F4_AHB1_CLOCK(CRC)>;
+   status = "disabled";
+   };
+
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts 
b/arch/arm/boot/dts/stm32f469-disco.dts
index 75470c3..8cb8b73 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -87,6 +87,10 @@
clock-frequency = <800>;
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk   *clk;
u8   pending_data[sizeof(u32)];
size_t   nb_pending_bytes;
+   bool key_support;
+   bool poly_support;
+   bool reverse_support;
 };
 
 struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
 
-   /* Reset, set key, poly and configure in bit reverse mode */
-   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
-   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
-   writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+   /* set key */
+   if (ctx->crc->key_support) {
+   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+   } else if (mctx->key != CRC_INIT_DEFAULT) {
+   dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
0x%x\n",
+   CRC_INIT_DEFAULT);
+   return -EINVAL;
+   }
+
+   /* set poly */
+   if (ctx->crc->poly_support)
+   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+   /* reset and configure in bit 

[PATCH] crypto: qat: use pcie_flr instead of duplicating it

[Christoph Hellwig]

Signed-off-by: Christoph Hellwig 
---
 drivers/crypto/qat/qat_common/adf_aer.c | 15 +--
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/crypto/qat/qat_common/adf_aer.c 
b/drivers/crypto/qat/qat_common/adf_aer.c
index 2839fccdd84b..d3e25c37dc33 100644
--- a/drivers/crypto/qat/qat_common/adf_aer.c
+++ b/drivers/crypto/qat/qat_common/adf_aer.c
@@ -109,20 +109,7 @@ EXPORT_SYMBOL_GPL(adf_reset_sbr);
 
 void adf_reset_flr(struct adf_accel_dev *accel_dev)
 {
-   struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
-   u16 control = 0;
-   int pos = 0;
-
-   dev_info(_DEV(accel_dev), "Function level reset\n");
-   pos = pci_pcie_cap(pdev);
-   if (!pos) {
-   dev_err(_DEV(accel_dev), "Restart device failed\n");
-   return;
-   }
-   pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, );
-   control |= PCI_EXP_DEVCTL_BCR_FLR;
-   pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, control);
-   msleep(100);
+   pcie_flr(accel_to_pci_dev(accel_dev));
 }
 EXPORT_SYMBOL_GPL(adf_reset_flr);
 
-- 
2.11.0

[PATCH v2 13/53] docs-rst: add crypto API book to pdf output

[Mauro Carvalho Chehab]

The crypto API book was added without the bits required to
generate PDF output. Add them.

Signed-off-by: Mauro Carvalho Chehab 
---
 Documentation/conf.py|  2 ++
 Documentation/crypto/conf.py | 10 ++
 2 files changed, 12 insertions(+)
 create mode 100644 Documentation/crypto/conf.py

diff --git a/Documentation/conf.py b/Documentation/conf.py
index 15f34d6863a7..ce62723491d4 100644
--- a/Documentation/conf.py
+++ b/Documentation/conf.py
@@ -351,6 +351,8 @@ latex_documents = [
  'The kernel development community', 'manual'),
 ('core-api/index', 'core-api.tex', 'The kernel core API manual',
  'The kernel development community', 'manual'),
+('crypto/index', 'crypto-api.tex', 'Linux Kernel Crypto API manual',
+ 'The kernel development community', 'manual'),
 ('doc-guide/index', 'kernel-doc-guide.tex', 'Linux Kernel Documentation 
Guide',
  'The kernel development community', 'manual'),
 ('driver-api/index', 'driver-api.tex', 'The kernel driver API manual',
diff --git a/Documentation/crypto/conf.py b/Documentation/crypto/conf.py
new file mode 100644
index ..4335d251ddf3
--- /dev/null
+++ b/Documentation/crypto/conf.py
@@ -0,0 +1,10 @@
+# -*- coding: utf-8; mode: python -*-
+
+project = 'Linux Kernel Crypto API'
+
+tags.add("subproject")
+
+latex_documents = [
+('index', 'crypto-api.tex', 'Linux Kernel Crypto API manual',
+ 'The kernel development community', 'manual'),
+]
-- 
2.9.3

[PATCH] drivers/staging/ccree: Replacing spaces by tab

[Pushkar Jambhlekar]

Fixing 'checkpatch.pl' ERROR: code indent should use tabs where possible

Signed-off-by: Pushkar Jambhlekar 
---
 drivers/staging/ccree/ssi_aead.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 0941da7..26afa87 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -96,7 +96,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
SSI_LOG_DEBUG("Clearing context @%p for %s\n",
crypto_aead_ctx(tfm), crypto_tfm_alg_name(&(tfm->base)));
 
-   dev = >drvdata->plat_dev->dev;
+   dev = >drvdata->plat_dev->dev;
/* Unmap enckey buffer */
if (ctx->enckey != NULL) {
SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->enckey_dma_addr);
@@ -2334,22 +2334,22 @@ static int ssi_gcm_setauthsize(struct crypto_aead 
*authenc,
 static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc,
  unsigned int authsize)
 {
-SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize()  authsize %d \n", 
authsize );
-
-switch (authsize) {
-case 8:
-case 12:
-case 16:
-break;
-default:
-return -EINVAL;
-}
-
-return ssi_aead_setauthsize(authenc, authsize);
+   SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize()  authsize %d \n", authsize 
);
+
+   switch (authsize) {
+   case 8:
+   case 12:
+   case 16:
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return ssi_aead_setauthsize(authenc, authsize);
 }
 
 static int ssi_rfc4543_gcm_setauthsize(struct crypto_aead *authenc,
- unsigned int authsize)
+  unsigned int authsize)
 {
SSI_LOG_DEBUG("ssi_rfc4543_gcm_setauthsize()  authsize %d \n", authsize 
);
 
@@ -2364,7 +2364,7 @@ static int ssi_rfc4106_gcm_encrypt(struct aead_request 
*req)
/* Very similar to ssi_aead_encrypt() above. */
 
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
-int rc = -EINVAL;
+   int rc = -EINVAL;
 
if (!valid_assoclen(req)) {
SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen);
@@ -2416,7 +2416,7 @@ static int ssi_rfc4106_gcm_decrypt(struct aead_request 
*req)
/* Very similar to ssi_aead_decrypt() above. */
 
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
-int rc = -EINVAL;
+   int rc = -EINVAL;
 
if (!valid_assoclen(req)) {
SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen);
-- 
2.7.4

[PATCH v1] crypto: img-hash - Handle return value of clk_prepare_enable

[Arvind Yadav]

Here, Clock enable can failed. So adding an error check for
clk_prepare_enable.

Signed-off-by: Arvind Yadav 
---
 drivers/crypto/img-hash.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/img-hash.c b/drivers/crypto/img-hash.c
index 9b07f3d8..0c6a917 100644
--- a/drivers/crypto/img-hash.c
+++ b/drivers/crypto/img-hash.c
@@ -1088,9 +1088,17 @@ static int img_hash_suspend(struct device *dev)
 static int img_hash_resume(struct device *dev)
 {
struct img_hash_dev *hdev = dev_get_drvdata(dev);
+   int ret;
 
-   clk_prepare_enable(hdev->hash_clk);
-   clk_prepare_enable(hdev->sys_clk);
+   ret = clk_prepare_enable(hdev->hash_clk);
+   if (ret)
+   return ret;
+
+   ret = clk_prepare_enable(hdev->sys_clk);
+   if (ret) {
+   clk_disable_unprepare(hdev->hash_clk);
+   return ret;
+   }
 
return 0;
 }
-- 
1.9.1

Re: [PATCH] drivers/staging/ccree: Fixing coding guideline errors

[Greg Kroah-Hartman]

On Tue, May 16, 2017 at 01:35:52PM +0530, Pushkar Jambhlekar wrote:
> Fixing coding guideline errors reported by 'checkpatch.pl'

That is very "vague", you are going to have to be specific here.

Also remember you can only do "one type of thing" per patch, and no,
"fix all warnings" is not one type of thing :)

thanks,

greg k-h

[PATCH] drivers/staging/ccree: Fixing coding guideline errors

[Pushkar Jambhlekar]

Fixing coding guideline errors reported by 'checkpatch.pl'

Signed-off-by: Pushkar Jambhlekar 
---
 drivers/staging/ccree/ssi_cipher.c | 158 +++--
 1 file changed, 80 insertions(+), 78 deletions(-)

diff --git a/drivers/staging/ccree/ssi_cipher.c 
b/drivers/staging/ccree/ssi_cipher.c
index d245a2b..6eb0f0b 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -68,11 +68,11 @@ struct ssi_ablkcipher_ctx {
 
 static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void 
__iomem *cc_base);
 
-
-static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) {
-   switch (ctx_p->flow_mode){
+static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size)
+{
+   switch (ctx_p->flow_mode) {
case S_DIN_to_AES:
-   switch (size){
+   switch (size) {
case CC_AES_128_BIT_KEY_SIZE:
case CC_AES_192_BIT_KEY_SIZE:
if (likely((ctx_p->cipher_mode != DRV_CIPHER_XTS) &&
@@ -110,11 +110,11 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx 
*ctx_p, u32 size) {
return -EINVAL;
 }
 
-
-static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int 
size) {
-   switch (ctx_p->flow_mode){
+static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int 
size)
+{
+   switch (ctx_p->flow_mode) {
case S_DIN_to_AES:
-   switch (ctx_p->cipher_mode){
+   switch (ctx_p->cipher_mode) {
case DRV_CIPHER_XTS:
if ((size >= SSI_MIN_AES_XTS_SIZE) &&
(size <= SSI_MAX_AES_XTS_SIZE) &&
@@ -260,46 +260,46 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
 }
 
 
-typedef struct tdes_keys{
-u8  key1[DES_KEY_SIZE];
-u8  key2[DES_KEY_SIZE];
-u8  key3[DES_KEY_SIZE];
-}tdes_keys_t;
+typedef struct tdes_keys {
+   u8  key1[DES_KEY_SIZE];
+   u8  key2[DES_KEY_SIZE];
+   u8  key3[DES_KEY_SIZE];
+} tdes_keys_t;
 
 static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
 
 /* The function verifies that tdes keys are not weak.*/
 static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
 {
 #ifdef CCREE_FIPS_SUPPORT
-tdes_keys_t *tdes_key = (tdes_keys_t*)key;
+   tdes_keys_t *tdes_key = (tdes_keys_t *)key;
 
/* verify key1 != key2 and key3 != key2*/
-if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, 
sizeof(tdes_key->key1)) == 0) ||
- (memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, 
sizeof(tdes_key->key3)) == 0) )) {
-return -ENOEXEC;
-}
+   if (unlikely((memcmp((u8 *)tdes_key->key1, (u8 *)tdes_key->key2, 
sizeof(tdes_key->key1)) == 0) ||
+ (memcmp((u8 *)tdes_key->key3, (u8 *)tdes_key->key2, 
sizeof(tdes_key->key3)) == 0))) {
+   return -ENOEXEC;
+   }
 #endif /* CCREE_FIPS_SUPPORT */
 
-return 0;
+   return 0;
 }
 
 /* The function verifies that xts keys are not weak.*/
 static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
 {
 #ifdef CCREE_FIPS_SUPPORT
-/* Weak key is define as key that its first half (128/256 lsb) equals 
its second half (128/256 msb) */
-int singleKeySize = keylen >> 1;
+   /* Weak key is define as key that its first half (128/256 lsb) equals 
its second half (128/256 msb) */
+   int singleKeySize = keylen >> 1;
 
if (unlikely(memcmp(key, [singleKeySize], singleKeySize) == 0)) {
return -ENOEXEC;
}
 #endif /* CCREE_FIPS_SUPPORT */
 
-return 0;
+   return 0;
 }
 
 static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
@@ -325,6 +325,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
struct device *dev = _p->drvdata->plat_dev->dev;
u32 tmp[DES_EXPKEY_WORDS];
unsigned int max_key_buf_size = get_max_keysize(tfm);
+
DECL_CYCLE_COUNT_RESOURCES;
 
SSI_LOG_DEBUG("Setting key in context @%p for %s. keylen=%u\n",
@@ -341,11 +342,11 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
 #if SSI_CC_HAS_MULTI2
/*last byte of key buffer is round number and should not be a part of 
key size*/
if (ctx_p->flow_mode == S_DIN_to_MULTI2) {
-   keylen -=1;
+   keylen -= 1;
}
 #endif /*SSI_CC_HAS_MULTI2*/
 
-   if