Re: [PATCH v2 2/2] chcr: Add support for Inline IPSec

[David Miller]

From: Atul Gupta 
Date: Thu,  9 Nov 2017 16:59:01 +0530

> register xfrmdev_ops callbacks, Send IPsec tunneled data
> to HW for inline processing.
> The driver use hardware crypto accelerator to encrypt and
> generate ICV for the transmitted packet in Inline mode.
> 
> Signed-off-by: Atul Gupta 
> Signed-off-by: Harsh Jain 
> Signed-off-by: Ganesh Goudar 
> ---
> V2: Fixed the build warnings and created patch against cryptodev
> to avoid possible merge conflicts

Herbert, feel free to merge these two patches via your crypto
tree.

Thanks!

Re: [PATCH 00/24] staging: ccree: more cleanup patches

[Dan Carpenter]

These cleanups look nice.  Thanks.

I hope you do a mass remove of likely/unlikely in a patch soon.
Whenever, I see one of those in a + line I always have to remind myself
that you're planning to do it in a later patch.

regards,
dan carpenter

Re: [PATCH 1/2] crypto: tcrypt - fix S/G table for test_aead_speed()

[Tudor Ambarus]

Hi,

On 11/12/2017 06:26 PM, Horia Geantă wrote:


-sg[0] - (1 entry) reserved for associated data, filled outside
sg_init_aead()


Let's fill the sg[0] with aad inside sg_init_aead()!

Cheers,
ta

Re: [PATCH 1/2] crypto: tcrypt - fix S/G table for test_aead_speed()

[Tudor Ambarus]

Hi,

On 10/10/2017 01:21 PM, Robert Baronescu wrote:

In case buffer length is a multiple of PAGE_SIZE,
the S/G table is incorrectly generated.
Fix this by handling buflen = k * PAGE_SIZE separately.

Signed-off-by: Robert Baronescu 
---
  crypto/tcrypt.c | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)


This patch fixes the segmentation fault listed below. The NULL
dereference can be seen starting with:
7aacbfc crypto: tcrypt - fix buffer lengths in test_aead_speed()

Cheers,
ta

# insmod tcrypt.ko mode=212

testing speed of rfc4309(ccm(aes)) 
(rfc4309(ccm_base(ctr(aes-generic),cbcmac(aes-generic encryption

test 0 (152 bit key, 16 byte blocks):
1 operation in 0 cycles (16 bytes)
test 1 (152 bit key, 64 byte blocks):
1 operation in 0 cycles (64 bytes)
test 2 (152 bit key, 256 byte blocks):
1 operation in 0 cycles (256 bytes)
test 3 (152 bit key, 512 byte blocks):
1 operation in 0 cycles (512 bytes)
test 4 (152 bit key, 1024 byte blocks):
1 operation in 0 cycles (1024 bytes)
test 5 (152 bit key, 2048 byte blocks):
1 operation in 0 cycles (2048 bytes)
test 6 (152 bit key, 4096 byte blocks):
Unable to handle kernel NULL pointer dereference at virtual address 0004
pgd = deee
[0004] *pgd=3f6b8831, *pte=, *ppte=
Internal error: Oops: 17 [#1] ARM
Modules linked in: tcrypt(+)
CPU: 0 PID: 795 Comm: insmod Not tainted 4.14.0-rc3+ #15
Hardware name: Atmel SAMA5
task: def4d000 task.stack: def4a000
PC is at scatterwalk_copychunks+0x14c/0x18c
LR is at scatterwalk_copychunks+0x144/0x18c
pc : []lr : []psr: 2013
sp : def4bbf8  ip :   fp : def4bcb4
r10: c02d1e5c  r9 :   r8 : def4a000
r7 : defd0090  r6 : def4bc58  r5 : 0010  r4 : 
r3 : dffe71e2  r2 : def4d000  r1 :   r0 : 
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
Control: 10c53c7d  Table: 3eee0059  DAC: 0051
Process insmod (pid: 795, stack limit = 0xdef4a208)
Stack: (0xdef4bbf8 to 0xdef4c000)
bbe0:   def4bc48 
0010
bc00: def4bcbc  0010  c02d1e5c c02c47f0 0010 
def4bc28
bc20: deefe110  deefe200 def11800 c02d1e5c c02cc178 00e7 
def4bc38
bc40: 0010 def4bcbc dffd8fc0 defd0090 dffd8fc0 defd0080  

bc60: 1000 def7e2a0  1000  defd0080 deefe200 
0010
bc80:  0010 0001   c02cc0bc  
ded1a4c0
bca0: 1000 deefe200 deefe0c0 deefe134 deefe164 c02c509c 1000 
deda5280
bcc0: deefe200 0400 deefe100 c02cec9c def4bd70 deefe000  
deefe000
bce0:  0004  def7e200 bf007144 ded19300  
bf001950
bd00: 014000c0 bf007234  0010 bf0075c0 def7e290 deda7a80 
0006
bd20: c0a4bd38 1000  ded19300 bf007140 ded19340  
defd0f00
bd40:  def4bd44 def4bd44 c0176ea4 df60f000 def5c000 def5e000 
deff1000
bd60: df4a5000 df651000 df648000 df646000 deebe000 dee59000 deeae000 
defd1000
bd80: deda defd3000 de806000 def82000 def63000 def78000 deec7000 
deeff000
bda0: deeb9000 deef2000 deeba000 deebd000   0004 
bf0075c0
bdc0: bf007440 defd0f00 bf007488 0001 2102f11c bf005238 df4ac000 
75c0
bde0: 0003 bf0075c0 bf007440 bf0075c0 0004 bf0075c0 bf007440 
defd0f00
be00: bf007488 bf00a054 bf007440 bf00a000  c01018e8  
ded17780
be20: df4ac000 c0a3a72c df42 c0844a4c c07df704 c01a5054 bf007488 
c0684d38
be40: 0012 deda7440 defd0f08 a013 deda7640 e0a7e000 0001 
defd0f00
be60: bf007440 defd0f08 deda7640 defd0f00 bf007488 c016203c bf007488 
0001
be80: def4bf50 defd0f08 0001 c0161390 bf00744c 7fff bf007440 
c015ea8c
bea0:  bf007590 0578 bf007528 c0844c7c c07018f0 c01b1060 
bf00
bec0: dcfb dcfb      

bee0:        

bf00:   7fff  0003 00099008 017b 
c0107964
bf20: def4a000   c0161a68 7fff  0003 
a013
bf40: dedd1c00 e0a7e000 dcfb  e0a83d03 e0a7e000 dcfb 
e0a85238
bf60: e0a850dd e0a8b258 8000 81d0    
2e84
bf80: 0021 0022 0019  0013  00099008 
bebd1f45
bfa0: 0003 c01077a0 00099008 bebd1f45 0003 00099008  
bebd1f45
bfc0: 00099008 bebd1f45 0003 017b bebd1f45   

bfe0: bebd1ca8 bebd1c98 0001f99d b6f3f2c4 8030 0003  

[] (scatterwalk_copychunks) from [] 
(blkcipher_walk_next+0x3a0/0x44c)
[] (blkcipher_walk_next) from [] 
(crypto_ctr_crypt+0xbc/0x1cc)
[] (crypto_ctr_crypt) from [] 
(skcipher_encrypt_blkcipher+0x44/0x4c)
[] (skcipher_encrypt_blkcipher) from [] 
(crypto_ccm_encrypt+0xc8/0xf8)
[] (crypto_ccm_encrypt) from [] 
(test_aead_speed.constprop.2+0x3e8/0x5a8 [tcrypt])
[] 

Re: [PATCH 07/24] staging: ccree: remove unneeded cast

[Joe Perches]

On Mon, 2017-11-13 at 14:45 +, Gilad Ben-Yossef wrote:
> Remove uneeded cast from writel_relaxed parameter.
[]
> diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
> b/drivers/staging/ccree/ssi_request_mgr.c
[]
> @@ -167,13 +167,13 @@ static inline void enqueue_seq(
>   int i;
>  
>   for (i = 0; i < seq_len; i++) {
> - writel_relaxed(seq[i].word[0], (volatile void __iomem 
> *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
> - writel_relaxed(seq[i].word[1], (volatile void __iomem 
> *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
> - writel_relaxed(seq[i].word[2], (volatile void __iomem 
> *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
> - writel_relaxed(seq[i].word[3], (volatile void __iomem 
> *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
> - writel_relaxed(seq[i].word[4], (volatile void __iomem 
> *)(cc_base + CC_REG(DSCRPTR_QUEUE_WORD0)));
> + writel_relaxed(seq[i].word[0], (cc_base + 
> CC_REG(DSCRPTR_QUEUE_WORD0)));

Maybe remove the now unnecessary parentheses around
(cc_case + CC_REG(foo))

Maybe review the use of inline in .c files too

$ git grep -w inline drivers/staging/ccree/*.c | wc -l
41

Re: [PATCH RESEND 1/4] crypto: caam: add caam-dma node to SEC4.0 device tree binding

[Kim Phillips]

On Mon, 13 Nov 2017 09:44:06 +
Radu Andrei Alexe  wrote:

> On 11/10/2017 6:44 PM, Kim Phillips wrote:
> > On Fri, 10 Nov 2017 08:02:01 +
> > Radu Andrei Alexe  wrote:
> > 
> >> On 11/9/2017 6:34 PM, Kim Phillips wrote:
> >>> On Thu, 9 Nov 2017 11:54:13 +
> >>> Radu Andrei Alexe  wrote:
>  The next patch version will create the platform device dynamically at
>  run time.
> >>>
> >>> Why create a new device when that h/w already has one?
> >>>
> >>> Why doesn't the existing crypto driver register dma capabilities with
> >>> the dma driver subsystem?
> >>>
> >> I can think of two reasons:
> >>
> >> 1. The code that this driver introduces has nothing to do with crypto
> >> and everything to do with dma.
> > 
> > I would think that at least a crypto "null" algorithm implementation
> > would share code.
> >
> >> Placing the code in the same directory as
> >> the caam subsystem would only create confusion for the reader of an
> >> already complex driver.
> > 
> > this different directory argument seems to be identical to your 2 below:
> > 
> >> 2. I wanted this driver to be tracked by the dma engine team. They have
> >> the right expertise to provide adequate feedback. If all the code was in
> >> the crypto directory they wouldn't know about this driver or any
> >> subsequent changes to it.
> > 
> > dma subsystem bits could still be put in the dma area if deemed
> > necessary but I don't think it is: I see
> > drivers/crypto/ccp/ccp-dmaengine.c calls dma_async_device_register for
> > example.
> > 
> > I also don't see how that complicates things much further.
> > 
> 
> So who made their review? The guys from crypto?

Don't see how that's relevant here, but people applying patches should
solicit acks from the appropriate sources, esp. if a patch is across
multiple subsystems.

> If someone wants to enable only the DMA functionality of the CCP and not 
> the crypto part how do they do it? Look for it in the crypto submenu?

Why would they want to do that?

In any case, I suspect you're thinking about cross-subsystem Kconfig
entries, which is common, but something like that can be a module
parameter, too.

I would say that maybe CRYPTO_DEV_FSL_CAAM should be made to not depend
on CRYPTO_HW, but I think that's overkill for the addition of this
minor feature.

> > What is the rationale for using the crypto h/w as a dma engine anyway?
> > Are there supporting performance figures?
> 
> We have a platform that doesn't have a dedicated DMA controller but has 
> the CAAM hardware block that can perform dma transfers.  We have a

OK, please mention that next time.

> use-case where we need to issue large transfers (hundred of MBs) 
> asynchronously, without using the core.

Curious: what subsystem does that?

Thanks,

Kim

Re: [PATCH RESEND 1/4] crypto: caam: add caam-dma node to SEC4.0 device tree binding

[Kim Phillips]

On Mon, 13 Nov 2017 08:32:24 +
Horia Geantă  wrote:

> On 11/10/2017 6:44 PM, Kim Phillips wrote:
> > On Fri, 10 Nov 2017 08:02:01 +
> > Radu Andrei Alexe  wrote:
> [snip]>> 2. I wanted this driver to be tracked by the dma engine team.
> They have
> >> the right expertise to provide adequate feedback. If all the code was in 
> >> the crypto directory they wouldn't know about this driver or any 
> >> subsequent changes to it.
> > 
> > dma subsystem bits could still be put in the dma area if deemed
> > necessary but I don't think it is: I see
> > drivers/crypto/ccp/ccp-dmaengine.c calls dma_async_device_register for
> > example.
> > 
> Please see previous discussion with Vinod:
> https://www.mail-archive.com/linux-crypto@vger.kernel.org/msg21468.html

Vinod says: "If the dma controller is internal to crypto, then it might
be okay to be inside the crypto driver."

Is that the case for the CCP driver?  Isn't it the case here?

In any case, I don't care that much about that, this all begat from new
*devices* coming out of nowhere.

> > What is the rationale for using the crypto h/w as a dma engine anyway?
> SoCs that don't have a system DMA, for e.g. LS1012A.

OK.

Kim

Re:

[Amos Kalonzo]

Attn:

I am wondering why You haven't respond to my email for some days now.
reference to my client's contract balance payment of (11.7M,USD)
Kindly get back to me for more details.

Best Regards

Amos Kalonzo

[PATCH 02/24] staging: ccree: alloc by instance not type

[Gilad Ben-Yossef]

Allocation by instance is preferred to allocation by type.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_sram_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/ccree/ssi_sram_mgr.c 
b/drivers/staging/ccree/ssi_sram_mgr.c
index 2263433..b71460c 100644
--- a/drivers/staging/ccree/ssi_sram_mgr.c
+++ b/drivers/staging/ccree/ssi_sram_mgr.c
@@ -51,7 +51,7 @@ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata)
 int ssi_sram_mgr_init(struct ssi_drvdata *drvdata)
 {
/* Allocate "this" context */
-   drvdata->sram_mgr_handle = kzalloc(sizeof(struct ssi_sram_mgr_ctx),
+   drvdata->sram_mgr_handle = kzalloc(sizeof(*drvdata->sram_mgr_handle),
   GFP_KERNEL);
 
if (!drvdata->sram_mgr_handle)
-- 
2.7.4

[PATCH 01/24] staging: ccree: fix typos

[Gilad Ben-Yossef]

Fix a bunch of comment typos.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_hash.c| 2 +-
 drivers/staging/ccree/ssi_hash.h| 2 +-
 drivers/staging/ccree/ssi_ivgen.c   | 2 +-
 drivers/staging/ccree/ssi_request_mgr.c | 2 +-
 drivers/staging/ccree/ssi_request_mgr.h | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 472d3b7..6687027 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -2484,7 +2484,7 @@ static void ssi_hash_create_data_desc(struct 
ahash_req_ctx *areq_ctx,
  * \param drvdata
  * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
  *
- * \return u32 The address of the inital digest in SRAM
+ * \return u32 The address of the initial digest in SRAM
  */
 ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
 {
diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index 2400e38..c884727 100644
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -95,7 +95,7 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 
mode);
  * \param drvdata
  * \param mode The Hash mode. Supported modes: 
MD5/SHA1/SHA224/SHA256/SHA384/SHA512
  *
- * \return u32 The address of the inital digest in SRAM
+ * \return u32 The address of the initial digest in SRAM
  */
 ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode);
 
diff --git a/drivers/staging/ccree/ssi_ivgen.c 
b/drivers/staging/ccree/ssi_ivgen.c
index a33fd76..2f9201e 100644
--- a/drivers/staging/ccree/ssi_ivgen.c
+++ b/drivers/staging/ccree/ssi_ivgen.c
@@ -198,7 +198,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata)
 
ivgen_ctx = drvdata->ivgen_handle;
 
-   /* Allocate pool's header for intial enc. key/IV */
+   /* Allocate pool's header for initial enc. key/IV */
ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE,
  _ctx->pool_meta_dma,
  GFP_KERNEL);
diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index e9a09b3..597a71f 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -205,7 +205,7 @@ static inline int request_mgr_queues_status_check(
struct device *dev = drvdata_to_dev(drvdata);
 
/* SW queue is checked only once as it will not
-* be chaned during the poll becasue the spinlock_bh
+* be chaned during the poll because the spinlock_bh
 * is held by the thread
 */
if (unlikely(((req_mgr_h->req_queue_head + 1) &
diff --git a/drivers/staging/ccree/ssi_request_mgr.h 
b/drivers/staging/ccree/ssi_request_mgr.h
index ba44ab4..23883e2 100644
--- a/drivers/staging/ccree/ssi_request_mgr.h
+++ b/drivers/staging/ccree/ssi_request_mgr.h
@@ -36,7 +36,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata);
  *   If "false": this function adds a dummy descriptor completion
  *   and waits upon completion signal.
  *
- * \return int Returns -EINPROGRESS if "is_dout=ture"; "0" if "is_dout=false"
+ * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false"
  */
 int send_request(
struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
-- 
2.7.4

[PATCH 04/24] staging: ccree: remove MIN/MAX macros

[Gilad Ben-Yossef]

The driver was using open coded MIN/MAX macros to
compute fixed defines. Remove them and use bigger
value always instead.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_aead.h   | 2 +-
 drivers/staging/ccree/ssi_driver.h | 3 ---
 drivers/staging/ccree/ssi_hash.c   | 2 +-
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h
index e85bcd9..580fdb8 100644
--- a/drivers/staging/ccree/ssi_aead.h
+++ b/drivers/staging/ccree/ssi_aead.h
@@ -28,7 +28,7 @@
 /* mac_cmp - HW writes 8 B but all bytes hold the same value */
 #define ICV_CMP_SIZE 8
 #define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3)
-#define MAX_MAC_SIZE MAX(SHA256_DIGEST_SIZE, AES_BLOCK_SIZE)
+#define MAX_MAC_SIZE SHA256_DIGEST_SIZE
 
 /* defines for AES GCM configuration buffer */
 #define GCM_BLOCK_LEN_SIZE 8
diff --git a/drivers/staging/ccree/ssi_driver.h 
b/drivers/staging/ccree/ssi_driver.h
index f4967ca..758268e 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -95,9 +95,6 @@
  * field in the HW descriptor. The DMA engine +8 that value.
  */
 
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-
 #define SSI_MAX_IVGEN_DMA_ADDRESSES3
 struct ssi_crypto_req {
void (*user_cb)(struct device *dev, void *req);
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 1fda84d..8414c25 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -32,7 +32,7 @@
 #include "ssi_sram_mgr.h"
 
 #define SSI_MAX_AHASH_SEQ_LEN 12
-#define SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE MAX(SSI_MAX_HASH_BLCK_SIZE, 3 * 
AES_BLOCK_SIZE)
+#define SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE SSI_MAX_HASH_BLCK_SIZE
 
 struct ssi_hash_handle {
ssi_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/
-- 
2.7.4

[PATCH 05/24] staging: ccree: move logical cont. to 1st line

[Gilad Ben-Yossef]

Move logical continuations to first line for readability.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_buffer_mgr.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 923a0df..cda5a30 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -1473,8 +1473,8 @@ int cc_map_hash_request_final(struct ssi_drvdata 
*drvdata, void *ctx,
   , _nents))) {
goto unmap_curr_buff;
}
-   if (src && mapped_nents == 1
-&& areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) {
+   if (src && mapped_nents == 1 &&
+   areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) {
memcpy(areq_ctx->buff_sg, src,
   sizeof(struct scatterlist));
areq_ctx->buff_sg->length = nbytes;
@@ -1590,8 +1590,8 @@ int cc_map_hash_request_update(struct ssi_drvdata 
*drvdata, void *ctx,
   _nents))) {
goto unmap_curr_buff;
}
-   if (mapped_nents == 1
-&& areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) {
+   if (mapped_nents == 1 &&
+   areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) {
/* only one entry in the SG and no previous data */
memcpy(areq_ctx->buff_sg, src,
   sizeof(struct scatterlist));
-- 
2.7.4

[PATCH 03/24] staging: ccree: remove unnecessary parentheses

[Gilad Ben-Yossef]

Remove unnecessary parentheses in if statements across the driver.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_aead.c   | 36 +-
 drivers/staging/ccree/ssi_buffer_mgr.c | 28 +-
 drivers/staging/ccree/ssi_cipher.c | 34 
 drivers/staging/ccree/ssi_hash.c   | 16 +++
 drivers/staging/ccree/ssi_ivgen.c  |  4 ++--
 5 files changed, 59 insertions(+), 59 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 9e24783..7abc352 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -391,9 +391,9 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
case DRV_HASH_SHA256:
break;
case DRV_HASH_XCBC_MAC:
-   if ((ctx->auth_keylen != AES_KEYSIZE_128) &&
-   (ctx->auth_keylen != AES_KEYSIZE_192) &&
-   (ctx->auth_keylen != AES_KEYSIZE_256))
+   if (ctx->auth_keylen != AES_KEYSIZE_128 &&
+   ctx->auth_keylen != AES_KEYSIZE_192 &&
+   ctx->auth_keylen != AES_KEYSIZE_256)
return -ENOTSUPP;
break;
case DRV_HASH_NULL: /* Not authenc (e.g., CCM) - no auth_key) */
@@ -412,9 +412,9 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
return -EINVAL;
}
} else { /* Default assumed to be AES ciphers */
-   if ((ctx->enc_keylen != AES_KEYSIZE_128) &&
-   (ctx->enc_keylen != AES_KEYSIZE_192) &&
-   (ctx->enc_keylen != AES_KEYSIZE_256)) {
+   if (ctx->enc_keylen != AES_KEYSIZE_128 &&
+   ctx->enc_keylen != AES_KEYSIZE_192 &&
+   ctx->enc_keylen != AES_KEYSIZE_256) {
dev_err(dev, "Invalid cipher(AES) key size: %u\n",
ctx->enc_keylen);
return -EINVAL;
@@ -676,8 +676,8 @@ static int ssi_aead_setauthsize(
struct device *dev = drvdata_to_dev(ctx->drvdata);
 
/* Unsupported auth. sizes */
-   if ((authsize == 0) ||
-   (authsize > crypto_aead_maxauthsize(authenc))) {
+   if (authsize == 0 ||
+   authsize > crypto_aead_maxauthsize(authenc)) {
return -ENOTSUPP;
}
 
@@ -744,8 +744,8 @@ ssi_aead_create_assoc_desc(
set_din_type([idx], DMA_DLLI, sg_dma_address(areq->src),
 areq->assoclen, NS_BIT); set_flow_mode([idx],
 flow_mode);
-   if ((ctx->auth_mode == DRV_HASH_XCBC_MAC) &&
-   (areq_ctx->cryptlen > 0))
+   if (ctx->auth_mode == DRV_HASH_XCBC_MAC &&
+   areq_ctx->cryptlen > 0)
set_din_not_last_indication([idx]);
break;
case SSI_DMA_BUF_MLLI:
@@ -754,8 +754,8 @@ ssi_aead_create_assoc_desc(
set_din_type([idx], DMA_MLLI, areq_ctx->assoc.sram_addr,
 areq_ctx->assoc.mlli_nents, NS_BIT);
set_flow_mode([idx], flow_mode);
-   if ((ctx->auth_mode == DRV_HASH_XCBC_MAC) &&
-   (areq_ctx->cryptlen > 0))
+   if (ctx->auth_mode == DRV_HASH_XCBC_MAC &&
+   areq_ctx->cryptlen > 0)
set_din_not_last_indication([idx]);
break;
case SSI_DMA_BUF_NULL:
@@ -1192,8 +1192,8 @@ static inline void ssi_aead_load_mlli_to_sram(
struct device *dev = drvdata_to_dev(ctx->drvdata);
 
if (unlikely(
-   (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) ||
-   (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) ||
+   req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI ||
+   req_ctx->data_buff_type == SSI_DMA_BUF_MLLI ||
!req_ctx->is_single_pass)) {
dev_dbg(dev, "Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n",
(unsigned int)ctx->drvdata->mlli_sram_addr,
@@ -1350,15 +1350,15 @@ static int validate_data_size(struct ssi_aead_ctx *ctx,
unsigned int cipherlen = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ?
(req->cryptlen - ctx->authsize) : req->cryptlen;
 
-   if (unlikely((direct == DRV_CRYPTO_DIRECTION_DECRYPT) &&
-(req->cryptlen < ctx->authsize)))
+   if (unlikely(direct == DRV_CRYPTO_DIRECTION_DECRYPT &&
+req->cryptlen < ctx->authsize))
goto data_size_err;
 
areq_ctx->is_single_pass = true; /*defaulted to fast flow*/
 
switch (ctx->flow_mode) {
case S_DIN_to_AES:
-   if (unlikely((ctx->cipher_mode == DRV_CIPHER_CBC) &&
+   if (unlikely(ctx->cipher_mode == DRV_CIPHER_CBC &&
 !IS_ALIGNED(cipherlen, 

[PATCH 06/24] staging: ccree: remove unneeded empty lines

[Gilad Ben-Yossef]

Remove uneeded empty lines that crept in to code.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_buffer_mgr.c | 1 -
 drivers/staging/ccree/ssi_hash.c   | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index cda5a30..684c934 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -691,7 +691,6 @@ void cc_unmap_aead_request(struct device *dev, struct 
aead_request *req)
if (drvdata->coherent &&
areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT &&
likely(req->src == req->dst)) {
-
/* copy back mac from temporary location to deal with possible
 * data memory overriding that caused by cache coherence 
problem.
 */
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 8414c25..66b011c 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -2064,7 +2064,6 @@ ssi_hash_create_alg(struct ssi_hash_template *template, 
struct device *dev,
if (!t_crypto_alg)
return ERR_PTR(-ENOMEM);
 
-
t_crypto_alg->ahash_alg = template->template_ahash;
halg = _crypto_alg->ahash_alg;
alg = >halg.base;
-- 
2.7.4

[PATCH 11/24] staging: ccree: constify help string

[Gilad Ben-Yossef]

Make help string static const

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_sysfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/ccree/ssi_sysfs.c 
b/drivers/staging/ccree/ssi_sysfs.c
index 5d39f15..8d50382 100644
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -47,7 +47,7 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj,
 static ssize_t ssi_sys_help_show(struct kobject *kobj,
 struct kobj_attribute *attr, char *buf)
 {
-   char *help_str[] = {
+   static const char * const help_str[] = {
"cat reg_dump  ", "Print several of 
CC register values",
};
int i = 0, offset = 0;
-- 
2.7.4

[PATCH 13/24] staging: ccree: Replace CONFIG_PM_RUNTIME with CONFIG_PM

[Gilad Ben-Yossef]

After commit b2b49ccbdd54
("PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is selected")
PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.

Replace CONFIG_PM_RUNTIME with CONFIG_PM.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_driver.c  |  4 ++--
 drivers/staging/ccree/ssi_pm.c  |  6 +++---
 drivers/staging/ccree/ssi_pm.h  |  2 +-
 drivers/staging/ccree/ssi_request_mgr.c | 14 +++---
 drivers/staging/ccree/ssi_request_mgr.h |  2 +-
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/staging/ccree/ssi_driver.c 
b/drivers/staging/ccree/ssi_driver.c
index 0d5c1a9..8d16823 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -495,13 +495,13 @@ static int cc7x_remove(struct platform_device *plat_dev)
return 0;
 }
 
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
 static const struct dev_pm_ops arm_cc7x_driver_pm = {
SET_RUNTIME_PM_OPS(cc_pm_suspend, cc_pm_resume, NULL)
 };
 #endif
 
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
 #defineDX_DRIVER_RUNTIME_PM(_cc7x_driver_pm)
 #else
 #defineDX_DRIVER_RUNTIME_PMNULL
diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c
index 86d403d..5e2ef5e 100644
--- a/drivers/staging/ccree/ssi_pm.c
+++ b/drivers/staging/ccree/ssi_pm.c
@@ -29,7 +29,7 @@
 #include "ssi_hash.h"
 #include "ssi_pm.h"
 
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
 
 #define POWER_DOWN_ENABLE 0x01
 #define POWER_DOWN_DISABLE 0x00
@@ -119,7 +119,7 @@ int cc_pm_put_suspend(struct device *dev)
 int cc_pm_init(struct ssi_drvdata *drvdata)
 {
int rc = 0;
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
struct device *dev = drvdata_to_dev(drvdata);
 
/* must be before the enabling to avoid resdundent suspending */
@@ -137,7 +137,7 @@ int cc_pm_init(struct ssi_drvdata *drvdata)
 
 void cc_pm_fini(struct ssi_drvdata *drvdata)
 {
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
pm_runtime_disable(drvdata_to_dev(drvdata));
 #endif
 }
diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h
index 557ec98..50bcf03 100644
--- a/drivers/staging/ccree/ssi_pm.h
+++ b/drivers/staging/ccree/ssi_pm.h
@@ -29,7 +29,7 @@ int cc_pm_init(struct ssi_drvdata *drvdata);
 
 void cc_pm_fini(struct ssi_drvdata *drvdata);
 
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
 int cc_pm_suspend(struct device *dev);
 
 int cc_pm_resume(struct device *dev);
diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index 1d9c038..ab18851 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -58,7 +58,7 @@ struct ssi_request_mgr_handle {
 #else
struct tasklet_struct comptask;
 #endif
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
bool is_runtime_suspended;
 #endif
 };
@@ -277,7 +277,7 @@ int send_request(
SSI_IVPOOL_SEQ_LEN) +
(!is_dout ? 1 : 0));
 
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
rc = cc_pm_get(dev);
if (rc) {
dev_err(dev, "ssi_power_mgr_runtime_get returned %x\n", rc);
@@ -304,7 +304,7 @@ int send_request(
/* Any error other than HW queue full
 * (SW queue is full)
 */
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
cc_pm_put_suspend(dev);
 #endif
return rc;
@@ -340,7 +340,7 @@ int send_request(
if (unlikely(rc)) {
dev_err(dev, "Failed to generate IV (rc=%d)\n", rc);
spin_unlock_bh(_mgr_h->hw_lock);
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
cc_pm_put_suspend(dev);
 #endif
return rc;
@@ -469,7 +469,7 @@ static void proc_completions(struct ssi_drvdata *drvdata)
struct device *dev = drvdata_to_dev(drvdata);
struct ssi_request_mgr_handle *request_mgr_handle =
drvdata->request_mgr_handle;
-#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
+#if defined(CONFIG_PM)
int rc = 0;
 #endif
 
@@ -513,7 +513,7 @@ static void proc_completions(struct ssi_drvdata *drvdata)
request_mgr_handle->req_queue_tail);
dev_dbg(dev, "Request completed. axi_completed=%d\n",

[PATCH 15/24] staging: ccree: trim long lines for readability

[Gilad Ben-Yossef]

The ccree driver did not adhere to the kernel max 80 chars per line limit
making the code hard to follow. Fix this by breaking long lines and
in some cases, moving comments to a separate line from code.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_aead.c| 152 ++--
 drivers/staging/ccree/ssi_aead.h|  15 ++--
 drivers/staging/ccree/ssi_buffer_mgr.c  | 100 +
 drivers/staging/ccree/ssi_cipher.c  |  66 ++
 drivers/staging/ccree/ssi_cipher.h  |   5 +-
 drivers/staging/ccree/ssi_config.h  |   6 +-
 drivers/staging/ccree/ssi_driver.c  |   8 +-
 drivers/staging/ccree/ssi_driver.h  |  15 ++--
 drivers/staging/ccree/ssi_fips.h|   3 +-
 drivers/staging/ccree/ssi_hash.c| 131 +++
 drivers/staging/ccree/ssi_hash.h|  10 ++-
 drivers/staging/ccree/ssi_ivgen.c   |   7 +-
 drivers/staging/ccree/ssi_ivgen.h   |   3 +-
 drivers/staging/ccree/ssi_request_mgr.c |  45 ++
 drivers/staging/ccree/ssi_sysfs.c   |  33 +--
 15 files changed, 406 insertions(+), 193 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 7abc352..e2cdf52 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -100,7 +100,8 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
 
/* Unmap enckey buffer */
if (ctx->enckey) {
-   dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, 
ctx->enckey_dma_addr);
+   dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey,
+ ctx->enckey_dma_addr);
dev_dbg(dev, "Freed enckey DMA buffer enckey_dma_addr=%pad\n",
>enckey_dma_addr);
ctx->enckey_dma_addr = 0;
@@ -259,12 +260,17 @@ static void ssi_aead_complete(struct device *dev, void 
*ssi_req)
   SSI_SG_FROM_BUF);
}
 
-   /* If an IV was generated, copy it back to the user provided 
buffer. */
+   /* If an IV was generated, copy it back to the user provided
+* buffer.
+*/
if (areq_ctx->backup_giv) {
if (ctx->cipher_mode == DRV_CIPHER_CTR)
-   memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + 
CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_IV_SIZE);
+   memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv +
+  CTR_RFC3686_NONCE_SIZE,
+  CTR_RFC3686_IV_SIZE);
else if (ctx->cipher_mode == DRV_CIPHER_CCM)
-   memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + 
CCM_BLOCK_IV_OFFSET, CCM_BLOCK_IV_SIZE);
+   memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv +
+  CCM_BLOCK_IV_OFFSET, CCM_BLOCK_IV_SIZE);
}
}
 
@@ -275,8 +281,9 @@ static int xcbc_setkey(struct cc_hw_desc *desc, struct 
ssi_aead_ctx *ctx)
 {
/* Load the AES key */
hw_desc_init([0]);
-   /* We are using for the source/user key the same buffer as for the 
output keys,
-* because after this key loading it is not needed anymore
+   /* We are using for the source/user key the same buffer
+* as for the output keys, * because after this key loading it
+* is not needed anymore
 */
set_din_type([0], DMA_DLLI,
 ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen,
@@ -428,7 +435,8 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
  * (copy to intenral buffer or hash in case of key longer than block
  */
 static int
-ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int 
keylen)
+ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key,
+  unsigned int keylen)
 {
dma_addr_t key_dma_addr = 0;
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -459,7 +467,8 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 
*key, unsigned int keyl
}
 
if (likely(keylen != 0)) {
-   key_dma_addr = dma_map_single(dev, (void *)key, keylen, 
DMA_TO_DEVICE);
+   key_dma_addr = dma_map_single(dev, (void *)key, keylen,
+ DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(dev, key_dma_addr))) {
dev_err(dev, "Mapping key va=0x%p len=%u for DMA 
failed\n",
key, keylen);
@@ -587,8 +596,9 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
unsigned int keylen)
/* Copy nonce from last 4 bytes in CTR key to
 *  first 4 bytes in CTR IV
 */
-   

[PATCH 16/24] staging: ccree: remove dead defs and decls

[Gilad Ben-Yossef]

Remove no longer definitions of enums and forward declaration of functions
dealing with sysfs interface of the long removed ccree cycle counter.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_sysfs.h | 23 ---
 1 file changed, 23 deletions(-)

diff --git a/drivers/staging/ccree/ssi_sysfs.h 
b/drivers/staging/ccree/ssi_sysfs.h
index 44ae3d4..5124528 100644
--- a/drivers/staging/ccree/ssi_sysfs.h
+++ b/drivers/staging/ccree/ssi_sysfs.h
@@ -26,30 +26,7 @@
 /* forward declaration */
 struct ssi_drvdata;
 
-enum stat_phase {
-   STAT_PHASE_0 = 0,
-   STAT_PHASE_1,
-   STAT_PHASE_2,
-   STAT_PHASE_3,
-   STAT_PHASE_4,
-   STAT_PHASE_5,
-   STAT_PHASE_6,
-   MAX_STAT_PHASES,
-};
-
-enum stat_op {
-   STAT_OP_TYPE_NULL = 0,
-   STAT_OP_TYPE_ENCODE,
-   STAT_OP_TYPE_DECODE,
-   STAT_OP_TYPE_SETKEY,
-   STAT_OP_TYPE_GENERIC,
-   MAX_STAT_OP_TYPES,
-};
-
 int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata);
 void ssi_sysfs_fini(void);
-void update_host_stat(unsigned int op_type, unsigned int phase, cycles_t 
result);
-void update_cc_stat(unsigned int op_type, unsigned int phase, unsigned int 
elapsed_cycles);
-void display_all_stat_db(void);
 
 #endif /*__SSI_SYSFS_H__*/
-- 
2.7.4

[PATCH 20/24] staging: ccree: remove unneeded wrapper function

[Gilad Ben-Yossef]

Remove unneeded wrapper function to simplify code.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_hash.c | 21 ++---
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index afdc44e..a2e8a9d 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -986,10 +986,8 @@ static int ssi_hash_init(struct ahash_req_ctx *state, 
struct ssi_hash_ctx *ctx)
return 0;
 }
 
-static int ssi_hash_setkey(void *hash,
-  const u8 *key,
-  unsigned int keylen,
-  bool synchronize)
+static int ssi_ahash_setkey(struct crypto_ahash *ahash, const u8 *key,
+   unsigned int keylen)
 {
unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST };
struct ssi_crypto_req ssi_req = {};
@@ -1001,12 +999,12 @@ static int ssi_hash_setkey(void *hash,
ssi_sram_addr_t larval_addr;
struct device *dev;
 
-   ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash));
+   ctx = crypto_ahash_ctx(ahash);
dev = drvdata_to_dev(ctx->drvdata);
dev_dbg(dev, "start keylen: %d", keylen);
 
-   blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash 
*)hash)->base);
-   digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash));
+   blocksize = crypto_tfm_alg_blocksize(>base);
+   digestsize = crypto_ahash_digestsize(ahash);
 
larval_addr = cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
 
@@ -1167,8 +1165,7 @@ static int ssi_hash_setkey(void *hash,
 
 out:
if (rc)
-   crypto_ahash_set_flags((struct crypto_ahash *)hash,
-  CRYPTO_TFM_RES_BAD_KEY_LEN);
+   crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
 
if (ctx->key_params.key_dma_addr) {
dma_unmap_single(dev, ctx->key_params.key_dma_addr,
@@ -1879,12 +1876,6 @@ static int ssi_ahash_import(struct ahash_request *req, 
const void *in)
return rc;
 }
 
-static int ssi_ahash_setkey(struct crypto_ahash *ahash,
-   const u8 *key, unsigned int keylen)
-{
-   return ssi_hash_setkey((void *)ahash, key, keylen, false);
-}
-
 struct ssi_hash_template {
char name[CRYPTO_MAX_ALG_NAME];
char driver_name[CRYPTO_MAX_ALG_NAME];
-- 
2.7.4

[PATCH 17/24] staging: ccree: refactor code with local vars

[Gilad Ben-Yossef]

Refactor the queue handling loop using local variables for better
code readability.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_request_mgr.c | 16 +++-
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index 001bbe9..a2a82ef 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -476,6 +476,8 @@ static void proc_completions(struct ssi_drvdata *drvdata)
struct device *dev = drvdata_to_dev(drvdata);
struct ssi_request_mgr_handle *request_mgr_handle =
drvdata->request_mgr_handle;
+   unsigned int *tail = _mgr_handle->req_queue_tail;
+   unsigned int *head = _mgr_handle->req_queue_head;
 #if defined(CONFIG_PM)
int rc = 0;
 #endif
@@ -484,18 +486,17 @@ static void proc_completions(struct ssi_drvdata *drvdata)
request_mgr_handle->axi_completed--;
 
/* Dequeue request */
-   if (unlikely(request_mgr_handle->req_queue_head ==
-request_mgr_handle->req_queue_tail)) {
+   if (unlikely(*head == *tail)) {
/* We are supposed to handle a completion but our
 * queue is empty. This is not normal. Return and
 * hope for the best.
 */
dev_err(dev, "Request queue is empty head == tail %u\n",
-   request_mgr_handle->req_queue_head);
+   *head);
break;
}
 
-   ssi_req = 
_mgr_handle->req_queue[request_mgr_handle->req_queue_tail];
+   ssi_req = _mgr_handle->req_queue[*tail];
 
 #ifdef FLUSH_CACHE_ALL
flush_cache_all();
@@ -516,11 +517,8 @@ static void proc_completions(struct ssi_drvdata *drvdata)
 
if (likely(ssi_req->user_cb))
ssi_req->user_cb(dev, ssi_req->user_arg);
-   request_mgr_handle->req_queue_tail =
-   (request_mgr_handle->req_queue_tail + 1) &
-   (MAX_REQUEST_QUEUE_SIZE - 1);
-   dev_dbg(dev, "Dequeue request tail=%u\n",
-   request_mgr_handle->req_queue_tail);
+   *tail = (*tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
+   dev_dbg(dev, "Dequeue request tail=%u\n", *tail);
dev_dbg(dev, "Request completed. axi_completed=%d\n",
request_mgr_handle->axi_completed);
 #if defined(CONFIG_PM)
-- 
2.7.4

[PATCH 18/24] staging: ccree: rename func for readability

[Gilad Ben-Yossef]

Rename the insanely long ssi_ahash_get_larval_digest_sram_addr() func
to cc_larval_digest_addr() for better code readability

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_aead.c |  7 +++
 drivers/staging/ccree/ssi_hash.c | 13 ++---
 drivers/staging/ccree/ssi_hash.h |  2 +-
 3 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index e2cdf52..fcff625 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -336,8 +336,8 @@ static int hmac_setkey(struct cc_hw_desc *desc, struct 
ssi_aead_ctx *ctx)
hw_desc_init([idx]);
set_cipher_mode([idx], hash_mode);
set_din_sram([idx],
-ssi_ahash_get_larval_digest_sram_addr(
-   ctx->drvdata, ctx->auth_mode),
+cc_larval_digest_addr(ctx->drvdata,
+  ctx->auth_mode),
 digest_size);
set_flow_mode([idx], S_DIN_to_HASH);
set_setup_mode([idx], SETUP_LOAD_STATE0);
@@ -441,8 +441,7 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 
*key,
dma_addr_t key_dma_addr = 0;
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct device *dev = drvdata_to_dev(ctx->drvdata);
-   u32 larval_addr = ssi_ahash_get_larval_digest_sram_addr(
-   ctx->drvdata, ctx->auth_mode);
+   u32 larval_addr = cc_larval_digest_addr(ctx->drvdata, ctx->auth_mode);
struct ssi_crypto_req ssi_req = {};
unsigned int blocksize;
unsigned int digestsize;
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 4d7e565..0f67737 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -150,8 +150,8 @@ static int ssi_hash_map_request(struct device *dev,
struct ssi_hash_ctx *ctx)
 {
bool is_hmac = ctx->is_hmac;
-   ssi_sram_addr_t larval_digest_addr = 
ssi_ahash_get_larval_digest_sram_addr(
-   ctx->drvdata, ctx->hash_mode);
+   ssi_sram_addr_t larval_digest_addr =
+   cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
struct ssi_crypto_req ssi_req = {};
struct cc_hw_desc desc;
int rc = -ENOMEM;
@@ -438,8 +438,8 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
bool is_hmac = ctx->is_hmac;
struct ssi_crypto_req ssi_req = {};
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
-   ssi_sram_addr_t larval_digest_addr = 
ssi_ahash_get_larval_digest_sram_addr(
-   ctx->drvdata, ctx->hash_mode);
+   ssi_sram_addr_t larval_digest_addr =
+   cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
int idx = 0;
int rc = 0;
 
@@ -1008,8 +1008,7 @@ static int ssi_hash_setkey(void *hash,
blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash 
*)hash)->base);
digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash));
 
-   larval_addr = ssi_ahash_get_larval_digest_sram_addr(
-   ctx->drvdata, ctx->hash_mode);
+   larval_addr = cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
 
/* The keylen value distinguishes HASH in case keylen is ZERO bytes,
 * any NON-ZERO value utilizes HMAC flow
@@ -2538,7 +2537,7 @@ static void ssi_hash_create_data_desc(struct 
ahash_req_ctx *areq_ctx,
  *
  * \return u32 The address of the initial digest in SRAM
  */
-ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode)
+ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode)
 {
struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata;
struct ssi_hash_handle *hash_handle = _drvdata->hash_handle;
diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index 8e6eee5..32eb473 100644
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -101,7 +101,7 @@ ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, 
u32 mode);
  *
  * \return u32 The address of the initial digest in SRAM
  */
-ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode);
+ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode);
 
 #endif /*__SSI_HASH_H__*/
 
-- 
2.7.4

[PATCH 19/24] staging: ccree: rename long define for readability

[Gilad Ben-Yossef]

Rename the too long  SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE
to SSI_MAX_OPAD_KEYS_SIZE for better code readability.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_hash.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 0f67737..afdc44e 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -32,7 +32,7 @@
 #include "ssi_sram_mgr.h"
 
 #define SSI_MAX_AHASH_SEQ_LEN 12
-#define SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE SSI_MAX_HASH_BLCK_SIZE
+#define SSI_MAX_OPAD_KEYS_SIZE SSI_MAX_HASH_BLCK_SIZE
 
 struct ssi_hash_handle {
ssi_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/
@@ -94,7 +94,7 @@ struct ssi_hash_ctx {
 * the initial digest if HASH.
 */
u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE]  cacheline_aligned;
-   u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE]  
cacheline_aligned;
+   u8 opad_tmp_keys_buff[SSI_MAX_OPAD_KEYS_SIZE]  cacheline_aligned;
 
dma_addr_t opad_tmp_keys_dma_addr  cacheline_aligned;
dma_addr_t digest_buff_dma_addr;
-- 
2.7.4

[PATCH 21/24] staging: ccree: remove unused field

[Gilad Ben-Yossef]

Field monitor_null_cycles of struct drvdata was not being used.
Remove it.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_driver.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/staging/ccree/ssi_driver.h 
b/drivers/staging/ccree/ssi_driver.h
index 7c266ff..ff9f5aa 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -125,10 +125,6 @@ struct ssi_drvdata {
int irq;
u32 irq_mask;
u32 fw_ver;
-   /* Calibration time of start/stop
-* monitor descriptors
-*/
-   u32 monitor_null_cycles;
struct platform_device *plat_dev;
ssi_sram_addr_t mlli_sram_addr;
void *buff_mgr_handle;
-- 
2.7.4

[PATCH 22/24] staging: ccree: replace msleep with a completion

[Gilad Ben-Yossef]

When the driver would try to queue commands to the HW FIFO but ran out of
slots it would use msleep as a delay until the FIFO would clear. This is
messy and not accurate.

Replace the msleep with a proper completion on the event of command
completion which should indicate at least one slot is free.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_driver.c  | 2 ++
 drivers/staging/ccree/ssi_driver.h  | 1 +
 drivers/staging/ccree/ssi_request_mgr.c | 7 +--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/ccree/ssi_driver.c 
b/drivers/staging/ccree/ssi_driver.c
index b17b811..3cb2296 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -251,6 +251,8 @@ static int init_cc_resources(struct platform_device 
*plat_dev)
}
dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);
 
+   init_completion(_drvdata->hw_queue_avail);
+
if (!plat_dev->dev.dma_mask)
plat_dev->dev.dma_mask = _dev->dev.coherent_dma_mask;
 
diff --git a/drivers/staging/ccree/ssi_driver.h 
b/drivers/staging/ccree/ssi_driver.h
index ff9f5aa..f92867b 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -125,6 +125,7 @@ struct ssi_drvdata {
int irq;
u32 irq_mask;
u32 fw_ver;
+   struct completion hw_queue_avail; /* wait for HW queue availability */
struct platform_device *plat_dev;
ssi_sram_addr_t mlli_sram_addr;
void *buff_mgr_handle;
diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index a2a82ef..0882efd 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -312,8 +312,9 @@ int send_request(
return rc;
}
 
-   /* HW queue is full - short sleep */
-   msleep(1);
+   /* HW queue is full - wait for it to clear up */
+   wait_for_completion_interruptible(>hw_queue_avail);
+   reinit_completion(>hw_queue_avail);
} while (1);
 
/* Additional completion descriptor is needed incase caller did not
@@ -452,6 +453,8 @@ void complete_request(struct ssi_drvdata *drvdata)
 {
struct ssi_request_mgr_handle *request_mgr_handle =
drvdata->request_mgr_handle;
+
+   complete(>hw_queue_avail);
 #ifdef COMP_IN_WQ
queue_delayed_work(request_mgr_handle->workq,
   _mgr_handle->compwork, 0);
-- 
2.7.4

[PATCH 23/24] staging: ccree: use local vars for readability

[Gilad Ben-Yossef]

Refactor cc_map_aead_request() to use local vars for addresses
for better readability of code.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_buffer_mgr.c | 64 +++---
 1 file changed, 29 insertions(+), 35 deletions(-)

diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 966033d..c542225 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -1259,7 +1259,7 @@ int cc_map_aead_request(
int rc = 0;
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
bool is_gcm4543 = areq_ctx->is_gcm4543;
-
+   dma_addr_t dma_addr;
u32 mapped_nents = 0;
u32 dummy = 0; /*used for the assoc data fragments */
u32 size_to_map = 0;
@@ -1281,32 +1281,31 @@ int cc_map_aead_request(
req->cryptlen :
(req->cryptlen - authsize);
 
-   areq_ctx->mac_buf_dma_addr = dma_map_single(dev, areq_ctx->mac_buf,
-   MAX_MAC_SIZE,
-   DMA_BIDIRECTIONAL);
-   if (unlikely(dma_mapping_error(dev, areq_ctx->mac_buf_dma_addr))) {
+   dma_addr = dma_map_single(dev, areq_ctx->mac_buf, MAX_MAC_SIZE,
+ DMA_BIDIRECTIONAL);
+   if (unlikely(dma_mapping_error(dev, dma_addr))) {
dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n",
MAX_MAC_SIZE, areq_ctx->mac_buf);
rc = -ENOMEM;
goto aead_map_failure;
}
+   areq_ctx->mac_buf_dma_addr = dma_addr;
 
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
-   areq_ctx->ccm_iv0_dma_addr =
-   dma_map_single(dev, (areq_ctx->ccm_config +
-CCM_CTR_COUNT_0_OFFSET),
-  AES_BLOCK_SIZE, DMA_TO_DEVICE);
+   void *addr = areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET;
 
-   if (unlikely(dma_mapping_error(dev,
-  areq_ctx->ccm_iv0_dma_addr))) {
+   dma_addr = dma_map_single(dev, addr, AES_BLOCK_SIZE,
+ DMA_TO_DEVICE);
+
+   if (unlikely(dma_mapping_error(dev, dma_addr))) {
dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA 
failed\n",
-   AES_BLOCK_SIZE,
-   (areq_ctx->ccm_config +
-CCM_CTR_COUNT_0_OFFSET));
+   AES_BLOCK_SIZE, addr);
areq_ctx->ccm_iv0_dma_addr = 0;
rc = -ENOMEM;
goto aead_map_failure;
}
+   areq_ctx->ccm_iv0_dma_addr = dma_addr;
+
if (ssi_aead_handle_config_buf(dev, areq_ctx,
   areq_ctx->ccm_config, _data,
   req->assoclen)) {
@@ -1317,54 +1316,49 @@ int cc_map_aead_request(
 
 #if SSI_CC_HAS_AES_GCM
if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) {
-   areq_ctx->hkey_dma_addr = dma_map_single(dev,
-areq_ctx->hkey,
-AES_BLOCK_SIZE,
-DMA_BIDIRECTIONAL);
-   if (unlikely(dma_mapping_error(dev,
-  areq_ctx->hkey_dma_addr))) {
+   dma_addr = dma_map_single(dev, areq_ctx->hkey, AES_BLOCK_SIZE,
+ DMA_BIDIRECTIONAL);
+   if (unlikely(dma_mapping_error(dev, dma_addr))) {
dev_err(dev, "Mapping hkey %u B at va=%pK for DMA 
failed\n",
AES_BLOCK_SIZE, areq_ctx->hkey);
rc = -ENOMEM;
goto aead_map_failure;
}
+   areq_ctx->hkey_dma_addr = dma_addr;
 
-   areq_ctx->gcm_block_len_dma_addr =
-   dma_map_single(dev, _ctx->gcm_len_block,
-  AES_BLOCK_SIZE, DMA_TO_DEVICE);
-   if (unlikely(dma_mapping_error(dev,
-  
areq_ctx->gcm_block_len_dma_addr))) {
+   dma_addr = dma_map_single(dev, _ctx->gcm_len_block,
+ AES_BLOCK_SIZE, DMA_TO_DEVICE);
+   if (unlikely(dma_mapping_error(dev, dma_addr))) {
dev_err(dev, "Mapping gcm_len_block %u B at va=%pK for 
DMA failed\n",
AES_BLOCK_SIZE, _ctx->gcm_len_block);
rc = -ENOMEM;
goto 

[PATCH 24/24] staging: ccree: drop unused macro

[Gilad Ben-Yossef]

The CC_REG_NAME macro is unused. Drop it.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_hw_queue_defs.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index 2ae0f65..c5aaa79 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -30,8 +30,6 @@
 /* Define max. available slots in HW queue */
 #define HW_QUEUE_SLOTS_MAX  15
 
-#define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name
-
 #define CC_REG_LOW(word, name)  \
(DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
 
-- 
2.7.4

[PATCH 14/24] staging: ccree: replace macro with inline func

[Gilad Ben-Yossef]

Replace GET_DMA_BUFFER_TYPE with an inline function
variant with type checking.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_buffer_mgr.c | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 684c934..5e01477 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -33,11 +33,6 @@
 #include "ssi_hash.h"
 #include "ssi_aead.h"
 
-#define GET_DMA_BUFFER_TYPE(buff_type) ( \
-   ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \
-   ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \
-   ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID")
-
 enum dma_buffer_type {
DMA_NULL_TYPE = -1,
DMA_SGL_TYPE = 1,
@@ -64,6 +59,20 @@ struct buffer_array {
u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
 };
 
+static inline char *cc_dma_buf_type(enum ssi_req_dma_buf_type type)
+{
+   switch (type) {
+   case SSI_DMA_BUF_NULL:
+   return "BUF_NULL";
+   case SSI_DMA_BUF_DLLI:
+   return "BUF_DLLI";
+   case SSI_DMA_BUF_MLLI:
+   return "BUF_MLLI";
+   default:
+   return "BUF_INVALID";
+   }
+}
+
 /**
  * cc_copy_mac() - Copy MAC to temporary location
  *
@@ -594,7 +603,7 @@ int cc_map_blkcipher_request(
}
 
dev_dbg(dev, "areq_ctx->dma_buf_type = %s\n",
-   GET_DMA_BUFFER_TYPE(req_ctx->dma_buf_type));
+   cc_dma_buf_type(req_ctx->dma_buf_type));
 
return 0;
 
@@ -819,7 +828,7 @@ static inline int cc_aead_chain_assoc(
areq_ctx->assoc.nents = 0;
areq_ctx->assoc.mlli_nents = 0;
dev_dbg(dev, "Chain assoc of length 0: buff_type=%s nents=%u\n",
-   GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type),
+   cc_dma_buf_type(areq_ctx->assoc_buff_type),
areq_ctx->assoc.nents);
goto chain_assoc_exit;
}
@@ -871,7 +880,7 @@ static inline int cc_aead_chain_assoc(
if (unlikely((do_chain) ||
 areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI)) {
dev_dbg(dev, "Chain assoc: buff_type=%s nents=%u\n",
-   GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type),
+   cc_dma_buf_type(areq_ctx->assoc_buff_type),
areq_ctx->assoc.nents);
cc_add_sg_entry(dev, sg_data, areq_ctx->assoc.nents, req->src,
req->assoclen, 0, is_last,
@@ -1496,7 +1505,7 @@ int cc_map_hash_request_final(struct ssi_drvdata 
*drvdata, void *ctx,
/* change the buffer index for the unmap function */
areq_ctx->buff_index = (areq_ctx->buff_index ^ 1);
dev_dbg(dev, "areq_ctx->data_dma_buf_type = %s\n",
-   GET_DMA_BUFFER_TYPE(areq_ctx->data_dma_buf_type));
+   cc_dma_buf_type(areq_ctx->data_dma_buf_type));
return 0;
 
 fail_unmap_din:
-- 
2.7.4

[PATCH 09/24] staging: ccree: replace open coded loop with for

[Gilad Ben-Yossef]

Replace open coded register writing loop with a for.
Further simplify code by using a local var to precompute
the register address for readability.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_request_mgr.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index f5041f7..65c4d9f 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -164,15 +164,17 @@ static inline void enqueue_seq(
void __iomem *cc_base,
struct cc_hw_desc seq[], unsigned int seq_len)
 {
-   int i;
+   int i, w;
+   void * __iomem reg = cc_base + CC_REG(DSCRPTR_QUEUE_WORD0);
+
+   /*
+* We do indeed write all 6 command words to the same
+* register. The HW supports this.
+*/
 
for (i = 0; i < seq_len; i++) {
-   writel_relaxed(seq[i].word[0], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
-   writel_relaxed(seq[i].word[1], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
-   writel_relaxed(seq[i].word[2], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
-   writel_relaxed(seq[i].word[3], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
-   writel_relaxed(seq[i].word[4], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
-   writel_relaxed(seq[i].word[5], (cc_base + 
CC_REG(DSCRPTR_QUEUE_WORD0)));
+   for (w = 0; w <= 5; w++)
+   writel_relaxed(seq[i].word[w], reg);
 #ifdef DX_DUMP_DESCS
dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 
0x%08X\n",
i, seq[i].word[0], seq[i].word[1], seq[i].word[2],
-- 
2.7.4

[PATCH 00/24] staging: ccree: more cleanup patches

[Gilad Ben-Yossef]

Another set of cleanup patches. 
This set goes on top of the previous fixes and cleanups patch set
sent to the list.

With this set of patches checkpatch now only reports one false
warning and a warning on device tree string being undocumented.

Gilad Ben-Yossef (24):
  staging: ccree: fix typos
  staging: ccree: alloc by instance not type
  staging: ccree: remove unnecessary parentheses
  staging: ccree: remove MIN/MAX macros
  staging: ccree: move logical cont. to 1st line
  staging: ccree: remove unneeded empty lines
  staging: ccree: remove unneeded cast
  staging: ccree: make mem barrier per request
  staging: ccree: replace open coded loop with for
  staging: ccree: document spinlock usage
  staging: ccree: constify help string
  staging: ccree: fix code indent
  staging: ccree: Replace CONFIG_PM_RUNTIME with CONFIG_PM
  staging: ccree: replace macro with inline func
  staging: ccree: trim long lines for readability
  staging: ccree: remove dead defs and decls
  staging: ccree: refactor code with local vars
  staging: ccree: rename func for readability
  staging: ccree: rename long define for readability
  staging: ccree: remove unneeded wrapper function
  staging: ccree: remove unused field
  staging: ccree: replace msleep with a completion
  staging: ccree: use local vars for readability
  staging: ccree: drop unused macro

 drivers/staging/ccree/cc_hw_queue_defs.h |   2 -
 drivers/staging/ccree/ssi_aead.c | 195 ---
 drivers/staging/ccree/ssi_aead.h |  17 ++-
 drivers/staging/ccree/ssi_buffer_mgr.c   | 174 +++
 drivers/staging/ccree/ssi_cipher.c   | 100 ++--
 drivers/staging/ccree/ssi_cipher.h   |   5 +-
 drivers/staging/ccree/ssi_config.h   |   6 +-
 drivers/staging/ccree/ssi_driver.c   |  14 ++-
 drivers/staging/ccree/ssi_driver.h   |  23 ++--
 drivers/staging/ccree/ssi_fips.h |   3 +-
 drivers/staging/ccree/ssi_hash.c | 180 +---
 drivers/staging/ccree/ssi_hash.h |  14 ++-
 drivers/staging/ccree/ssi_ivgen.c|  13 ++-
 drivers/staging/ccree/ssi_ivgen.h|   3 +-
 drivers/staging/ccree/ssi_pm.c   |   6 +-
 drivers/staging/ccree/ssi_pm.h   |   2 +-
 drivers/staging/ccree/ssi_request_mgr.c  | 106 ++---
 drivers/staging/ccree/ssi_request_mgr.h  |   4 +-
 drivers/staging/ccree/ssi_sram_mgr.c |   2 +-
 drivers/staging/ccree/ssi_sysfs.c|  39 +--
 drivers/staging/ccree/ssi_sysfs.h|  23 
 21 files changed, 562 insertions(+), 369 deletions(-)

-- 
2.7.4

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Re: [PATCH v5 2/2] crypto: stm32 - Support for STM32 CRYP crypto module

[Fabien DESSENNE]

Hi Herbert,

Can you check if this patchset (removed the AEAD part as you suggested + 
libkcapi test OK as suggested by Corentin) can be applied now?

BR

Fabien


On 07/11/17 15:40, Fabien DESSENNE wrote:
>
> On 22/10/17 09:26, Corentin Labbe wrote:
>> On Thu, Oct 19, 2017 at 05:10:30PM +0200, Fabien Dessenne wrote:
>>> This module registers block cipher algorithms that make use of the
>>> STMicroelectronics STM32 crypto "CRYP1" hardware.
>>> The following algorithms are supported:
>>> - aes: ecb, cbc, ctr
>>> - des: ecb, cbc
>>> - tdes: ecb, cbc
>>>
>>> Signed-off-by: Fabien Dessenne 
>>> ---
>>>drivers/crypto/stm32/Kconfig  |9 +
>>>drivers/crypto/stm32/Makefile |3 +-
>>>drivers/crypto/stm32/stm32-cryp.c | 1172 
>>> +
>>>3 files changed, 1183 insertions(+), 1 deletion(-)
>>>create mode 100644 drivers/crypto/stm32/stm32-cryp.c
>>>
>>> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
>>> +static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
>>> +{
>>> +   unsigned int i, j;
>>> +   u32 *src;
>>> +   u8 d8[4];
>>> +
>>> +   src = sg_virt(cryp->in_sg) + _walked_in;
>>> +
>>> +   for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++) {
>>> +   if (likely(cryp->total_in >= sizeof(u32))) {
>>> +   /* Write a full u32 */
>>> +   stm32_cryp_write(cryp, CRYP_DIN, *src);
>> Hello
>>
>> Try also to test your driver with userspace via AF_ALG (libkcapi is a good 
>> start).
>> It should probably crash here.
>> I have do the same on my first sunxi-ss driver and you should use kmap().
>>
>> Regards
> Hi Corentin,
>
> Thank you for suggesting to test from userspace through the AF_ALG
> socket with libkcapi.
> This increases my test coverage.
>
> I ran the miscellaneous tests (kcapi-enc-test(large).sh + test.sh) and
> could not observe any crash.
> Note that I had already fixed some 'memory crashes' while testing with
> testmgr / tcrypt while testing from the kernel.
>
> So it looks like the proposed implementation is fine.
>
> BR
>
> Fabien

Re: [PATCH RESEND 1/4] crypto: caam: add caam-dma node to SEC4.0 device tree binding

[Radu Andrei Alexe]

On 11/10/2017 6:44 PM, Kim Phillips wrote:
> On Fri, 10 Nov 2017 08:02:01 +
> Radu Andrei Alexe  wrote:
> 
>> On 11/9/2017 6:34 PM, Kim Phillips wrote:
>>> On Thu, 9 Nov 2017 11:54:13 +
>>> Radu Andrei Alexe  wrote:
 The next patch version will create the platform device dynamically at
 run time.
>>>
>>> Why create a new device when that h/w already has one?
>>>
>>> Why doesn't the existing crypto driver register dma capabilities with
>>> the dma driver subsystem?
>>>
>> I can think of two reasons:
>>
>> 1. The code that this driver introduces has nothing to do with crypto
>> and everything to do with dma.
> 
> I would think that at least a crypto "null" algorithm implementation
> would share code.
>
>> Placing the code in the same directory as
>> the caam subsystem would only create confusion for the reader of an
>> already complex driver.
> 
> this different directory argument seems to be identical to your 2 below:
> 
>> 2. I wanted this driver to be tracked by the dma engine team. They have
>> the right expertise to provide adequate feedback. If all the code was in
>> the crypto directory they wouldn't know about this driver or any
>> subsequent changes to it.
> 
> dma subsystem bits could still be put in the dma area if deemed
> necessary but I don't think it is: I see
> drivers/crypto/ccp/ccp-dmaengine.c calls dma_async_device_register for
> example.
> 
> I also don't see how that complicates things much further.
> 

So who made their review? The guys from crypto?

If someone wants to enable only the DMA functionality of the CCP and not 
the crypto part how do they do it? Look for it in the crypto submenu?

> What is the rationale for using the crypto h/w as a dma engine anyway?
> Are there supporting performance figures?

We have a platform that doesn't have a dedicated DMA controller but has 
the CAAM hardware block that can perform dma transfers. We have a 
use-case where we need to issue large transfers (hundred of MBs) 
asynchronously, without using the core.

> 
> Kim
> 


BR,
Radu

Re: [PATCH RESEND 1/4] crypto: caam: add caam-dma node to SEC4.0 device tree binding

[Horia Geantă]

On 11/10/2017 6:44 PM, Kim Phillips wrote:
> On Fri, 10 Nov 2017 08:02:01 +
> Radu Andrei Alexe  wrote:
[snip]>> 2. I wanted this driver to be tracked by the dma engine team.
They have
>> the right expertise to provide adequate feedback. If all the code was in 
>> the crypto directory they wouldn't know about this driver or any 
>> subsequent changes to it.
> 
> dma subsystem bits could still be put in the dma area if deemed
> necessary but I don't think it is: I see
> drivers/crypto/ccp/ccp-dmaengine.c calls dma_async_device_register for
> example.
> 
Please see previous discussion with Vinod:
https://www.mail-archive.com/linux-crypto@vger.kernel.org/msg21468.html

> What is the rationale for using the crypto h/w as a dma engine anyway?
SoCs that don't have a system DMA, for e.g. LS1012A.

Horia