Crypto Fixes for 4.15
Hi Linus: This push fixes the following issues: - Racy use of ctx->rcvused in af_alg. - algif_aead crash in chacha20poly1305. - Freeing bogus pointer in pcrypt. - Build error on MIPS in mpi. - Memory leak in inside-secure. - Memory overwrite in inside-secure. - NULL pointer dereference in inside-secure. - State corruption in inside-secure. - Build error without CRYPTO_GF128MUL in chelsio. - Use after free in n2. Please pull from git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git linus Antoine Ténart (3): crypto: inside-secure - free requests even if their handling failed crypto: inside-secure - fix request allocations in invalidation path crypto: inside-secure - do not use areq->result for partial results Arnd Bergmann (1): crypto: chelsio - select CRYPTO_GF128MUL Eric Biggers (2): crypto: chacha20poly1305 - validate the digest size crypto: pcrypt - fix freeing pcrypt instances James Hogan (1): lib/mpi: Fix umul_ppmm() for MIPS64r6 Jan Engelhardt (1): crypto: n2 - cure use after free Jonathan Cameron (1): crypto: af_alg - Fix race around ctx->rcvused by making it atomic_t Ofer Heifetz (1): crypto: inside-secure - per request invalidation crypto/af_alg.c|4 +- crypto/algif_aead.c|2 +- crypto/algif_skcipher.c|2 +- crypto/chacha20poly1305.c |6 +- crypto/pcrypt.c| 19 ++--- drivers/crypto/chelsio/Kconfig |1 + drivers/crypto/inside-secure/safexcel.c|1 + drivers/crypto/inside-secure/safexcel_cipher.c | 85 -- drivers/crypto/inside-secure/safexcel_hash.c | 89 +--- drivers/crypto/n2_core.c |3 + include/crypto/if_alg.h|5 +- lib/mpi/longlong.h | 18 - 12 files changed, 173 insertions(+), 62 deletions(-) Thanks, -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH 6/8] net: caif: remove unused hardirq.h
Hi David, I'm not sure if CAIF is still maintained by Dmitry Tarnyagin. Do you have any comment on this one? Thanks, Yang On 12/7/17 11:13 AM, Yang Shi wrote: Hi folks, Any comment on this one? Thanks, Yang On 11/17/17 3:02 PM, Yang Shi wrote: Preempt counter APIs have been split out, currently, hardirq.h just includes irq_enter/exit APIs which are not used by caif at all. So, remove the unused hardirq.h. Signed-off-by: Yang Shi Cc: Dmitry Tarnyagin Cc: "David S. Miller" --- net/caif/cfpkt_skbuff.c | 1 - net/caif/chnl_net.c | 1 - 2 files changed, 2 deletions(-) diff --git a/net/caif/cfpkt_skbuff.c b/net/caif/cfpkt_skbuff.c index 71b6ab2..38c2b7a 100644 --- a/net/caif/cfpkt_skbuff.c +++ b/net/caif/cfpkt_skbuff.c @@ -8,7 +8,6 @@ #include #include -#include #include #include diff --git a/net/caif/chnl_net.c b/net/caif/chnl_net.c index 922ac1d..53ecda1 100644 --- a/net/caif/chnl_net.c +++ b/net/caif/chnl_net.c @@ -8,7 +8,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ":%s(): " fmt, __func__ #include -#include #include #include #include
Re: [ovs-dev] [PATCH 7/8] net: ovs: remove unused hardirq.h
Hi David, Any comment is appreciated. Thanks, Yang On 12/7/17 11:27 AM, Pravin Shelar wrote: On Fri, Nov 17, 2017 at 3:02 PM, Yang Shi wrote: Preempt counter APIs have been split out, currently, hardirq.h just includes irq_enter/exit APIs which are not used by openvswitch at all. So, remove the unused hardirq.h. Signed-off-by: Yang Shi Cc: Pravin Shelar Cc: "David S. Miller" Cc: d...@openvswitch.org Acked-by: Pravin B Shelar
Re: [PATCH 8/8] net: tipc: remove unused hardirq.h
Hi David, Any more comment on this change? Thanks, Yang On 12/7/17 5:40 PM, Ying Xue wrote: On 11/18/2017 07:02 AM, Yang Shi wrote: Preempt counter APIs have been split out, currently, hardirq.h just includes irq_enter/exit APIs which are not used by TIPC at all. So, remove the unused hardirq.h. Signed-off-by: Yang Shi Cc: Jon Maloy Cc: Ying Xue Cc: "David S. Miller" Tested-by: Ying Xue Acked-by: Ying Xue --- net/tipc/core.h | 1 - 1 file changed, 1 deletion(-) diff --git a/net/tipc/core.h b/net/tipc/core.h index 5cc5398..099e072 100644 --- a/net/tipc/core.h +++ b/net/tipc/core.h @@ -49,7 +49,6 @@ #include #include #include -#include #include #include #include
[PATCH v10 8/8] ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header
Clean up the ifdefs which conditionally defined the io{read|write}64
functions in favour of the new common io-64-nonatomic-lo-hi header.
Signed-off-by: Logan Gunthorpe
Cc: Jon Mason
---
drivers/ntb/hw/mscc/ntb_hw_switchtec.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
index afe8ed6f3b23..53d3a34cddf3 100644
--- a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
+++ b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver");
MODULE_VERSION("0.1");
@@ -35,35 +36,6 @@ module_param(use_lut_mws, bool, 0644);
MODULE_PARM_DESC(use_lut_mws,
"Enable the use of the LUT based memory windows");
-#ifndef ioread64
-#ifdef readq
-#define ioread64 readq
-#else
-#define ioread64 _ioread64
-static inline u64 _ioread64(void __iomem *mmio)
-{
- u64 low, high;
-
- low = ioread32(mmio);
- high = ioread32(mmio + sizeof(u32));
- return low | (high << 32);
-}
-#endif
-#endif
-
-#ifndef iowrite64
-#ifdef writeq
-#define iowrite64 writeq
-#else
-#define iowrite64 _iowrite64
-static inline void _iowrite64(u64 val, void __iomem *mmio)
-{
- iowrite32(val, mmio);
- iowrite32(val >> 32, mmio + sizeof(u32));
-}
-#endif
-#endif
-
#define SWITCHTEC_NTB_MAGIC 0x45CC0001
#define MAX_MWS 128
--
2.11.0
[PATCH v10 0/8] Add io{read|write}64 to io-64-atomic headers
This is v10 of my cleanup series to push a number of instances of people
defining their own io{read|write}64 functions into common headers seing
they don't exist in non-64bit systems. This series adds inline functions to the
io-64-nonatomic headers and then cleans up the drivers that defined their
own.
This cleanup was originally requested by Greg after he reviewed my
Switchtec NTB code.
Changes since v9:
- Rebased onto v4.15-rc6
- Fixed a couple of issues in the new version of the CAAM patch as
pointed out by Horia
Changes since v8:
- Rebased onto v4.15-rc2, as a result rewrote patch 7 seeing someone did
some similar cleanup in that area.
- Added a patch to clean up the Switchtec NTB driver which landed in
v4.15-rc1
Changes since v7:
- Fix minor nits from Andy Shevchenko
- Rebased onto v4.14-rc1
Changes since v6:
** none **
Changes since v5:
- Added a fix to the tilcdc driver to ensure it doesn't use the
non-atomic operation. (This includes adding io{read|write}64[be]_is_nonatomic
defines).
Changes since v4:
- Add functions so the powerpc implementation of iomap.c compiles. (As
noticed by Horia)
Changes since v3:
- I noticed powerpc didn't use the appropriate functions seeing
readq/writeq were not defined when iomap.h was included. Thus I've
included a patch to adjust this
- Fixed some mistakes with a couple of the defines in io-64-nonatomic*
headers
- Fixed a typo noticed by Horia.
(earlier versions were drastically different)
Logan Gunthorpe (8):
drm/tilcdc: ensure nonatomic iowrite64 is not used
powerpc: io.h: move iomap.h include so that it can use readq/writeq
defs
powerpc: iomap.c: introduce io{read|write}64_{lo_hi|hi_lo}
iomap: introduce io{read|write}64_{lo_hi|hi_lo}
io-64-nonatomic: add io{read|write}64[be]{_lo_hi|_hi_lo} macros
ntb: ntb_hw_intel: use io-64-nonatomic instead of in-driver hacks
crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64
ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common
header
arch/powerpc/include/asm/io.h | 6 +-
arch/powerpc/kernel/iomap.c| 40 ++
drivers/crypto/caam/regs.h | 30 +---
drivers/gpu/drm/tilcdc/tilcdc_regs.h | 2 +-
drivers/ntb/hw/intel/ntb_hw_intel.c| 30 +---
drivers/ntb/hw/mscc/ntb_hw_switchtec.c | 30 +---
include/asm-generic/iomap.h| 26 +--
include/linux/io-64-nonatomic-hi-lo.h | 64
include/linux/io-64-nonatomic-lo-hi.h | 64
lib/iomap.c| 132 +
10 files changed, 330 insertions(+), 94 deletions(-)
--
2.11.0
[PATCH v10 1/8] drm/tilcdc: ensure nonatomic iowrite64 is not used
Add a check to ensure iowrite64 is only used if it is atomic. It was decided in [1] that the tilcdc driver should not be using an atomic operation (so it was left out of this patchset). However, it turns out that through the drm code, a nonatomic header is actually included: include/linux/io-64-nonatomic-lo-hi.h is included from include/drm/drm_os_linux.h:9:0, from include/drm/drmP.h:74, from include/drm/drm_modeset_helper.h:26, from include/drm/drm_atomic_helper.h:33, from drivers/gpu/drm/tilcdc/tilcdc_crtc.c:19: And thus, without this change, this patchset would inadvertantly change the behaviour of the tilcdc driver. [1] lkml.kernel.org/r/cak8p3a2hho_zcnstzq7hmwsz5la5thu19fwzpun16imnyyn...@mail.gmail.com Signed-off-by: Logan Gunthorpe Reviewed-by: Andy Shevchenko Cc: Jyri Sarha Cc: Arnd Bergmann Cc: Tomi Valkeinen Cc: David Airlie --- drivers/gpu/drm/tilcdc/tilcdc_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h index 9d528c0a67a4..5048ebb86835 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h @@ -133,7 +133,7 @@ static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data) struct tilcdc_drm_private *priv = dev->dev_private; volatile void __iomem *addr = priv->mmio + reg; -#ifdef iowrite64 +#if defined(iowrite64) && !defined(iowrite64_is_nonatomic) iowrite64(data, addr); #else __iowmb(); -- 2.11.0
[PATCH v10 4/8] iomap: introduce io{read|write}64_{lo_hi|hi_lo}
In order to provide non-atomic functions for io{read|write}64 that will
use readq and writeq when appropriate. We define a number of variants
of these functions in the generic iomap that will do non-atomic
operations on pio but atomic operations on mmio.
These functions are only defined if readq and writeq are defined. If
they are not, then the wrappers that always use non-atomic operations
from include/linux/io-64-nonatomic*.h will be used.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Arnd Bergmann
Cc: Suresh Warrier
Cc: Nicholas Piggin
---
arch/powerpc/include/asm/io.h | 2 +
include/asm-generic/iomap.h | 26 +++--
lib/iomap.c | 132 ++
3 files changed, 154 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index af074923d598..4cc420cfaa78 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -788,8 +788,10 @@ extern void __iounmap_at(void *ea, unsigned long size);
#define mmio_read16be(addr)readw_be(addr)
#define mmio_read32be(addr)readl_be(addr)
+#define mmio_read64be(addr)readq_be(addr)
#define mmio_write16be(val, addr) writew_be(val, addr)
#define mmio_write32be(val, addr) writel_be(val, addr)
+#define mmio_write64be(val, addr) writeq_be(val, addr)
#define mmio_insb(addr, dst, count)readsb(addr, dst, count)
#define mmio_insw(addr, dst, count)readsw(addr, dst, count)
#define mmio_insl(addr, dst, count)readsl(addr, dst, count)
diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h
index 5b63b94ef6b5..5a4af0199b32 100644
--- a/include/asm-generic/iomap.h
+++ b/include/asm-generic/iomap.h
@@ -31,9 +31,16 @@ extern unsigned int ioread16(void __iomem *);
extern unsigned int ioread16be(void __iomem *);
extern unsigned int ioread32(void __iomem *);
extern unsigned int ioread32be(void __iomem *);
-#ifdef CONFIG_64BIT
-extern u64 ioread64(void __iomem *);
-extern u64 ioread64be(void __iomem *);
+
+#ifdef readq
+#define ioread64_lo_hi ioread64_lo_hi
+#define ioread64_hi_lo ioread64_hi_lo
+#define ioread64be_lo_hi ioread64be_lo_hi
+#define ioread64be_hi_lo ioread64be_hi_lo
+extern u64 ioread64_lo_hi(void __iomem *addr);
+extern u64 ioread64_hi_lo(void __iomem *addr);
+extern u64 ioread64be_lo_hi(void __iomem *addr);
+extern u64 ioread64be_hi_lo(void __iomem *addr);
#endif
extern void iowrite8(u8, void __iomem *);
@@ -41,9 +48,16 @@ extern void iowrite16(u16, void __iomem *);
extern void iowrite16be(u16, void __iomem *);
extern void iowrite32(u32, void __iomem *);
extern void iowrite32be(u32, void __iomem *);
-#ifdef CONFIG_64BIT
-extern void iowrite64(u64, void __iomem *);
-extern void iowrite64be(u64, void __iomem *);
+
+#ifdef writeq
+#define iowrite64_lo_hi iowrite64_lo_hi
+#define iowrite64_hi_lo iowrite64_hi_lo
+#define iowrite64be_lo_hi iowrite64be_lo_hi
+#define iowrite64be_hi_lo iowrite64be_hi_lo
+extern void iowrite64_lo_hi(u64 val, void __iomem *addr);
+extern void iowrite64_hi_lo(u64 val, void __iomem *addr);
+extern void iowrite64be_lo_hi(u64 val, void __iomem *addr);
+extern void iowrite64be_hi_lo(u64 val, void __iomem *addr);
#endif
/*
diff --git a/lib/iomap.c b/lib/iomap.c
index 541d926da95e..d324b6c013af 100644
--- a/lib/iomap.c
+++ b/lib/iomap.c
@@ -67,6 +67,7 @@ static void bad_io_access(unsigned long port, const char
*access)
#ifndef mmio_read16be
#define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
+#define mmio_read64be(addr) be64_to_cpu(__raw_readq(addr))
#endif
unsigned int ioread8(void __iomem *addr)
@@ -100,6 +101,80 @@ EXPORT_SYMBOL(ioread16be);
EXPORT_SYMBOL(ioread32);
EXPORT_SYMBOL(ioread32be);
+#ifdef readq
+static u64 pio_read64_lo_hi(unsigned long port)
+{
+ u64 lo, hi;
+
+ lo = inl(port);
+ hi = inl(port + sizeof(u32));
+
+ return lo | (hi << 32);
+}
+
+static u64 pio_read64_hi_lo(unsigned long port)
+{
+ u64 lo, hi;
+
+ hi = inl(port + sizeof(u32));
+ lo = inl(port);
+
+ return lo | (hi << 32);
+}
+
+static u64 pio_read64be_lo_hi(unsigned long port)
+{
+ u64 lo, hi;
+
+ lo = pio_read32be(port + sizeof(u32));
+ hi = pio_read32be(port);
+
+ return lo | (hi << 32);
+}
+
+static u64 pio_read64be_hi_lo(unsigned long port)
+{
+ u64 lo, hi;
+
+ hi = pio_read32be(port);
+ lo = pio_read32be(port + sizeof(u32));
+
+ return lo | (hi << 32);
+}
+
+u64 ioread64_lo_hi(void __iomem *addr)
+{
+ IO_COND(addr, return pio_read64_lo_hi(port), return readq(addr));
+ return 0xULL;
+}
+
+u64 ioread64_hi_lo(void __iomem *addr)
+{
+ IO_COND(addr, return pio_read64_hi_lo(port), return readq(addr));
+ return 0xULL;
+}
+
+u64 ioread64be_lo_
[PATCH v10 3/8] powerpc: iomap.c: introduce io{read|write}64_{lo_hi|hi_lo}
These functions will be introduced into the generic iomap.c so
they can deal with PIO accesses in hi-lo/lo-hi variants. Thus,
the powerpc version of iomap.c will need to provide the same
functions even though, in this arch, they are identical to the
regular io{read|write}64 functions.
Signed-off-by: Logan Gunthorpe
Tested-by: Horia Geantă
Reviewed-by: Andy Shevchenko
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
---
arch/powerpc/kernel/iomap.c | 40
1 file changed, 40 insertions(+)
diff --git a/arch/powerpc/kernel/iomap.c b/arch/powerpc/kernel/iomap.c
index aab456ed2a00..5ac84efc6ede 100644
--- a/arch/powerpc/kernel/iomap.c
+++ b/arch/powerpc/kernel/iomap.c
@@ -45,12 +45,32 @@ u64 ioread64(void __iomem *addr)
{
return readq(addr);
}
+u64 ioread64_lo_hi(void __iomem *addr)
+{
+ return readq(addr);
+}
+u64 ioread64_hi_lo(void __iomem *addr)
+{
+ return readq(addr);
+}
u64 ioread64be(void __iomem *addr)
{
return readq_be(addr);
}
+u64 ioread64be_lo_hi(void __iomem *addr)
+{
+ return readq_be(addr);
+}
+u64 ioread64be_hi_lo(void __iomem *addr)
+{
+ return readq_be(addr);
+}
EXPORT_SYMBOL(ioread64);
+EXPORT_SYMBOL(ioread64_lo_hi);
+EXPORT_SYMBOL(ioread64_hi_lo);
EXPORT_SYMBOL(ioread64be);
+EXPORT_SYMBOL(ioread64be_lo_hi);
+EXPORT_SYMBOL(ioread64be_hi_lo);
#endif /* __powerpc64__ */
void iowrite8(u8 val, void __iomem *addr)
@@ -83,12 +103,32 @@ void iowrite64(u64 val, void __iomem *addr)
{
writeq(val, addr);
}
+void iowrite64_lo_hi(u64 val, void __iomem *addr)
+{
+ writeq(val, addr);
+}
+void iowrite64_hi_lo(u64 val, void __iomem *addr)
+{
+ writeq(val, addr);
+}
void iowrite64be(u64 val, void __iomem *addr)
{
writeq_be(val, addr);
}
+void iowrite64be_lo_hi(u64 val, void __iomem *addr)
+{
+ writeq_be(val, addr);
+}
+void iowrite64be_hi_lo(u64 val, void __iomem *addr)
+{
+ writeq_be(val, addr);
+}
EXPORT_SYMBOL(iowrite64);
+EXPORT_SYMBOL(iowrite64_lo_hi);
+EXPORT_SYMBOL(iowrite64_hi_lo);
EXPORT_SYMBOL(iowrite64be);
+EXPORT_SYMBOL(iowrite64be_lo_hi);
+EXPORT_SYMBOL(iowrite64be_hi_lo);
#endif /* __powerpc64__ */
/*
--
2.11.0
[PATCH v10 5/8] io-64-nonatomic: add io{read|write}64[be]{_lo_hi|_hi_lo} macros
This patch adds generic io{read|write}64[be]{_lo_hi|_hi_lo} macros if
they are not already defined by the architecture. (As they are provided
by the generic iomap library).
The patch also points io{read|write}64[be] to the variant specified by the
header name.
This is because new drivers are encouraged to use ioreadXX, et al instead
of readX[1], et al -- and mixing ioreadXX with readq is pretty ugly.
[1] LDD3: section 9.4.2
Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Cc: Christoph Hellwig
Cc: Arnd Bergmann
Cc: Alan Cox
Cc: Greg Kroah-Hartman
---
include/linux/io-64-nonatomic-hi-lo.h | 64 +++
include/linux/io-64-nonatomic-lo-hi.h | 64 +++
2 files changed, 128 insertions(+)
diff --git a/include/linux/io-64-nonatomic-hi-lo.h
b/include/linux/io-64-nonatomic-hi-lo.h
index 862d786a904f..ae21b72cce85 100644
--- a/include/linux/io-64-nonatomic-hi-lo.h
+++ b/include/linux/io-64-nonatomic-hi-lo.h
@@ -55,4 +55,68 @@ static inline void hi_lo_writeq_relaxed(__u64 val, volatile
void __iomem *addr)
#define writeq_relaxed hi_lo_writeq_relaxed
#endif
+#ifndef ioread64_hi_lo
+#define ioread64_hi_lo ioread64_hi_lo
+static inline u64 ioread64_hi_lo(void __iomem *addr)
+{
+ u32 low, high;
+
+ high = ioread32(addr + sizeof(u32));
+ low = ioread32(addr);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
+#ifndef iowrite64_hi_lo
+#define iowrite64_hi_lo iowrite64_hi_lo
+static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
+{
+ iowrite32(val >> 32, addr + sizeof(u32));
+ iowrite32(val, addr);
+}
+#endif
+
+#ifndef ioread64be_hi_lo
+#define ioread64be_hi_lo ioread64be_hi_lo
+static inline u64 ioread64be_hi_lo(void __iomem *addr)
+{
+ u32 low, high;
+
+ high = ioread32be(addr);
+ low = ioread32be(addr + sizeof(u32));
+
+ return low + ((u64)high << 32);
+}
+#endif
+
+#ifndef iowrite64be_hi_lo
+#define iowrite64be_hi_lo iowrite64be_hi_lo
+static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
+{
+ iowrite32be(val >> 32, addr);
+ iowrite32be(val, addr + sizeof(u32));
+}
+#endif
+
+#ifndef ioread64
+#define ioread64_is_nonatomic
+#define ioread64 ioread64_hi_lo
+#endif
+
+#ifndef iowrite64
+#define iowrite64_is_nonatomic
+#define iowrite64 iowrite64_hi_lo
+#endif
+
+#ifndef ioread64be
+#define ioread64be_is_nonatomic
+#define ioread64be ioread64be_hi_lo
+#endif
+
+#ifndef iowrite64be
+#define iowrite64be_is_nonatomic
+#define iowrite64be iowrite64be_hi_lo
+#endif
+
#endif /* _LINUX_IO_64_NONATOMIC_HI_LO_H_ */
diff --git a/include/linux/io-64-nonatomic-lo-hi.h
b/include/linux/io-64-nonatomic-lo-hi.h
index d042e7bb5adb..faaa842dbdb9 100644
--- a/include/linux/io-64-nonatomic-lo-hi.h
+++ b/include/linux/io-64-nonatomic-lo-hi.h
@@ -55,4 +55,68 @@ static inline void lo_hi_writeq_relaxed(__u64 val, volatile
void __iomem *addr)
#define writeq_relaxed lo_hi_writeq_relaxed
#endif
+#ifndef ioread64_lo_hi
+#define ioread64_lo_hi ioread64_lo_hi
+static inline u64 ioread64_lo_hi(void __iomem *addr)
+{
+ u32 low, high;
+
+ low = ioread32(addr);
+ high = ioread32(addr + sizeof(u32));
+
+ return low + ((u64)high << 32);
+}
+#endif
+
+#ifndef iowrite64_lo_hi
+#define iowrite64_lo_hi iowrite64_lo_hi
+static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
+{
+ iowrite32(val, addr);
+ iowrite32(val >> 32, addr + sizeof(u32));
+}
+#endif
+
+#ifndef ioread64be_lo_hi
+#define ioread64be_lo_hi ioread64be_lo_hi
+static inline u64 ioread64be_lo_hi(void __iomem *addr)
+{
+ u32 low, high;
+
+ low = ioread32be(addr + sizeof(u32));
+ high = ioread32be(addr);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
+#ifndef iowrite64be_lo_hi
+#define iowrite64be_lo_hi iowrite64be_lo_hi
+static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
+{
+ iowrite32be(val, addr + sizeof(u32));
+ iowrite32be(val >> 32, addr);
+}
+#endif
+
+#ifndef ioread64
+#define ioread64_is_nonatomic
+#define ioread64 ioread64_lo_hi
+#endif
+
+#ifndef iowrite64
+#define iowrite64_is_nonatomic
+#define iowrite64 iowrite64_lo_hi
+#endif
+
+#ifndef ioread64be
+#define ioread64be_is_nonatomic
+#define ioread64be ioread64be_lo_hi
+#endif
+
+#ifndef iowrite64be
+#define iowrite64be_is_nonatomic
+#define iowrite64be iowrite64be_lo_hi
+#endif
+
#endif /* _LINUX_IO_64_NONATOMIC_LO_HI_H_ */
--
2.11.0
[PATCH v10 2/8] powerpc: io.h: move iomap.h include so that it can use readq/writeq defs
Subsequent patches in this series makes use of the readq and writeq defines in iomap.h. However, as is, they get missed on the powerpc platform seeing the include comes before the define. This patch moves the include down to fix this. Signed-off-by: Logan Gunthorpe Acked-by: Michael Ellerman Reviewed-by: Andy Shevchenko Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Suresh Warrier Cc: "Oliver O'Halloran" --- arch/powerpc/include/asm/io.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 422f99cf9924..af074923d598 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -33,8 +33,6 @@ extern struct pci_dev *isa_bridge_pcidev; #include #include -#include - #ifdef CONFIG_PPC64 #include #endif @@ -663,6 +661,8 @@ static inline void name at \ #define writel_relaxed(v, addr)writel(v, addr) #define writeq_relaxed(v, addr)writeq(v, addr) +#include + #ifdef CONFIG_PPC32 #define mmiowb() #else -- 2.11.0
[PATCH v10 7/8] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64
Clean up the extra ifdefs which defined the wr_reg64 and rd_reg64
functions in non-64bit cases in favour of the new common
io-64-nonatomic-lo-hi header.
To be consistent with CAAM engine HW spec: in case of 64-bit registers,
irrespective of device endianness, the lower address should be read from
/ written to first, followed by the upper address. Indeed the I/O
accessors in CAAM driver currently don't follow the spec, however this
is a good opportunity to fix the code.
Signed-off-by: Logan Gunthorpe
Cc: Andy Shevchenko
Cc: Horia Geantă
Cc: Dan Douglass
Cc: Herbert Xu
Cc: "David S. Miller"
---
drivers/crypto/caam/regs.h | 30 +++---
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index fee363865d88..f887b371040f 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
/*
* Architecture-specific register access methods
@@ -136,10 +136,9 @@ static inline void clrsetbits_32(void __iomem *reg, u32
clear, u32 set)
*base + 0x : least-significant 32 bits
*base + 0x0004 : most-significant 32 bits
*/
-#ifdef CONFIG_64BIT
static inline void wr_reg64(void __iomem *reg, u64 data)
{
- if (caam_little_end)
+ if (!caam_imx && caam_little_end)
iowrite64(data, reg);
else
iowrite64be(data, reg);
@@ -147,35 +146,12 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
static inline u64 rd_reg64(void __iomem *reg)
{
- if (caam_little_end)
+ if (!caam_imx && caam_little_end)
return ioread64(reg);
else
return ioread64be(reg);
}
-#else /* CONFIG_64BIT */
-static inline void wr_reg64(void __iomem *reg, u64 data)
-{
- if (!caam_imx && caam_little_end) {
- wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
- wr_reg32((u32 __iomem *)(reg), data);
- } else {
- wr_reg32((u32 __iomem *)(reg), data >> 32);
- wr_reg32((u32 __iomem *)(reg) + 1, data);
- }
-}
-
-static inline u64 rd_reg64(void __iomem *reg)
-{
- if (!caam_imx && caam_little_end)
- return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
- (u64)rd_reg32((u32 __iomem *)(reg)));
-
- return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
- (u64)rd_reg32((u32 __iomem *)(reg) + 1));
-}
-#endif /* CONFIG_64BIT */
-
static inline u64 cpu_to_caam_dma64(dma_addr_t value)
{
if (caam_imx)
--
2.11.0
[PATCH v10 6/8] ntb: ntb_hw_intel: use io-64-nonatomic instead of in-driver hacks
Now that ioread64 and iowrite64 are available in io-64-nonatomic,
we can remove the hack at the top of ntb_hw_intel.c and replace it
with an include.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Acked-by: Dave Jiang
Acked-by: Allen Hubbe
Acked-by: Jon Mason
# Please enter the commit message for your changes. Lines starting
# with '#' will be ignored, and an empty message aborts the commit.
#
# Date: Mon Jun 19 12:18:31 2017 -0600
#
# interactive rebase in progress; onto ae64f9bd1d36
# Last commands done (6 commands done):
#pick cf3e4dab2173 io-64-nonatomic: add io{read|write}64[be]{_lo_hi|_hi_lo}
macros
#r 79b4c4b8490c ntb: ntb_hw_intel: use io-64-nonatomic instead of in-driver
hacks
# Next commands to do (2 remaining commands):
#r 19b6c1f3b15d crypto: caam: cleanup CONFIG_64BIT ifdefs when using
io{read|write}64
#r f3c8723446ef ntb_hw_switchtec: Cleanup 64bit IO defines to use the
common header
# You are currently editing a commit while rebasing branch 'io64_v9' on
'ae64f9bd1d36'.
#
# Changes to be committed:
# modified: drivers/ntb/hw/intel/ntb_hw_intel.c
#
---
drivers/ntb/hw/intel/ntb_hw_intel.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c
b/drivers/ntb/hw/intel/ntb_hw_intel.c
index 4de074a86073..119cfc45617e 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.c
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
@@ -59,6 +59,7 @@
#include
#include
#include
+#include
#include "ntb_hw_intel.h"
@@ -155,35 +156,6 @@ MODULE_PARM_DESC(xeon_b2b_dsd_bar5_addr32,
static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);
static int xeon_init_isr(struct intel_ntb_dev *ndev);
-#ifndef ioread64
-#ifdef readq
-#define ioread64 readq
-#else
-#define ioread64 _ioread64
-static inline u64 _ioread64(void __iomem *mmio)
-{
- u64 low, high;
-
- low = ioread32(mmio);
- high = ioread32(mmio + sizeof(u32));
- return low | (high << 32);
-}
-#endif
-#endif
-
-#ifndef iowrite64
-#ifdef writeq
-#define iowrite64 writeq
-#else
-#define iowrite64 _iowrite64
-static inline void _iowrite64(u64 val, void __iomem *mmio)
-{
- iowrite32(val, mmio);
- iowrite32(val >> 32, mmio + sizeof(u32));
-}
-#endif
-#endif
-
static inline int pdev_is_atom(struct pci_dev *pdev)
{
switch (pdev->device) {
--
2.11.0
Re: [PATCH v9 7/8] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64
On 04/01/18 12:25 AM, Horia Geantă wrote:
+#include
Typo: lo-hi should be used instead (see previous patch versions).
Please add in the commit message the explanation (which was there in v8 but
removed in v9):
To be consistent with CAAM engine HW spec: in case of 64-bit registers,
irrespective of device endianness, the lower address should be read from
/ written to first, followed by the upper address. Indeed the I/O
accessors in CAAM driver currently don't follow the spec, however this
is a good opportunity to fix the code.
Ok, well I just copied what the latest code did. I assumed that seeing
it was cleaned up very recently that they would have done it correctly.
/*
* Architecture-specific register access methods
@@ -136,7 +136,6 @@ static inline void clrsetbits_32(void __iomem *reg, u32
clear, u32 set)
*base + 0x : least-significant 32 bits
*base + 0x0004 : most-significant 32 bits
*/
-#ifdef CONFIG_64BIT
static inline void wr_reg64(void __iomem *reg, u64 data)
{
if (caam_little_end)
Since the 2 cases (32/64-bit) are merged, caam_imx should be accounted for the
logic to stay the same.
Oops, my mistake. I'll fix this and the above and send a revised set.
Logan
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Re: [PATCH] [v2] crypto: aes-generic - build with -Os on gcc-7+
On 3 January 2018 at 22:39, Arnd Bergmann wrote: > While testing other changes, I discovered that gcc-7.2.1 produces badly > optimized code for aes_encrypt/aes_decrypt. This is especially true when > CONFIG_UBSAN_SANITIZE_ALL is enabled, where it leads to extremely > large stack usage that in turn might cause kernel stack overflows: > > crypto/aes_generic.c: In function 'aes_encrypt': > crypto/aes_generic.c:1371:1: warning: the frame size of 4880 bytes is larger > than 2048 bytes [-Wframe-larger-than=] > crypto/aes_generic.c: In function 'aes_decrypt': > crypto/aes_generic.c:1441:1: warning: the frame size of 4864 bytes is larger > than 2048 bytes [-Wframe-larger-than=] > > I verified that this problem exists on all architectures that are > supported by gcc-7.2, though arm64 in particular is less affected than > the others. I also found that gcc-7.1 and gcc-8 do not show the extreme > stack usage but still produce worse code than earlier versions for this > file, apparently because of optimization passes that generally provide > a substantial improvement in object code quality but understandably fail > to find any shortcuts in the AES algorithm. > > Possible workarounds include > > a) disabling -ftree-pre and -ftree-sra optimizations, this was an earlier >patch I tried, which reliably fixed the stack usage, but caused a >serious performance regression in some versions, as later testing >found. > > b) disabling UBSAN on this file or all ciphers, as suggested by Ard >Biesheuvel. This would lead to massively better crypto performance in >UBSAN-enabled kernels and avoid the stack usage, but there is a concern >over whether we should exclude arbitrary files from UBSAN at all. > > c) Forcing the optimization level in a different way. Similar to a), >but rather than deselecting specific optimization stages, >this now uses "gcc -Os" for this file, regardless of the >CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE/SIZE option. This is a reliable >workaround for the stack consumption on all architecture, and I've >retested the performance results now on x86, cycles/byte (lower is >better) for cbc(aes-generic) with 256 bit keys: > > -O2 -Os > gcc-6.3.1 14.915.1 > gcc-7.0.1 14.715.3 > gcc-7.1.1 15.314.7 > gcc-7.2.1 16.815.9 > gcc-8.0.0 15.515.6 > > This implements the option c) by enabling forcing -Os on all compiler > versions starting with gcc-7.1. As a workaround for PR83356, it would > only be needed for gcc-7.2+ with UBSAN enabled, but since it also shows > better performance on gcc-7.1 without UBSAN, it seems appropriate to > use the faster version here as well. > > Side note: during testing, I also played with the AES code in libressl, > which had a similar performance regression from gcc-6 to gcc-7.2, > but was three times slower overall. It might be interesting to > investigate that further and possibly port the Linux implementation > into that. > > Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83356 > Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83651 > Cc: Richard Biener > Cc: Jakub Jelinek > Cc: Ard Biesheuvel > Signed-off-by: Arnd Bergmann Acked-by: Ard Biesheuvel > --- > crypto/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/crypto/Makefile b/crypto/Makefile > index d674884b2d51..daa69360e054 100644 > --- a/crypto/Makefile > +++ b/crypto/Makefile > @@ -99,6 +99,7 @@ obj-$(CONFIG_CRYPTO_TWOFISH_COMMON) += twofish_common.o > obj-$(CONFIG_CRYPTO_SERPENT) += serpent_generic.o > CFLAGS_serpent_generic.o := $(call cc-option,-fsched-pressure) # > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149 > obj-$(CONFIG_CRYPTO_AES) += aes_generic.o > +CFLAGS_aes_generic.o := $(call cc-ifversion, -ge, 0701, -Os) # > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83356 > obj-$(CONFIG_CRYPTO_AES_TI) += aes_ti.o > obj-$(CONFIG_CRYPTO_CAMELLIA) += camellia_generic.o > obj-$(CONFIG_CRYPTO_CAST_COMMON) += cast_common.o > -- > 2.9.0 >
