[PATCH v5] crypto : stm32 - Add STM32F4 CRC32 support
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
Changes in v5:
- shash_alg struct definitons are defined seperately according to
the platform type.
Changes in v4:
- Edited patch summary.
Changes in v3:
- Rearranged patch order to fix build test error.
Changes in v2:
- Patchset created instead of one patch.
drivers/crypto/stm32/stm32_crc32.c | 101 -
1 file changed, 89 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..39b28b8 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -1,12 +1,14 @@
/*
* Copyright (C) STMicroelectronics SA 2017
* Author: Fabien Dessenne <fabien.desse...@st.com>
+ * Author: Cosar Dindar <cosardin...@gmail.com>
* License terms: GNU General Public License (GPL), version 2
*/
#include
#include
#include
+#include
#include
#include
@@ -37,8 +39,12 @@ struct stm32_crc {
struct device*dev;
void __iomem *regs;
struct clk *clk;
+ struct shash_alg *algs;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +112,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should be:
0x%x\n",
+ CRC_INIT_DEFAULT);
+ return -EINVAL;
+ }
+
+ /* set poly */
+ if (ctx->crc->poly_support)
+ writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+ /* reset and configure in bit reverse mode if supported */
+ if (ctx->crc->reverse_support)
+ writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ else
+ writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+ /* store partial result */
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(ctx->crc->regs + CRC_DR);
- /* Store partial result */
- ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
return 0;
@@ -135,7 +159,12 @@ static int stm32_crc_update(struct shash_desc *desc, const
u8 *d8,
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
- writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(u32 *)crc->pending_data),
+ crc->regs + CRC_DR);
+ else
+ writel(*(u32 *)crc->pending_data,
+ crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +172,16 @@ static int stm32_crc_update(struct shash_desc *desc,
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
- writel(*(d32++), crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+ else
+ writel(*(d32++), crc->regs + CRC_DR);
/* Store partial result */
- ctx->partial = readl(crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(crc->regs + CRC_DR);
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -192,7 +227,7 @@ static int stm32_crc_digest(struct shash_desc *desc, const
u8 *data,
return stm32_crc_init(desc) ?:
Re: [RESEND,PATCH v4 3/3] crypto : stm32 - Add STM32F4 CRC32 support
On Thu, Aug 03, 2017 at 01:44:23PM +0800, Herbert Xu wrote: > On Mon, Jul 17, 2017 at 11:27:36AM +0300, Cosar Dindar wrote: > > This patch adds CRC (CRC32 Crypto) support for STM32F4 series. > > > > As an hardware limitation polynomial and key setting are not supported. > > They are fixed as 0x4C11DB7 (poly) and 0x (key). > > CRC32C Castagnoli algorithm is not used. > > > > Signed-off-by: Cosar Dindar <cosardin...@gmail.com> > > Reviewed-by: Fabien Dessenne <fabien.desse...@st.com> > > This patch doesn't apply anymore. Please rebase. > > Thanks, OK, I'll rebase and send a new patch including new changes. Thanks, Best Regards, Cosar. > -- > Email: Herbert Xu <herb...@gondor.apana.org.au> > Home Page: http://gondor.apana.org.au/~herbert/ > PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [RESEND,PATCH v4 3/3] crypto : stm32 - Add STM32F4 CRC32 support
On Mon, Jul 17, 2017 at 02:23:44PM +, Lionel DEBIEVE wrote:
> Hi Cosar,
>
> - ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
> + /* For F4 series only CRC32 algorithm will be used */
> + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc"))
> + algs_size = 1;
> + else
> + algs_size = ARRAY_SIZE(algs);
> +
> + ret = crypto_register_shashes(algs, algs_size);
>
> Should it be better to have a dedicated array per platform data instead?
> Could be new platform update?
>
> BR,
>
> Lionel
>
Hi Lionel,
Thanks for the comment.
It might be better to seperate shash_alg array according to the platform, one
alg array for F7 and one for M4.
Adding a new array definition for M4 platform with only CRC-32 algorithm might
be enough.
This action would be necessary since it might cause problem while unregistering
with your last patch.
BR,
Cosar
>
> On 07/17/2017 10:27 AM, Cosar Dindar wrote:
> > This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
> >
> > As an hardware limitation polynomial and key setting are not supported.
> > They are fixed as 0x4C11DB7 (poly) and 0x (key).
> > CRC32C Castagnoli algorithm is not used.
> >
> > Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
> > Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
> > ---
> > drivers/crypto/stm32/stm32_crc32.c | 68
> > --
> > 1 file changed, 58 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/crypto/stm32/stm32_crc32.c
> > b/drivers/crypto/stm32/stm32_crc32.c
> > index ec83b1e..12fbd98 100644
> > --- a/drivers/crypto/stm32/stm32_crc32.c
> > +++ b/drivers/crypto/stm32/stm32_crc32.c
> > @@ -7,6 +7,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > #include
> > @@ -39,6 +40,9 @@ struct stm32_crc {
> > struct clk *clk;
> > u8 pending_data[sizeof(u32)];
> > size_t nb_pending_bytes;
> > + bool key_support;
> > + bool poly_support;
> > + bool reverse_support;
> > };
> >
> > struct stm32_crc_list {
> > @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
> > }
> > spin_unlock_bh(_list.lock);
> >
> > - /* Reset, set key, poly and configure in bit reverse mode */
> > - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> > - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> > - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> > + /* set key */
> > + if (ctx->crc->key_support) {
> > + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> > + } else if (mctx->key != CRC_INIT_DEFAULT) {
> > + dev_err(ctx->crc->dev, "Unsupported key value! Should be:
> > 0x%x\n",
> > + CRC_INIT_DEFAULT);
> > + return -EINVAL;
> > + }
> > +
> > + /* set poly */
> > + if (ctx->crc->poly_support)
> > + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> > +
> > + /* reset and configure in bit reverse mode if supported */
> > + if (ctx->crc->reverse_support)
> > + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> > + else
> > + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> > +
> > + /* store partial result */
> > + if (!ctx->crc->reverse_support)
> > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> > + else
> > + ctx->partial = readl(ctx->crc->regs + CRC_DR);
> >
> > - /* Store partial result */
> > - ctx->partial = readl(ctx->crc->regs + CRC_DR);
> > ctx->crc->nb_pending_bytes = 0;
> >
> > return 0;
> > @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc,
> > const u8 *d8,
> >
> > if (crc->nb_pending_bytes == sizeof(u32)) {
> > /* Process completed pending data */
> > - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> > + if (!ctx->crc->reverse_support)
> > + writel(bitrev32(*(u32 *)crc->pending_data),
> > + crc->regs + CRC_DR);
> > + else
>
[RESEND,PATCH v4 3/3] crypto : stm32 - Add STM32F4 CRC32 support
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
---
drivers/crypto/stm32/stm32_crc32.c | 68 --
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk *clk;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should be:
0x%x\n",
+ CRC_INIT_DEFAULT);
+ return -EINVAL;
+ }
+
+ /* set poly */
+ if (ctx->crc->poly_support)
+ writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+ /* reset and configure in bit reverse mode if supported */
+ if (ctx->crc->reverse_support)
+ writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ else
+ writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+ /* store partial result */
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(ctx->crc->regs + CRC_DR);
- /* Store partial result */
- ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const
u8 *d8,
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
- writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(u32 *)crc->pending_data),
+ crc->regs + CRC_DR);
+ else
+ writel(*(u32 *)crc->pending_data,
+ crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc,
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
- writel(*(d32++), crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+ else
+ writel(*(d32++), crc->regs + CRC_DR);
/* Store partial result */
- ctx->partial = readl(crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(crc->regs + CRC_DR);
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
struct stm32_crc *crc;
struct resource *res;
int ret;
+ int algs_size;
crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret;
}
+ /* set key, poly and reverse support if device is of F7 series */
+ if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+ crc->key_support = true;
+ crc->poly_support = true;
+ crc->reverse_support = tr
[RESEND,PATCH v4 2/3] dt-bindings : Document the STM32F4 CRC32 binding
Add device tree binding for STM32F4. Signed-off-by: Cosar Dindar <cosardin...@gmail.com> --- Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt index 3ba92a5..1e9af69 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt @@ -1,7 +1,9 @@ * STMicroelectronics STM32 CRC Required properties: -- compatible: Should be "st,stm32f7-crc". +- compatible: Should be one of the following string. + "st,stm32f7-crc" + "st,stm32f4-crc" - reg: The address and length of the peripheral registers space - clocks: The input clock of the CRC instance -- 2.7.4
[RESEND,PATCH v4 0/2] Add support for the STM32F4 CRC32
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.
Changes in v4:
- Edited patchset brief.
Cosar Dindar (2):
dt-bindings : Document the STM32F4 CRC32 binding
crypto : stm32 - Add STM32F4 CRC32 support
[RESEND,PATCH v4 2/5] crypto : stm32 - Add STM32F4 CRC32 support
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
Reviewed-by: Fabien Dessenne <fabien.desse...@st.com>
---
Changes in v4:
- Add Fabien Dessenne's Reviewed-by tag.
drivers/crypto/stm32/stm32_crc32.c | 68 --
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk *clk;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should be:
0x%x\n",
+ CRC_INIT_DEFAULT);
+ return -EINVAL;
+ }
+
+ /* set poly */
+ if (ctx->crc->poly_support)
+ writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+ /* reset and configure in bit reverse mode if supported */
+ if (ctx->crc->reverse_support)
+ writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ else
+ writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+ /* store partial result */
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(ctx->crc->regs + CRC_DR);
- /* Store partial result */
- ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const
u8 *d8,
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
- writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(u32 *)crc->pending_data),
+ crc->regs + CRC_DR);
+ else
+ writel(*(u32 *)crc->pending_data,
+ crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc,
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
- writel(*(d32++), crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+ else
+ writel(*(d32++), crc->regs + CRC_DR);
/* Store partial result */
- ctx->partial = readl(crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(crc->regs + CRC_DR);
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
struct stm32_crc *crc;
struct resource *res;
int ret;
+ int algs_size;
crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret;
}
+ /* set key, poly and reverse support if device is of F7 series */
+ if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+ crc->key_support = true;
+ crc-
[RESEND,PATCH v4 1/5] dt-bindings : Document the STM32F4 CRC32 binding
Add device tree binding for STM32F4. Signed-off-by: Cosar Dindar <cosardin...@gmail.com> --- Changes in V4: - Edited binding explanations. Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt index 3ba92a5..1e9af69 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt @@ -1,7 +1,9 @@ * STMicroelectronics STM32 CRC Required properties: -- compatible: Should be "st,stm32f7-crc". +- compatible: Should be one of the following string. + "st,stm32f7-crc" + "st,stm32f4-crc" - reg: The address and length of the peripheral registers space - clocks: The input clock of the CRC instance -- 2.7.4
[RESEND,PATCH v4 0/5] Add support for the STM32F4 CRC32
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.
Changes in v4:
- Edited patch summary.
Cosar Dindar (5):
dt-bindings : Document the STM32F4 CRC32 binding
crypto : stm32 - Add STM32F4 CRC32 support
ARM: dts: stm32: Add CRC support to stm32f429 (Merged-by Alexander TORGUE)
ARM: dts: stm32: enable CRC32 on stm32429-disco board (Merged-by Alexander
TORGUE)
ARM: dts: stm32: enable CRC32 on stm32429i-eval board (Merged-by Alexander
TORGUE)
.../devicetree/bindings/crypto/st,stm32-crc.txt| 4 +-
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
drivers/crypto/stm32/stm32_crc32.c | 68 ++
5 files changed, 75 insertions(+), 12 deletions(-)
--
2.7.4
Re: [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support
Hi Fabien,
Thanks for your review.
On Mon, May 29, 2017 at 07:56:48AM +, Fabien DESSENNE wrote:
> Hi Cosar,
>
> Thank you for the patch
>
> On 22/05/17 16:34, Cosar Dindar wrote:
> > This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
> >
> > As an hardware limitation polynomial and key setting are not supported.
> > They are fixed as 0x4C11DB7 (poly) and 0x (key).
> > CRC32C Castagnoli algorithm is not used.
> >
> > Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
> > ---
> > drivers/crypto/stm32/stm32_crc32.c | 68
> > --
> > 1 file changed, 58 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/crypto/stm32/stm32_crc32.c
> > b/drivers/crypto/stm32/stm32_crc32.c
> > index ec83b1e..12fbd98 100644
> > --- a/drivers/crypto/stm32/stm32_crc32.c
> > +++ b/drivers/crypto/stm32/stm32_crc32.c
> > @@ -7,6 +7,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > #include
> > @@ -39,6 +40,9 @@ struct stm32_crc {
> > struct clk *clk;
> > u8 pending_data[sizeof(u32)];
> > size_t nb_pending_bytes;
> > + bool key_support;
> > + bool poly_support;
> > + bool reverse_support;
> > };
> >
> > struct stm32_crc_list {
> > @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
> > }
> > spin_unlock_bh(_list.lock);
> >
> > - /* Reset, set key, poly and configure in bit reverse mode */
> > - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> > - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> > - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> > + /* set key */
> > + if (ctx->crc->key_support) {
> > + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
> > + } else if (mctx->key != CRC_INIT_DEFAULT) {
> > + dev_err(ctx->crc->dev, "Unsupported key value! Should be:
> > 0x%x\n",
> > + CRC_INIT_DEFAULT);
> > + return -EINVAL;
> > + }
> > +
> > + /* set poly */
> > + if (ctx->crc->poly_support)
> > + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
> > +
> > + /* reset and configure in bit reverse mode if supported */
> > + if (ctx->crc->reverse_support)
> > + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
> > + else
> > + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
> > +
> > + /* store partial result */
> > + if (!ctx->crc->reverse_support)
> > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
> > + else
> > + ctx->partial = readl(ctx->crc->regs + CRC_DR);
> >
> > - /* Store partial result */
> > - ctx->partial = readl(ctx->crc->regs + CRC_DR);
> > ctx->crc->nb_pending_bytes = 0;
> >
> > return 0;
> > @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc,
> > const u8 *d8,
> >
> > if (crc->nb_pending_bytes == sizeof(u32)) {
> > /* Process completed pending data */
> > - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
> > + if (!ctx->crc->reverse_support)
> > + writel(bitrev32(*(u32 *)crc->pending_data),
> > + crc->regs + CRC_DR);
> > + else
> > + writel(*(u32 *)crc->pending_data,
> > + crc->regs + CRC_DR);
> > crc->nb_pending_bytes = 0;
> > }
> > }
> > @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc,
> > const u8 *d8,
> > d32 = (u32 *)d8;
> > for (i = 0; i < length >> 2; i++)
> > /* Process 32 bits data */
> > - writel(*(d32++), crc->regs + CRC_DR);
> > + if (!ctx->crc->reverse_support)
> > + writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
> > + else
> > + writel(*(d32++), crc->regs + CRC_DR);
> >
> > /* Store partial result */
> > - ctx->partial = readl(crc->regs + CRC_DR);
> &
Re: [PATCH v2 2/5] dt-bindings : Document the STM32F4 CRC32 binding
On Tue, May 30, 2017 at 05:50:24PM -0500, Rob Herring wrote:
> On Sat, May 20, 2017 at 04:32:12PM +0300, Cosar Dindar wrote:
> > Add device tree binding for STM32F4.
> >
> > Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
> > ---
> > Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
> > b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
> > index 3ba92a5..7b30f1e 100644
> > --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
> > +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
> > @@ -1,7 +1,7 @@
> > * STMicroelectronics STM32 CRC
> >
> > Required properties:
> > -- compatible: Should be "st,stm32f7-crc".
> > +- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
>
> Here you say either, but the example has both.
>
Thanks for reviewing. Here it could be changed as :
Should be one of the following string
"st,stm32f7-crc"
"st,stm32f4-crc"
Also, example may not contain both binding strings, I think. It could be leaved
unchanged
as in the previous version. I will make these changes with this way if it is OK.
> > - reg: The address and length of the peripheral registers space
> > - clocks: The input clock of the CRC instance
> >
> > @@ -10,7 +10,7 @@ Optional properties: none
> > Example:
> >
> > crc: crc@40023000 {
> > - compatible = "st,stm32f7-crc";
> > + compatible = "st,stm32f7-crc", "st,stm32f4-crc";
> > reg = <0x40023000 0x400>;
> > clocks = < 0 12>;
> > };
> > --
> > 2.7.4
> >
[PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
drivers/crypto/stm32/stm32_crc32.c | 68 --
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk *clk;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should be:
0x%x\n",
+ CRC_INIT_DEFAULT);
+ return -EINVAL;
+ }
+
+ /* set poly */
+ if (ctx->crc->poly_support)
+ writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+ /* reset and configure in bit reverse mode if supported */
+ if (ctx->crc->reverse_support)
+ writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ else
+ writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+ /* store partial result */
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(ctx->crc->regs + CRC_DR);
- /* Store partial result */
- ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const
u8 *d8,
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
- writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(u32 *)crc->pending_data),
+ crc->regs + CRC_DR);
+ else
+ writel(*(u32 *)crc->pending_data,
+ crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc,
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
- writel(*(d32++), crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+ else
+ writel(*(d32++), crc->regs + CRC_DR);
/* Store partial result */
- ctx->partial = readl(crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(crc->regs + CRC_DR);
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
struct stm32_crc *crc;
struct resource *res;
int ret;
+ int algs_size;
crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret;
}
+ /* set key, poly and reverse support if device is of F7 series */
+ if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+ crc->key_support = true;
+ crc->poly_support = true;
+ crc->reverse_support = true;
+ }
+
platform_set_drvdata(pd
[PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding
Add device tree binding for STM32F4.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
index 3ba92a5..7b30f1e 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -1,7 +1,7 @@
* STMicroelectronics STM32 CRC
Required properties:
-- compatible: Should be "st,stm32f7-crc".
+- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
- reg: The address and length of the peripheral registers space
- clocks: The input clock of the CRC instance
@@ -10,7 +10,7 @@ Optional properties: none
Example:
crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
+ compatible = "st,stm32f7-crc", "st,stm32f4-crc";
reg = <0x40023000 0x400>;
clocks = < 0 12>;
};
--
2.7.4
[PATCH v3 0/5] Add support for the STM32F4 CRC32
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.
Changes in v3:
Rearranged patch order to fix build test error.
Cosar Dindar (5):
dt-bindings : Document the STM32F4 CRC32 binding
crypto : stm32 - Add STM32F4 CRC32 support
ARM: dts: stm32: Add CRC support to stm32f429
ARM: dts: stm32: enable CRC32 on stm32429-disco board
ARM: dts: stm32: enable CRC32 on stm32429i-eval board
.../devicetree/bindings/crypto/st,stm32-crc.txt| 4 +-
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
drivers/crypto/stm32/stm32_crc32.c | 68 ++
5 files changed, 75 insertions(+), 12 deletions(-)
--
2.7.4
[PATCH v2 2/5] dt-bindings : Document the STM32F4 CRC32 binding
Add device tree binding for STM32F4.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
index 3ba92a5..7b30f1e 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -1,7 +1,7 @@
* STMicroelectronics STM32 CRC
Required properties:
-- compatible: Should be "st,stm32f7-crc".
+- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
- reg: The address and length of the peripheral registers space
- clocks: The input clock of the CRC instance
@@ -10,7 +10,7 @@ Optional properties: none
Example:
crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
+ compatible = "st,stm32f7-crc", "st,stm32f4-crc";
reg = <0x40023000 0x400>;
clocks = < 0 12>;
};
--
2.7.4
[PATCH v2 1/5] crypto : stm32 - Add STM32F4 CRC32 support
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
drivers/crypto/stm32/stm32_crc32.c | 68 --
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk *clk;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should be:
0x%x\n",
+ CRC_INIT_DEFAULT);
+ return -EINVAL;
+ }
+
+ /* set poly */
+ if (ctx->crc->poly_support)
+ writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+ /* reset and configure in bit reverse mode if supported */
+ if (ctx->crc->reverse_support)
+ writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ else
+ writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+ /* store partial result */
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(ctx->crc->regs + CRC_DR);
- /* Store partial result */
- ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const
u8 *d8,
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
- writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(u32 *)crc->pending_data),
+ crc->regs + CRC_DR);
+ else
+ writel(*(u32 *)crc->pending_data,
+ crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc,
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
- writel(*(d32++), crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+ else
+ writel(*(d32++), crc->regs + CRC_DR);
/* Store partial result */
- ctx->partial = readl(crc->regs + CRC_DR);
+ if (!ctx->crc->reverse_support)
+ ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+ else
+ ctx->partial = readl(crc->regs + CRC_DR);
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
struct stm32_crc *crc;
struct resource *res;
int ret;
+ int algs_size;
crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret;
}
+ /* set key, poly and reverse support if device is of F7 series */
+ if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+ crc->key_support = true;
+ crc->poly_support = true;
+ crc->reverse_support = true;
+ }
+
platform_set_drvdata(pd
[PATCH v2 0/5] Add support for the STM32F4 CRC32
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0xFFFF.
Cosar Dindar (5):
crypto : stm32 - Add STM32F4 CRC32 support
dt-bindings : Document the STM32F4 CRC32 binding
ARM: dts: stm32: enable CRC32 on stm32429-disco board
ARM: dts: stm32: enable CRC32 on stm32429i-eval board
ARM: dts: stm32: Add CRC support to stm32f429
.../devicetree/bindings/crypto/st,stm32-crc.txt| 4 +-
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
drivers/crypto/stm32/stm32_crc32.c | 68 ++
5 files changed, 75 insertions(+), 12 deletions(-)
--
2.7.4
[PATCH] crypto: stm32 - Add CRC32 support for STM32F4XX
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F4XX series devices.
As an hardware limitation polynomial and key setting are not supported
as they are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not supported also.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.
Signed-off-by: Cosar Dindar <cosardin...@gmail.com>
---
.../devicetree/bindings/crypto/st,stm32-crc.txt| 4 +-
arch/arm/boot/dts/stm32429i-eval.dts | 4 ++
arch/arm/boot/dts/stm32f429-disco.dts | 4 ++
arch/arm/boot/dts/stm32f429.dtsi | 7 +++
arch/arm/boot/dts/stm32f469-disco.dts | 4 ++
drivers/crypto/stm32/stm32_crc32.c | 68 ++
6 files changed, 79 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
index 3ba92a5..7b30f1e 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -1,7 +1,7 @@
* STMicroelectronics STM32 CRC
Required properties:
-- compatible: Should be "st,stm32f7-crc".
+- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
- reg: The address and length of the peripheral registers space
- clocks: The input clock of the CRC instance
@@ -10,7 +10,7 @@ Optional properties: none
Example:
crc: crc@40023000 {
- compatible = "st,stm32f7-crc";
+ compatible = "st,stm32f7-crc", "st,stm32f4-crc";
reg = <0x40023000 0x400>;
clocks = < 0 12>;
};
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index b633114..360fb19 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -141,6 +141,10 @@
clock-frequency = <2500>;
};
+ {
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 191fa50..ae47cde 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -102,6 +102,10 @@
clock-frequency = <800>;
};
+ {
+ status = "okay";
+};
+
{
assigned-clocks = < 1 CLK_RTC>;
assigned-clock-parents = < 1 CLK_LSI>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..18343de 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -766,6 +766,13 @@
};
};
+ crc: crc@40023000 {
+ compatible = "st,stm32f4-crc";
+ reg = <0x40023000 0x400>;
+ clocks = < 0 STM32F4_AHB1_CLOCK(CRC)>;
+ status = "disabled";
+ };
+
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 75470c3..8cb8b73 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -87,6 +87,10 @@
clock-frequency = <800>;
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk *clk;
u8 pending_data[sizeof(u32)];
size_t nb_pending_bytes;
+ bool key_support;
+ bool poly_support;
+ bool reverse_support;
};
struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(_list.lock);
- /* Reset, set key, poly and configure in bit reverse mode */
- writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
- writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
- writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+ /* set key */
+ if (ctx->crc->key_support) {
+ writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+ } else if (mctx->key != CRC_INIT_DEFAULT) {
+ dev_err(ctx->crc->dev, "Unsupported key value! Should
