RE: [PATCH] crypto: caam - fix DECO RSR polling
:- Ruchika Gupta
Tested on P4080DS.
Ported and tested on LS1 platform also (This platform has the virtualization
enabled).
Thanks,
Ruchika
> -Original Message-
> From: Horia Geanta [mailto:horia.gea...@freescale.com]
> Sent: Monday, July 21, 2014 6:33 PM
> To: Herbert Xu; linux-crypto@vger.kernel.org; Gupta Ruchika-R66431; Phillips
> Kim-R1AAHA
> Cc: David S. Miller
> Subject: [PATCH] crypto: caam - fix DECO RSR polling
>
> RSR (Request Source Register) is not used when virtualization is disabled,
> thus don't poll for Valid bit.
>
> Besides this, if used, timeout has to be reinitialized.
>
> Signed-off-by: Horia Geanta
> ---
> Only compile-tested.
> Ruchika / Kim, please review / test.
>
> drivers/crypto/caam/ctrl.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index
> c6e9d3b2d502..84d4b95c761e 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -89,12 +89,15 @@ static inline int run_descriptor_deco0(struct device
> *ctrldev, u32 *desc,
> /* Set the bit to request direct access to DECO0 */
> topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
>
> - if (ctrlpriv->virt_en == 1)
> + if (ctrlpriv->virt_en == 1) {
> setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
>
> - while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
> ---timeout)
> - cpu_relax();
> + while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
> +--timeout)
> + cpu_relax();
> +
> + timeout = 10;
> + }
>
> setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
>
> --
> 1.8.3.1
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[PATCH][v2] crypto: caam - Check for CAAM block presence before registering with crypto layer
The layer which registers with the crypto API should check for the presence of
the CAAM device it is going to use. If the platform's device tree doesn't have
the required CAAM node, the layer should return an error and not register the
algorithms with crypto API layer.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/caamalg.c | 29 +
drivers/crypto/caam/caamhash.c | 28
drivers/crypto/caam/caamrng.c | 28
3 files changed, 85 insertions(+)
Changes from v1
Removed the memory leak of dev_node in case of error
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 87d9de4..64c606d 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2441,8 +2441,37 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
caam_alg_template
static int __init caam_algapi_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
+
INIT_LIST_HEAD(&alg_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 2ab057b..7754df4 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -1793,8 +1793,36 @@ caam_hash_alloc(struct caam_hash_template *template,
static int __init caam_algapi_hash_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
INIT_LIST_HEAD(&hash_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 8c07d31..a4afa8a 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -278,6 +278,34 @@ static void __exit caam_rng_exit(void)
static int __init caam_rng_init(void)
{
struct device *dev;
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
dev = caam_jr_alloc();
if (IS_ERR(dev)) {
--
1.8.1.4
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[PATCH][v2] crypto: caam - Check for CAAM block presence before registering with crypto layer
The layer which registers with the crypto API should check for the presence of
the CAAM device it is going to use. If the platform's device tree doesn't have
the required CAAM node, the layer should return an error and not register the
algorithms with crypto API layer.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/caamalg.c | 29 +
drivers/crypto/caam/caamhash.c | 28
drivers/crypto/caam/caamrng.c | 28
3 files changed, 85 insertions(+)
Changes from v1
Removed the memory leak of dev_node in case of error
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 87d9de4..64c606d 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2441,8 +2441,37 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
caam_alg_template
static int __init caam_algapi_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
+
INIT_LIST_HEAD(&alg_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 2ab057b..7754df4 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -1793,8 +1793,36 @@ caam_hash_alloc(struct caam_hash_template *template,
static int __init caam_algapi_hash_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
INIT_LIST_HEAD(&hash_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 8c07d31..a4afa8a 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -278,6 +278,34 @@ static void __exit caam_rng_exit(void)
static int __init caam_rng_init(void)
{
struct device *dev;
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ of_node_put(dev_node);
+ return -ENODEV;
+ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
dev = caam_jr_alloc();
if (IS_ERR(dev)) {
--
1.8.1.4
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[PATCH] crypto: caam - Check for CAAM block presence before registering with crypto layer
The layer which registers with the crypto API should check for the presence of
the CAAM device it is going to use. If the platform's device tree doesn't have
the required CAAM node, the layer should return an error and not register the
algorithms with crypto API layer.
Signed-off-by: Ruchika Gupta
Reviewed-by: Horia Ioan Geanta Neag
---
drivers/crypto/caam/caamalg.c | 27 +++
drivers/crypto/caam/caamhash.c | 26 ++
drivers/crypto/caam/caamrng.c | 26 ++
3 files changed, 79 insertions(+)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 87d9de4..d479dfb 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2441,8 +2441,35 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
caam_alg_template
static int __init caam_algapi_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
+
INIT_LIST_HEAD(&alg_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 2ab057b..5e172a2 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -1793,8 +1793,34 @@ caam_hash_alloc(struct caam_hash_template *template,
static int __init caam_algapi_hash_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
INIT_LIST_HEAD(&hash_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 8c07d31..c4c36c4 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -278,6 +278,32 @@ static void __exit caam_rng_exit(void)
static int __init caam_rng_init(void)
{
struct device *dev;
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
dev = caam_jr_alloc();
if (IS_ERR(dev)) {
--
1.8.1.4
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[PATCH] crypto:caam - Correct the dma mapping for sg table
At few places in caamhash and caamalg, after allocating a dmable buffer for sg table , the buffer was being modified. As per definition of DMA_FROM_DEVICE ,afer allocation the memory should be treated as read-only by the driver. This patch shifts the allocation of dmable buffer for sg table after it is populated by the driver, making it read-only as per the DMA API's requirement. Signed-off-by: Ruchika Gupta --- drivers/crypto/caam/caamalg.c | 8 drivers/crypto/caam/caamhash.c | 40 +++- 2 files changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index c09ce1f..87d9de4 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -1345,8 +1345,6 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, edesc->sec4_sg_bytes = sec4_sg_bytes; edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) + desc_bytes; - edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, - sec4_sg_bytes, DMA_TO_DEVICE); *all_contig_ptr = all_contig; sec4_sg_index = 0; @@ -1369,6 +1367,8 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, sg_to_sec4_sg_last(req->dst, dst_nents, edesc->sec4_sg + sec4_sg_index, 0); } + edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, + sec4_sg_bytes, DMA_TO_DEVICE); return edesc; } @@ -1534,8 +1534,6 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request edesc->sec4_sg_bytes = sec4_sg_bytes; edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) + desc_bytes; - edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, - sec4_sg_bytes, DMA_TO_DEVICE); *contig_ptr = contig; sec4_sg_index = 0; @@ -1559,6 +1557,8 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request sg_to_sec4_sg_last(req->dst, dst_nents, edesc->sec4_sg + sec4_sg_index, 0); } + edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, + sec4_sg_bytes, DMA_TO_DEVICE); return edesc; } diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c index 0d9284e..2ab057b 100644 --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c @@ -808,9 +808,6 @@ static int ahash_update_ctx(struct ahash_request *req) edesc->sec4_sg_bytes = sec4_sg_bytes; edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN; - edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -sec4_sg_bytes, -DMA_TO_DEVICE); ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg, DMA_BIDIRECTIONAL); @@ -839,6 +836,10 @@ static int ahash_update_ctx(struct ahash_request *req) init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE); + edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, +sec4_sg_bytes, +DMA_TO_DEVICE); + append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + to_hash, LDST_SGF); @@ -911,8 +912,6 @@ static int ahash_final_ctx(struct ahash_request *req) edesc->sec4_sg_bytes = sec4_sg_bytes; edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN; - edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, - sec4_sg_bytes, DMA_TO_DEVICE); edesc->src_nents = 0; ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg, @@ -923,6 +922,9 @@ static int ahash_final_ctx(struct ahash_request *req) last_buflen); (edesc->sec4_sg + sec4_sg_bytes - 1)->len |= SEC4_SG_LEN_FIN; + edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, + sec4_sg_bytes, DMA_TO_DEVICE); + append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen, LDST_SGF); @@ -989,8 +991,6 @@ static int ahash_finup_ctx(struct ahash_requ
[PATCH] crypto: caam - Add definition of rd/wr_reg64 for little endian platform
CAAM IP has certain 64 bit registers . 32 bit architectures cannot force
atomic-64 operations. This patch adds definition of these atomic-64
operations for little endian platforms. The definitions which existed
previously were for big endian platforms.
Signed-off-by: Ruchika Gupta
---
Tested on LS1021 platform
drivers/crypto/caam/regs.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..2825067 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -84,6 +84,7 @@
#endif
#ifndef CONFIG_64BIT
+#ifdef __BIG_ENDIAN
static inline void wr_reg64(u64 __iomem *reg, u64 data)
{
wr_reg32((u32 __iomem *)reg, (data & 0xull) >> 32);
@@ -95,6 +96,21 @@ static inline u64 rd_reg64(u64 __iomem *reg)
return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
((u64)rd_reg32((u32 __iomem *)reg + 1));
}
+#else
+#ifdef __LITTLE_ENDIAN
+static inline void wr_reg64(u64 __iomem *reg, u64 data)
+{
+ wr_reg32((u32 __iomem *)reg + 1, (data & 0xull) >> 32);
+ wr_reg32((u32 __iomem *)reg, data & 0xull);
+}
+
+static inline u64 rd_reg64(u64 __iomem *reg)
+{
+ return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
+ ((u64)rd_reg32((u32 __iomem *)reg));
+}
+#endif
+#endif
#endif
/*
--
1.8.1.4
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[PATCH] crypto:caam - Configuration for platforms with virtualization enabled in CAAM
For platforms with virtualization enabled
1. The job ring registers can be written to only is the job ring has been
started i.e STARTR bit in JRSTART register is 1
2. For DECO's under direct software control, with virtualization enabled
PL, BMT, ICID and SDID values need to be provided. These are provided by
selecting a Job ring in start mode whose parameters would be used for the
DECO access programming.
Signed-off-by: Ruchika Gupta
---
The current patch used the 32 bit register comp_params_ms defined in another
patch.
The link of patch thsi patch is depnedent on is given below:
crypto: caam - Correct definition of registers in memory map
(https://lkml.org/lkml/2014/6/23/3)
drivers/crypto/caam/ctrl.c | 39 +++
drivers/crypto/caam/intern.h | 1 +
drivers/crypto/caam/regs.h | 18 --
3 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 066a4d4..7acaaa4 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -88,6 +88,14 @@ static inline int run_descriptor_deco0(struct device
*ctrldev, u32 *desc,
/* Set the bit to request direct access to DECO0 */
topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
+
+ if (ctrlpriv->virt_en == 1)
+ setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
+
+ while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
+ --timeout)
+ cpu_relax();
+
setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
@@ -130,6 +138,9 @@ static inline int run_descriptor_deco0(struct device
*ctrldev, u32 *desc,
*status = rd_reg32(&topregs->deco.op_status_hi) &
DECO_OP_STATUS_HI_ERR_MASK;
+ if (ctrlpriv->virt_en == 1)
+ clrbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
+
/* Mark the DECO as free */
clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
@@ -378,6 +389,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
+ u32 scfgr, comp_params;
u32 cha_vid_ls;
ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
@@ -412,6 +424,33 @@ static int caam_probe(struct platform_device *pdev)
setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+ /*
+* Read the Compile Time paramters and SCFGR to determine
+* if Virtualization is enabled for this platform
+*/
+ comp_params = rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms);
+ scfgr = rd_reg32(&topregs->ctrl.scfgr);
+
+ ctrlpriv->virt_en = 0;
+ if (comp_params & CTPR_MS_VIRT_EN_INCL) {
+ /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
+* VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
+*/
+ if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
+ (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
+ (scfgr & SCFGR_VIRT_EN)))
+ ctrlpriv->virt_en = 1;
+ } else {
+ /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
+ if (comp_params & CTPR_MS_VIRT_EN_POR)
+ ctrlpriv->virt_en = 1;
+ }
+
+ if (ctrlpriv->virt_en == 1)
+ setbits32(&topregs->ctrl.jrstart, JRSTART_JR0_START |
+ JRSTART_JR1_START | JRSTART_JR2_START |
+ JRSTART_JR3_START);
+
if (sizeof(dma_addr_t) == sizeof(u64))
if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
dma_set_mask(dev, DMA_BIT_MASK(40));
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 6d85fcc..97363db 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -82,6 +82,7 @@ struct caam_drv_private {
u8 total_jobrs; /* Total Job Rings in device */
u8 qi_present; /* Nonzero if QI present in device */
int secvio_irq; /* Security violation interrupt number */
+ int virt_en;/* Virtualization enabled in CAAM */
#defineRNG4_MAX_HANDLES 2
/* RNG4 block */
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 7bb898d..69e3562 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -176,6 +176,8 @@ struct caam_perfmon {
u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
#define CTPR_MS_QI_SHIFT 25
#define
[PATCH][v4] crypto: caam - Correct definition of registers in memory map
Some registers like SECVID, CHAVID, CHA Revision Number,
CTPR were defined as 64 bit resgisters. The IP provides
a DWT bit(Double word Transpose) to transpose the two words when
a double word register is accessed. However setting this bit
would also affect the operation of job descriptors as well as
other registers which are truly double word in nature.
So, for the IP to work correctly on big-endian as well as
little-endian SoC's, change is required to access all 32 bit
registers as 32 bit quantities.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 14 +
drivers/crypto/caam/regs.h | 71 +-
2 files changed, 46 insertions(+), 39 deletions(-)
Changed in v4
Rebased the patch
Changes in v3
Fixed caam_id to print complete 64 bit register
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 34ffc35..066a4d4 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -378,7 +378,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u64 cha_vid;
+ u32 cha_vid_ls;
ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
GFP_KERNEL);
@@ -456,8 +456,9 @@ static int caam_probe(struct platform_device *pdev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
- CTPR_QI_MASK);
+ ctrlpriv->qi_present =
+ !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
+ CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
/* This is all that's required to physically enable QI */
@@ -471,13 +472,13 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
- cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+ cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
* already instantiated, do RNG instantiation
*/
- if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
+ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
/*
@@ -531,7 +532,8 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+ caam_id = (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ms) << 32 |
+ (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ls);
/* Report "alive" for developer to see */
dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..7bb898d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -114,45 +114,45 @@ struct jr_outentry {
*/
/* Number of DECOs */
-#define CHA_NUM_DECONUM_SHIFT 56
-#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+#define CHA_NUM_MS_DECONUM_SHIFT 24
+#define CHA_NUM_MS_DECONUM_MASK(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
/* CHA Version IDs */
-#define CHA_ID_AES_SHIFT 0
-#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+#define CHA_ID_LS_AES_SHIFT0
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
-#define CHA_ID_DES_SHIFT 4
-#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+#define CHA_ID_LS_DES_SHIFT4
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
-#define CHA_ID_ARC4_SHIFT 8
-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+#define CHA_ID_LS_ARC4_SHIFT 8
+#define CHA_ID_LS_ARC4_MASK(0xfull << CHA_ID_LS_ARC4_SHIFT)
-#define CHA_ID_MD_SHIFT12
-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+#define CHA_ID_LS_MD_SHIFT 12
+#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
-#define CHA_ID_RNG_SHIFT 16
-#define CHA_ID_RNG_MASK(0xfull << CHA_ID_RNG_SHIFT)
+#define CHA_ID_LS_RNG_SHIFT16
+#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
-#define CHA_ID_SNW8_SHIFT 20
-#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
+#define CHA_ID_LS_SNW8_SHIFT 20
+#define CHA_ID_LS_SNW8_MASK(0xfull << CHA_ID_LS_SNW8_SHIFT)
-#def
[PATCH][v3] crypto: caam - Correct definition of registers in memory map
Some registers like SECVID, CHAVID, CHA Revision Number,
CTPR were defined as 64 bit resgisters. The IP provides
a DWT bit(Double word Transpose) to transpose the two words when
a double word register is accessed. However setting this bit
would also affect the operation of job descriptors as well as
other registers which are truly double word in nature.
So, for the IP to work correctly on big-endian as well as
little-endian SoC's, change is required to access all 32 bit
registers as 32 bit quantities.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 14 +
drivers/crypto/caam/regs.h | 71 +-
2 files changed, 46 insertions(+), 39 deletions(-)
Changes in v3
Fixed caam_id to print complete 64 bit register
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1c38f86..3600c40 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -380,7 +380,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u64 cha_vid;
+ u32 cha_vid_ls;
ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
if (!ctrlpriv)
@@ -456,8 +456,9 @@ static int caam_probe(struct platform_device *pdev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
- CTPR_QI_MASK);
+ ctrlpriv->qi_present =
+ !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
+ CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
/* This is all that's required to physically enable QI */
@@ -471,13 +472,13 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
- cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+ cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
* already instantiated, do RNG instantiation
*/
- if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
+ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
/*
@@ -531,7 +532,8 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+ caam_id = (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ms) << 32 |
+ (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ls);
/* Report "alive" for developer to see */
dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..7bb898d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -114,45 +114,45 @@ struct jr_outentry {
*/
/* Number of DECOs */
-#define CHA_NUM_DECONUM_SHIFT 56
-#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+#define CHA_NUM_MS_DECONUM_SHIFT 24
+#define CHA_NUM_MS_DECONUM_MASK(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
/* CHA Version IDs */
-#define CHA_ID_AES_SHIFT 0
-#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+#define CHA_ID_LS_AES_SHIFT0
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
-#define CHA_ID_DES_SHIFT 4
-#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+#define CHA_ID_LS_DES_SHIFT4
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
-#define CHA_ID_ARC4_SHIFT 8
-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+#define CHA_ID_LS_ARC4_SHIFT 8
+#define CHA_ID_LS_ARC4_MASK(0xfull << CHA_ID_LS_ARC4_SHIFT)
-#define CHA_ID_MD_SHIFT12
-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+#define CHA_ID_LS_MD_SHIFT 12
+#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
-#define CHA_ID_RNG_SHIFT 16
-#define CHA_ID_RNG_MASK(0xfull << CHA_ID_RNG_SHIFT)
+#define CHA_ID_LS_RNG_SHIFT16
+#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
-#define CHA_ID_SNW8_SHIFT 20
-#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
+#define CHA_ID_LS_SNW8_SHIFT 20
+#define CHA_ID_LS_SNW8_MASK(0xfull << CHA_ID_LS_SNW8_SHIFT)
-#define CHA_ID_KAS_SHIFT 24
-#define CHA_ID_KAS_MASK
[PATCH][v2] crypto: caam - Correct definition of registers in memory map
Some registers like SECVID, CHAVID, CHA Revision Number,
CTPR were defined as 64 bit resgisters. The IP provides
a DWT bit(Double word Transpose) to transpose the two words when
a double word register is accessed. However setting this bit
would also affect the operation of job descriptors as well as
other registers which are truly double word in nature.
So, for the IP to work correctly on big-endian as well as
little-endian SoC's, change is required to access all 32 bit
registers as 32 bit quantities.
Signed-off-by: Ruchika Gupta
---
Changed in v2:
1. Review comments incorporated
2. Subject message modified
drivers/crypto/caam/ctrl.c | 17 +--
drivers/crypto/caam/regs.h | 71 +-
2 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1c38f86..807af4f 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -371,7 +371,7 @@ EXPORT_SYMBOL(caam_get_era);
static int caam_probe(struct platform_device *pdev)
{
int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- u64 caam_id;
+ u32 caam_id;
struct device *dev;
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
@@ -380,7 +380,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u64 cha_vid;
+ u32 cha_vid_ls;
ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
if (!ctrlpriv)
@@ -456,8 +456,9 @@ static int caam_probe(struct platform_device *pdev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
- CTPR_QI_MASK);
+ ctrlpriv->qi_present =
+ !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
+ CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
/* This is all that's required to physically enable QI */
@@ -471,13 +472,13 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
- cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+ cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
* already instantiated, do RNG instantiation
*/
- if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
+ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
/*
@@ -531,10 +532,10 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+ caam_id = rd_reg32(&topregs->ctrl.perfmon.caam_id_ms);
/* Report "alive" for developer to see */
- dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
+ dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id,
caam_get_era());
dev_info(dev, "job rings = %d, qi = %d\n",
ctrlpriv->total_jobrs, ctrlpriv->qi_present);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..7bb898d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -114,45 +114,45 @@ struct jr_outentry {
*/
/* Number of DECOs */
-#define CHA_NUM_DECONUM_SHIFT 56
-#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+#define CHA_NUM_MS_DECONUM_SHIFT 24
+#define CHA_NUM_MS_DECONUM_MASK(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
/* CHA Version IDs */
-#define CHA_ID_AES_SHIFT 0
-#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+#define CHA_ID_LS_AES_SHIFT0
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
-#define CHA_ID_DES_SHIFT 4
-#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+#define CHA_ID_LS_DES_SHIFT4
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
-#define CHA_ID_ARC4_SHIFT 8
-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+#define CHA_ID_LS_ARC4_SHIFT 8
+#define CHA_ID_LS_ARC4_MASK(0xfull << CHA_ID_LS_ARC4_SHIFT)
-#define CHA_ID_MD_SHIFT12
-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+#define CHA_ID_LS_MD_SHIFT 12
+#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
-#define CHA_ID
RE: [PATCH] crypto:caam - Modify width of few read only registers
Hi Kim > -Original Message- > From: Kim Phillips [mailto:kim.phill...@freescale.com] > Sent: Thursday, June 12, 2014 4:23 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@vger.kernel.org; herb...@gondor.apana.org.au > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 29 Apr 2014 15:34:37 +0530 > Ruchika Gupta wrote: > > > Few read only registers like CHAVID, CTPR etc were wrongly defined as > > 64 bit registers. This functioned properly on the powerpc platforms. > > However ARM SoC's wouldn't function correctly if these registers are > > defined as 64 bit. So correcting the definition to two 32 bit registers. > > please rewrite, adding the details of the problem posted toward the end of > this thread, e.g., what registers are affected, and how that renders > MCFGR:DWT ineffective in this case. Ok. I will add the details in the commit message. > > > /* Check to see if QI present. If so, enable */ > > - ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) & > > - CTPR_QI_MASK); > > + ctrlpriv->qi_present = > > + !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) & > > + CTPR_MS_QI_MASK); > > alignment Ok. I will correct it. > > > /* Report "alive" for developer to see */ > > - dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, > > + dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id, > > caam_get_era()); > > Why are we dropping the upper 32 bits here? The upper 32 bit contain the IP ID of SEC, the major number and the minor number while the lower 32 bits have the details of the compile option, integration and configuration options of SEC. So device ID is actually contained only in the most significant 32 bits which are being printed here. Ruchika > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] crypto:caam - Modify width of few read only registers
Hi Kim, I contacted the Hardware folks and below is the statement from them : Unfortunately setting the DWT bit will also affect the operation of job descriptors, so I don't think that is a viable option. It looks like you will have to change the software to access all 32-bit registers as 32-bit quantities, even if two 32-bit registers appear to be two halves of a 64-bit register. If you do that it will work correctly on both big-endian and little-endian SoCs. Regards, Ruchika > -Original Message- > From: Kim Phillips [mailto:kim.phill...@freescale.com] > Sent: Thursday, May 08, 2014 5:25 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@vger.kernel.org; herb...@gondor.apana.org.au > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 6 May 2014 23:09:15 -0500 > Gupta Ruchika-R66431 wrote: > > > Hi Kim, > > Hi Ruchika, > > > > From: Kim Phillips [mailto:kim.phill...@freescale.com] > > > Sent: Wednesday, May 07, 2014 2:02 AM > > > > > > On Tue, 6 May 2014 05:11:23 -0500 > > > Gupta Ruchika-R66431 wrote: > > > > > > > > From: Kim Phillips [mailto:kim.phill...@freescale.com] > > > > > Sent: Friday, May 02, 2014 2:15 AM > > > > > > > > > > On Tue, 29 Apr 2014 15:34:37 +0530 Ruchika Gupta > > > > > wrote: > > > > > > > > > > > Few read only registers like CHAVID, CTPR etc were wrongly > > > > > > defined as > > > > > > 64 bit registers. This functioned properly on the powerpc > platforms. > > > > > > However ARM SoC's wouldn't function correctly if these > > > > > > registers are defined as 64 bit. > > > > > > > > > > why wouldn't they function correctly? > > > > > > > > The SEC IP guide states these registers as 2 32 bit registers. So > > > > register definition in > > > > > > I'm looking at LS2100A's SEC reference manual, it clearly has the > > > CHAVID defined as one, single 64-bit register. What are you looking at? > > > > In the first version of guide they were defined as 64 bit. They were later > changed to 32 bit once issue was reported while testing on emulator. Latest > guide of LS2100 has them modified. A register width column has also been > added in the memory map now. > > I love how they try to cover up h/w bugs by amending the documentation... > > > > > crypto code should also have them defined as 32 bit registers. > > > > Defining > > > them as 64 bit in this case would be incorrect. > > > > > > > > Endianness of the CAAM IP varies with core's endiannes. In ARM > > > > SoC's , CAAM > > > block is also little endian. So in case the 2 - 32 bit registers > > > are treated as a 64 bit register, the result would be word swapped > > > as compared to powerpc platforms. As a result, the reads won't return the > right result. > > > > > > > > For eg. > > > > For the 2 32 bit registers CHAVID_MS(at address 0x0) and > > > > CHAVID_LS(address 0x4) , if core reads them as 64 bit word, > > > > > > > > In powerpc (big endian) platform - CHAVID_MS would be available in > > > > most significant portion of the 64 bit > > > word. > > > > CHAVID_LS would be the in least significant portion. > > > > This is as expected. > > > > > > > > In ARM (little endian) platform, 64 bit read would result in - > > > > CHAVID_MS in Least significant portion of the word and CHAVID_LS > > > > in the most significant location. > > > > This result is word swapped and the value read wouldn't be correct. > > > > > > hmm, have you looked at using the DWT "Double Word Transpose" bit in > > > the MCFGR? > > I am not able to locate this bit in MCFGR. > > It's bit 19: "Double Word Transpose. Setting this bit affects whether the > two words within a Dword are transposed when a double-word register is > accessed, ..." > > > However there are few swapping options present in Job ring configuration > and QICTL registers. Are you referring to these ? > > no. Plus, those don't sound relevant to accessing CHAVID... > > > Since these are 32 bit registers by nature, shouldn't we just treat them as > 32 bit instead of enabling the swapping option . > > depends on the definition of 'treat': I'd rather still use the superior 64- > bit accessors on all possible arches, if we can get them to work. > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] crypto:caam - Modify width of few read only registers
Hi Kim, > -Original Message- > From: Kim Phillips [mailto:kim.phill...@freescale.com] > Sent: Wednesday, May 07, 2014 2:02 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@vger.kernel.org; herb...@gondor.apana.org.au > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 6 May 2014 05:11:23 -0500 > Gupta Ruchika-R66431 wrote: > > > > From: Kim Phillips [mailto:kim.phill...@freescale.com] > > > Sent: Friday, May 02, 2014 2:15 AM > > > > > > On Tue, 29 Apr 2014 15:34:37 +0530 > > > Ruchika Gupta wrote: > > > > > > > Few read only registers like CHAVID, CTPR etc were wrongly defined > > > > as > > > > 64 bit registers. This functioned properly on the powerpc platforms. > > > > However ARM SoC's wouldn't function correctly if these registers > > > > are defined as 64 bit. > > > > > > why wouldn't they function correctly? > > > > The SEC IP guide states these registers as 2 32 bit registers. So > > register definition in > > I'm looking at LS2100A's SEC reference manual, it clearly has the CHAVID > defined as one, single 64-bit register. What are you looking at? In the first version of guide they were defined as 64 bit. They were later changed to 32 bit once issue was reported while testing on emulator. Latest guide of LS2100 has them modified. A register width column has also been added in the memory map now. > > > crypto code should also have them defined as 32 bit registers. Defining > them as 64 bit in this case would be incorrect. > > > > Endianness of the CAAM IP varies with core's endiannes. In ARM SoC's , CAAM > block is also little endian. So in case the 2 - 32 bit registers are treated > as a 64 bit register, the result would be word swapped as compared to powerpc > platforms. As a result, the reads won't return the right result. > > > > For eg. > > For the 2 32 bit registers CHAVID_MS(at address 0x0) and > > CHAVID_LS(address 0x4) , if core reads them as 64 bit word, > > > > In powerpc (big endian) platform - > > CHAVID_MS would be available in most significant portion of the 64 bit > word. > > CHAVID_LS would be the in least significant portion. > > This is as expected. > > > > In ARM (little endian) platform, 64 bit read would result in - > > CHAVID_MS in Least significant portion of the word and CHAVID_LS in > > the most significant location. > > This result is word swapped and the value read wouldn't be correct. > > hmm, have you looked at using the DWT "Double Word Transpose" bit in the > MCFGR? I am not able to locate this bit in MCFGR. However there are few swapping options present in Job ring configuration and QICTL registers. Are you referring to these ? Since these are 32 bit registers by nature, shouldn't we just treat them as 32 bit instead of enabling the swapping option . Ruchika > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] crypto:caam - Modify width of few read only registers
> -Original Message- > From: Kim Phillips [mailto:kim.phill...@freescale.com] > Sent: Friday, May 02, 2014 2:15 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@vger.kernel.org; herb...@gondor.apana.org.au > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 29 Apr 2014 15:34:37 +0530 > Ruchika Gupta wrote: > > > Few read only registers like CHAVID, CTPR etc were wrongly defined as > > 64 bit registers. This functioned properly on the powerpc platforms. > > However ARM SoC's wouldn't function correctly if these registers are > > defined as 64 bit. > > why wouldn't they function correctly? The SEC IP guide states these registers as 2 32 bit registers. So register definition in crypto code should also have them defined as 32 bit registers. Defining them as 64 bit in this case would be incorrect. Endianness of the CAAM IP varies with core's endiannes. In ARM SoC's , CAAM block is also little endian. So in case the 2 - 32 bit registers are treated as a 64 bit register, the result would be word swapped as compared to powerpc platforms. As a result, the reads won't return the right result. For eg. For the 2 32 bit registers CHAVID_MS(at address 0x0) and CHAVID_LS(address 0x4) , if core reads them as 64 bit word, In powerpc (big endian) platform - CHAVID_MS would be available in most significant portion of the 64 bit word. CHAVID_LS would be the in least significant portion. This is as expected. In ARM (little endian) platform, 64 bit read would result in - CHAVID_MS in Least significant portion of the word and CHAVID_LS in the most significant location. This result is word swapped and the value read wouldn't be correct. Ruchika > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] crypto:caam - Define setbits32() and clrbits32() for ARM in the Freescale CAAM driver
The kernel defines setbits32() and clrbits32() macros only for
Power-based architectures. This patch modifies the Freescale CAAM
driver to add macros for use on ARM architectures.
Signed-off-by: Victoria Milhoan
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/regs.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 7bb898d..16a3d2e 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -83,6 +83,12 @@
#endif
#endif
+#ifdef CONFIG_ARM
+/* These are common macros for Power, put here for ARMs */
+#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
+#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+#endif
+
#ifndef CONFIG_64BIT
static inline void wr_reg64(u64 __iomem *reg, u64 data)
{
--
1.8.1.4
--
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[PATCH] crypto:caam - Modify width of few read only registers
Few read only registers like CHAVID, CTPR etc were wrongly defined
as 64 bit registers. This functioned properly on the powerpc platforms.
However ARM SoC's wouldn't function correctly if these registers
are defined as 64 bit. So correcting the definition to two 32 bit registers.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 17 +--
drivers/crypto/caam/regs.h | 71 +-
2 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1c38f86..5d8782e8 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -371,7 +371,7 @@ EXPORT_SYMBOL(caam_get_era);
static int caam_probe(struct platform_device *pdev)
{
int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- u64 caam_id;
+ u32 caam_id;
struct device *dev;
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
@@ -380,7 +380,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u64 cha_vid;
+ u32 cha_vid_ls;
ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
if (!ctrlpriv)
@@ -456,8 +456,9 @@ static int caam_probe(struct platform_device *pdev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
- CTPR_QI_MASK);
+ ctrlpriv->qi_present =
+ !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
+ CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
/* This is all that's required to physically enable QI */
@@ -471,13 +472,13 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
- cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+ cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
* already instantiated, do RNG instantiation
*/
- if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
+ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
/*
@@ -531,10 +532,10 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+ caam_id = rd_reg32(&topregs->ctrl.perfmon.caam_id_ms);
/* Report "alive" for developer to see */
- dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
+ dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id,
caam_get_era());
dev_info(dev, "job rings = %d, qi = %d\n",
ctrlpriv->total_jobrs, ctrlpriv->qi_present);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..7bb898d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -114,45 +114,45 @@ struct jr_outentry {
*/
/* Number of DECOs */
-#define CHA_NUM_DECONUM_SHIFT 56
-#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+#define CHA_NUM_MS_DECONUM_SHIFT 24
+#define CHA_NUM_MS_DECONUM_MASK(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
/* CHA Version IDs */
-#define CHA_ID_AES_SHIFT 0
-#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+#define CHA_ID_LS_AES_SHIFT0
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
-#define CHA_ID_DES_SHIFT 4
-#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+#define CHA_ID_LS_DES_SHIFT4
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
-#define CHA_ID_ARC4_SHIFT 8
-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+#define CHA_ID_LS_ARC4_SHIFT 8
+#define CHA_ID_LS_ARC4_MASK(0xfull << CHA_ID_LS_ARC4_SHIFT)
-#define CHA_ID_MD_SHIFT12
-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+#define CHA_ID_LS_MD_SHIFT 12
+#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
-#define CHA_ID_RNG_SHIFT 16
-#define CHA_ID_RNG_MASK(0xfull << CHA_ID_RNG_SHIFT)
+#define CHA_ID_LS_RNG_SHIFT16
+#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
-#define CHA_ID_SNW8_SHIFT 20
-#define CHA_ID_SNW8_MASK (0x
[PATCH] crypto:caam - Modify width of few read only registers
Few read only registers like CHAVID, CTPR etc were wrongly defined
as 64 bit registers. This functioned properly on the powerpc platforms.
However ARM SoC's wouldn't function correctly if these registers
are defined as 64 bit. So correcting the definition to two 32 bit registers.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 17 +--
drivers/crypto/caam/regs.h | 71 +-
2 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1c38f86..5d8782e8 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -371,7 +371,7 @@ EXPORT_SYMBOL(caam_get_era);
static int caam_probe(struct platform_device *pdev)
{
int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- u64 caam_id;
+ u32 caam_id;
struct device *dev;
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
@@ -380,7 +380,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
- u64 cha_vid;
+ u32 cha_vid_ls;
ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
if (!ctrlpriv)
@@ -456,8 +456,9 @@ static int caam_probe(struct platform_device *pdev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
- CTPR_QI_MASK);
+ ctrlpriv->qi_present =
+ !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) &
+ CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
/* This is all that's required to physically enable QI */
@@ -471,13 +472,13 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
- cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+ cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
* already instantiated, do RNG instantiation
*/
- if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
+ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
/*
@@ -531,10 +532,10 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
+ caam_id = rd_reg32(&topregs->ctrl.perfmon.caam_id_ms);
/* Report "alive" for developer to see */
- dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
+ dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id,
caam_get_era());
dev_info(dev, "job rings = %d, qi = %d\n",
ctrlpriv->total_jobrs, ctrlpriv->qi_present);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cbde8b9..7bb898d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -114,45 +114,45 @@ struct jr_outentry {
*/
/* Number of DECOs */
-#define CHA_NUM_DECONUM_SHIFT 56
-#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+#define CHA_NUM_MS_DECONUM_SHIFT 24
+#define CHA_NUM_MS_DECONUM_MASK(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
/* CHA Version IDs */
-#define CHA_ID_AES_SHIFT 0
-#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+#define CHA_ID_LS_AES_SHIFT0
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
-#define CHA_ID_DES_SHIFT 4
-#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+#define CHA_ID_LS_DES_SHIFT4
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
-#define CHA_ID_ARC4_SHIFT 8
-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+#define CHA_ID_LS_ARC4_SHIFT 8
+#define CHA_ID_LS_ARC4_MASK(0xfull << CHA_ID_LS_ARC4_SHIFT)
-#define CHA_ID_MD_SHIFT12
-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+#define CHA_ID_LS_MD_SHIFT 12
+#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
-#define CHA_ID_RNG_SHIFT 16
-#define CHA_ID_RNG_MASK(0xfull << CHA_ID_RNG_SHIFT)
+#define CHA_ID_LS_RNG_SHIFT16
+#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
-#define CHA_ID_SNW8_SHIFT 20
-#define CHA_ID_SNW8_MASK (0x
RE: [PATCH] crypto: caam - Fix key inlining in AEAD shared descriptors
Reviewed-by: Ruchika Gupta > -Original Message- > From: Vakul Garg [mailto:va...@freescale.com] > Sent: Sunday, April 27, 2014 8:56 PM > To: linux-crypto@vger.kernel.org > Cc: herb...@gondor.apana.org.au; Geanta Neag Horia Ioan-B05471; Gupta > Ruchika-R66431; Porosanu Alexandru-B06830 > Subject: [PATCH] crypto: caam - Fix key inlining in AEAD shared descriptors > > The variable 'keys_fit_inline' is initialised correctly to avoid using its > stale value while creating shared descriptor for decryption and given-iv- > encryption. > > Signed-off-by: Vakul Garg > --- > drivers/crypto/caam/caamalg.c | 15 +-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c > index 5f89125..99fda94 100644 > --- a/drivers/crypto/caam/caamalg.c > +++ b/drivers/crypto/caam/caamalg.c > @@ -209,7 +209,7 @@ static int aead_null_set_sh_desc(struct crypto_aead > *aead) > struct aead_tfm *tfm = &aead->base.crt_aead; > struct caam_ctx *ctx = crypto_aead_ctx(aead); > struct device *jrdev = ctx->jrdev; > - bool keys_fit_inline = false; > + bool keys_fit_inline; > u32 *key_jump_cmd, *jump_cmd, *read_move_cmd, *write_move_cmd; > u32 *desc; > > @@ -220,6 +220,8 @@ static int aead_null_set_sh_desc(struct crypto_aead > *aead) > if (DESC_AEAD_NULL_ENC_LEN + DESC_JOB_IO_LEN + > ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX) > keys_fit_inline = true; > + else > + keys_fit_inline = false; > > /* aead_encrypt shared descriptor */ > desc = ctx->sh_desc_enc; > @@ -306,6 +308,8 @@ static int aead_null_set_sh_desc(struct crypto_aead > *aead) > if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN + > ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX) > keys_fit_inline = true; > + else > + keys_fit_inline = false; > > desc = ctx->sh_desc_dec; > > @@ -399,7 +403,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead) > struct aead_tfm *tfm = &aead->base.crt_aead; > struct caam_ctx *ctx = crypto_aead_ctx(aead); > struct device *jrdev = ctx->jrdev; > - bool keys_fit_inline = false; > + bool keys_fit_inline; > u32 geniv, moveiv; > u32 *desc; > > @@ -418,6 +422,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead) > ctx->split_key_pad_len + ctx->enckeylen <= > CAAM_DESC_BYTES_MAX) > keys_fit_inline = true; > + else > + keys_fit_inline = false; > + > > /* aead_encrypt shared descriptor */ > desc = ctx->sh_desc_enc; > @@ -476,6 +483,8 @@ static int aead_set_sh_desc(struct crypto_aead *aead) > ctx->split_key_pad_len + ctx->enckeylen <= > CAAM_DESC_BYTES_MAX) > keys_fit_inline = true; > + else > + keys_fit_inline = false; > > /* aead_decrypt shared descriptor */ > desc = ctx->sh_desc_dec; > @@ -531,6 +540,8 @@ static int aead_set_sh_desc(struct crypto_aead *aead) > ctx->split_key_pad_len + ctx->enckeylen <= > CAAM_DESC_BYTES_MAX) > keys_fit_inline = true; > + else > + keys_fit_inline = false; > > /* aead_givencrypt shared descriptor */ > desc = ctx->sh_desc_givenc; > -- > 1.8.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] crypto: caam - Check for CAAM block presence before registering with crypto layer
The layer which registers with the crypto API should check for the presence of
the CAAM device it is going to use. If the platform's device tree doesn't have
the required CAAM node, the layer should return an error and not register the
algorithms with crypto API layer.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/caamalg.c | 27 +++
drivers/crypto/caam/caamhash.c | 26 ++
drivers/crypto/caam/caamrng.c | 26 ++
3 files changed, 79 insertions(+)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index b71f2fd..4335e38 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2164,8 +2164,35 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
caam_alg_template
static int __init caam_algapi_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
+
INIT_LIST_HEAD(&alg_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 0378328..5592fec 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -1797,8 +1797,34 @@ caam_hash_alloc(struct caam_hash_template *template,
static int __init caam_algapi_hash_init(void)
{
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
int i = 0, err = 0;
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
+
INIT_LIST_HEAD(&hash_list);
/* register crypto algorithms the device supports */
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 403d8d5..7c9803b 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -281,6 +281,32 @@ static void __exit caam_rng_exit(void)
static int __init caam_rng_init(void)
{
struct device *dev;
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ void *priv;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
+ if (!dev_node)
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev)
+ return -ENODEV;
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+ /*
+* If priv is NULL, it's probably because the caam driver wasn't
+* properly initialized (e.g. RNG4 init failed). Thus, bail out here.
+*/
+ if (!priv)
+ return -ENODEV;
dev = caam_jr_alloc();
if (IS_ERR(dev)) {
--
1.8.1.4
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RE: [PATCH v2] crypto: caam - fix caamrng compilation warning
Acked-by: Ruchika Gupta > -Original Message- > From: Yashpal Dutta [mailto:yashpal.du...@freescale.com] > Sent: Friday, March 21, 2014 12:30 AM > To: linux-crypto@vger.kernel.org; Gupta Ruchika-R66431; Garg Vakul-B16394; > Geanta Neag Horia Ioan-B05471 > Cc: Dutta Yashpal-B05456; sta...@vger.kernel.org > Subject: [PATCH v2] crypto: caam - fix caamrng compilation warning > > caam_init_rng was erroneously passed pointer address instead of rng context > pointer. This results in Linux compilation warnings > > Cc: # 3.13.6: 6e4e603: crypto: caam - Dynamic > memory > Cc: # 3.13.6 > Signed-off-by: Yashpal Dutta > --- > drivers/crypto/caam/caamrng.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c > index 403d8d5..3529b54 100644 > --- a/drivers/crypto/caam/caamrng.c > +++ b/drivers/crypto/caam/caamrng.c > @@ -290,7 +290,7 @@ static int __init caam_rng_init(void) > rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_DMA); > if (!rng_ctx) > return -ENOMEM; > - caam_init_rng(&rng_ctx, dev); > + caam_init_rng(rng_ctx, dev); > > dev_info(dev, "registering rng-caam\n"); > return hwrng_register(&caam_rng); > -- > 1.8.1.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v3] crypto: caam - power management support for caam job-ring
Acked-by: Ruchika Gupta
> -Original Message-
> From: Yashpal Dutta [mailto:yashpal.du...@freescale.com]
> Sent: Friday, March 21, 2014 12:21 AM
> To: linux-crypto@vger.kernel.org; Geanta Neag Horia Ioan-B05471; Garg Vakul-
> B16394; Gupta Ruchika-R66431
> Cc: Dutta Yashpal-B05456; sta...@vger.kernel.org
> Subject: [PATCH v3] crypto: caam - power management support for caam job-
> ring
>
> Job ring is suspended gracefully and resume afresh.
>
> Both Sleep (where device will remain powered-on) and Deep-sleep (where
> device will be powered-down are handled gracefully. Persistance sessions are
> not supported across deep-sleep.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Yashpal Dutta
> ---
> drivers/crypto/caam/intern.h | 2 +
> drivers/crypto/caam/jr.c | 257 +++-
> ---
> 2 files changed, 190 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
> index 6d85fcc..0d41d05 100644
> --- a/drivers/crypto/caam/intern.h
> +++ b/drivers/crypto/caam/intern.h
> @@ -54,6 +54,8 @@ struct caam_drv_private_jr {
> int inp_ring_write_index; /* Input index "tail" */
> int head; /* entinfo (s/w ring) head index */
> dma_addr_t *inpring;/* Base of input ring, alloc DMA-safe */
> + dma_addr_t inpbusaddr; /* Input ring physical address */
> + dma_addr_t outbusaddr; /* Output ring physical address */
> spinlock_t outlock cacheline_aligned; /* Output ring index lock
> */
> int out_ring_read_index;/* Output index "tail" */
> int tail; /* entinfo (s/w ring) tail index */
> diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index
> 1d80bd3..2a79218 100644
> --- a/drivers/crypto/caam/jr.c
> +++ b/drivers/crypto/caam/jr.c
> @@ -68,7 +68,6 @@ static int caam_reset_hw_jr(struct device *dev) int
> caam_jr_shutdown(struct device *dev) {
> struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
> - dma_addr_t inpbusaddr, outbusaddr;
> int ret;
>
> ret = caam_reset_hw_jr(dev);
> @@ -78,13 +77,10 @@ int caam_jr_shutdown(struct device *dev)
> /* Release interrupt */
> free_irq(jrp->irq, dev);
>
> - /* Free rings */
> - inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
> - outbusaddr = rd_reg64(&jrp->rregs->outring_base);
> dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
> - jrp->inpring, inpbusaddr);
> + jrp->inpring, jrp->inpbusaddr);
> dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
> - jrp->outring, outbusaddr);
> + jrp->outring, jrp->outbusaddr);
> kfree(jrp->entinfo);
>
> return ret;
> @@ -159,78 +155,82 @@ static irqreturn_t caam_jr_interrupt(int irq, void
> *st_dev)
> return IRQ_HANDLED;
> }
>
> -/* Deferred service handler, run as interrupt-fired tasklet */ -static void
> caam_jr_dequeue(unsigned long devarg)
> +/* Consume the processed output ring Job */ static inline void
> +caam_jr_consume(struct device *dev)
> {
> int hw_idx, sw_idx, i, head, tail;
> - struct device *dev = (struct device *)devarg;
> struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
> void (*usercall)(struct device *dev, u32 *desc, u32 status, void
> *arg);
> u32 *userdesc, userstatus;
> void *userarg;
>
> - while (rd_reg32(&jrp->rregs->outring_used)) {
> + head = ACCESS_ONCE(jrp->head);
> + spin_lock(&jrp->outlock);
>
> - head = ACCESS_ONCE(jrp->head);
> + sw_idx = tail = jrp->tail;
> + hw_idx = jrp->out_ring_read_index;
>
> - spin_lock(&jrp->outlock);
> + for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) {
> + sw_idx = (tail + i) & (JOBR_DEPTH - 1);
>
> - sw_idx = tail = jrp->tail;
> - hw_idx = jrp->out_ring_read_index;
> + smp_read_barrier_depends();
> + if (jrp->outring[hw_idx].desc ==
> + jrp->entinfo[sw_idx].desc_addr_dma)
> + break; /* found */
> + }
> + /* we should never fail to find a matching descriptor */
> + BUG_ON(CIRC_CNT(head, tail + i, JOBR_DEPTH) <= 0);
>
> - for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) {
> - sw_idx = (tail + i) & (JOBR_DEPTH - 1);
> + /* Unmap just-run descriptor so we can post-process */
RE: [PATCH] crypto: caam - Dynamic memory allocation for caam_rng_ctx object
Acked-by: Ruchika Gupta
> -Original Message-
> From: Nitesh Lal [mailto:niteshnarayan...@freescale.com]
> Sent: Friday, March 07, 2014 4:06 PM
> To: linux-crypto@vger.kernel.org; Gupta Ruchika-R66431; Dutta Yashpal-
> B05456; herb...@gondor.apana.org
> Cc: Lal Nitesh-B44382
> Subject: [PATCH] crypto: caam - Dynamic memory allocation for caam_rng_ctx
> object
>
> This patch allocates memory from DMAable region to the caam_rng_ctx object,
> earlier it had been statically allocated which resulted in errorneous
> behaviour on inserting the caamrng module at the runtime.
>
> Signed-off-by: Nitesh Lal
> ---
> drivers/crypto/caam/caamrng.c | 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
> index 28486b1..403d8d5 100644
> --- a/drivers/crypto/caam/caamrng.c
> +++ b/drivers/crypto/caam/caamrng.c
> @@ -76,7 +76,7 @@ struct caam_rng_ctx {
> struct buf_data bufs[2];
> };
>
> -static struct caam_rng_ctx rng_ctx;
> +static struct caam_rng_ctx *rng_ctx;
>
> static inline void rng_unmap_buf(struct device *jrdev, struct buf_data *bd)
> { @@ -137,7 +137,7 @@ static inline int submit_job(struct caam_rng_ctx *ctx,
> int to_current)
>
> static int caam_read(struct hwrng *rng, void *data, size_t max, bool wait)
> {
> - struct caam_rng_ctx *ctx = &rng_ctx;
> + struct caam_rng_ctx *ctx = rng_ctx;
> struct buf_data *bd = &ctx->bufs[ctx->current_buf];
> int next_buf_idx, copied_idx;
> int err;
> @@ -237,12 +237,12 @@ static void caam_cleanup(struct hwrng *rng)
> struct buf_data *bd;
>
> for (i = 0; i < 2; i++) {
> - bd = &rng_ctx.bufs[i];
> + bd = &rng_ctx->bufs[i];
> if (atomic_read(&bd->empty) == BUF_PENDING)
> wait_for_completion(&bd->filled);
> }
>
> - rng_unmap_ctx(&rng_ctx);
> + rng_unmap_ctx(rng_ctx);
> }
>
> static void caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) @@ -273,8
> +273,9 @@ static struct hwrng caam_rng = {
>
> static void __exit caam_rng_exit(void)
> {
> - caam_jr_free(rng_ctx.jrdev);
> + caam_jr_free(rng_ctx->jrdev);
> hwrng_unregister(&caam_rng);
> + kfree(rng_ctx);
> }
>
> static int __init caam_rng_init(void)
> @@ -286,7 +287,9 @@ static int __init caam_rng_init(void)
> pr_err("Job Ring Device allocation for transform failed\n");
> return PTR_ERR(dev);
> }
> -
> + rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_DMA);
> + if (!rng_ctx)
> + return -ENOMEM;
> caam_init_rng(&rng_ctx, dev);
>
> dev_info(dev, "registering rng-caam\n");
> --
> 1.8.1.4
>
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RE: [PATCH] crypto/caam/jr.c: include linux/of_address.h
A Patch for this has already been submitted. Regards, Ruchika > -Original Message- > From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto- > ow...@vger.kernel.org] On Behalf Of shh@gmail.com > Sent: Tuesday, November 26, 2013 12:00 PM > To: linux-crypto@vger.kernel.org; linux-ker...@vger.kernel.org > Cc: herb...@gondor.hengli.com.au; da...@davemloft.net; Xie Shaohui-B21989 > Subject: [PATCH] crypto/caam/jr.c: include linux/of_address.h > > From: Shaohui Xie > > to avoid a compile error: > > drivers/crypto/caam/jr.c: In function 'caam_jr_probe': > drivers/crypto/caam/jr.c:468:2: error: implicit declaration of function > 'of_iomap' [-Werror=implicit-function-declaration] > drivers/crypto/caam/jr.c:468:7: warning: assignment makes pointer from > integer without a cast [enabled by default] > > Signed-off-by: Shaohui Xie > --- > drivers/crypto/caam/jr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index > d23356d2..1d80bd3 100644 > --- a/drivers/crypto/caam/jr.c > +++ b/drivers/crypto/caam/jr.c > @@ -6,6 +6,7 @@ > */ > > #include > +#include > > #include "compat.h" > #include "regs.h" > -- > 1.8.4.1 > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-crypto" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html --- Begin Message --- Acked-by: Ruchika Gupta > -Original Message- > From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto- > ow...@vger.kernel.org] On Behalf Of Michael Neuling > Sent: Monday, November 18, 2013 9:50 AM > To: Gupta Ruchika-R66431 > Cc: Garg Vakul-B16394; Herbert Xu; linux-crypto@vger.kernel.org; > s...@canb.auug.org.au > Subject: [PATCH] crypto: caam - Add missing Job Ring include > > linuxnext currently doesn't compile with the powerpc mpc85xx_defconfig > giving: > > drivers/crypto/caam/jr.c: In function 'caam_jr_probe': > drivers/crypto/caam/jr.c:468:2: error: implicit declaration of function > 'of_iomap' [-Werror=implicit-function-declaration] > > In: > commit 313ea293e9c4d1eabcaddd2c0800f083b03c2a2e > Author: Ruchika Gupta > crypto: caam - Add Platform driver for Job Ring > > We added a reference to of_iomap but did add the necessary include file. > > The below adds this include. > > Signed-off-by: Michael Neuling > > diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index > d23356d2..1d80bd3 100644 > --- a/drivers/crypto/caam/jr.c > +++ b/drivers/crypto/caam/jr.c > @@ -6,6 +6,7 @@ > */ > > #include > +#include > > #include "compat.h" > #include "regs.h" > -- > To unsubscribe from this list: send the line "unsubscribe linux-crypto" in > the body of a message to majord...@vger.kernel.org More majordomo info at > http://vger.kernel.org/majordomo-info.html --- End Message ---
RE: [PATCH] crypto: caam - Add missing Job Ring include
Hi Herbert, Can you please apply this patch. Regards, Ruchika > -Original Message- > From: Gupta Ruchika-R66431 > Sent: Tuesday, November 19, 2013 9:47 AM > To: 'Michael Neuling' > Cc: Garg Vakul-B16394; Herbert Xu; linux-crypto@vger.kernel.org; > s...@canb.auug.org.au > Subject: RE: [PATCH] crypto: caam - Add missing Job Ring include > > Acked-by: Ruchika Gupta > > > -Original Message- > > From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto- > > ow...@vger.kernel.org] On Behalf Of Michael Neuling > > Sent: Monday, November 18, 2013 9:50 AM > > To: Gupta Ruchika-R66431 > > Cc: Garg Vakul-B16394; Herbert Xu; linux-crypto@vger.kernel.org; > > s...@canb.auug.org.au > > Subject: [PATCH] crypto: caam - Add missing Job Ring include > > > > linuxnext currently doesn't compile with the powerpc mpc85xx_defconfig > > giving: > > > > drivers/crypto/caam/jr.c: In function 'caam_jr_probe': > > drivers/crypto/caam/jr.c:468:2: error: implicit declaration of > > function 'of_iomap' [-Werror=implicit-function-declaration] > > > > In: > > commit 313ea293e9c4d1eabcaddd2c0800f083b03c2a2e > > Author: Ruchika Gupta > > crypto: caam - Add Platform driver for Job Ring > > > > We added a reference to of_iomap but did add the necessary include file. > > > > The below adds this include. > > > > Signed-off-by: Michael Neuling > > > > diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index > > d23356d2..1d80bd3 100644 > > --- a/drivers/crypto/caam/jr.c > > +++ b/drivers/crypto/caam/jr.c > > @@ -6,6 +6,7 @@ > > */ > > > > #include > > +#include > > > > #include "compat.h" > > #include "regs.h" > > -- > > To unsubscribe from this list: send the line "unsubscribe > > linux-crypto" in the body of a message to majord...@vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] crypto: caam - Add missing Job Ring include
Acked-by: Ruchika Gupta > -Original Message- > From: linux-crypto-ow...@vger.kernel.org [mailto:linux-crypto- > ow...@vger.kernel.org] On Behalf Of Michael Neuling > Sent: Monday, November 18, 2013 9:50 AM > To: Gupta Ruchika-R66431 > Cc: Garg Vakul-B16394; Herbert Xu; linux-crypto@vger.kernel.org; > s...@canb.auug.org.au > Subject: [PATCH] crypto: caam - Add missing Job Ring include > > linuxnext currently doesn't compile with the powerpc mpc85xx_defconfig > giving: > > drivers/crypto/caam/jr.c: In function 'caam_jr_probe': > drivers/crypto/caam/jr.c:468:2: error: implicit declaration of function > 'of_iomap' [-Werror=implicit-function-declaration] > > In: > commit 313ea293e9c4d1eabcaddd2c0800f083b03c2a2e > Author: Ruchika Gupta > crypto: caam - Add Platform driver for Job Ring > > We added a reference to of_iomap but did add the necessary include file. > > The below adds this include. > > Signed-off-by: Michael Neuling > > diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index > d23356d2..1d80bd3 100644 > --- a/drivers/crypto/caam/jr.c > +++ b/drivers/crypto/caam/jr.c > @@ -6,6 +6,7 @@ > */ > > #include > +#include > > #include "compat.h" > #include "regs.h" > -- > To unsubscribe from this list: send the line "unsubscribe linux-crypto" in > the body of a message to majord...@vger.kernel.org More majordomo info at > http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] crypto: caam - Modify the interface layers to use JR API's
- Earlier interface layers - caamalg, caamhash, caamrng were
directly using the Controller driver private structure to access
the Job ring.
- Changed the above to use alloc/free API's provided by Job Ring Drive
Signed-off-by: Ruchika Gupta
Reviewed-by: Garg Vakul-B16394
---
drivers/crypto/caam/caamalg.c | 92 +--
drivers/crypto/caam/caamhash.c | 97 +++---
drivers/crypto/caam/caamrng.c | 37
drivers/crypto/caam/intern.h | 7 ---
4 files changed, 55 insertions(+), 178 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index ad9781e..4f44b71 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -86,6 +86,7 @@
#else
#define debug(format, arg...)
#endif
+static struct list_head alg_list;
/* Set DK bit in class 1 operation if shared */
static inline void append_dec_op1(u32 *desc, u32 type)
@@ -2057,7 +2058,6 @@ static struct caam_alg_template driver_algs[] = {
struct caam_crypto_alg {
struct list_head entry;
- struct device *ctrldev;
int class1_alg_type;
int class2_alg_type;
int alg_op;
@@ -2070,16 +2070,12 @@ static int caam_cra_init(struct crypto_tfm *tfm)
struct caam_crypto_alg *caam_alg =
container_of(alg, struct caam_crypto_alg, crypto_alg);
struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
- struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
- struct platform_device *pdev;
- int tgt_jr = atomic_inc_return(&priv->tfm_count);
- /*
-* distribute tfms across job rings to ensure in-order
-* crypto request processing per tfm
-*/
- pdev = priv->jrpdev[(tgt_jr / 2) % priv->total_jobrs];
- ctx->jrdev = &pdev->dev;
+ ctx->jrdev = caam_jr_alloc();
+ if (IS_ERR(ctx->jrdev)) {
+ pr_err("Job Ring Device allocation for transform failed\n");
+ return PTR_ERR(ctx->jrdev);
+ }
/* copy descriptor header template value */
ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
@@ -2106,44 +2102,26 @@ static void caam_cra_exit(struct crypto_tfm *tfm)
dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
desc_bytes(ctx->sh_desc_givenc),
DMA_TO_DEVICE);
+
+ caam_jr_free(ctx->jrdev);
}
static void __exit caam_algapi_exit(void)
{
- struct device_node *dev_node;
- struct platform_device *pdev;
- struct device *ctrldev;
- struct caam_drv_private *priv;
struct caam_crypto_alg *t_alg, *n;
- dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
- if (!dev_node) {
- dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
- if (!dev_node)
- return;
- }
-
- pdev = of_find_device_by_node(dev_node);
- if (!pdev)
- return;
-
- ctrldev = &pdev->dev;
- of_node_put(dev_node);
- priv = dev_get_drvdata(ctrldev);
-
- if (!priv->alg_list.next)
+ if (!alg_list.next)
return;
- list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
+ list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
crypto_unregister_alg(&t_alg->crypto_alg);
list_del(&t_alg->entry);
kfree(t_alg);
}
}
-static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
- struct caam_alg_template
+static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
*template)
{
struct caam_crypto_alg *t_alg;
@@ -2151,7 +2129,7 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
device *ctrldev,
t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
if (!t_alg) {
- dev_err(ctrldev, "failed to allocate t_alg\n");
+ pr_err("failed to allocate t_alg\n");
return ERR_PTR(-ENOMEM);
}
@@ -2183,69 +2161,39 @@ static struct caam_crypto_alg *caam_alg_alloc(struct
device *ctrldev,
t_alg->class1_alg_type = template->class1_alg_type;
t_alg->class2_alg_type = template->class2_alg_type;
t_alg->alg_op = template->alg_op;
- t_alg->ctrldev = ctrldev;
return t_alg;
}
static int __init caam_algapi_init(void)
{
- struct device_node *dev_node;
- struct platform_device *pdev;
- struct device *ctrldev;
- struct caam_drv_private *priv;
int i = 0, err = 0;
- dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.
[PATCH 1/3] crypto: caam - Add Platform driver for Job Ring
The SEC Job Rings are now available as individual devices. This would enable sharing of job rings between kernel and user space. Job Rings can now be dynamically bound/unbound from kernel. Changes are made in the following layers of CAAM Driver 1. Controller driver - Does basic initialization of CAAM Block. - Creates platform devices for Job Rings. (Earlier the initialization of Job ring was done by the controller driver) 2. JobRing Platform driver - Manages the platform Job Ring devices created by the controller driver Signed-off-by: Ruchika Gupta Reviewed-by: Garg Vakul-B16394 --- drivers/crypto/caam/Kconfig| 25 +++- drivers/crypto/caam/Makefile | 4 +- drivers/crypto/caam/caamalg.c | 4 +- drivers/crypto/caam/caamhash.c | 4 +- drivers/crypto/caam/caamrng.c | 7 +- drivers/crypto/caam/ctrl.c | 30 +++-- drivers/crypto/caam/intern.h | 6 +- drivers/crypto/caam/jr.c | 285 + drivers/crypto/caam/jr.h | 3 - 9 files changed, 232 insertions(+), 136 deletions(-) diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig index ca89f6b..e7555ff 100644 --- a/drivers/crypto/caam/Kconfig +++ b/drivers/crypto/caam/Kconfig @@ -4,16 +4,29 @@ config CRYPTO_DEV_FSL_CAAM help Enables the driver module for Freescale's Cryptographic Accelerator and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). - This module adds a job ring operation interface, and configures h/w + This module creates job ring devices, and configures h/w to operate as a DPAA component automatically, depending on h/w feature availability. To compile this driver as a module, choose M here: the module will be called caam. +config CRYPTO_DEV_FSL_CAAM_JR + tristate "Freescale CAAM Job Ring driver backend" + depends on CRYPTO_DEV_FSL_CAAM + default y + help + Enables the driver module for Job Rings which are part of + Freescale's Cryptographic Accelerator + and Assurance Module (CAAM). This module adds a job ring operation + interface. + + To compile this driver as a module, choose M here: the module + will be called caam_jr. + config CRYPTO_DEV_FSL_CAAM_RINGSIZE int "Job Ring size" - depends on CRYPTO_DEV_FSL_CAAM + depends on CRYPTO_DEV_FSL_CAAM_JR range 2 9 default "9" help @@ -31,7 +44,7 @@ config CRYPTO_DEV_FSL_CAAM_RINGSIZE config CRYPTO_DEV_FSL_CAAM_INTC bool "Job Ring interrupt coalescing" - depends on CRYPTO_DEV_FSL_CAAM + depends on CRYPTO_DEV_FSL_CAAM_JR default n help Enable the Job Ring's interrupt coalescing feature. @@ -62,7 +75,7 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD config CRYPTO_DEV_FSL_CAAM_CRYPTO_API tristate "Register algorithm implementations with the Crypto API" - depends on CRYPTO_DEV_FSL_CAAM + depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR default y select CRYPTO_ALGAPI select CRYPTO_AUTHENC @@ -76,7 +89,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API config CRYPTO_DEV_FSL_CAAM_AHASH_API tristate "Register hash algorithm implementations with Crypto API" - depends on CRYPTO_DEV_FSL_CAAM + depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR default y select CRYPTO_HASH help @@ -88,7 +101,7 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API config CRYPTO_DEV_FSL_CAAM_RNG_API tristate "Register caam device for hwrng API" - depends on CRYPTO_DEV_FSL_CAAM + depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR default y select CRYPTO_RNG select HW_RANDOM diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile index d56bd0e..550758a 100644 --- a/drivers/crypto/caam/Makefile +++ b/drivers/crypto/caam/Makefile @@ -6,8 +6,10 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y) endif obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o -caam-objs := ctrl.o jr.o error.o key_gen.o +caam-objs := ctrl.o +caam_jr-objs := jr.o key_gen.o error.o diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index 86a0d41..ad9781e 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -2071,13 +2071,15 @@ static int caam_cra_init(struct crypto_tfm *tfm) container_of(alg, struct caam_crypto_alg, crypto_alg); struct caam_ctx *ctx = crypto_tfm_ctx(tfm); struct caam_drv_private *priv = dev_get_d
[PATCH 2/3] crypto: caam - Add API's to allocate/free Job Rings
With each of the Job Ring available as a platform device, the
Job Ring driver needs to take care of allocation/deallocation
of the Job Rings to the above interface layers. Added APIs
in Job Ring Driver to allocate/free Job rings
Signed-off-by: Ruchika Gupta
Reviewed-by: Garg Vakul-B16394
---
drivers/crypto/caam/intern.h | 3 +++
drivers/crypto/caam/jr.c | 60 +---
drivers/crypto/caam/jr.h | 2 ++
3 files changed, 62 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index bff4acd..b781445 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -44,6 +44,9 @@ struct caam_drv_private_jr {
struct tasklet_struct irqtask;
int irq;/* One per queue */
+ /* Number of scatterlist crypt transforms active on the JobR */
+ atomic_t tfm_count cacheline_aligned;
+
/* Job ring info */
int ringsize; /* Size of rings (assume input = output) */
struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index cdeaf25..636bb53 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -97,10 +97,9 @@ static int caam_jr_remove(struct platform_device *pdev)
jrpriv = dev_get_drvdata(jrdev);
/*
-* Make sure ring is empty before release
+* Return EBUSY if job ring already allocated.
*/
- if (rd_reg32(&jrpriv->rregs->outring_used) ||
- (rd_reg32(&jrpriv->rregs->inpring_avail) != JOBR_DEPTH)) {
+ if (atomic_read(&jrpriv->tfm_count)) {
dev_err(jrdev, "Device is busy\n");
return -EBUSY;
}
@@ -234,6 +233,59 @@ static void caam_jr_dequeue(unsigned long devarg)
}
/**
+ * caam_jr_alloc() - Alloc a job ring for someone to use as needed.
+ *
+ * returns : pointer to the newly allocated physical
+ * JobR dev can be written to if successful.
+ **/
+struct device *caam_jr_alloc(void)
+{
+ struct caam_drv_private_jr *jrpriv, *min_jrpriv = NULL;
+ struct device *dev = NULL;
+ int min_tfm_cnt = INT_MAX;
+ int tfm_cnt;
+
+ spin_lock(&driver_data.jr_alloc_lock);
+
+ if (list_empty(&driver_data.jr_list)) {
+ spin_unlock(&driver_data.jr_alloc_lock);
+ return ERR_PTR(-ENODEV);
+ }
+
+ list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) {
+ tfm_cnt = atomic_read(&jrpriv->tfm_count);
+ if (tfm_cnt < min_tfm_cnt) {
+ min_tfm_cnt = tfm_cnt;
+ min_jrpriv = jrpriv;
+ }
+ if (!min_tfm_cnt)
+ break;
+ }
+
+ if (min_jrpriv) {
+ atomic_inc(&min_jrpriv->tfm_count);
+ dev = min_jrpriv->dev;
+ }
+ spin_unlock(&driver_data.jr_alloc_lock);
+
+ return dev;
+}
+EXPORT_SYMBOL(caam_jr_alloc);
+
+/**
+ * caam_jr_free() - Free the Job Ring
+ * @rdev - points to the dev that identifies the Job ring to
+ * be released.
+ **/
+void caam_jr_free(struct device *rdev)
+{
+ struct caam_drv_private_jr *jrpriv = dev_get_drvdata(rdev);
+
+ atomic_dec(&jrpriv->tfm_count);
+}
+EXPORT_SYMBOL(caam_jr_free);
+
+/**
* caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK,
* -EBUSY if the queue is full, -EIO if it cannot map the caller's
* descriptor.
@@ -442,6 +494,8 @@ static int caam_jr_probe(struct platform_device *pdev)
list_add_tail(&jrpriv->list_node, &driver_data.jr_list);
spin_unlock(&driver_data.jr_alloc_lock);
+ atomic_set(&jrpriv->tfm_count, 0);
+
return 0;
}
diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h
index 02f69bb..97113a6 100644
--- a/drivers/crypto/caam/jr.h
+++ b/drivers/crypto/caam/jr.h
@@ -8,6 +8,8 @@
#define JR_H
/* Prototypes for backend-level services exposed to APIs */
+struct device *caam_jr_alloc(void);
+void caam_jr_free(struct device *rdev);
int caam_jr_enqueue(struct device *dev, u32 *desc,
void (*cbk)(struct device *dev, u32 *desc, u32 status,
void *areq),
--
1.8.1.4
--
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[PATCH] crypto: caam - Remove unused functions from Job Ring
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 3 --
drivers/crypto/caam/intern.h | 5
drivers/crypto/caam/jr.c | 67
drivers/crypto/caam/jr.h | 2 --
4 files changed, 77 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 86c9600..b010d42 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -313,9 +313,6 @@ static int caam_probe(struct platform_device *pdev)
/* NOTE: RTIC detection ought to go here, around Si time */
- /* Initialize queue allocator lock */
- spin_lock_init(&ctrlpriv->jr_alloc_lock);
-
caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
/* Report "alive" for developer to see */
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index e4a16b7..34c4b9f 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -9,9 +9,6 @@
#ifndef INTERN_H
#define INTERN_H
-#define JOBR_UNASSIGNED 0
-#define JOBR_ASSIGNED 1
-
/* Currently comes from Kconfig param as a ^2 (driver-required) */
#define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
@@ -46,7 +43,6 @@ struct caam_drv_private_jr {
struct caam_job_ring __iomem *rregs;/* JobR's register space */
struct tasklet_struct irqtask;
int irq;/* One per queue */
- int assign; /* busy/free */
/* Job ring info */
int ringsize; /* Size of rings (assume input = output) */
@@ -68,7 +64,6 @@ struct caam_drv_private {
struct device *dev;
struct device **jrdev; /* Alloc'ed array per sub-device */
- spinlock_t jr_alloc_lock;
struct platform_device *pdev;
/* Physical-presence section */
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index b4aa773e..105ba4d 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -126,72 +126,6 @@ static void caam_jr_dequeue(unsigned long devarg)
}
/**
- * caam_jr_register() - Alloc a ring for someone to use as needed. Returns
- * an ordinal of the rings allocated, else returns -ENODEV if no rings
- * are available.
- * @ctrldev: points to the controller level dev (parent) that
- * owns rings available for use.
- * @dev: points to where a pointer to the newly allocated queue's
- * dev can be written to if successful.
- **/
-int caam_jr_register(struct device *ctrldev, struct device **rdev)
-{
- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
- struct caam_drv_private_jr *jrpriv = NULL;
- int ring;
-
- /* Lock, if free ring - assign, unlock */
- spin_lock(&ctrlpriv->jr_alloc_lock);
- for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
- jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
- if (jrpriv->assign == JOBR_UNASSIGNED) {
- jrpriv->assign = JOBR_ASSIGNED;
- *rdev = ctrlpriv->jrdev[ring];
- spin_unlock(&ctrlpriv->jr_alloc_lock);
- return ring;
- }
- }
-
- /* If assigned, write dev where caller needs it */
- spin_unlock(&ctrlpriv->jr_alloc_lock);
- *rdev = NULL;
-
- return -ENODEV;
-}
-EXPORT_SYMBOL(caam_jr_register);
-
-/**
- * caam_jr_deregister() - Deregister an API and release the queue.
- * Returns 0 if OK, -EBUSY if queue still contains pending entries
- * or unprocessed results at the time of the call
- * @dev - points to the dev that identifies the queue to
- *be released.
- **/
-int caam_jr_deregister(struct device *rdev)
-{
- struct caam_drv_private_jr *jrpriv = dev_get_drvdata(rdev);
- struct caam_drv_private *ctrlpriv;
-
- /* Get the owning controller's private space */
- ctrlpriv = dev_get_drvdata(jrpriv->parentdev);
-
- /*
-* Make sure ring empty before release
-*/
- if (rd_reg32(&jrpriv->rregs->outring_used) ||
- (rd_reg32(&jrpriv->rregs->inpring_avail) != JOBR_DEPTH))
- return -EBUSY;
-
- /* Release ring */
- spin_lock(&ctrlpriv->jr_alloc_lock);
- jrpriv->assign = JOBR_UNASSIGNED;
- spin_unlock(&ctrlpriv->jr_alloc_lock);
-
- return 0;
-}
-EXPORT_SYMBOL(caam_jr_deregister);
-
-/**
* caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK,
* -EBUSY if the queue is full, -EIO if it cannot map the caller's
* descriptor.
@@ -379,7 +313,6 @@ static int caam_jr_init(struct device *dev)
(JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) |
(JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT));
- jrp->assign = JOBR_UNASSIGNED;
return 0;
}
diff --git a/drivers
[PATCH] crypto: caam - RNG instantiation by directly programming DECO
Remove the dependency of RNG instantiation on Job Ring. Now
RNG instantiation for devices with RNG version > 4 is done
by directly programming DECO 0.
Signed-off-by: Ruchika Gupta
---
drivers/crypto/caam/ctrl.c | 74 ++
drivers/crypto/caam/regs.h | 12 +++-
2 files changed, 47 insertions(+), 39 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index f5d6dec..86c9600 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -75,55 +75,53 @@ static void build_instantiation_desc(u32 *desc)
OP_ALG_RNG4_SK);
}
-struct instantiate_result {
- struct completion completion;
- int err;
-};
-
-static void rng4_init_done(struct device *dev, u32 *desc, u32 err,
- void *context)
+static int instantiate_rng(struct device *ctrldev)
{
- struct instantiate_result *instantiation = context;
-
- if (err) {
- char tmp[CAAM_ERROR_STR_MAX];
-
- dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
- }
-
- instantiation->err = err;
- complete(&instantiation->completion);
-}
-
-static int instantiate_rng(struct device *jrdev)
-{
- struct instantiate_result instantiation;
-
- dma_addr_t desc_dma;
+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
+ struct caam_full __iomem *topregs;
+ unsigned int timeout = 10;
u32 *desc;
- int ret;
+ int i, ret = 0;
desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA);
if (!desc) {
- dev_err(jrdev, "cannot allocate RNG init descriptor memory\n");
+ dev_err(ctrldev, "can't allocate RNG init descriptor memory\n");
return -ENOMEM;
}
-
build_instantiation_desc(desc);
- desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE);
- init_completion(&instantiation.completion);
- ret = caam_jr_enqueue(jrdev, desc, rng4_init_done, &instantiation);
- if (!ret) {
- wait_for_completion_interruptible(&instantiation.completion);
- ret = instantiation.err;
- if (ret)
- dev_err(jrdev, "unable to instantiate RNG\n");
+
+ /* Set the bit to request direct access to DECO0 */
+ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
+ setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
+
+ while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
+--timeout)
+ cpu_relax();
+
+ if (!timeout) {
+ dev_err(ctrldev, "failed to acquire DECO 0\n");
+ ret = -EIO;
+ goto out;
}
- dma_unmap_single(jrdev, desc_dma, desc_bytes(desc), DMA_TO_DEVICE);
+ for (i = 0; i < desc_len(desc); i++)
+ topregs->deco.descbuf[i] = *(desc + i);
- kfree(desc);
+ wr_reg32(&topregs->deco.jr_ctl_hi, DECO_JQCR_WHL | DECO_JQCR_FOUR);
+
+ timeout = 1000;
+ while ((rd_reg32(&topregs->deco.desc_dbg) & DECO_DBG_VALID) &&
+--timeout)
+ cpu_relax();
+ if (!timeout) {
+ dev_err(ctrldev, "failed to instantiate RNG\n");
+ ret = -EIO;
+ }
+
+ clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
+out:
+ kfree(desc);
return ret;
}
@@ -303,7 +301,7 @@ static int caam_probe(struct platform_device *pdev)
if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 &&
!(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) {
kick_trng(pdev);
- ret = instantiate_rng(ctrlpriv->jrdev[0]);
+ ret = instantiate_rng(dev);
if (ret) {
caam_remove(pdev);
return ret;
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index c09142f..4455396 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -341,6 +341,8 @@ struct caam_ctrl {
#define MCFGR_DMA_RESET0x1000
#define MCFGR_LONG_PTR 0x0001 /* Use >32-bit desc addressing */
#define SCFGR_RDBENABLE0x0400
+#define DECORR_RQD0ENABLE 0x0001 /* Enable DECO0 for direct access */
+#define DECORR_DEN00x0001 /* DECO0 available for access*/
/* AXI read cache control */
#define MCFGR_ARCACHE_SHIFT12
@@ -703,9 +705,16 @@ struct caam_deco {
struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
u32 rsvd29[48];
u32 descbuf[64];/* DxD
[PATCH] crypto: caam - FIX RNG init for RNG greater than equal to 4
For SEC including a RNG block version >= 4, special initialization
must occur before any descriptor that uses RNG block can be
submitted. This initialization is required not only for SEC
with version greater than 5.0, but for SEC with RNG version >=4.
There may be a case where RNG has already been instantiated by
u-boot or boot ROM code.In such SoCs, if RNG is initialized again
SEC would returns "Instantiation error". Hence, the initialization
status of RNG4 should be also checked before doing RNG init.
Signed-off-by: Ruchika Gupta
Signed-off-by: Alex Porosanu
Signed-off-by: Andy Fleming
---
This patch supersedes the patchset submitted earlier
http://www.mail-archive.com/linux-crypto@vger.kernel.org/msg08348.html
crypto: caam - support for RNG version retrieval
crypto: caam - fix RNG init for SEC with RNG version greater than 4
drivers/crypto/caam/ctrl.c | 10 +++---
drivers/crypto/caam/regs.h | 42 +-
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 19faea2..644d145 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -202,6 +202,7 @@ static int caam_probe(struct platform_device *pdev)
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
+ u64 cha_vid;
ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
if (!ctrlpriv)
@@ -293,11 +294,14 @@ static int caam_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
+
/*
-* RNG4 based SECs (v5+) need special initialization prior
-* to executing any descriptors
+* If SEC has RNG version >= 4 and RNG state handle has not been
+* already instantiated ,do RNG instantiation
*/
- if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) {
+ if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 &&
+ !(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) {
kick_trng(pdev);
ret = instantiate_rng(ctrlpriv->jrdev[0]);
if (ret) {
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cd6feda..c09142f 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -117,6 +117,43 @@ struct jr_outentry {
#define CHA_NUM_DECONUM_SHIFT 56
#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+/* CHA Version IDs */
+#define CHA_ID_AES_SHIFT 0
+#define CHA_ID_AES_MASK(0xfull << CHA_ID_AES_SHIFT)
+
+#define CHA_ID_DES_SHIFT 4
+#define CHA_ID_DES_MASK(0xfull << CHA_ID_DES_SHIFT)
+
+#define CHA_ID_ARC4_SHIFT 8
+#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
+
+#define CHA_ID_MD_SHIFT12
+#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
+
+#define CHA_ID_RNG_SHIFT 16
+#define CHA_ID_RNG_MASK(0xfull << CHA_ID_RNG_SHIFT)
+
+#define CHA_ID_SNW8_SHIFT 20
+#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
+
+#define CHA_ID_KAS_SHIFT 24
+#define CHA_ID_KAS_MASK(0xfull << CHA_ID_KAS_SHIFT)
+
+#define CHA_ID_PK_SHIFT28
+#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
+
+#define CHA_ID_CRC_SHIFT 32
+#define CHA_ID_CRC_MASK(0xfull << CHA_ID_CRC_SHIFT)
+
+#define CHA_ID_SNW9_SHIFT 36
+#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
+
+#define CHA_ID_DECO_SHIFT 56
+#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
+
+#define CHA_ID_JR_SHIFT60
+#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
+
struct sec_vid {
u16 ip_id;
u8 maj_rev;
@@ -228,7 +265,10 @@ struct rng4tst {
u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
u32 rtfrqcnt; /* PRGM=0: freq. count register */
};
- u32 rsvd1[56];
+ u32 rsvd1[40];
+#define RDSTA_IF0 0x0001
+ u32 rdsta;
+ u32 rsvd2[15];
};
/*
--
1.7.7.6
--
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