From: Fabio Estevam
This reverts commit 46e4bf08f6388ba748597275012d715d5e1861e6.
Commit 46e4bf08f6388 ("crypto: caam: cleanup CONFIG_64BIT ifdefs
when using io{read|write}64") causes kernel crash on imx6 systems:
[2.041187] caam_jr 2101000.jr0: job ring error: irqstate: 0103
[2.049878] Internal error: Oops - undefined instruction: 0 [#1] SMP ARM
[2.056591] Modules linked in:
[2.059671] CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.18.0-rc3-next-20180703 #484
[2.067338] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[2.073892] PC is at caam_jr_interrupt+0x120/0x12c
[2.078702] LR is at vprintk_emit+0x228/0x43c
[2.083069] pc : []lr : []psr: 6193
[2.089344] sp : c1001d80 ip : c1001be0 fp : c1001da4
[2.094576] r10: c107ffe7 r9 : ec749e00 r8 : 012d
[2.099810] r7 : c1001de0 r6 : c17ecc10 r5 : ec7a6010 r4 : 0103
[2.106346] r3 : ba36048e r2 : ba36048e r1 : 0001 r0 : 0037
[2.112884] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment none
Revert it for now.
Signed-off-by: Fabio Estevam
---
drivers/crypto/caam/regs.h | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 5826acd..4fb91ba 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
/*
* Architecture-specific register access methods
@@ -136,9 +136,10 @@ static inline void clrsetbits_32(void __iomem *reg, u32
clear, u32 set)
*base + 0x : least-significant 32 bits
*base + 0x0004 : most-significant 32 bits
*/
+#ifdef CONFIG_64BIT
static inline void wr_reg64(void __iomem *reg, u64 data)
{
- if (!caam_imx && caam_little_end)
+ if (caam_little_end)
iowrite64(data, reg);
else
iowrite64be(data, reg);
@@ -146,12 +147,35 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
static inline u64 rd_reg64(void __iomem *reg)
{
- if (!caam_imx && caam_little_end)
+ if (caam_little_end)
return ioread64(reg);
else
return ioread64be(reg);
}
+#else /* CONFIG_64BIT */
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+ if (!caam_imx && caam_little_end) {
+ wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
+ wr_reg32((u32 __iomem *)(reg), data);
+ } else {
+ wr_reg32((u32 __iomem *)(reg), data >> 32);
+ wr_reg32((u32 __iomem *)(reg) + 1, data);
+ }
+}
+
+static inline u64 rd_reg64(void __iomem *reg)
+{
+ if (!caam_imx && caam_little_end)
+ return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
+ (u64)rd_reg32((u32 __iomem *)(reg)));
+
+ return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
+ (u64)rd_reg32((u32 __iomem *)(reg) + 1));
+}
+#endif /* CONFIG_64BIT */
+
static inline u64 cpu_to_caam_dma64(dma_addr_t value)
{
if (caam_imx)
--
2.7.4