Re: [PATCH 2/2] crypto: stm32 - Support for STM32 HASH module

[Kamil Konieczny]

On 13.07.2017 15:32, Lionel Debieve wrote:
> This module register a HASH module that support multiples
> algorithms: MD5, SHA1, SHA224, SHA256. [...]

> +static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
> +{
> + struct stm32_hash_dev *hdev = dev_id;
> + int err;

The 'err' var is used without initialize.

> +
> + if (HASH_FLAGS_CPU & hdev->flags) {
> + if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
> + hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
> + goto finish;
> + }
> + } else if (HASH_FLAGS_DMA_READY & hdev->flags) {
> + if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
> + hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
> + goto finish;
> + }
> + }
> +
> + return IRQ_HANDLED;
> +
> +finish:
> + /*Finish current request */
> + stm32_hash_finish_req(hdev->req, err);
> +
> + return IRQ_HANDLED;
> +}
> +
and here is beginnig for finish_req:

+static void stm32_hash_finish_req(struct ahash_request *req, int err)
+{
+   struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
+   struct stm32_hash_dev *hdev = rctx->hdev;
+
+   if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {

-- 
Best regards,
Kamil Konieczny
Samsung R Institute Poland

[PATCH 2/2] crypto: stm32 - Support for STM32 HASH module

[Lionel Debieve]

This module register a HASH module that support multiples
algorithms: MD5, SHA1, SHA224, SHA256.

It includes the support of HMAC hardware processing corresponding
to the supported algorithms. DMA or IRQ mode are used depending
on data length.

Signed-off-by: Lionel Debieve 
---
 drivers/crypto/stm32/Kconfig  |   13 +
 drivers/crypto/stm32/Makefile |1 +
 drivers/crypto/stm32/stm32-hash.c | 1576 +
 3 files changed, 1590 insertions(+)
 create mode 100644 drivers/crypto/stm32/stm32-hash.c

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 7dd14f8..602332e 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -5,3 +5,16 @@ config CRC_DEV_STM32
help
   This enables support for the CRC32 hw accelerator which can be found
  on STMicroelectronics STM32 SOC.
+
+config HASH_DEV_STM32
+   tristate "Support for STM32 hash accelerators"
+   depends on ARCH_STM32
+   depends on HAS_DMA
+   select CRYPTO_HASH
+   select CRYPTO_MD5
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_ENGINE
+   help
+  This enables support for the HASH hw accelerator which can be found
+ on STMicroelectronics STM32 SOC.
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 4db2f28..73cd56c 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
+obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
\ No newline at end of file
diff --git a/drivers/crypto/stm32/stm32-hash.c 
b/drivers/crypto/stm32/stm32-hash.c
new file mode 100644
index 000..7bba90c
--- /dev/null
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -0,0 +1,1576 @@
+/*
+ * This file is part of STM32 Crypto driver for Linux.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Lionel DEBIEVE  for STMicroelectronics.
+ *
+ * License terms: GPL V2.0.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HASH_CR0x00
+#define HASH_DIN   0x04
+#define HASH_STR   0x08
+#define HASH_IMR   0x20
+#define HASH_SR0x24
+#define HASH_CSR(x)(0x0F8 + ((x) * 0x04))
+#define HASH_HREG(x)   (0x310 + ((x) * 0x04))
+#define HASH_HWCFGR0x3F0
+#define HASH_VER   0x3F4
+#define HASH_ID0x3F8
+
+/* Control Register */
+#define HASH_CR_INIT   BIT(2)
+#define HASH_CR_DMAE   BIT(3)
+#define HASH_CR_DATATYPE_POS   4
+#define HASH_CR_MODE   BIT(6)
+#define HASH_CR_MDMAT  BIT(13)
+#define HASH_CR_DMAA   BIT(14)
+#define HASH_CR_LKEY   BIT(16)
+
+#define HASH_CR_ALGO_SHA1  0x0
+#define HASH_CR_ALGO_MD5   0x80
+#define HASH_CR_ALGO_SHA2240x4
+#define HASH_CR_ALGO_SHA2560x40080
+
+/* Interrupt */
+#define HASH_DINIE BIT(0)
+#define HASH_DCIE  BIT(1)
+
+/* Interrupt Mask */
+#define HASH_MASK_CALC_COMPLETION  BIT(0)
+#define HASH_MASK_DATA_INPUT   BIT(1)
+
+/* Context swap register */
+#define HASH_CSR_REGISTER_NUMBER   53
+
+/* Status Flags */
+#define HASH_SR_DATA_INPUT_READY   BIT(0)
+#define HASH_SR_OUTPUT_READY   BIT(1)
+#define HASH_SR_DMA_ACTIVE BIT(2)
+#define HASH_SR_BUSY   BIT(3)
+
+/* STR Register */
+#define HASH_STR_NBLW_MASK GENMASK(4, 0)
+#define HASH_STR_DCAL  BIT(8)
+
+#define HASH_FLAGS_INITBIT(0)
+#define HASH_FLAGS_OUTPUT_READYBIT(1)
+#define HASH_FLAGS_CPU BIT(2)
+#define HASH_FLAGS_DMA_READY   BIT(3)
+#define HASH_FLAGS_DMA_ACTIVE  BIT(4)
+#define HASH_FLAGS_HMAC_INIT   BIT(5)
+#define HASH_FLAGS_HMAC_FINAL  BIT(6)
+#define HASH_FLAGS_HMAC_KEYBIT(7)
+
+#define HASH_FLAGS_FINAL