Re: [PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller

[Karthik Ramasubramanian]

On 1/11/2018 8:12 AM, Rob Herring wrote:

On Tue, Jan 9, 2018 at 12:36 PM, Karthik Ramasubramanian
 wrote:



On 1/2/2018 8:55 AM, Rob Herring wrote:


On Wed, Dec 27, 2017 at 09:27:25AM -0700, Karthikeyan Ramasubramanian
wrote:


Add device tree binding support for GENI based UART Controller in the
QUP Wrapper.

Signed-off-by: Karthikeyan Ramasubramanian 
Signed-off-by: Girish Mahadevan 
---
   .../devicetree/bindings/serial/qcom,geni-uart.txt  | 31
++
   1 file changed, 31 insertions(+)
   create mode 100644
Documentation/devicetree/bindings/serial/qcom,geni-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 000..e60ec6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
@@ -0,0 +1,31 @@
+Qualcomm Technologies Inc. GENI based Serial UART Controller driver
+
+This serial UART driver supports console use-cases. This driver is meant
+only for Generic Interface (GENI) based Qualcomm Universal Peripheral
(QUP)
+cores and isn't backwards compatible.
+
+Required properties:
+- compatible: should contain "qcom,geni-uart, qcom,geni-console"



Is console different programming model or just how you are using the
h/w? for the latter, drop it as we have stdout-path to select a console.


The console programming model is different from a regular UART port and
hence the compatible field contains console in it.


And "console" is what the h/w reference manual calls it? If so, then
it is fine. If not, sounds like a Linuxism.
The hardware reference manual calls it Debug UART. I can change the 

compatible string to contain "qcom,geni-debug-uart".

Rob

Regards,
Karthik.

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Re: [PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller

[Rob Herring]

On Tue, Jan 9, 2018 at 12:36 PM, Karthik Ramasubramanian
 wrote:
>
>
> On 1/2/2018 8:55 AM, Rob Herring wrote:
>>
>> On Wed, Dec 27, 2017 at 09:27:25AM -0700, Karthikeyan Ramasubramanian
>> wrote:
>>>
>>> Add device tree binding support for GENI based UART Controller in the
>>> QUP Wrapper.
>>>
>>> Signed-off-by: Karthikeyan Ramasubramanian 
>>> Signed-off-by: Girish Mahadevan 
>>> ---
>>>   .../devicetree/bindings/serial/qcom,geni-uart.txt  | 31
>>> ++
>>>   1 file changed, 31 insertions(+)
>>>   create mode 100644
>>> Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
>>> b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
>>> new file mode 100644
>>> index 000..e60ec6a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
>>> @@ -0,0 +1,31 @@
>>> +Qualcomm Technologies Inc. GENI based Serial UART Controller driver
>>> +
>>> +This serial UART driver supports console use-cases. This driver is meant
>>> +only for Generic Interface (GENI) based Qualcomm Universal Peripheral
>>> (QUP)
>>> +cores and isn't backwards compatible.
>>> +
>>> +Required properties:
>>> +- compatible: should contain "qcom,geni-uart, qcom,geni-console"
>>
>>
>> Is console different programming model or just how you are using the
>> h/w? for the latter, drop it as we have stdout-path to select a console.
>
> The console programming model is different from a regular UART port and
> hence the compatible field contains console in it.

And "console" is what the h/w reference manual calls it? If so, then
it is fine. If not, sounds like a Linuxism.

Rob
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Re: [PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller

[Karthik Ramasubramanian]

On 1/2/2018 8:55 AM, Rob Herring wrote:

On Wed, Dec 27, 2017 at 09:27:25AM -0700, Karthikeyan Ramasubramanian wrote:

Add device tree binding support for GENI based UART Controller in the
QUP Wrapper.

Signed-off-by: Karthikeyan Ramasubramanian 
Signed-off-by: Girish Mahadevan 
---
  .../devicetree/bindings/serial/qcom,geni-uart.txt  | 31 ++
  1 file changed, 31 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt 
b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 000..e60ec6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
@@ -0,0 +1,31 @@
+Qualcomm Technologies Inc. GENI based Serial UART Controller driver
+
+This serial UART driver supports console use-cases. This driver is meant
+only for Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP)
+cores and isn't backwards compatible.
+
+Required properties:
+- compatible: should contain "qcom,geni-uart, qcom,geni-console"


Is console different programming model or just how you are using the
h/w? for the latter, drop it as we have stdout-path to select a console.
The console programming model is different from a regular UART port and 
hence the compatible field contains console in it.



+- reg: Should contain UART register location and length.
+- interrupts: Should contain UART core interrupts.
+- clocks: clocks needed for UART, includes the core and AHB clock.
+- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+  Should be "active" and "sleep" for the pin confuguration when core is active
+  or when entering sleep state.
+- qcom,wrapper-core: Wrapper QUP core containing this UART controller.
+
+Example:
+qup_uart11: qcom,qup_uart@0xa88000 {


Use generic node names and no '0x':

serial@a88000

I will update as per the recommendation.



+   compatible = "qcom,geni-uart";
+   reg = <0xa88000 0x7000>;
+   reg-names = "se_phys";
+   clock-names = "se-clk", "m-ahb", "s-ahb";


Not documented.

I will add the documentation for the missing element.



+   clocks = <_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+   <_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+   <_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_1_uart_3_active>;
+   pinctrl-1 = <_1_uart_3_sleep>;
+   interrupts = <0 355 0>;
+   qcom,wrapper-core = <_0>;
+};
--
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


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Regards,
Karthik.
--
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
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Re: [PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller

[Rob Herring]

On Wed, Dec 27, 2017 at 09:27:25AM -0700, Karthikeyan Ramasubramanian wrote:
> Add device tree binding support for GENI based UART Controller in the
> QUP Wrapper.
> 
> Signed-off-by: Karthikeyan Ramasubramanian 
> Signed-off-by: Girish Mahadevan 
> ---
>  .../devicetree/bindings/serial/qcom,geni-uart.txt  | 31 
> ++
>  1 file changed, 31 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
> 
> diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt 
> b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
> new file mode 100644
> index 000..e60ec6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
> @@ -0,0 +1,31 @@
> +Qualcomm Technologies Inc. GENI based Serial UART Controller driver
> +
> +This serial UART driver supports console use-cases. This driver is meant
> +only for Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP)
> +cores and isn't backwards compatible.
> +
> +Required properties:
> +- compatible: should contain "qcom,geni-uart, qcom,geni-console"

Is console different programming model or just how you are using the 
h/w? for the latter, drop it as we have stdout-path to select a console.

> +- reg: Should contain UART register location and length.
> +- interrupts: Should contain UART core interrupts.
> +- clocks: clocks needed for UART, includes the core and AHB clock.
> +- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
> +  Should be "active" and "sleep" for the pin confuguration when core is 
> active
> +  or when entering sleep state.
> +- qcom,wrapper-core: Wrapper QUP core containing this UART controller.
> +
> +Example:
> +qup_uart11: qcom,qup_uart@0xa88000 {

Use generic node names and no '0x':

serial@a88000

> + compatible = "qcom,geni-uart";
> + reg = <0xa88000 0x7000>;
> + reg-names = "se_phys";
> + clock-names = "se-clk", "m-ahb", "s-ahb";

Not documented.

> + clocks = <_gcc GCC_QUPV3_WRAP0_S0_CLK>,
> + <_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <_1_uart_3_active>;
> + pinctrl-1 = <_1_uart_3_sleep>;
> + interrupts = <0 355 0>;
> + qcom,wrapper-core = <_0>;
> +};
> -- 
> Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
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[PATCH RFC 6/7] serial: Add device tree bindings for GENI based UART Controller

[Karthikeyan Ramasubramanian]

Add device tree binding support for GENI based UART Controller in the
QUP Wrapper.

Signed-off-by: Karthikeyan Ramasubramanian 
Signed-off-by: Girish Mahadevan 
---
 .../devicetree/bindings/serial/qcom,geni-uart.txt  | 31 ++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/qcom,geni-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt 
b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
new file mode 100644
index 000..e60ec6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,geni-uart.txt
@@ -0,0 +1,31 @@
+Qualcomm Technologies Inc. GENI based Serial UART Controller driver
+
+This serial UART driver supports console use-cases. This driver is meant
+only for Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP)
+cores and isn't backwards compatible.
+
+Required properties:
+- compatible: should contain "qcom,geni-uart, qcom,geni-console"
+- reg: Should contain UART register location and length.
+- interrupts: Should contain UART core interrupts.
+- clocks: clocks needed for UART, includes the core and AHB clock.
+- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
+  Should be "active" and "sleep" for the pin confuguration when core is active
+  or when entering sleep state.
+- qcom,wrapper-core: Wrapper QUP core containing this UART controller.
+
+Example:
+qup_uart11: qcom,qup_uart@0xa88000 {
+   compatible = "qcom,geni-uart";
+   reg = <0xa88000 0x7000>;
+   reg-names = "se_phys";
+   clock-names = "se-clk", "m-ahb", "s-ahb";
+   clocks = <_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+   <_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+   <_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_1_uart_3_active>;
+   pinctrl-1 = <_1_uart_3_sleep>;
+   interrupts = <0 355 0>;
+   qcom,wrapper-core = <_0>;
+};
-- 
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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