Re: [PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Chen-Yu Tsai]

Hi,

On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng  wrote:
> From: Chen-Yu Tsai 
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
>
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Pinmux changes.
>
>  arch/arm/boot/dts/sun8i-r40.dtsi | 408 
> +++
>  1 file changed, 408 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index ..1d36485c6ef7
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,408 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai 
> + * Copyright 2017 Icenowy Zheng 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   interrupt-parent = <>;
> +
> +   aliases {
> +   };
> +
> +   chosen {
> +   };
> +
> +   clocks {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   ranges;
> +
> +   osc24M: osc24M {
> +   #clock-cells = <0>;
> +   compatible = "fixed-clock";
> +   clock-frequency = <2400>;

Please add the accuracy of the oscillator. Allwinner requires it
to be within +/- 50 ppm for this one.

> +   };
> +
> +   osc32k: osc32k {
> +   #clock-cells = <0>;
> +   compatible = "fixed-clock";
> +   clock-frequency = <32768>;

And +/- 20 ppm for this one.

> +   clock-output-names = "osc32k";
> +   };
> +   };
> +
> +   cpus {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   cpu@0 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <0>;
> +   };
> +
> +   cpu@1 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <1>;
> +   };
> +
> +   cpu@2 {
> +   compatible = "arm,cortex-a7";
> +   device_type = "cpu";
> +   reg = <2>;
> +   };
> +
> +   cpu@3 {
> +   compatible = "arm,cortex-a7";

[PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Icenowy Zheng]

From: Chen-Yu Tsai 

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Icenowy Zheng 
---
Changes in v3:
- Pinmux changes.

 arch/arm/boot/dts/sun8i-r40.dtsi | 408 +++
 1 file changed, 408 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..1d36485c6ef7
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai 
+ * Copyright 2017 Icenowy Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   aliases {
+   };
+
+   chosen {
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x4000 0x8000>;
+   };
+
+   soc@1c0 {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   nmi_intc: interrupt-controller@1c00030 {
+