Re: [PATCH v4 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
Hi Mark,
On 2017/8/15 18:16, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote:
>> +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
>> +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
>> +{
>> +u64 mpidr;
>> +
>> +mpidr = read_cpuid_mpidr();
>> +if (mpidr & MPIDR_MT_BITMASK) {
>> +if (sccl_id)
>> +*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
>> +if (ccl_id)
>> +*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>> +} else {
>> +if (sccl_id)
>> +*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>> +if (ccl_id)
>> +*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
>> +}
>> +}
>
> How exactly are SCCLs organised w.r.t. MPIDRS?
>
For single-thread core, sccl_id is in MPIDR[aff2] and ccl_id is MPIDR[aff1];
For MT core, sccl_id is in MPIDR[aff3] and ccl_id in MPIDR[aff2].
I shall add comments here.
> Is this guaranteed to be correct for future SoCs?
>
Sorry that it is uncertain.
> It would be nicer if this were described explicitly by FW rather than
> guessed at based on the MPIDR.
>
Whilst I agree, we assume this isn't going to happen now and the logic
can be updated to support this if it we have more complex topology in
the future.
>> +static bool hisi_validate_event_group(struct perf_event *event)
>> +{
>> +struct perf_event *sibling, *leader = event->group_leader;
>> +struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
>> +/* Include count for the event */
>> +int counters = 1;
>> +
>> +/*
>> + * We must NOT create groups containing mixed PMUs, although
>> + * software events are acceptable
>> + */
>> +if (leader->pmu != event->pmu && !is_software_event(leader))
>> +return false;
>> +
>> +/* Increment counter for the leader */
>> +counters++;
>
> If this event is the leader, you account for it twice.
>
> I guess you get away with that assuming you have at least two counters,
> but it's less than ideal.
>
We update this as per
https://marc.info/?l=linux-arm-kernel&m=149096885106554&w=2
Any thoughts to avoid this issue?
>> +
>> +list_for_each_entry(sibling, &event->group_leader->sibling_list,
>> +group_entry) {
>> +if (is_software_event(sibling))
>> +continue;
>> +if (sibling->pmu != event->pmu)
>> +return false;
>> +/* Increment counter for each sibling */
>> +counters++;
>> +}
>> +
>> +/* The group can not count events more than the counters in the HW */
>> +return counters <= hisi_pmu->num_counters;
>> +}
>
> [...]
>
>> +/*
>> + * Set the counter to count the event that we're interested in,
>> + * and enable counter and interrupt.
>> + */
>> +static void hisi_uncore_pmu_enable_event(struct perf_event *event)
>> +{
>> +struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
>> +struct hw_perf_event *hwc = &event->hw;
>> +
>> +/*
>> + * Write event code in event select registers(for DDRC PMU,
>> + * event has been mapped to fixed-purpose counter, there is
>> + * no need to write event type).
>> + */
>> +if (hisi_pmu->ops->write_evtype)
>> +hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
>> +HISI_GET_EVENTID(event));
>
> It looks like this is the only op which might be NULL. It would be
> cleaner for the DDRC PMU code to provide an empty callback.
>
Ok.
> [...]
>
>> +struct hisi_pmu *hisi_pmu_alloc(struct device *dev, u32 num_cntrs)
>> +{
>> +struct hisi_pmu *hisi_pmu;
>> +struct hisi_pmu_hwevents *pmu_events;
>> +
>> +hisi_pmu = devm_kzalloc(dev, sizeof(*hisi_pmu), GFP_KERNEL);
>> +if (!hisi_pmu)
>> +return ERR_PTR(-ENOMEM);
>> +
>> +pmu_events = &hisi_pmu->pmu_events;
>> +pmu_events->hw_events = devm_kcalloc(dev,
>> + num_cntrs,
>> + sizeof(*pmu_events->hw_events),
>> + GFP_KERNEL);
>> +if (!pmu_events->hw_events)
>> +return ERR_PTR(-ENOMEM);
>> +
>> +pmu_events->used_mask = devm_kcalloc(dev,
>> + BITS_TO_LONGS(num_cntrs),
>> + sizeof(*pmu_events->used_mask),
>> + GFP_KERNEL);
>
> How big can num_counters be?
>
At the moment, the max num_counters is 0x10 for HHA PMU.
> Assuming it's not too big, it would be nicer to embed these within the
> hisi_pmu_hwevents.
>
Ok, shall refactor hisi_pmu_hwevents, will use the max num_counters and
remove num_cntrs for hisi_pmu_alloc function.
> [...]
>
>> +
>> +/* Generic pmu struct for different pmu types */
>> +struct hisi_pmu {
>> +const char *name;
>> +struct pmu pmu;
>
> struct pmu has a name
Re: [PATCH v4 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
Hi,
On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote:
> +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
> +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
> +{
> + u64 mpidr;
> +
> + mpidr = read_cpuid_mpidr();
> + if (mpidr & MPIDR_MT_BITMASK) {
> + if (sccl_id)
> + *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
> + if (ccl_id)
> + *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
> + } else {
> + if (sccl_id)
> + *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
> + if (ccl_id)
> + *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> + }
> +}
How exactly are SCCLs organised w.r.t. MPIDRS?
Is this guaranteed to be correct for future SoCs?
It would be nicer if this were described explicitly by FW rather than
guessed at based on the MPIDR.
> +static bool hisi_validate_event_group(struct perf_event *event)
> +{
> + struct perf_event *sibling, *leader = event->group_leader;
> + struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
> + /* Include count for the event */
> + int counters = 1;
> +
> + /*
> + * We must NOT create groups containing mixed PMUs, although
> + * software events are acceptable
> + */
> + if (leader->pmu != event->pmu && !is_software_event(leader))
> + return false;
> +
> + /* Increment counter for the leader */
> + counters++;
If this event is the leader, you account for it twice.
I guess you get away with that assuming you have at least two counters,
but it's less than ideal.
> +
> + list_for_each_entry(sibling, &event->group_leader->sibling_list,
> + group_entry) {
> + if (is_software_event(sibling))
> + continue;
> + if (sibling->pmu != event->pmu)
> + return false;
> + /* Increment counter for each sibling */
> + counters++;
> + }
> +
> + /* The group can not count events more than the counters in the HW */
> + return counters <= hisi_pmu->num_counters;
> +}
[...]
> +/*
> + * Set the counter to count the event that we're interested in,
> + * and enable counter and interrupt.
> + */
> +static void hisi_uncore_pmu_enable_event(struct perf_event *event)
> +{
> + struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> +
> + /*
> + * Write event code in event select registers(for DDRC PMU,
> + * event has been mapped to fixed-purpose counter, there is
> + * no need to write event type).
> + */
> + if (hisi_pmu->ops->write_evtype)
> + hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
> + HISI_GET_EVENTID(event));
It looks like this is the only op which might be NULL. It would be
cleaner for the DDRC PMU code to provide an empty callback.
[...]
> +struct hisi_pmu *hisi_pmu_alloc(struct device *dev, u32 num_cntrs)
> +{
> + struct hisi_pmu *hisi_pmu;
> + struct hisi_pmu_hwevents *pmu_events;
> +
> + hisi_pmu = devm_kzalloc(dev, sizeof(*hisi_pmu), GFP_KERNEL);
> + if (!hisi_pmu)
> + return ERR_PTR(-ENOMEM);
> +
> + pmu_events = &hisi_pmu->pmu_events;
> + pmu_events->hw_events = devm_kcalloc(dev,
> + num_cntrs,
> + sizeof(*pmu_events->hw_events),
> + GFP_KERNEL);
> + if (!pmu_events->hw_events)
> + return ERR_PTR(-ENOMEM);
> +
> + pmu_events->used_mask = devm_kcalloc(dev,
> + BITS_TO_LONGS(num_cntrs),
> + sizeof(*pmu_events->used_mask),
> + GFP_KERNEL);
How big can num_counters be?
Assuming it's not too big, it would be nicer to embed these within the
hisi_pmu_hwevents.
[...]
> +
> +/* Generic pmu struct for different pmu types */
> +struct hisi_pmu {
> + const char *name;
> + struct pmu pmu;
struct pmu has a name field. Why do we need another?
> + union {
> + u32 ddrc_chn_id;
> + u32 l3c_tag_id;
> + u32 hha_uid;
> + };
This would be simpler as a `u32 id` rather than a union.
> + int num_counters;
> + int num_events;
Subsequent patches intialise num_events, but it is never used. Was it
supposed to be checked at event_init time? Or is it unnnecessary?
Thanks,
Mark.
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[PATCH v4 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Reviewed-by: Jonathan Cameron
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile| 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_pmu.c | 398 +++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 103
5 files changed, 510 insertions(+)
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index e5197ff..78fc4bc 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -17,6 +17,13 @@ config ARM_PMU_ACPI
depends on ARM_PMU && ACPI
def_bool y
+config HISI_PMU
+ bool "HiSilicon SoC PMU"
+ depends on ARM64 && ACPI
+ help
+ Support for HiSilicon SoC uncore performance monitoring
+ unit (PMU), such as: L3C, HHA and DDRC.
+
config QCOM_L2_PMU
bool "Qualcomm Technologies L2-cache PMU"
depends on ARCH_QCOM && ARM64 && ACPI
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index 6420bd4..41d3342 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
+obj-$(CONFIG_HISI_PMU) += hisilicon/
obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
new file mode 100644
index 000..2783bb3
--- /dev/null
+++ b/drivers/perf/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c
b/drivers/perf/hisilicon/hisi_uncore_pmu.c
new file mode 100644
index 000..d868447
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -0,0 +1,398 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2017 Hisilicon Limited
+ * Author: Anurup M
+ * Shaokun Zhang
+ *
+ * This code is based on the uncore PMUs like arm-cci and arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include "hisi_uncore_pmu.h"
+
+#define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
+#define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
+
+/*
+ * PMU format attributes
+ */
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(buf, "%s\n", (char *)eattr->var);
+}
+
+/*
+ * PMU event attributes
+ */
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
+}
+
+/*
+ * sysfs cpumask attributes
+ */
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
+
+ return cpumap_print_to_pagebuf(true, buf, &hisi_pmu->cpus);
+}
+
+/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
+void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
+{
+ u64 mpidr;
+
+ mpidr = read_cpuid_mpidr();
+ if (mpidr & MPIDR_MT_BITMASK) {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ } else {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ }
+}
+
+static bool hisi_validate_event_group(struct perf_event *event)
+{
+ struct perf_event *sibling, *leader = event->group_leader;
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
+ /* Include count for the event */
+ int counters = 1;
+
+ /*
+* We must NOT create groups containing mixed PMUs, although
+* software events are acceptable
+*/
+ if (leader->pmu != event->pmu && !is_software_event(leader))
+ return false;
+
+ /* Increment counter for the leader */
+ counters++;
+
+ list_for_each_entry(sibling, &e
