Re: [PATCH 0/3 v2] i2c: i801: enable irq

2012-05-09 Thread Daniel Kurtz
Jean? Anyone? ping?

On Mon, Feb 20, 2012 at 7:23 PM, Daniel Kurtz djku...@chromium.org wrote:
 On Fri, Jan 6, 2012 at 7:35 PM, Jean Delvare kh...@linux-fr.org wrote:
 Hi Daniel,

 On Fri,  6 Jan 2012 18:58:19 +0800, Daniel Kurtz wrote:
 This is a second version of a set of patches enables the Intel PCH SMBus
 controller interrupt.  It refactors the second two patches a little bit by
 relying on DEV_ERR interrupt for timeouts, instead of using an explicit
 wait_event_timeout.

 The first attempt received absolutely no response. Maybe this time someone
 will be interested.

 I was on vacation. But I am very interested and will review and test
 your patches. There have been several attempts to add IRQ support to
 i2c-i801 in the past but each time there was a blocker issue which
 prevented it from making it into mainline. Hopefully this time we'll
 get it there!


 The SMBus Host Controller Interrupt can signify:
  INTR - the end of a complete transaction
  DEV_ERR - that a device did not ACK a transaction
  BYTE_DONE - the completion of a single byte during a byte-by-byte 
 transaction

 This patchset arrives with the following caveats:

  1)  It has only been tested with a Cougar Point (Intel 6 Series PCH) SMBus
 controller, so the irq is only enabled for that chip type.

 I can test on ICH10 easily, and also on ICH7 and ICH3-M if needed.

  2) It has not been tested with any devices that do transactions that use 
 the
     PEC.  In fact, I believe that an additional small patch would be 
 required
     to the driver working correctly in interrupt mode with PEC.

  3) It has not been tested in SMBus Slave mode.

  4) It has not been tested with SMI#-type interrupts.

  5) The BIOS has to configure the PCH SMBus IRQ properly.

  6) It has not been tested with a device that does byte-by-byte smbus 
 (non-i2c)
     reads.

 I think I can test this.

  7) It has not been tested with smbus 'process call' transactions.

 But not this.

 If would be very helpful if somebody could help test on other chipsets, with
 a PEC device, or on additional BIOS that woudl be very helpful.

 I will do what I can with the hardware I have here.

 Jean,
 Ping?



 In the meantime, the interrupt behavior is only enabled on the Cougar Point,
 and even here, it can be completely disabled with the Interrupt feature 
 like
 other advanced features of the driver.

 Daniel Kurtz (3):
   i2c: i801: refactor i801_block_transaction_byte_by_byte
   i2c: i801: enable irq for i801 smbus transactions
   i2c: i801: enable irq for byte_by_byte transactions

  drivers/i2c/busses/i2c-i801.c |  199 
 -
  1 files changed, 175 insertions(+), 24 deletions(-)

 --
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Re: [PATCH 02/15] ARM: ux500: Remove unused i2c platform_data initialisation code

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 Now that u5500 is obsolete, u8500 is the only user of the Nomadik
 i2c driver.

Well actually arch/arm/mach-nomadik has this block too,
but it's not making use of it right now, so why not.

 As such there is no requirement to differentiate between
 initialisation values. By the time a new SoC is released, almost all
 of the ux500 platform will be DT:ed, so we can make decisions based
 on the compatible property instead.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

So why not copy the contents of arch/arm/plat-nomadik/include/plat/i2c.h
into drivers/i2c/busses/i2c-nomadik.c and delete that header from
plat at the same time?

Then there sure is no way for platforms to sneak in any platform
data any other way.

Yours,
Linus Walleij
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Re: [PATCH 03/15] ARM: ux500: Provide auxdata to be used as name base clock search for nmk-i2c

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 This patch provides a way for find_clk() to complete its name-based
 searches and still find the nmk-i2c clocks. As Device Tree has a
 different naming structure to that of more traditional initialisation
 methods, find_clk() not succeed without these bindings.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Thanks,
Linus Walleij
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Re: [PATCH 04/15] ARM: ux500: CONFIG: Compile in support for leds-gpio

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 Code exists in the mop500 board file (used for HREF and
 Snowball) to initialise Snowball's user LED via the
 leds-gpio driver. However, the driver isn't currently
 built when using the default configuration file. This
 patch aims to change that behavior.

 Signed-off-by: Lee Jones lee.jo...@linaro.org
(...)
 +CONFIG_LEDS_GPIO=y
  CONFIG_RTC_CLASS=y
  CONFIG_RTC_DRV_AB8500=y
  CONFIG_RTC_DRV_PL031=y

Why not just edit arch/arm/mach-ux500/Kconfig like this:

config MACH_SNOWBALL
bool U8500 Snowball platform
select MACH_MOP500
+select LEDS_GPIO

Yours,
Linus Walleij
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Re: [PATCH 07/15] drivers/power: Carry out platform_data error checking on ab8500 devices

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 In their current state the ab8500 power devices explode if platform data
 isn't provided. This patch prevents this from happening and informs the
 user of what has happened.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

This or equivalent is already submitted and merged by Anton into the
power tree I think?

Yours,
Linus Walleij
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Re: [PATCH 08/15] ARM: ux500: PRCMU related configuration and layout corrections for Device Tree

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 Apply db8500 related PRCMU Device Tree settings and clean up some formatting
 errors. We also remove one of the PRCMU assigned IRQs, as it is currently not
 used.

 Signed-off-by: Lee Jones lee.jo...@linaro.org
(...)
 -                       interrupts = 46 47;
 +                       interrupts = 0 47 0x4;

Sorry I don't get it, why is two values in decimal and one in hex?

Please choose one and stick to it...

Yours,
Linus Walleij
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Re: [PATCH 09/15] drivers/mfd: Enable Device Tree support for the db8500-prcmu

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 This patch will enable probing to occur during a Device Tree enabled
 boot. The IRQ base is expected to be located in and will be fetched
 from the DT itself. We also prevent any of the db8500 regulators
 from being registered here, as they will be enabled via DT instead.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
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Re: [PATCH 10/15] drivers/mfd: db8500-prcmu: Add support for regulator supply for nmk-i2c.4

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 This applies a supply alias for the db8500's fifth Nomadik i2c port.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
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Re: [PATCH 11/15] drivers/mfd: Enable Device Tree for ab8500-core driver

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 This patch will allow the ab8500-core driver to be probed and set up
 when booting when Device Tree is enabled. This includes platform ID
 look-up which identifies the machine it is currently running on. If
 we are undergoing a DT enabled boot, we will refuse to setup each of
 the other ab8500-* devices, as they will be probed individually by DT.

 Signed-off-by: Lee Jones lee.jo...@linaro.org
(...)
 +       else if (np)
 +               ret = of_property_read_u32(np, stericsson,irq-base, 
 ab8500-irq_base);
 +
 +       if (ab8500-irq_base == 0) {

Shouldn't this be (av8500-irq_base == NO_IRQ) now that we're tranisitioning to
use 0 as NO_IRQ?

Apart from that it looks good to me:
Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
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Re: [PATCH 13/15] ARM: ux500: Add support for ab8500 regulators into the Device Tree

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 Here we supply the information required to setup regulators
 successfully on Snowball and other db8500 variants which use
 the ab8500 regulators. This information includes values used
 for regulator related register initialisation and platform
 specific regulator setup information.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
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Re: [PATCH 15/15] ARM: ux500: Disable platform setup of the ab8500 when DT is enabled

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 The final piece of the ab8500 puzzle. Here we prevent any of the ab8500-*
 drivers from being registered from platform code when Device Tree is
 enabled, as we expect DT do probe each of these individually. We also
 provide the relevant compatible strings, so that DT knows which nodes
 it needs to pay attention to during population.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
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Re: [PATCH 04/15] ARM: ux500: CONFIG: Compile in support for leds-gpio

2012-05-09 Thread Lee Jones

On 09/05/12 09:49, Linus Walleij wrote:

On Fri, May 4, 2012 at 8:23 PM, Lee Joneslee.jo...@linaro.org  wrote:


Code exists in the mop500 board file (used for HREF and
Snowball) to initialise Snowball's user LED via the
leds-gpio driver. However, the driver isn't currently
built when using the default configuration file. This
patch aims to change that behavior.

Signed-off-by: Lee Joneslee.jo...@linaro.org

(...)

+CONFIG_LEDS_GPIO=y
  CONFIG_RTC_CLASS=y
  CONFIG_RTC_DRV_AB8500=y
  CONFIG_RTC_DRV_PL031=y


Why not just edit arch/arm/mach-ux500/Kconfig like this:

config MACH_SNOWBALL
 bool U8500 Snowball platform
 select MACH_MOP500
+select LEDS_GPIO


I can do that. Is it not useful for any of the other platforms?

--
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Re: [PATCH 07/15] drivers/power: Carry out platform_data error checking on ab8500 devices

2012-05-09 Thread Lee Jones

On 09/05/12 09:51, Linus Walleij wrote:

On Fri, May 4, 2012 at 8:23 PM, Lee Joneslee.jo...@linaro.org  wrote:


In their current state the ab8500 power devices explode if platform data
isn't provided. This patch prevents this from happening and informs the
user of what has happened.

Signed-off-by: Lee Joneslee.jo...@linaro.org


This or equivalent is already submitted and merged by Anton into the
power tree I think?


It is, and I sent him a derivative of this patch which he has also 
applied, hence his can now be ignored.


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Re: [PATCH 08/15] ARM: ux500: PRCMU related configuration and layout corrections for Device Tree

2012-05-09 Thread Lee Jones

On 09/05/12 09:53, Linus Walleij wrote:

On Fri, May 4, 2012 at 8:23 PM, Lee Joneslee.jo...@linaro.org  wrote:


Apply db8500 related PRCMU Device Tree settings and clean up some formatting
errors. We also remove one of the PRCMU assigned IRQs, as it is currently not
used.

Signed-off-by: Lee Joneslee.jo...@linaro.org

(...)

-   interrupts =46 47;
+   interrupts =0 47 0x4;


Sorry I don't get it, why is two values in decimal and one in hex?

Please choose one and stick to it...


Because the one on the end is a mask.

[PPI|SPI] [IRQ Number] [Configuration mask]


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Re: [PATCH 11/15] drivers/mfd: Enable Device Tree for ab8500-core driver

2012-05-09 Thread Mark Brown
On Wed, May 09, 2012 at 11:28:49AM +0100, Lee Jones wrote:

 Shouldn't this be (av8500-irq_base == NO_IRQ) now that we're tranisitioning 
 to
 use 0 as NO_IRQ?

 Sure, why not.

I think the endgame is to phase out NO_IRQ entirely...


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[PATCH V2 01/11] dma: imx-sdma: make channel0 operations atomic

2012-05-09 Thread Richard Zhao
device_prep_dma_cyclic may be call in audio trigger function which is
atomic context, so we make it atomic too.

 - change channel0 lock to spinlock.
 - Use polling to wait for channel0 finish running.

Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 drivers/dma/imx-sdma.c |   57 ++-
 1 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index fddccae..4fd48eb 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -24,7 +24,7 @@
 #include linux/mm.h
 #include linux/interrupt.h
 #include linux/clk.h
-#include linux/wait.h
+#include linux/delay.h
 #include linux/sched.h
 #include linux/semaphore.h
 #include linux/spinlock.h
@@ -324,7 +324,7 @@ struct sdma_engine {
struct dma_device   dma_device;
struct clk  *clk_ipg;
struct clk  *clk_ahb;
-   struct mutexchannel_0_lock;
+   spinlock_t  channel_0_lock;
struct sdma_script_start_addrs  *script_addrs;
 };
 
@@ -402,19 +402,27 @@ static void sdma_enable_channel(struct sdma_engine *sdma, 
int channel)
 }
 
 /*
- * sdma_run_channel - run a channel and wait till it's done
+ * sdma_run_channel0 - run a channel and wait till it's done
  */
-static int sdma_run_channel(struct sdma_channel *sdmac)
+static int sdma_run_channel0(struct sdma_engine *sdma)
 {
-   struct sdma_engine *sdma = sdmac-sdma;
-   int channel = sdmac-channel;
int ret;
+   unsigned long timeout = 500;
 
-   init_completion(sdmac-done);
+   sdma_enable_channel(sdma, 0);
 
-   sdma_enable_channel(sdma, channel);
+   while (!(ret = readl_relaxed(sdma-regs + SDMA_H_INTR)  1)) {
+   if (timeout-- = 0)
+   break;
+   udelay(1);
+   }
 
-   ret = wait_for_completion_timeout(sdmac-done, HZ);
+   if (ret) {
+   /* Clear the interrupt status */
+   writel_relaxed(ret, sdma-regs + SDMA_H_INTR);
+   } else {
+   dev_err(sdma-dev, Timeout waiting for CH0 ready\n);
+   }
 
return ret ? 0 : -ETIMEDOUT;
 }
@@ -426,17 +434,17 @@ static int sdma_load_script(struct sdma_engine *sdma, 
void *buf, int size,
void *buf_virt;
dma_addr_t buf_phys;
int ret;
-
-   mutex_lock(sdma-channel_0_lock);
+   unsigned long flags;
 
buf_virt = dma_alloc_coherent(NULL,
size,
buf_phys, GFP_KERNEL);
if (!buf_virt) {
-   ret = -ENOMEM;
-   goto err_out;
+   return -ENOMEM;
}
 
+   spin_lock_irqsave(sdma-channel_0_lock, flags);
+
bd0-mode.command = C0_SETPM;
bd0-mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
bd0-mode.count = size / 2;
@@ -445,12 +453,11 @@ static int sdma_load_script(struct sdma_engine *sdma, 
void *buf, int size,
 
memcpy(buf_virt, buf, size);
 
-   ret = sdma_run_channel(sdma-channel[0]);
+   ret = sdma_run_channel0(sdma);
 
-   dma_free_coherent(NULL, size, buf_virt, buf_phys);
+   spin_unlock_irqrestore(sdma-channel_0_lock, flags);
 
-err_out:
-   mutex_unlock(sdma-channel_0_lock);
+   dma_free_coherent(NULL, size, buf_virt, buf_phys);
 
return ret;
 }
@@ -539,10 +546,6 @@ static void mxc_sdma_handle_channel(struct sdma_channel 
*sdmac)
 {
complete(sdmac-done);
 
-   /* not interested in channel 0 interrupts */
-   if (sdmac-channel == 0)
-   return;
-
if (sdmac-flags  IMX_DMA_SG_LOOP)
sdma_handle_channel_loop(sdmac);
else
@@ -555,6 +558,8 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
unsigned long stat;
 
stat = readl_relaxed(sdma-regs + SDMA_H_INTR);
+   /* not interested in channel 0 interrupts */
+   stat = ~1;
writel_relaxed(stat, sdma-regs + SDMA_H_INTR);
 
while (stat) {
@@ -660,6 +665,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
struct sdma_context_data *context = sdma-context;
struct sdma_buffer_descriptor *bd0 = sdma-channel[0].bd;
int ret;
+   unsigned long flags;
 
if (sdmac-direction == DMA_DEV_TO_MEM) {
load_address = sdmac-pc_from_device;
@@ -677,7 +683,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
dev_dbg(sdma-dev, event_mask0 = 0x%08x\n, (u32)sdmac-event_mask[0]);
dev_dbg(sdma-dev, event_mask1 = 0x%08x\n, (u32)sdmac-event_mask[1]);
 
-   mutex_lock(sdma-channel_0_lock);
+   spin_lock_irqsave(sdma-channel_0_lock, flags);
 
memset(context, 0, sizeof(*context));
context-channel_state.pc = load_address;
@@ -696,10 +702,9 @@ static int sdma_load_context(struct sdma_channel *sdmac)
bd0-mode.count = sizeof(*context) / 4;
bd0-buffer_addr = sdma-context_phys;
   

[PATCH V2 02/11] ARM: dts: imx6q-sabrelite: add i2c1 pinctrl support

2012-05-09 Thread Richard Zhao
Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |2 ++
 arch/arm/boot/dts/imx6q.dtsi  |7 +++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts 
b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 2f631f2..85b7c6c 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -76,6 +76,8 @@
i2c@021a { /* I2C1 */
status = okay;
clock-frequency = 10;
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_i2c1_1;
 
codec: sgtl5000@0a {
compatible = fsl,sgtl5000;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 949f979..f95aa3c 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -486,6 +486,13 @@
reg = 0x020e 0x4000;
 
/* shared pinctrl settings */
+   i2c1 {
+   pinctrl_i2c1_1: i2c1grp-1 {
+   fsl,pins = 137 0x4001b8b1  
/* MX6Q_PAD_EIM_D21__I2C1_SCL */
+   196 0x4001b8b1;
/* MX6Q_PAD_EIM_D28__I2C1_SDA */
+   };
+   };
+
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = 1273 0x17059
/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-- 
1.7.5.4


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[PATCH V2 06/11] ASoC: fsl_ssi: convert to use devm_clk_get

2012-05-09 Thread Richard Zhao
Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 sound/soc/fsl/fsl_ssi.c |7 ++-
 1 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 4ed2afd..b10a427 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -725,7 +725,7 @@ static int __devinit fsl_ssi_probe(struct platform_device 
*pdev)
u32 dma_events[2];
ssi_private-ssi_on_imx = true;
 
-   ssi_private-clk = clk_get(pdev-dev, NULL);
+   ssi_private-clk = devm_clk_get(pdev-dev, NULL);
if (IS_ERR(ssi_private-clk)) {
ret = PTR_ERR(ssi_private-clk);
dev_err(pdev-dev, could not get clock: %d\n, ret);
@@ -842,10 +842,8 @@ error_dev:
device_remove_file(pdev-dev, dev_attr);
 
 error_clk:
-   if (ssi_private-ssi_on_imx) {
+   if (ssi_private-ssi_on_imx)
clk_disable_unprepare(ssi_private-clk);
-   clk_put(ssi_private-clk);
-   }
 
 error_irq:
free_irq(ssi_private-irq, ssi_private);
@@ -871,7 +869,6 @@ static int fsl_ssi_remove(struct platform_device *pdev)
if (ssi_private-ssi_on_imx) {
platform_device_unregister(ssi_private-imx_pcm_pdev);
clk_disable_unprepare(ssi_private-clk);
-   clk_put(ssi_private-clk);
}
snd_soc_unregister_dai(pdev-dev);
device_remove_file(pdev-dev, ssi_private-dev_attr);
-- 
1.7.5.4


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[PATCH V2 05/11] ARM: imx6q: add ssi1_ipg clk_lookup

2012-05-09 Thread Richard Zhao
It's used by audio drivers.

Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/mach-imx/clk-imx6q.c |   10 ++
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f40a35d..92550c5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -155,7 +155,8 @@ enum mx6q_clks {
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-   pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, clk_max
+   pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+   ssi2_ipg, ssi3_ipg, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -367,9 +368,9 @@ int __init mx6q_clocks_init(void)
clk[sata] = imx_clk_gate2(sata,  ipg,   
base + 0x7c, 4);
clk[sdma] = imx_clk_gate2(sdma,  ahb,   
base + 0x7c, 6);
clk[spba] = imx_clk_gate2(spba,  ipg,   
base + 0x7c, 12);
-   clk[ssi1] = imx_clk_gate2(ssi1,  ssi1_podf, 
base + 0x7c, 18);
-   clk[ssi2] = imx_clk_gate2(ssi2,  ssi2_podf, 
base + 0x7c, 20);
-   clk[ssi3] = imx_clk_gate2(ssi3,  ssi3_podf, 
base + 0x7c, 22);
+   clk[ssi1_ipg] = imx_clk_gate2(ssi1_ipg,  ipg,   
base + 0x7c, 18);
+   clk[ssi2_ipg] = imx_clk_gate2(ssi2_ipg,  ipg,   
base + 0x7c, 20);
+   clk[ssi3_ipg] = imx_clk_gate2(ssi3_ipg,  ipg,   
base + 0x7c, 22);
clk[uart_ipg] = imx_clk_gate2(uart_ipg,  ipg,   
base + 0x7c, 24);
clk[uart_serial]  = imx_clk_gate2(uart_serial,   uart_serial_podf,  
base + 0x7c, 26);
clk[usboh3]   = imx_clk_gate2(usboh3,ipg,   
base + 0x80, 0);
@@ -418,6 +419,7 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[sdma], NULL, 20ec000.sdma);
clk_register_clkdev(clk[dummy], NULL, 20bc000.wdog);
clk_register_clkdev(clk[dummy], NULL, 20c.wdog);
+   clk_register_clkdev(clk[ssi1_ipg], NULL, 2028000.ssi);
 
for (i = 0; i  ARRAY_SIZE(clks_init_on); i++) {
c = clk_get_sys(clks_init_on[i], NULL);
-- 
1.7.5.4


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[PATCH V2 08/11] ARM: dts: imx6q-sabrelite: add sound device imx6q-sabrelite-sgtl5000

2012-05-09 Thread Richard Zhao
Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts 
b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 5b51deb..5a35bfd 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -110,4 +110,18 @@
regulator-always-on;
};
};
+
+   sound {
+   compatible = fsl,imx6q-sabrelite-sgtl5000,
+fsl,imx-audio-sgtl5000;
+   model = imx6q-sabrelite-sgtl5000;
+   ssi-controller = ssi1;
+   audio-codec = codec;
+   audio-routing =
+   MIC_IN, Mic Jack,
+   Mic Jack, Mic Bias,
+   Headphone Jack, HP_OUT;
+   mux-int-port = 1;
+   mux-ext-port = 4;
+   };
 };
-- 
1.7.5.4


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[PATCH V2 10/11] ARM: imx6q: change clkdev device name from xxxx.uart to xxxx.serial

2012-05-09 Thread Richard Zhao
It's because the dts changed the node name.

Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/mach-imx/clk-imx6q.c |   20 ++--
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 096fcfb..4ac1282 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -393,16 +393,16 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[gpt_ipg_per], per, imx-gpt.0);
clk_register_clkdev(clk[twd], NULL, smp_twd);
clk_register_clkdev(clk[usboh3], NULL, usboh3);
-   clk_register_clkdev(clk[uart_serial], per, 202.uart);
-   clk_register_clkdev(clk[uart_ipg], ipg, 202.uart);
-   clk_register_clkdev(clk[uart_serial], per, 21e8000.uart);
-   clk_register_clkdev(clk[uart_ipg], ipg, 21e8000.uart);
-   clk_register_clkdev(clk[uart_serial], per, 21ec000.uart);
-   clk_register_clkdev(clk[uart_ipg], ipg, 21ec000.uart);
-   clk_register_clkdev(clk[uart_serial], per, 21f.uart);
-   clk_register_clkdev(clk[uart_ipg], ipg, 21f.uart);
-   clk_register_clkdev(clk[uart_serial], per, 21f4000.uart);
-   clk_register_clkdev(clk[uart_ipg], ipg, 21f4000.uart);
+   clk_register_clkdev(clk[uart_serial], per, 202.serial);
+   clk_register_clkdev(clk[uart_ipg], ipg, 202.serial);
+   clk_register_clkdev(clk[uart_serial], per, 21e8000.serial);
+   clk_register_clkdev(clk[uart_ipg], ipg, 21e8000.serial);
+   clk_register_clkdev(clk[uart_serial], per, 21ec000.serial);
+   clk_register_clkdev(clk[uart_ipg], ipg, 21ec000.serial);
+   clk_register_clkdev(clk[uart_serial], per, 21f.serial);
+   clk_register_clkdev(clk[uart_ipg], ipg, 21f.serial);
+   clk_register_clkdev(clk[uart_serial], per, 21f4000.serial);
+   clk_register_clkdev(clk[uart_ipg], ipg, 21f4000.serial);
clk_register_clkdev(clk[enet], NULL, 2188000.enet);
clk_register_clkdev(clk[usdhc1], NULL, 219.usdhc);
clk_register_clkdev(clk[usdhc2], NULL, 2194000.usdhc);
-- 
1.7.5.4


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[PATCH V2 09/11] ARM: dts: imx6q-sabrelite: add serial2 pinctrl support

2012-05-09 Thread Richard Zhao
Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |2 ++
 arch/arm/boot/dts/imx6q.dtsi  |7 +++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts 
b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 5a35bfd..e0ec929 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -73,6 +73,8 @@
 
uart2: serial@021e8000 {
status = okay;
+   pinctrl-names = default;
+   pinctrl-0 = pinctrl_serial2_1;
};
 
i2c@021a { /* I2C1 */
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 5795b93..31c3d5f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -502,6 +502,13 @@
};
};
 
+   serial2 {
+   pinctrl_serial2_1: serial2grp-1 {
+   fsl,pins = 183 0x1b0b1 
/* MX6Q_PAD_EIM_D26__UART2_TXD */
+   191 0x1b0b1;   
/* MX6Q_PAD_EIM_D27__UART2_RXD */
+   };
+   };
+
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = 1273 0x17059
/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-- 
1.7.5.4


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[PATCH V2 11/11] ARM: imx6q: change clkdev device name from xxxx.enet to xxxx.ethernet

2012-05-09 Thread Richard Zhao
It's because the dts changed the node name.

Signed-off-by: Richard Zhao richard.z...@freescale.com
---
 arch/arm/mach-imx/clk-imx6q.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4ac1282..cab02d0 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -403,7 +403,7 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[uart_ipg], ipg, 21f.serial);
clk_register_clkdev(clk[uart_serial], per, 21f4000.serial);
clk_register_clkdev(clk[uart_ipg], ipg, 21f4000.serial);
-   clk_register_clkdev(clk[enet], NULL, 2188000.enet);
+   clk_register_clkdev(clk[enet], NULL, 2188000.ethernet);
clk_register_clkdev(clk[usdhc1], NULL, 219.usdhc);
clk_register_clkdev(clk[usdhc2], NULL, 2194000.usdhc);
clk_register_clkdev(clk[usdhc3], NULL, 2198000.usdhc);
-- 
1.7.5.4


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Re: [PATCH V2 06/11] ASoC: fsl_ssi: convert to use devm_clk_get

2012-05-09 Thread Mark Brown
On Wed, May 09, 2012 at 07:33:05PM +0800, Richard Zhao wrote:
 Signed-off-by: Richard Zhao richard.z...@freescale.com

I'll apply this when devm_clk_get() makes it into mainline (hopefully in
the merge window); please remind me if I forget.


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Description: Digital signature


Re: [PATCH 06/15] mfd/ab8500: Remove confusing ab8500-i2c file and merge into ab8500-core

2012-05-09 Thread Linus Walleij
On Fri, May 4, 2012 at 8:23 PM, Lee Jones lee.jo...@linaro.org wrote:

 ab8500-i2c is used as core code to register the ab8500 device.
 After allocating ab8500 memory, it immediately calls into
 ab8500-core where the real initialisation takes place. This
 patch moves all core registration and memory allocation into
 the true ab8500-core file and removes ab8500-i2c completely.

 Signed-off-by: Lee Jones lee.jo...@linaro.org

This code is in a separate file for a reason:

git checkout v2.6.37
$ ls drivers/mfd/
ab8500-core.c
ab8500-debugfs.c
ab8500-i2c.c
ab8500-spi.c

So the driver supports different backendsm and at one point
there was both the SPI and I2C (actually PRCMU) backend.

And the physical component has an SPI port as well.

However nowadays it's not used, since the component is design to
be used by the PRCMU I2C channel and nothing else, the SPI
mode was just for prototyping and testing. On newer boards
and the Snowball the SPI isn't even routed.

(...)
+static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data)
+static int ab8500_i2c_read(struct ab8500 *ab8500, u16 addr)

As you might have noticed, many people have been confused by
the i2c naming of these things. Yes, there is physically an I2C
carrying these out but in Linux terms that's just confusing, it's mixing
hardware and software terminology. Take this opportunity to
rename them:

static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)

etc, so they have a meaningful name.

Yours,
Linus Walleij
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Re: [PATCH 09/15] drivers/mfd: Enable Device Tree support for the db8500-prcmu

2012-05-09 Thread Samuel Ortiz
Hi Lee,

On Fri, May 04, 2012 at 07:23:19PM +0100, Lee Jones wrote:
 This patch will enable probing to occur during a Device Tree enabled
 boot. The IRQ base is expected to be located in and will be fetched
 from the DT itself. We also prevent any of the db8500 regulators
 from being registered here, as they will be enabled via DT instead.
 
 Signed-off-by: Lee Jones lee.jo...@linaro.org
 ---
  drivers/mfd/db8500-prcmu.c |   29 +++--
  1 file changed, 19 insertions(+), 10 deletions(-)
Patch applied, thanks.

Cheers,
Samuel.

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Re: [PATCH V2 06/11] ASoC: fsl_ssi: convert to use devm_clk_get

2012-05-09 Thread Timur Tabi
Richard Zhao wrote:
 Signed-off-by: Richard Zhao richard.z...@freescale.com
 ---

It's a simple change that only affects i.MX, so ...

Acked-by: Timur Tabi ti...@freescale.com

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Re: [PATCH 0/4] MXS: I2C improvements

2012-05-09 Thread Marek Vasut
 This patchset implements support for adjustment of I2C bus speed via
 platform data. Further, it implements support for DMA transfers into the
 mxs-i2c driver. Lastly, there is a fix for GCC4.7 warning included.
 
 Marek Vasut (4):
   MXS: Allow passing i2c bus speed via platform data
   MXS: Set I2C timing registers for mxs-i2c
   MXS: Implement DMA support into mxs-i2c
   MXS: Fix GCC4.7 complaint in mxs-i2c

Bump?

Best regards,
Marek Vasut
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Re: [PATCH V2 03/11] ASoC: imx-audmux: add pinctrl support

2012-05-09 Thread Richard Zhao
On Wed, May 09, 2012 at 05:00:06PM +0100, Mark Brown wrote:
 On Wed, May 09, 2012 at 07:33:02PM +0800, Richard Zhao wrote:
  Signed-off-by: Richard Zhao richard.z...@freescale.com
 
 I guess this depends on some other tree and can't just be directly
 applied to ASoC?
It's based on your for-next. But for working, it depends on
pinctl/for-next.

Thanks
Richard

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Re: [PATCH V2 01/11] dma: imx-sdma: make channel0 operations atomic

2012-05-09 Thread Vinod Koul
On Wed, 2012-05-09 at 19:33 +0800, Richard Zhao wrote:
 device_prep_dma_cyclic may be call in audio trigger function which is
 atomic context, so we make it atomic too.
 
  - change channel0 lock to spinlock.
  - Use polling to wait for channel0 finish running.
 
 Signed-off-by: Richard Zhao richard.z...@freescale.com
Acked By: Vinod Koul vinod.k...@linux.intel.com

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