[PATCH] i2c: rk3x: Add two new features for rk3399
1. support highspeed.
2. check i2c bus idle status.
Change-Id: I9c22e752af621c0f8dbcbd399c86b34fd810ec38
Signed-off-by: David Wu <w...@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 336 --
1 file changed, 320 insertions(+), 16 deletions(-)
mode change 100644 => 100755 drivers/i2c/busses/i2c-rk3x.c
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
old mode 100644
new mode 100755
index c1935eb..b1aa702
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
/* Register Map */
@@ -37,6 +38,7 @@
#define REG_IEN0x18 /* interrupt enable */
#define REG_IPD0x1c /* interrupt pending */
#define REG_FCNT 0x20 /* finished count */
+#define I2C_ST 0x220 /* i2c pin status */
/* Data buffer offsets */
#define TXBUFFER_BASE 0x100
@@ -58,6 +60,12 @@ enum {
#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
#define REG_CON_ACTACKBIT(6) /* 1: stop if NACK is received */
+#define VERSION_MASK 0x
+#define VERSION_SHIFT16
+
+#define RK3X_I2C_V0 0x0
+#define RK3X_I2C_V1 0x1
+
/* REG_MRXADDR bits */
#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid
*/
@@ -71,6 +79,13 @@ enum {
#define REG_INT_NAKRCVBIT(6) /* NACK received */
#define REG_INT_ALL 0x7f
+enum {
+ I2C_IDLE = 0,
+ I2C_SDA_LOW,
+ I2C_SCL_LOW,
+ BOTH_LOW,
+};
+
/* Constants */
#define WAIT_TIMEOUT 1000 /* ms */
#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
@@ -90,10 +105,23 @@ struct rk3x_i2c_soc_data {
int grf_offset;
};
+struct rk3x_i2c_ops {
+ int (*check_idle)(void __iomem *);
+ int (*calc_divs)(unsigned long,
+unsigned long,
+unsigned long,
+unsigned long,
+unsigned long,
+unsigned long *,
+unsigned long *,
+unsigned int *);
+};
+
struct rk3x_i2c {
struct i2c_adapter adap;
struct device *dev;
struct rk3x_i2c_soc_data *soc_data;
+ struct rk3x_i2c_ops ops;
/* Hardware resources */
void __iomem *regs;
@@ -116,6 +144,7 @@ struct rk3x_i2c {
u8 addr;
unsigned int mode;
bool is_last_msg;
+ unsigned int time_con;
/* I2C state machine */
enum rk3x_i2c_state state;
@@ -151,7 +180,8 @@ static void rk3x_i2c_start(struct rk3x_i2c *i2c)
i2c_writel(i2c, REG_INT_START, REG_IEN);
/* enable adapter with correct mode, send START condition */
- val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
+ val = i2c->time_con | REG_CON_EN | REG_CON_MOD(i2c->mode)
+ | REG_CON_START;
/* if we want to react to NACK, set ACTACK bit */
if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
@@ -443,16 +473,19 @@ out:
* @sda_fall_ns: How many ns it takes for SDA to fall.
* @div_low: Divider output for low
* @div_high: Divider output for high
+ * @con: version0 is not used
*
* Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that
case
* a best-effort divider value is returned in divs. If the target rate is
* too high, we silently use the highest possible rate.
*/
-static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
- unsigned long scl_rise_ns,
- unsigned long scl_fall_ns,
- unsigned long sda_fall_ns,
- unsigned long *div_low, unsigned long *div_high)
+static int rk3x_i2c_v0_calc_divs(unsigned long clk_rate, unsigned long
scl_rate,
+unsigned long scl_rise_ns,
+unsigned long scl_fall_ns,
+unsigned long sda_fall_ns,
+unsigned long *div_low,
+unsigned long *div_high,
+unsigned int *con)
{
unsigned long spec_min_low_ns, spec_min_high_ns;
unsigned long spec_setup_start, spec_max_data_hold_ns;
@@ -614,19 +647,244 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate,
unsigned long scl_rate,
return ret;
}
+/**
+ * Calculate divider values for desired SCL frequency
+ *
+ * @clk_rate: I2C input clock rate
+ * @scl_rate: Desired SCL rate
+ * @scl_rise_ns: How many ns it takes for SCL to rise.
+ * @scl_fall_ns: How many ns it takes for SCL to fall.
+ * @sda_fall_ns: How many ns it takes for SDA to fall.
+ * @div_low: Divider output for low
+ * @div_high: Divider output for high
+ * @con: SDA update point config used to adjust setup/hold time,
+ * start setup config for setup_start and hold_start time,
+ * stop_setu
[PATCH v1 2/3] i2c: rk3x: new way to calc_divs for new version
From: David Wu <david...@rock-chips.com>
There was an issue about "repeated start" timing at the I2C controller
of old version:
- controller appears to drop SDA at .875x (7/8) programmed clk high.
- controller appears to keep SCL high for 2x programmed clk high.
The first rule isn't enough to meet tSU;STA requirements in Standard-mode
on the system. To resolve the issue, some configs for I2C timing is added,
and new rules is designed for cal_div.
Every i2c scl cycle includes 8 low FSM and 8 high FSM time.
SCL = Pclk / SCL Divisor;
SCL Divisor = 8 * (divl + 1 + divh + 1);
l: how many Pclk cycles of every low FSM(finite state machine).
h: how many Pclk cycles of every high FSM(finite state machine).
s: how many l is it taken in the tLow time, it is a value between 1~8,
determines the tHD;sda and tSU;sda time.
u: start setup timing config, determines the tSU;sta and tHD;sta time.
p: stop setup timing config, determines the tSU;sto time.
T = 10 / Pclk_i2c;
l = divl + 1;
h = divh + 1;
s = data_upd_st + 1;
u = start_setup_cnt + 1;
p = stop_setup_cnt + 1;
tHigh = 8 * h * T;
tLow = 8 * l * T;
tLow = tHD;sda + tSU;sda;
tHD;sda = (l * s + 1) * T;
tSU;sda = [(8 - l) * s + 1] * T;
tI2C = 8 * (l + h) * T;
tSU;sta = (8h * u + 1) * T;
tHD;sta = [8h * (u + 1) - 1] * T;
tSU;sto = (8h * p + 1) * T;
There are two examples of div calculated by the rules, not include
hardware elements like scl_rise time, scl_fall time and sda_rise time:
1. Standard-mode:
Source Pclk: 80M, Target scl:100K, Final scl = 100K;
Tpclk = 12.5ns;
divl = divh = 0x31;
l = h = 0x32;
tHigh = tLow = 5.0us
start_setup_cnt = stop_setup_cnt = 0;
u = p = 1;
tSU;sta = (8h * u + 1) * T = 5.0125us;
tHD;sta = [8h * (u + 1) - 1] * T = 9.9875us;
tSU;sto = (8h * p + 1) * T = 5.0125us;
data_upd_st = 2;
s = data_upd_st + 1 = 3;
tHD;sda = (l * s + 1) * T = 1.8875us;
tSU;sda = [(8 - l) * s + 1] * T = 3.1125us;
2. Fast-mode:
Source Pclk: 80M, Target scl:400K, Final scl = 400K;
Tpclk = 12.5ns;
divl = 0xf;
divh = 0x8;
l = 0x10;
h = 0x9;
tHigh = 0.9us;
tLow = 1.6us;
start_setup_cnt = stop_setup_cnt = 0;
u = p = 1;
tSU;sta = (8h * u + 1) * T = 0.9125us;
tHD;sta = [8h * (u + 1) - 1] * T = 1.5875us;
tSU;sto = (8h * p + 1) * T = 0.9125us;
data_upd_st = 1;
s = data_upd_st + 1 = 2;
tHD;sda = (l * s + 1) * T = 0.4125us;
tSU;sda = [(8 - l) * s + 1] * T = 1.1875us;
The rules make the timing meet the I2C spec requirements whether
Standard-mode or Fast-mode.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 201 +-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 0ff299f..fae5099 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -637,6 +637,203 @@ static int rk3x_i2c_v0_calc_divs(unsigned long clk_rate,
unsigned long scl_rate,
return ret;
}
+/**
+ * Calculate divider values for desired SCL frequency
+ *
+ * @clk_rate: I2C input clock rate
+ * @scl_rate: Desired SCL rate
+ * @scl_rise_ns: How many ns it takes for SCL to rise.
+ * @scl_fall_ns: How many ns it takes for SCL to fall.
+ * @sda_fall_ns: How many ns it takes for SDA to fall.
+ * @div_low: Divider output for low
+ * @div_high: Divider output for high
+ * @con: SDA update point config used to adjust setup/hold time,
+ * start setup config for setup_start and hold_start time,
+ * stop_setup config for setup_stop time.
+ *
+ * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that
case
+ * a best-effort divider value is returned in divs. If the target rate is
+ * too high, we silently use the highest possible rate.
+
+ * l = divl + 1;
+ * h = divh + 1;
+ * s = data_upd_st + 1;
+ * u = start_setup_cnt + 1;
+ * p = stop_setup_cnt + 1;
+ * T = Tclk_i2c;
+
+ * tHigh = 8 * h * T;
+ * tLow = 8 * l * T;
+
+ * tHD;sda = (l * s + 1) * T;
+ * tSU;sda = ((8 - l) * s + 1) * T;
+ * tI2C = 8 * (l + h) * T;
+
+ * tSU;sta = (8h * u + 1) * T;
+ * tHD;sta = [8h * (u + 1) - 1] * T;
+ * tSU;sto =(8h * p + 1) * T;
+ */
+static int rk3x_i2c_v1_calc_divs(unsigned long clk_rate, unsigned long
scl_rate,
+unsigned long scl_rise_ns,
+unsigned long scl_fall_ns,
+unsigned long sda_fall_ns,
+unsigned long *div_low,
+unsigned long *div_high,
+unsigned int *con)
+{
+ unsigned long spec_min_low_ns, spec_min_high_ns;
+ unsigned long spec_min_setup_start, spec_min_hold_s
[PATCH v1 3/3] i2c: rk3x: support I2C Hs-mode for rk3399
From: David Wu <david...@rock-chips.com>
The i2c controller of new version1 supports highspeed mode,
1.7M and 3.4M rate. It also could be calculated divs by the rules.
The final divs would be effected a lot by hardware elements like
scl_rise_ns, scl_fall_ns and sda_rise_ns,sds_fall_ns.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/i2c/busses/i2c-rk3x.c | 56 ---
1 file changed, 48 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index fae5099..ec0e37f 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -700,8 +700,8 @@ static int rk3x_i2c_v1_calc_divs(unsigned long clk_rate,
unsigned long scl_rate,
int ret = 0;
- if (WARN_ON(scl_rate > 40))
- scl_rate = 40;
+ if (WARN_ON(scl_rate > 340))
+ scl_rate = 340;
if (WARN_ON(scl_rate < 10))
scl_rate = 10;
@@ -719,7 +719,7 @@ static int rk3x_i2c_v1_calc_divs(unsigned long clk_rate,
unsigned long scl_rate,
start_setup_cnt = 0;
stop_setup_cnt = 0;
- } else {
+ } else if (scl_rate <= 40) {
spec_min_setup_start = 600;
spec_min_hold_start = 600;
@@ -732,6 +732,32 @@ static int rk3x_i2c_v1_calc_divs(unsigned long clk_rate,
unsigned long scl_rate,
start_setup_cnt = 0;
stop_setup_cnt = 0;
+ } else if (scl_rate <= 170) {
+ spec_min_low_ns = 320;
+ spec_min_high_ns = 120;
+
+ spec_min_setup_start = 160;
+ spec_min_hold_start = 160;
+
+ spec_max_data_hold_ns = 150;
+ spec_min_data_setup = 10;
+ spec_min_stop_setup = 160;
+
+ start_setup_cnt = 1;
+ stop_setup_cnt = 1;
+ } else {
+ spec_min_low_ns = 160;
+ spec_min_high_ns = 60;
+
+ spec_min_setup_start = 160;
+ spec_min_hold_start = 160;
+
+ spec_min_data_setup = 10;
+ spec_max_data_hold_ns = 70;
+ spec_min_stop_setup = 160;
+
+ start_setup_cnt = 2;
+ stop_setup_cnt = 2;
}
clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
@@ -1126,15 +1152,29 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
>scl_rise_ns)) {
if (i2c->scl_frequency <= 10)
i2c->scl_rise_ns = 1000;
- else
+ else if (i2c->scl_frequency <= 40)
i2c->scl_rise_ns = 300;
+ else if (i2c->scl_frequency <= 170)
+ i2c->scl_rise_ns = 80;
+ else
+ i2c->scl_rise_ns = 40;
}
if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns",
->scl_fall_ns))
- i2c->scl_fall_ns = 300;
+>scl_fall_ns)) {
+ if (i2c->scl_frequency <= 40)
+ i2c->scl_fall_ns = 300;
+ else if (i2c->scl_frequency <= 170)
+ i2c->scl_fall_ns = 80;
+ else
+ i2c->scl_fall_ns = 40;
+ }
if (of_property_read_u32(pdev->dev.of_node, "i2c-sda-falling-time-ns",
->scl_fall_ns))
- i2c->sda_fall_ns = i2c->scl_fall_ns;
+>scl_fall_ns)) {
+ if (i2c->scl_frequency <= 40)
+ i2c->sda_fall_ns = i2c->scl_fall_ns;
+ else
+ i2c->sda_fall_ns = 2 * i2c->scl_fall_ns;
+ }
strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
i2c->adap.owner = THIS_MODULE;
--
1.9.1
--
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