Re: ath10k: fix spelling mistake "montior" -> "monitor"

[Kalle Valo]

Colin Ian King  wrote:
> From: Colin Ian King 
> 
> Trivial fix to spelling mistake in ath10k_warn message.
> 
> Signed-off-by: Colin Ian King 
> Reviewed-by: Julian Calaby 

Thanks, 1 patch applied to ath-next branch of ath.git:

7f03d3069381 ath10k: fix spelling mistake "montior" -> "monitor"

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9301869/

Re: ath10k: fix spelling mistake "montior" -> "monitor"

[Kalle Valo]

Colin Ian King  wrote:
> From: Colin Ian King 
> 
> Trivial fix to spelling mistake in ath10k_warn message.
> 
> Signed-off-by: Colin Ian King 
> Reviewed-by: Julian Calaby 

Thanks, 1 patch applied to ath-next branch of ath.git:

7f03d3069381 ath10k: fix spelling mistake "montior" -> "monitor"

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9301869/

Re: [PATCH v4 3/3] tracing: Histogram for missed timer offsets

[Masami Hiramatsu]

2016-09-02 21:41 GMT+09:00 Binoy Jayan :
> On 30 August 2016 at 16:20, Masami Hiramatsu
>  wrote:
>> Hi Binoy,
>>>
>>> +static inline void trace_latency_hrtimer_mark_ts(struct hrtimer *timer,
>>> +struct hrtimer_clock_base 
>>> *new_base,
>>> +ktime_t tim)
>>> +{
>>> +#if defined(CONFIG_PREEMPT_TRACER) || defined(CONFIG_IRQSOFF_TRACER)
>>> +   if (trace_latency_hrtimer_interrupt_enabled()) {
>>
>> You would better use unlikely() here.
>>
>>> +   ktime_t now = new_base->get_time();
>>> +
>>> +   if (ktime_to_ns(tim) < ktime_to_ns(now))
>>
>> Wouldn't we need to consider the case of wrap around?
>>
>>> +   timer->praecox = now;
>>> +   else
>>> +   timer->praecox = ktime_set(0, 0);
>>> +   }
>>> +#endif
>>> +}
>
> Hi Masami,
>
> I always see these values to be relative and not absolute time. I
> found 'praecox' to be always zero during test.
> What do you think.

Ah, right. Since "tim" is expire time (timer target), that should
always be "now + x"
(x is enough larger than how long setting the hrtimer takes). Or,
hrtimer expires
before finished to set. :)

Thank you,
-- 
Masami Hiramatsu

Re: [PATCH] trivial treewide: Convert dev_set_uevent_suppress argument to bool

[Bart Van Assche]

On 09/02/2016 08:41 AM, Joe Perches wrote:

On Fri, 2016-09-02 at 13:41 +, Bart Van Assche wrote:

On 09/01/16 17:51, Joe Perches wrote:

On Fri, 2016-09-02 at 00:47 +, Bart Van Assche wrote:

On 09/01/16 13:11, Joe Perches wrote:

Assigning an int to a bitfield:1 can lose precision.
Change the caller argument uses from 1/0 to true/false.

Can you clarify how assigning 0 or 1 to a one-bit bitfield can cause a
loss of precision?

There are no existing defects.
Using 1/0 is not a loss of precision, it's just
changing to use bool avoids potential errors and
promotes consistency.
Other uses of this function already use true/false.

In the patch description you refer to loss of precision. However, your
patch does not address any loss of precision issues. So I think that the
patch description is misleading and could be made more clear.


I tend towards terse being better than verbose.
The original patch description says

"no change to objects"

What would you suggest?


Hello Joe,

How about the following:

dev_set_uevent_suppress() expects a boolean as second argument. Make 
this clear by passing true/false instead of 1/0 as the second argument.


Bart.

Re: ath10k: replace config_enabled() with IS_REACHABLE()

[Kalle Valo]

Masahiro Yamada  wrote:
> Commit 97f2645f358b ("tree-wide: replace config_enabled() with
> IS_ENABLED()") mostly did away with config_enabled().
> 
> This is one of the postponed TODO items as config_enabled() is used
> for a tristate option here.  Theoretically, config_enabled() is
> equivalent to IS_BUILTIN(), but I guess IS_REACHABLE() is the best
> fit for this case because both CONFIG_HWMON and CONFIG_ATH10K are
> tristate.
> 
> Signed-off-by: Masahiro Yamada 

Thanks, 1 patch applied to ath-next branch of ath.git:

749bc03ae2cd ath10k: replace config_enabled() with IS_REACHABLE()

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9295945/

Re: [PATCH v4 3/3] tracing: Histogram for missed timer offsets

[Masami Hiramatsu]

2016-09-02 21:41 GMT+09:00 Binoy Jayan :
> On 30 August 2016 at 16:20, Masami Hiramatsu
>  wrote:
>> Hi Binoy,
>>>
>>> +static inline void trace_latency_hrtimer_mark_ts(struct hrtimer *timer,
>>> +struct hrtimer_clock_base 
>>> *new_base,
>>> +ktime_t tim)
>>> +{
>>> +#if defined(CONFIG_PREEMPT_TRACER) || defined(CONFIG_IRQSOFF_TRACER)
>>> +   if (trace_latency_hrtimer_interrupt_enabled()) {
>>
>> You would better use unlikely() here.
>>
>>> +   ktime_t now = new_base->get_time();
>>> +
>>> +   if (ktime_to_ns(tim) < ktime_to_ns(now))
>>
>> Wouldn't we need to consider the case of wrap around?
>>
>>> +   timer->praecox = now;
>>> +   else
>>> +   timer->praecox = ktime_set(0, 0);
>>> +   }
>>> +#endif
>>> +}
>
> Hi Masami,
>
> I always see these values to be relative and not absolute time. I
> found 'praecox' to be always zero during test.
> What do you think.

Ah, right. Since "tim" is expire time (timer target), that should
always be "now + x"
(x is enough larger than how long setting the hrtimer takes). Or,
hrtimer expires
before finished to set. :)

Thank you,
-- 
Masami Hiramatsu

Re: [PATCH] trivial treewide: Convert dev_set_uevent_suppress argument to bool

[Bart Van Assche]

On 09/02/2016 08:41 AM, Joe Perches wrote:

On Fri, 2016-09-02 at 13:41 +, Bart Van Assche wrote:

On 09/01/16 17:51, Joe Perches wrote:

On Fri, 2016-09-02 at 00:47 +, Bart Van Assche wrote:

On 09/01/16 13:11, Joe Perches wrote:

Assigning an int to a bitfield:1 can lose precision.
Change the caller argument uses from 1/0 to true/false.

Can you clarify how assigning 0 or 1 to a one-bit bitfield can cause a
loss of precision?

There are no existing defects.
Using 1/0 is not a loss of precision, it's just
changing to use bool avoids potential errors and
promotes consistency.
Other uses of this function already use true/false.

In the patch description you refer to loss of precision. However, your
patch does not address any loss of precision issues. So I think that the
patch description is misleading and could be made more clear.


I tend towards terse being better than verbose.
The original patch description says

"no change to objects"

What would you suggest?


Hello Joe,

How about the following:

dev_set_uevent_suppress() expects a boolean as second argument. Make 
this clear by passing true/false instead of 1/0 as the second argument.


Bart.

Re: ath10k: replace config_enabled() with IS_REACHABLE()

[Kalle Valo]

Masahiro Yamada  wrote:
> Commit 97f2645f358b ("tree-wide: replace config_enabled() with
> IS_ENABLED()") mostly did away with config_enabled().
> 
> This is one of the postponed TODO items as config_enabled() is used
> for a tristate option here.  Theoretically, config_enabled() is
> equivalent to IS_BUILTIN(), but I guess IS_REACHABLE() is the best
> fit for this case because both CONFIG_HWMON and CONFIG_ATH10K are
> tristate.
> 
> Signed-off-by: Masahiro Yamada 

Thanks, 1 patch applied to ath-next branch of ath.git:

749bc03ae2cd ath10k: replace config_enabled() with IS_REACHABLE()

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9295945/

Re: [PATCH 1/4] KVM: x86: always fill in vcpu->arch.hv_clock

[Roman Kagan]

On Thu, Sep 01, 2016 at 05:26:12PM +0200, Paolo Bonzini wrote:
> We will use it in the next patches for KVM_GET_CLOCK and as a basis for the
> contents of the Hyper-V TSC page.  Get the values from the Linux
> timekeeper even if kvmclock is not enabled.
> 
> Signed-off-by: Paolo Bonzini 
> ---
>  arch/x86/kvm/x86.c | 109 
> +
>  1 file changed, 59 insertions(+), 50 deletions(-)
> 
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 19f9f9e05c2a..65974dd0565f 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1716,6 +1716,60 @@ static void kvm_gen_update_masterclock(struct kvm *kvm)
>  #endif
>  }
>  
> +static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
> +{
> + struct kvm_vcpu_arch *vcpu = >arch;
> + struct pvclock_vcpu_time_info guest_hv_clock;
> +
> + if (unlikely(kvm_read_guest_cached(v->kvm, >pv_time,
> + _hv_clock, sizeof(guest_hv_clock
> + return;
> +
> + /* This VCPU is paused, but it's legal for a guest to read another
> +  * VCPU's kvmclock, so we really have to follow the specification where
> +  * it says that version is odd if data is being modified, and even after
> +  * it is consistent.
> +  *
> +  * Version field updates must be kept separate.  This is because
> +  * kvm_write_guest_cached might use a "rep movs" instruction, and
> +  * writes within a string instruction are weakly ordered.  So there
> +  * are three writes overall.
> +  *
> +  * As a small optimization, only write the version field in the first
> +  * and third write.  The vcpu->pv_time cache is still valid, because the
> +  * version field is the first in the struct.
> +  */
> + BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
> +
> + vcpu->hv_clock.version = guest_hv_clock.version + 1;
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock.version));
> +
> + smp_wmb();
> +
> + /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
> + vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
> +
> + if (vcpu->pvclock_set_guest_stopped_request) {
> + vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
> + vcpu->pvclock_set_guest_stopped_request = false;
> + }
> +
> + trace_kvm_pvclock_update(v->vcpu_id, >hv_clock);
> +
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock));
> +
> + smp_wmb();
> +
> + vcpu->hv_clock.version++;
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock.version));
> +}
> +
>  static int kvm_guest_time_update(struct kvm_vcpu *v)
>  {
>   unsigned long flags, tgt_tsc_khz;
> @@ -1723,7 +1777,6 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>   struct kvm_arch *ka = >kvm->arch;
>   s64 kernel_ns;
>   u64 tsc_timestamp, host_tsc;
> - struct pvclock_vcpu_time_info guest_hv_clock;
>   u8 pvclock_flags;
>   bool use_master_clock;
>  
> @@ -1777,8 +1830,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>  
>   local_irq_restore(flags);
>  
> - if (!vcpu->pv_time_enabled)
> - return 0;

Strictly speaking, you only need .hv_clock updated if either kvmclock or
tsc_ref_page is enabled, so you may want to still skip the calculations
otherwise.

> + /* With all the info we got, fill in the values */
>  
>   if (kvm_has_tsc_control)
>   tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
> @@ -1790,64 +1842,21 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>   vcpu->hw_tsc_khz = tgt_tsc_khz;
>   }
>  
> - /* With all the info we got, fill in the values */
>   vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
>   vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
>   vcpu->last_guest_tsc = tsc_timestamp;
>  
> - if (unlikely(kvm_read_guest_cached(v->kvm, >pv_time,
> - _hv_clock, sizeof(guest_hv_clock
> - return 0;
> -
> - /* This VCPU is paused, but it's legal for a guest to read another
> -  * VCPU's kvmclock, so we really have to follow the specification where
> -  * it says that version is odd if data is being modified, and even after
> -  * it is consistent.
> -  *
> -  * Version field updates must be kept separate.  This is because
> -  * kvm_write_guest_cached might use a "rep movs" instruction, and
> -  * writes within a string instruction are weakly ordered.  So there
> -  * are three writes overall.
> -  *
> -  * As a small optimization, only write the version field in the first
> -  * and third write.  The vcpu->pv_time cache is 

Re: [PATCH 1/4] KVM: x86: always fill in vcpu->arch.hv_clock

[Roman Kagan]

On Thu, Sep 01, 2016 at 05:26:12PM +0200, Paolo Bonzini wrote:
> We will use it in the next patches for KVM_GET_CLOCK and as a basis for the
> contents of the Hyper-V TSC page.  Get the values from the Linux
> timekeeper even if kvmclock is not enabled.
> 
> Signed-off-by: Paolo Bonzini 
> ---
>  arch/x86/kvm/x86.c | 109 
> +
>  1 file changed, 59 insertions(+), 50 deletions(-)
> 
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 19f9f9e05c2a..65974dd0565f 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1716,6 +1716,60 @@ static void kvm_gen_update_masterclock(struct kvm *kvm)
>  #endif
>  }
>  
> +static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
> +{
> + struct kvm_vcpu_arch *vcpu = >arch;
> + struct pvclock_vcpu_time_info guest_hv_clock;
> +
> + if (unlikely(kvm_read_guest_cached(v->kvm, >pv_time,
> + _hv_clock, sizeof(guest_hv_clock
> + return;
> +
> + /* This VCPU is paused, but it's legal for a guest to read another
> +  * VCPU's kvmclock, so we really have to follow the specification where
> +  * it says that version is odd if data is being modified, and even after
> +  * it is consistent.
> +  *
> +  * Version field updates must be kept separate.  This is because
> +  * kvm_write_guest_cached might use a "rep movs" instruction, and
> +  * writes within a string instruction are weakly ordered.  So there
> +  * are three writes overall.
> +  *
> +  * As a small optimization, only write the version field in the first
> +  * and third write.  The vcpu->pv_time cache is still valid, because the
> +  * version field is the first in the struct.
> +  */
> + BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
> +
> + vcpu->hv_clock.version = guest_hv_clock.version + 1;
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock.version));
> +
> + smp_wmb();
> +
> + /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
> + vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
> +
> + if (vcpu->pvclock_set_guest_stopped_request) {
> + vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
> + vcpu->pvclock_set_guest_stopped_request = false;
> + }
> +
> + trace_kvm_pvclock_update(v->vcpu_id, >hv_clock);
> +
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock));
> +
> + smp_wmb();
> +
> + vcpu->hv_clock.version++;
> + kvm_write_guest_cached(v->kvm, >pv_time,
> + >hv_clock,
> + sizeof(vcpu->hv_clock.version));
> +}
> +
>  static int kvm_guest_time_update(struct kvm_vcpu *v)
>  {
>   unsigned long flags, tgt_tsc_khz;
> @@ -1723,7 +1777,6 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>   struct kvm_arch *ka = >kvm->arch;
>   s64 kernel_ns;
>   u64 tsc_timestamp, host_tsc;
> - struct pvclock_vcpu_time_info guest_hv_clock;
>   u8 pvclock_flags;
>   bool use_master_clock;
>  
> @@ -1777,8 +1830,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>  
>   local_irq_restore(flags);
>  
> - if (!vcpu->pv_time_enabled)
> - return 0;

Strictly speaking, you only need .hv_clock updated if either kvmclock or
tsc_ref_page is enabled, so you may want to still skip the calculations
otherwise.

> + /* With all the info we got, fill in the values */
>  
>   if (kvm_has_tsc_control)
>   tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
> @@ -1790,64 +1842,21 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
>   vcpu->hw_tsc_khz = tgt_tsc_khz;
>   }
>  
> - /* With all the info we got, fill in the values */
>   vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
>   vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
>   vcpu->last_guest_tsc = tsc_timestamp;
>  
> - if (unlikely(kvm_read_guest_cached(v->kvm, >pv_time,
> - _hv_clock, sizeof(guest_hv_clock
> - return 0;
> -
> - /* This VCPU is paused, but it's legal for a guest to read another
> -  * VCPU's kvmclock, so we really have to follow the specification where
> -  * it says that version is odd if data is being modified, and even after
> -  * it is consistent.
> -  *
> -  * Version field updates must be kept separate.  This is because
> -  * kvm_write_guest_cached might use a "rep movs" instruction, and
> -  * writes within a string instruction are weakly ordered.  So there
> -  * are three writes overall.
> -  *
> -  * As a small optimization, only write the version field in the first
> -  * and third write.  The vcpu->pv_time cache is still valid, because the

[PATCH v2 14/15] Simplify testing of link status and speed testing.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   36 +++-
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a2610dd..e33d2f7 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -52,9 +52,8 @@
 #define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
 #define  PCIE_CLIENT_GEN_SEL_2   HIWORD_UPDATE(0x0040, 0x0040)
 #define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
-#define  PCIE_CLIENT_LINK_STATUS_UP0x3
-#define  PCIE_CLIENT_LINK_STATUS_SHIFT 20
-#define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
+#define  PCIE_CLIENT_LINK_STATUS_UP0x0030
+#define  PCIE_CLIENT_LINK_STATUS_MASK  0x0030
 #define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
 #define  PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
@@ -89,11 +88,10 @@
 
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
-#define  PCIE_CORE_PL_CONF_SPEED_5G0x1
-#define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
-#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
+#define  PCIE_CORE_PL_CONF_SPEED_5G0x0008
+#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x0018
+#define  PCIE_CORE_PL_CONF_LANE_MASK   0x0006
 #define  PCIE_CORE_PL_CONF_LANE_SHIFT  1
-#define  PCIE_CORE_PL_CONF_LANE_MASK   0x3
 #define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
@@ -477,9 +475,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
for (;;) {
status = rockchip_pcie_read(rockchip,
PCIE_CLIENT_BASIC_STATUS1);
-   if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
- PCIE_CLIENT_LINK_STATUS_MASK) ==
- PCIE_CLIENT_LINK_STATUS_UP) {
+   if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+   PCIE_CLIENT_LINK_STATUS_UP) {
dev_dbg(dev, "PCIe link training gen1 pass!\n");
break;
}
@@ -496,9 +493,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (err) {
status = rockchip_pcie_read(rockchip,
PCIE_CLIENT_BASIC_STATUS1);
-   err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
-   PCIE_CLIENT_LINK_STATUS_MASK) ==
-   PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
+   err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+  PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
if (err) {
dev_err(dev, "PCIe link training gen1 timeout!\n");
return err;
@@ -516,9 +512,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-PCIE_CORE_PL_CONF_SPEED_MASK) ==
-PCIE_CORE_PL_CONF_SPEED_5G) {
+   if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+   PCIE_CORE_PL_CONF_SPEED_5G) {
dev_dbg(dev, "PCIe link training gen2 pass!\n");
break;
}
@@ -534,17 +529,16 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
/* Double check gen2 training */
if (err) {
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-   PCIE_CORE_PL_CONF_SPEED_MASK) ==
-   PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
+   err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+  PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
if (err)
dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
}
 
/* Check the final link width from negotiated lane counter from MGMT */
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
-  PCIE_CORE_PL_CONF_LANE_MASK);
+   status =  0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+ PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
 
rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,

[PATCH 1/6] ASoC: arizona: Correct handling of FLL theta in synchroniser mode

[Charles Keepax]

Theta/lambda is used to give the fractional portion of the FLL
frequency multiplication. When the synchroniser is active the
reference path lambda value is hard coded in the hardware to
65536. This patch corrects the handling of theta such that it
is scaled to match this denominator, when the synchroniser is
active.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index ccb3ca2..ded235f 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -1920,8 +1920,8 @@ static struct {
 
 struct arizona_fll_cfg {
int n;
-   int theta;
-   int lambda;
+   unsigned int theta;
+   unsigned int lambda;
int refdiv;
int outdiv;
int fratio;
@@ -2233,6 +2233,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
fll->ref_src != fll->sync_src) {
arizona_calc_fll(fll, , fll->ref_freq, false);
 
+   /* Ref path hardcodes lambda to 65536 when sync is on */
+   if (fll->sync_src >= 0 && cfg.lambda)
+   cfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda;
+
arizona_apply_fll(arizona, fll->base, , fll->ref_src,
  false);
if (fll->sync_src >= 0) {
-- 
2.1.4

[PATCH v2 14/15] Simplify testing of link status and speed testing.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   36 +++-
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a2610dd..e33d2f7 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -52,9 +52,8 @@
 #define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
 #define  PCIE_CLIENT_GEN_SEL_2   HIWORD_UPDATE(0x0040, 0x0040)
 #define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
-#define  PCIE_CLIENT_LINK_STATUS_UP0x3
-#define  PCIE_CLIENT_LINK_STATUS_SHIFT 20
-#define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
+#define  PCIE_CLIENT_LINK_STATUS_UP0x0030
+#define  PCIE_CLIENT_LINK_STATUS_MASK  0x0030
 #define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
 #define  PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
@@ -89,11 +88,10 @@
 
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
-#define  PCIE_CORE_PL_CONF_SPEED_5G0x1
-#define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
-#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
+#define  PCIE_CORE_PL_CONF_SPEED_5G0x0008
+#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x0018
+#define  PCIE_CORE_PL_CONF_LANE_MASK   0x0006
 #define  PCIE_CORE_PL_CONF_LANE_SHIFT  1
-#define  PCIE_CORE_PL_CONF_LANE_MASK   0x3
 #define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
@@ -477,9 +475,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
for (;;) {
status = rockchip_pcie_read(rockchip,
PCIE_CLIENT_BASIC_STATUS1);
-   if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
- PCIE_CLIENT_LINK_STATUS_MASK) ==
- PCIE_CLIENT_LINK_STATUS_UP) {
+   if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+   PCIE_CLIENT_LINK_STATUS_UP) {
dev_dbg(dev, "PCIe link training gen1 pass!\n");
break;
}
@@ -496,9 +493,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (err) {
status = rockchip_pcie_read(rockchip,
PCIE_CLIENT_BASIC_STATUS1);
-   err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
-   PCIE_CLIENT_LINK_STATUS_MASK) ==
-   PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
+   err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
+  PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
if (err) {
dev_err(dev, "PCIe link training gen1 timeout!\n");
return err;
@@ -516,9 +512,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-PCIE_CORE_PL_CONF_SPEED_MASK) ==
-PCIE_CORE_PL_CONF_SPEED_5G) {
+   if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+   PCIE_CORE_PL_CONF_SPEED_5G) {
dev_dbg(dev, "PCIe link training gen2 pass!\n");
break;
}
@@ -534,17 +529,16 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
/* Double check gen2 training */
if (err) {
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
-   PCIE_CORE_PL_CONF_SPEED_MASK) ==
-   PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
+   err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
+  PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
if (err)
dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
}
 
/* Check the final link width from negotiated lane counter from MGMT */
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
-  PCIE_CORE_PL_CONF_LANE_MASK);
+   status =  0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+ PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
 
rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,

[PATCH 1/6] ASoC: arizona: Correct handling of FLL theta in synchroniser mode

[Charles Keepax]

Theta/lambda is used to give the fractional portion of the FLL
frequency multiplication. When the synchroniser is active the
reference path lambda value is hard coded in the hardware to
65536. This patch corrects the handling of theta such that it
is scaled to match this denominator, when the synchroniser is
active.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index ccb3ca2..ded235f 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -1920,8 +1920,8 @@ static struct {
 
 struct arizona_fll_cfg {
int n;
-   int theta;
-   int lambda;
+   unsigned int theta;
+   unsigned int lambda;
int refdiv;
int outdiv;
int fratio;
@@ -2233,6 +2233,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
fll->ref_src != fll->sync_src) {
arizona_calc_fll(fll, , fll->ref_freq, false);
 
+   /* Ref path hardcodes lambda to 65536 when sync is on */
+   if (fll->sync_src >= 0 && cfg.lambda)
+   cfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda;
+
arizona_apply_fll(arizona, fll->base, , fll->ref_src,
  false);
if (fll->sync_src >= 0) {
-- 
2.1.4

Re: [PATCH] usb: dwc3: host: inherit dma configuration from parent dev

[Arnd Bergmann]

On Friday, September 2, 2016 10:21:23 AM CEST Alan Stern wrote:
> On Fri, 2 Sep 2016, Felipe Balbi wrote:
> 
> > Hi,
> > 
> > Russell King - ARM Linux  writes:
> > > On Fri, Sep 02, 2016 at 12:43:39PM +0200, Arnd Bergmann wrote:
> > >> On Thursday, September 1, 2016 5:14:28 PM CEST Leo Li wrote:
> > >> > 
> > >> > Hi Felipe and Arnd,
> > >> > 
> > >> > It has been a while since the last response to this discussion, but we
> > >> > haven't reached an agreement yet!  Can we get to a conclusion on if it
> > >> > is valid to create child platform device for abstraction purpose?  If
> > >> > yes, can this child device do DMA by itself?
> > >> 
> > >> I'd say it's no problem for a driver to create child devices in order
> > >> to represent different aspects of a device, but you should not rely on
> > >> those devices working when used with the dma-mapping interfaces.
> > >
> > > That's absolutely right.  Consider the USB model - only the USB host
> > > controller can perform DMA, not the USB devices themselves.  All DMA
> > > mappings need to be mapped using the USB host controller device struct
> > > not the USB device struct.
> > >
> > > The same _should_ be true everywhere else: the struct device representing
> > > the device performing DMA must be the one used to map the transfer.
> > 
> > How do we fix dwc3 in dual-role, then?
> > 
> > Peripheral-side dwc3 is easy, we just require a glue-layer to be present
> > and use dwc3.ko's parent device (which will be the PCI device or OF
> > device). But for host side dwc3, the problem is slightly more complex
> > because we're using xhci-plat.ko by just instantiating a xhci-platform
> > device so xhci-plat can probe.
> > 
> > xhci core has no means to know if its own device or the parent of its
> > parent should be used for DMA. Any ideas?
> 
> In theory, you can store a flag somewhere in the platform device,
> something that would tell xhci-hcd that it has to use the parent's
> parent for DMA purposes.
> 
> I know it would be somewhat of a hack, but ought to work.

Speaking of that flag, I suppose we need the same logic to know where
to look for USB devices attached to a dwc3 host when we need to describe
them in DT. By default we look for child device nodes under the
node of the HCD device node, but that would be wrong here too.

Arnd 

[PATCH v2 10/15] Group related CSR definitions together.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |  148 +++---
 1 file changed, 74 insertions(+), 74 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 6edfce5..fe1b52f 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -37,21 +37,27 @@
 #include 
 #include 
 
-#define PCIE_CLIENT_BASE   0x0
-#define PCIE_RC_CONFIG_BASE0xa0
-#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   (PCIE_RC_CONFIG_BASE + 0x90c)
-#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0x0d0)
-#define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
-#define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
-#define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
-#define  PCIE_RC_CONFIG_LCS_LBMS   BIT(30)
-#define  PCIE_RC_CONFIG_LCS_LAMS   BIT(31)
-#define PCIE_CORE_CTRL_MGMT_BASE   0x90
-#define PCIE_CORE_AXI_CONF_BASE0xc0
-#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
-#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
-#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
+/*
+ * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16
+ * bits.  This allows atomic updates of the register without locking.
+ */
+#define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
+
+#define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
+
+#define PCIE_CLIENT_BASE   0x0
+#define  PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE(0x0001, 0x0001)
+#define  PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE(0x0002, 0x0002)
+#define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
+#define  PCIE_CLIENT_GEN_SEL_2   HIWORD_UPDATE(0x0040, 0x0040)
+#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
+#define  PCIE_CLIENT_LINK_STATUS_UP0x3
+#define  PCIE_CLIENT_LINK_STATUS_SHIFT 20
+#define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
+#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
+#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
+#define  ROCKCHIP_PCIE_RPIFR1_INTR_MASKGENMASK(8, 5)
+#define  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT   5
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -68,18 +74,25 @@
 #define  PCIE_CLIENT_INT_PHY   BIT(2)
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
-#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
-#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 
0x300)
-#define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
-#define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
-#define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
-#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
-#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
-#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 
0x4)
-#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 
0x210)
-#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 
0x20c)
+
+#define PCIE_CLIENT_INT_LEGACY \
+   (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
+   PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
+
+#define PCIE_CLIENT_INT_CLI \
+   (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
+   PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
+   PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
+   PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
+   PCIE_CLIENT_INT_PHY)
+
+#define PCIE_CORE_CTRL_MGMT_BASE   0x90
+#define  PCIE_CORE_PL_CONF_SPEED_5G0x1
+#define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
+#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
+#define  PCIE_CORE_PL_CONF_LANE_SHIFT  1
+#define  PCIE_CORE_PL_CONF_LANE_MASK   0x3
+#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
 #define  PCIE_CORE_INT_RRPEBIT(2)
@@ -94,6 +107,40 @@
 #define  PCIE_CORE_INT_CT  BIT(11)
 #define  PCIE_CORE_INT_UTC BIT(18)
 #define  PCIE_CORE_INT_MMVCBIT(19)
+#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
+#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
+

Re: [PATCH] genirq: Generic chip: verify irqs_per_chip <= 32

[Thomas Gleixner]

On Tue, 16 Aug 2016, Sebastian Frias wrote:
> Most (if not all) code here implicitly assumes that the maximum number of
> IRQs per chip will be 32, and thus uses 'u32' or 'unsigned long' for many
> tasks (for example "struct irq_data" declares its 'mask' field as 'u32',
> and "struct irq_chip_generic" declares its 'installed' field as 'unsigned
> long')
> 
> However, there is no check to verify that irqs_per_chip is <= 32.
> Hence, calling irq_alloc_domain_generic_chips() with a bigger value would
> result in unexpected results depending on how the 'mask' is accessed later
> on.
> For example, if set_bit() is used on the 'installed' field of "struct
> irq_chip_generic", it would result in the next field (in this case
> the 'unused' field) being overwritten, because set_bit() is designed to
> treat its parameter as a field of bits of arbitrary size organised as
> "unsigned long" words.

We really do not need examples for the potential wreckage. Your explanation
that the code has implict assumptions about the maximum number of
interrupts per chip is sufficient. We all know what out of bound access can
cause.

> This patch renames irq_alloc_domain_generic_chips() to
> __irq_alloc_domain_generic_chips() and creates a macro to replace it.
> The macro uses MAYBE_BUILD_BUG_ON to check the irqs_per_chip parameter to
> stop compilation (if the compiler can resolve the parameter to a constant
> at compile time) or to warn during run-time, if the parameter given is
> bigger than 32.

There is no point in explaining the implementation in the changelog. It's
obvious from the patch itself.

I'll fix that up as well.

Thanks,

tglx

[PATCH v2 05/15] Use a local "dev" to avoid repetition of "rockchip->dev".

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   98 --
 1 file changed, 51 insertions(+), 47 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 63fb0ebc..ea75f35 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -380,6 +380,7 @@ static struct pci_ops rockchip_pcie_ops = {
  */
 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 {
+   struct device *dev = rockchip->dev;
int err;
u32 status;
unsigned long timeout;
@@ -388,31 +389,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
err = phy_init(rockchip->phy);
if (err < 0) {
-   dev_err(rockchip->dev, "fail to init phy, err %d\n", err);
+   dev_err(dev, "fail to init phy, err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->core_rst);
if (err) {
-   dev_err(rockchip->dev, "assert core_rst err %d\n", err);
+   dev_err(dev, "assert core_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
-   dev_err(rockchip->dev, "assert mgmt_rst err %d\n", err);
+   dev_err(dev, "assert mgmt_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
-   dev_err(rockchip->dev, "assert mgmt_sticky_rst err %d\n", err);
+   dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
-   dev_err(rockchip->dev, "assert pipe_rst err %d\n", err);
+   dev_err(dev, "assert pipe_rst err %d\n", err);
return err;
}
 
@@ -436,31 +437,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
err = phy_power_on(rockchip->phy);
if (err) {
-   dev_err(rockchip->dev, "fail to power on phy, err %d\n", err);
+   dev_err(dev, "fail to power on phy, err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->core_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert core_rst err %d\n", err);
+   dev_err(dev, "deassert core_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert mgmt_rst err %d\n", err);
+   dev_err(dev, "deassert mgmt_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert mgmt_sticky_rst err %d\n", 
err);
+   dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert pipe_rst err %d\n", err);
+   dev_err(dev, "deassert pipe_rst err %d\n", err);
return err;
}
 
@@ -492,7 +493,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
  PCIE_CLIENT_LINK_STATUS_MASK) ==
  PCIE_CLIENT_LINK_STATUS_UP) {
-   dev_dbg(rockchip->dev, "PCIe link training gen1 
pass!\n");
+   dev_dbg(dev, "PCIe link training gen1 pass!\n");
break;
}
 
@@ -511,7 +512,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CLIENT_LINK_STATUS_MASK) ==
PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
if (err) {
-   dev_err(rockchip->dev, "PCIe link training gen1 
timeout!\n");
+   dev_err(dev, "PCIe link training gen1 timeout!\n");
return err;
}
}
@@ -532,7 +533,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 PCIE_CORE_PL_CONF_SPEED_MASK) ==
 PCIE_CORE_PL_CONF_SPEED_5G) {
-   dev_dbg(rockchip->dev, "PCIe link training gen2 
pass!\n");
+   dev_dbg(dev, "PCIe link training gen2 pass!\n");
break;
}
 
@@ -551,14 +552,14 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CORE_PL_CONF_SPEED_MASK) ==
PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
if (err)
-   

[PATCH v2 01/15] Remove unused symbols, unnecessary parens, other minor comments from

[Bjorn Helgaas]

Guenter.
---
 drivers/pci/host/pcie-rockchip.c |   69 --
 1 file changed, 21 insertions(+), 48 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e77aec3..a7006be 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -38,7 +38,6 @@
 #include 
 
 #define PCIE_CLIENT_BASE   0x0
-#define PCIE_RC_CONFIG_NORMAL_BASE 0x80
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
 #define PCIE_RC_CONFIG_LCSR0xd0
@@ -126,9 +125,6 @@
 #define RC_REGION_0_ADDR_TRANS_H   0x
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
-#define RC_REGION_1_ADDR_TRANS_H   0x
-#define RC_REGION_1_ADDR_TRANS_L   0x0040
-#define RC_REGION_1_PASS_BITS  (20 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
 #define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
 #define PCIE_CLIENT_CONF_ENABLEBIT(0)
@@ -147,15 +143,12 @@
 #define PCIE_CLIENT_MODE_SHIFT 6
 #define PCIE_CLIENT_MODE_MASK  0x1
 #define PCIE_CLIENT_GEN_SEL_2  1
-#define PCIE_CLIENT_GEN_SEL_1  0
 #define PCIE_CLIENT_GEN_SEL_SHIFT  7
 #define PCIE_CLIENT_GEN_SEL_MASK   0x1
 #define PCIE_CLIENT_LINK_STATUS_UP 0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT  20
 #define PCIE_CLIENT_LINK_STATUS_MASK   0x3
-#define PCIE_CORE_PL_CONF_SPEED_2_5G   0x0
 #define PCIE_CORE_PL_CONF_SPEED_5G 0x1
-#define PCIE_CORE_PL_CONF_SPEED_8G 0x2
 #define PCIE_CORE_PL_CONF_SPEED_SHIFT  3
 #define PCIE_CORE_PL_CONF_SPEED_MASK   0x3
 #define PCIE_CORE_PL_CONF_LANE_SHIFT   1
@@ -174,11 +167,6 @@
 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
 PCIE_CORE_INT_MMVC)
 
-#define PCIE_CLIENT_INT_SUBSYSTEM \
-   (PCIE_CLIENT_INT_PWR_STCG | PCIE_CLIENT_INT_HOT_PLUG | \
-   PCIE_CLIENT_INT_PHY | PCIE_CLIENT_INT_UDMA | \
-   PCIE_CLIENT_INT_LOCAL)
-
 #define PCIE_CLIENT_INT_LEGACY \
(PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
@@ -191,8 +179,8 @@
PCIE_CLIENT_INT_PHY)
 
 struct rockchip_pcie_port {
-   void__iomem *reg_base;
-   void__iomem *apb_base;
+   void__iomem *reg_base;  /* DT axi-base */
+   void__iomem *apb_base;  /* DT apb-base */
struct  phy *phy;
struct  reset_control *core_rst;
struct  reset_control *mgmt_rst;
@@ -240,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct 
rockchip_pcie_port *port)
pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
@@ -286,7 +274,7 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *pp,
 {
u32 mask, tmp, offset;
 
-   offset = (where & (~0x3));
+   offset = where & ~0x3;
 
if (size == 4) {
writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
@@ -357,7 +345,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
 {
struct rockchip_pcie_port *pp = bus->sysdata;
 
-   if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn))) {
+   if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
*val = 0x;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -366,7 +354,6 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
return rockchip_pcie_rd_own_conf(pp, where, size, val);
 
return rockchip_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
-
 }
 
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
@@ -374,7 +361,7 @@ static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 
devfn,
 {
struct rockchip_pcie_port *pp = bus->sysdata;
 
-   if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)))
+   if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
 
if (bus->number == pp->root_bus_nr)
@@ -516,7 +503,6 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
err = -ETIMEDOUT;
break;
}
-
}
 
/* Double check gen1 training */
@@ -744,11 +730,6 @@ static int rockchip_pcie_parse_dt(struct 
rockchip_pcie_port *port)
regs = platform_get_resource_byname(pdev,

[PATCH 2/6] ASoC: arizona: Allow specification of base for arizona_is_enabled_fll

[Charles Keepax]

In preparation for future improvements allow a base to be passed to
arizona_is_enabled_fll, this will allow it to be used to check the state
of the synchroniser path as well.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index ded235f..463979f4 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2188,13 +2188,13 @@ static void arizona_apply_fll(struct arizona *arizona, 
unsigned int base,
 ARIZONA_FLL1_CTRL_UPD | cfg->n);
 }
 
-static int arizona_is_enabled_fll(struct arizona_fll *fll)
+static int arizona_is_enabled_fll(struct arizona_fll *fll, int base)
 {
struct arizona *arizona = fll->arizona;
unsigned int reg;
int ret;
 
-   ret = regmap_read(arizona->regmap, fll->base + 1, );
+   ret = regmap_read(arizona->regmap, base + 1, );
if (ret != 0) {
arizona_fll_err(fll, "Failed to read current state: %d\n",
ret);
@@ -2208,7 +2208,7 @@ static int arizona_enable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
bool use_sync = false;
-   int already_enabled = arizona_is_enabled_fll(fll);
+   int already_enabled = arizona_is_enabled_fll(fll, fll->base);
struct arizona_fll_cfg cfg;
int i;
unsigned int val;
-- 
2.1.4

Re: [PATCH 2/2] arm64: Use static keys for CPU features

[Catalin Marinas]

On Fri, Aug 26, 2016 at 10:22:13AM +0100, Suzuki K. Poulose wrote:
> On 25/08/16 18:26, Catalin Marinas wrote:
> > static inline int __attribute_const__
> >diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> >index 62272eac1352..919b2d0d68ae 100644
> >--- a/arch/arm64/kernel/cpufeature.c
> >+++ b/arch/arm64/kernel/cpufeature.c
> >@@ -46,6 +46,9 @@ unsigned int compat_elf_hwcap2 __read_mostly;
> >
> > DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
> >
> >+DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
> >+EXPORT_SYMBOL(cpu_hwcap_keys);
> >+
> > #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
> > {   \
> > .sign = SIGNED, \
> >diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> >index ed1b84fe6925..6a141e399daf 100644
> >--- a/arch/arm64/kernel/cpuinfo.c
> >+++ b/arch/arm64/kernel/cpuinfo.c
> >@@ -377,6 +377,12 @@ void cpuinfo_store_cpu(void)
> > void __init cpuinfo_store_boot_cpu(void)
> > {
> > struct cpuinfo_arm64 *info = _cpu(cpu_data, 0);
> >+
> >+/*
> >+ * Initialise the static keys early as they may be enabled by
> >+ * check_local_cpu_errata() -> update_cpu_capabilities().
> >+ */
> >+jump_label_init();
> > __cpuinfo_store_cpu(info);
> 
> Just a heads up. I have a patch [1] which moves the "check_local_cpu_errata()"
> around to smp_prepare_boot_cpu(). This patch should still work fine with that
> case. Only that may be we could move the jump_lable_init() to 
> smp_prepare_boot_cpu(),
> before we call "update_cpu_errata_work_arounds()" for Boot CPU.

IIUC, we wouldn't call update_cpu_errata_work_arounds() until the CPU
feature infrastructure is initialised via cpuinfo_store_boot_cpu(). So
I don't think moving the jump_label_init() call above is necessary.

> [1] 
> https://lkml.kernel.org/r/1471525832-21209-4-git-send-email-suzuki.poul...@arm.com

-- 
Catalin

[PATCH 0/6] Arizona FLL fixes and Clocking Improvements

[Charles Keepax]

Hi,

The first 3 patches in this series fix some small issues with
the FLL configuration in the driver. The second 3 patches add
support for requesting the input clocks for the CODEC through the
clock framework. This is some what of an intermediate step until
all the clocking itself in the CODEC can be brought under the
clock framework but as there are machine drivers that want to be
merged now with source clocks that require gating and difficult
to resolve issues between the SPI and clock framework an
intermediate solution seems warranted.

Whilst the two halfs of this series do fairly different things,
I have sent them as once series as they touch a lot of the same
code, so this seemed the simpler approach to pushing them both
through. The series is based of Mark's ASoC for-next tree.

Thanks,
Charles

Charles Keepax (5):
  ASoC: arizona: Correct handling of FLL theta in synchroniser mode
  ASoC: arizona: Allow specification of base for arizona_is_enabled_fll
  ASoC: arizona: Avoid changing SYNC_ENA whilst the FLL_ENA is set
  ASoC: arizona: Add gating for clock when used for direct MCLK
  ASoC: arizona: Add gating for source clocks of the FLLs

Sylwester Nawrocki (1):
  mfd: arizona: Add gating of external MCLKn clocks

 drivers/mfd/arizona-core.c   |  30 +-
 include/linux/mfd/arizona/core.h |   9 +++
 sound/soc/codecs/arizona.c   | 124 +++
 sound/soc/codecs/arizona.h   |   2 +
 sound/soc/codecs/cs47l24.c   |   6 +-
 sound/soc/codecs/wm5102.c|   9 ++-
 sound/soc/codecs/wm5110.c|  10 +++-
 sound/soc/codecs/wm8997.c|   9 ++-
 sound/soc/codecs/wm8998.c|   6 +-
 9 files changed, 179 insertions(+), 26 deletions(-)

-- 
2.1.4

[PATCH 10/12] MIPS: Malta: Remove custom halt implementation

[Paul Burton]

The arch code will hang the machine with an infinite loop if the board
doesn't provide an impelementation of halt - let it, rather than
duplicating it.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-reset.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/arch/mips/mti-malta/malta-reset.c 
b/arch/mips/mti-malta/malta-reset.c
index 04d6b9c..dd6f62a 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -13,11 +13,6 @@
 #include 
 #include 
 
-static void mips_machine_halt(void)
-{
-   while (true);
-}
-
 static void mips_machine_power_off(void)
 {
mips_pm_suspend(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF);
@@ -28,7 +23,6 @@ static void mips_machine_power_off(void)
 
 static int __init mips_reboot_setup(void)
 {
-   _machine_halt = mips_machine_halt;
pm_power_off = mips_machine_power_off;
 
return 0;
-- 
2.9.3

Re: [2/2] ath10k: use complete() instead complete_all()

[Kalle Valo]

Daniel Wagner  wrote:
> From: Daniel Wagner 
> 
> There is only one waiter for the completion, therefore there
> is no need to use complete_all(). Let's make that clear by
> using complete() instead of complete_all().
> 
> The usage pattern of the completion is:
> 
> waiter context  waker context
> 
> scan.started
> 
> 
> ath10k_start_scan()
>   lockdep_assert_held(conf_mutex)
>   auth10k_wmi_start_scan()
>   wait_for_completion_timeout(scan.started)
> 
>   ath10k_wmi_event_scan_start_failed()
> complete(scan.started)
> 
>   ath10k_wmi_event_scan_started()
> complete(scan.started)
> 
> scan.completed
> --
> 
> ath10k_scan_stop()
>   lockdep_assert_held(conf_mutex)
>   ath10k_wmi_stop_scan()
>   wait_for_completion_timeout(scan.completed)
> 
>   __ath10k_scan_finish()
> complete(scan.completed)
> 
> scan.on_channel
> ---
> 
> ath10k_remain_on_channel()
>   mutex_lock(conf_mutex)
>   ath10k_start_scan()
>   wait_for_completion_timeout(scan.on_channel)
> 
>   ath10k_wmi_event_scan_foreign_chan()
> complete(scan.on_channel)
> 
> offchan_tx_completed
> 
> 
> ath10k_offchan_tx_work()
>   mutex_lock(conf_mutex)
>   reinit_completion(offchan_tx_completed)
>   wait_for_completion_timeout(offchan_tx_completed)
> 
>   ath10k_report_offchain_tx()
> complete(offchan_tx_completed)
> 
> install_key_done
> 
> ath10k_install_key()
>   lockep_assert_held(conf_mutex)
>   reinit_completion(install_key_done)
>   wait_for_completion_timeout(install_key_done)
> 
>   ath10k_htt_t2h_msg_handler()
> complete(install_key_done)
> 
> vdev_setup_done
> ---
> 
> ath10k_monitor_vdev_start()
>   lockdep_assert_held(conf_mutex)
>reinit_completion(vdev_setup_done)
>   ath10k_vdev_setup_sync()
> wait_for_completion_timeout(vdev_setup_done)
> 
>   ath10k_wmi_event_vdev_start_resp()
> complete(vdev_setup_done)
> 
> ath10k_monitor_vdev_stop()
>   lockdep_assert_held(conf_mutex)
>   reinit_completion(vdev_setup_done()
>   ath10k_vdev_setup_sync()
> wait_for_completion_timeout(vdev_setup_done)
> 
>   ath10k_wmi_event_vdev_stopped()
>complete(vdev_setup_done)
> 
> thermal.wmi_sync
> 
> ath10k_thermal_show_temp()
>   mutex_lock(conf_mutex)
>   reinit_completion(thermal.wmi_sync)
>   wait_for_completion_timeout(thermal.wmi_sync)
> 
>   ath10k_thermal_event_temperature()
> complete(thermal.wmi_sync)
> 
> bss_survey_done
> ---
> ath10k_mac_update_bss_chan_survey
>   lockdep_assert_held(conf_mutex)
>   reinit_completion(bss_survey_done)
>   wait_for_completion_timeout(bss_survey_done)
> 
>   ath10k_wmi_event_pdev_bss_chan_info()
> complete(bss_survey_done)
> 
> All complete() calls happen while the conf_mutex is taken. That means
> at max one waiter is possible.
> 
> Signed-off-by: Daniel Wagner 

Thanks, 1 patch applied to ath-next branch of ath.git:

881ed54ecc13 ath10k: use complete() instead complete_all()

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9287731/

[PATCH v2 01/15] Remove unused symbols, unnecessary parens, other minor comments from

[Bjorn Helgaas]

Guenter.
---
 drivers/pci/host/pcie-rockchip.c |   69 --
 1 file changed, 21 insertions(+), 48 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e77aec3..a7006be 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -38,7 +38,6 @@
 #include 
 
 #define PCIE_CLIENT_BASE   0x0
-#define PCIE_RC_CONFIG_NORMAL_BASE 0x80
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
 #define PCIE_RC_CONFIG_LCSR0xd0
@@ -126,9 +125,6 @@
 #define RC_REGION_0_ADDR_TRANS_H   0x
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
-#define RC_REGION_1_ADDR_TRANS_H   0x
-#define RC_REGION_1_ADDR_TRANS_L   0x0040
-#define RC_REGION_1_PASS_BITS  (20 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
 #define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
 #define PCIE_CLIENT_CONF_ENABLEBIT(0)
@@ -147,15 +143,12 @@
 #define PCIE_CLIENT_MODE_SHIFT 6
 #define PCIE_CLIENT_MODE_MASK  0x1
 #define PCIE_CLIENT_GEN_SEL_2  1
-#define PCIE_CLIENT_GEN_SEL_1  0
 #define PCIE_CLIENT_GEN_SEL_SHIFT  7
 #define PCIE_CLIENT_GEN_SEL_MASK   0x1
 #define PCIE_CLIENT_LINK_STATUS_UP 0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT  20
 #define PCIE_CLIENT_LINK_STATUS_MASK   0x3
-#define PCIE_CORE_PL_CONF_SPEED_2_5G   0x0
 #define PCIE_CORE_PL_CONF_SPEED_5G 0x1
-#define PCIE_CORE_PL_CONF_SPEED_8G 0x2
 #define PCIE_CORE_PL_CONF_SPEED_SHIFT  3
 #define PCIE_CORE_PL_CONF_SPEED_MASK   0x3
 #define PCIE_CORE_PL_CONF_LANE_SHIFT   1
@@ -174,11 +167,6 @@
 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
 PCIE_CORE_INT_MMVC)
 
-#define PCIE_CLIENT_INT_SUBSYSTEM \
-   (PCIE_CLIENT_INT_PWR_STCG | PCIE_CLIENT_INT_HOT_PLUG | \
-   PCIE_CLIENT_INT_PHY | PCIE_CLIENT_INT_UDMA | \
-   PCIE_CLIENT_INT_LOCAL)
-
 #define PCIE_CLIENT_INT_LEGACY \
(PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
@@ -191,8 +179,8 @@
PCIE_CLIENT_INT_PHY)
 
 struct rockchip_pcie_port {
-   void__iomem *reg_base;
-   void__iomem *apb_base;
+   void__iomem *reg_base;  /* DT axi-base */
+   void__iomem *apb_base;  /* DT apb-base */
struct  phy *phy;
struct  reset_control *core_rst;
struct  reset_control *mgmt_rst;
@@ -240,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct 
rockchip_pcie_port *port)
pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
@@ -286,7 +274,7 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *pp,
 {
u32 mask, tmp, offset;
 
-   offset = (where & (~0x3));
+   offset = where & ~0x3;
 
if (size == 4) {
writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
@@ -357,7 +345,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
 {
struct rockchip_pcie_port *pp = bus->sysdata;
 
-   if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn))) {
+   if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
*val = 0x;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -366,7 +354,6 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
return rockchip_pcie_rd_own_conf(pp, where, size, val);
 
return rockchip_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
-
 }
 
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
@@ -374,7 +361,7 @@ static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 
devfn,
 {
struct rockchip_pcie_port *pp = bus->sysdata;
 
-   if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)))
+   if (!rockchip_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
 
if (bus->number == pp->root_bus_nr)
@@ -516,7 +503,6 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
err = -ETIMEDOUT;
break;
}
-
}
 
/* Double check gen1 training */
@@ -744,11 +730,6 @@ static int rockchip_pcie_parse_dt(struct 
rockchip_pcie_port *port)
regs = platform_get_resource_byname(pdev,

[PATCH 2/6] ASoC: arizona: Allow specification of base for arizona_is_enabled_fll

[Charles Keepax]

In preparation for future improvements allow a base to be passed to
arizona_is_enabled_fll, this will allow it to be used to check the state
of the synchroniser path as well.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index ded235f..463979f4 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2188,13 +2188,13 @@ static void arizona_apply_fll(struct arizona *arizona, 
unsigned int base,
 ARIZONA_FLL1_CTRL_UPD | cfg->n);
 }
 
-static int arizona_is_enabled_fll(struct arizona_fll *fll)
+static int arizona_is_enabled_fll(struct arizona_fll *fll, int base)
 {
struct arizona *arizona = fll->arizona;
unsigned int reg;
int ret;
 
-   ret = regmap_read(arizona->regmap, fll->base + 1, );
+   ret = regmap_read(arizona->regmap, base + 1, );
if (ret != 0) {
arizona_fll_err(fll, "Failed to read current state: %d\n",
ret);
@@ -2208,7 +2208,7 @@ static int arizona_enable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
bool use_sync = false;
-   int already_enabled = arizona_is_enabled_fll(fll);
+   int already_enabled = arizona_is_enabled_fll(fll, fll->base);
struct arizona_fll_cfg cfg;
int i;
unsigned int val;
-- 
2.1.4

Re: [PATCH 2/2] arm64: Use static keys for CPU features

[Catalin Marinas]

On Fri, Aug 26, 2016 at 10:22:13AM +0100, Suzuki K. Poulose wrote:
> On 25/08/16 18:26, Catalin Marinas wrote:
> > static inline int __attribute_const__
> >diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> >index 62272eac1352..919b2d0d68ae 100644
> >--- a/arch/arm64/kernel/cpufeature.c
> >+++ b/arch/arm64/kernel/cpufeature.c
> >@@ -46,6 +46,9 @@ unsigned int compat_elf_hwcap2 __read_mostly;
> >
> > DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
> >
> >+DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
> >+EXPORT_SYMBOL(cpu_hwcap_keys);
> >+
> > #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
> > {   \
> > .sign = SIGNED, \
> >diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> >index ed1b84fe6925..6a141e399daf 100644
> >--- a/arch/arm64/kernel/cpuinfo.c
> >+++ b/arch/arm64/kernel/cpuinfo.c
> >@@ -377,6 +377,12 @@ void cpuinfo_store_cpu(void)
> > void __init cpuinfo_store_boot_cpu(void)
> > {
> > struct cpuinfo_arm64 *info = _cpu(cpu_data, 0);
> >+
> >+/*
> >+ * Initialise the static keys early as they may be enabled by
> >+ * check_local_cpu_errata() -> update_cpu_capabilities().
> >+ */
> >+jump_label_init();
> > __cpuinfo_store_cpu(info);
> 
> Just a heads up. I have a patch [1] which moves the "check_local_cpu_errata()"
> around to smp_prepare_boot_cpu(). This patch should still work fine with that
> case. Only that may be we could move the jump_lable_init() to 
> smp_prepare_boot_cpu(),
> before we call "update_cpu_errata_work_arounds()" for Boot CPU.

IIUC, we wouldn't call update_cpu_errata_work_arounds() until the CPU
feature infrastructure is initialised via cpuinfo_store_boot_cpu(). So
I don't think moving the jump_label_init() call above is necessary.

> [1] 
> https://lkml.kernel.org/r/1471525832-21209-4-git-send-email-suzuki.poul...@arm.com

-- 
Catalin

[PATCH 0/6] Arizona FLL fixes and Clocking Improvements

[Charles Keepax]

Hi,

The first 3 patches in this series fix some small issues with
the FLL configuration in the driver. The second 3 patches add
support for requesting the input clocks for the CODEC through the
clock framework. This is some what of an intermediate step until
all the clocking itself in the CODEC can be brought under the
clock framework but as there are machine drivers that want to be
merged now with source clocks that require gating and difficult
to resolve issues between the SPI and clock framework an
intermediate solution seems warranted.

Whilst the two halfs of this series do fairly different things,
I have sent them as once series as they touch a lot of the same
code, so this seemed the simpler approach to pushing them both
through. The series is based of Mark's ASoC for-next tree.

Thanks,
Charles

Charles Keepax (5):
  ASoC: arizona: Correct handling of FLL theta in synchroniser mode
  ASoC: arizona: Allow specification of base for arizona_is_enabled_fll
  ASoC: arizona: Avoid changing SYNC_ENA whilst the FLL_ENA is set
  ASoC: arizona: Add gating for clock when used for direct MCLK
  ASoC: arizona: Add gating for source clocks of the FLLs

Sylwester Nawrocki (1):
  mfd: arizona: Add gating of external MCLKn clocks

 drivers/mfd/arizona-core.c   |  30 +-
 include/linux/mfd/arizona/core.h |   9 +++
 sound/soc/codecs/arizona.c   | 124 +++
 sound/soc/codecs/arizona.h   |   2 +
 sound/soc/codecs/cs47l24.c   |   6 +-
 sound/soc/codecs/wm5102.c|   9 ++-
 sound/soc/codecs/wm5110.c|  10 +++-
 sound/soc/codecs/wm8997.c|   9 ++-
 sound/soc/codecs/wm8998.c|   6 +-
 9 files changed, 179 insertions(+), 26 deletions(-)

-- 
2.1.4

Re: [PATCH] usb: dwc3: host: inherit dma configuration from parent dev

[Arnd Bergmann]

On Friday, September 2, 2016 10:21:23 AM CEST Alan Stern wrote:
> On Fri, 2 Sep 2016, Felipe Balbi wrote:
> 
> > Hi,
> > 
> > Russell King - ARM Linux  writes:
> > > On Fri, Sep 02, 2016 at 12:43:39PM +0200, Arnd Bergmann wrote:
> > >> On Thursday, September 1, 2016 5:14:28 PM CEST Leo Li wrote:
> > >> > 
> > >> > Hi Felipe and Arnd,
> > >> > 
> > >> > It has been a while since the last response to this discussion, but we
> > >> > haven't reached an agreement yet!  Can we get to a conclusion on if it
> > >> > is valid to create child platform device for abstraction purpose?  If
> > >> > yes, can this child device do DMA by itself?
> > >> 
> > >> I'd say it's no problem for a driver to create child devices in order
> > >> to represent different aspects of a device, but you should not rely on
> > >> those devices working when used with the dma-mapping interfaces.
> > >
> > > That's absolutely right.  Consider the USB model - only the USB host
> > > controller can perform DMA, not the USB devices themselves.  All DMA
> > > mappings need to be mapped using the USB host controller device struct
> > > not the USB device struct.
> > >
> > > The same _should_ be true everywhere else: the struct device representing
> > > the device performing DMA must be the one used to map the transfer.
> > 
> > How do we fix dwc3 in dual-role, then?
> > 
> > Peripheral-side dwc3 is easy, we just require a glue-layer to be present
> > and use dwc3.ko's parent device (which will be the PCI device or OF
> > device). But for host side dwc3, the problem is slightly more complex
> > because we're using xhci-plat.ko by just instantiating a xhci-platform
> > device so xhci-plat can probe.
> > 
> > xhci core has no means to know if its own device or the parent of its
> > parent should be used for DMA. Any ideas?
> 
> In theory, you can store a flag somewhere in the platform device,
> something that would tell xhci-hcd that it has to use the parent's
> parent for DMA purposes.
> 
> I know it would be somewhat of a hack, but ought to work.

Speaking of that flag, I suppose we need the same logic to know where
to look for USB devices attached to a dwc3 host when we need to describe
them in DT. By default we look for child device nodes under the
node of the HCD device node, but that would be wrong here too.

Arnd 

[PATCH v2 10/15] Group related CSR definitions together.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |  148 +++---
 1 file changed, 74 insertions(+), 74 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 6edfce5..fe1b52f 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -37,21 +37,27 @@
 #include 
 #include 
 
-#define PCIE_CLIENT_BASE   0x0
-#define PCIE_RC_CONFIG_BASE0xa0
-#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   (PCIE_RC_CONFIG_BASE + 0x90c)
-#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0x0d0)
-#define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
-#define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
-#define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
-#define  PCIE_RC_CONFIG_LCS_LBMS   BIT(30)
-#define  PCIE_RC_CONFIG_LCS_LAMS   BIT(31)
-#define PCIE_CORE_CTRL_MGMT_BASE   0x90
-#define PCIE_CORE_AXI_CONF_BASE0xc0
-#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
-#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
-#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
+/*
+ * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16
+ * bits.  This allows atomic updates of the register without locking.
+ */
+#define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
+
+#define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
+
+#define PCIE_CLIENT_BASE   0x0
+#define  PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE(0x0001, 0x0001)
+#define  PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE(0x0002, 0x0002)
+#define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
+#define  PCIE_CLIENT_GEN_SEL_2   HIWORD_UPDATE(0x0040, 0x0040)
+#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
+#define  PCIE_CLIENT_LINK_STATUS_UP0x3
+#define  PCIE_CLIENT_LINK_STATUS_SHIFT 20
+#define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
+#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
+#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
+#define  ROCKCHIP_PCIE_RPIFR1_INTR_MASKGENMASK(8, 5)
+#define  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT   5
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -68,18 +74,25 @@
 #define  PCIE_CLIENT_INT_PHY   BIT(2)
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
-#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
-#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 
0x300)
-#define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
-#define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
-#define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
-#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
-#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
-#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 
0x4)
-#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 
0x210)
-#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 
0x20c)
+
+#define PCIE_CLIENT_INT_LEGACY \
+   (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
+   PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
+
+#define PCIE_CLIENT_INT_CLI \
+   (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
+   PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
+   PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
+   PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
+   PCIE_CLIENT_INT_PHY)
+
+#define PCIE_CORE_CTRL_MGMT_BASE   0x90
+#define  PCIE_CORE_PL_CONF_SPEED_5G0x1
+#define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
+#define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
+#define  PCIE_CORE_PL_CONF_LANE_SHIFT  1
+#define  PCIE_CORE_PL_CONF_LANE_MASK   0x3
+#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
 #define  PCIE_CORE_INT_RRPEBIT(2)
@@ -94,6 +107,40 @@
 #define  PCIE_CORE_INT_CT  BIT(11)
 #define  PCIE_CORE_INT_UTC BIT(18)
 #define  PCIE_CORE_INT_MMVCBIT(19)
+#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
+#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
+

Re: [PATCH] genirq: Generic chip: verify irqs_per_chip <= 32

[Thomas Gleixner]

On Tue, 16 Aug 2016, Sebastian Frias wrote:
> Most (if not all) code here implicitly assumes that the maximum number of
> IRQs per chip will be 32, and thus uses 'u32' or 'unsigned long' for many
> tasks (for example "struct irq_data" declares its 'mask' field as 'u32',
> and "struct irq_chip_generic" declares its 'installed' field as 'unsigned
> long')
> 
> However, there is no check to verify that irqs_per_chip is <= 32.
> Hence, calling irq_alloc_domain_generic_chips() with a bigger value would
> result in unexpected results depending on how the 'mask' is accessed later
> on.
> For example, if set_bit() is used on the 'installed' field of "struct
> irq_chip_generic", it would result in the next field (in this case
> the 'unused' field) being overwritten, because set_bit() is designed to
> treat its parameter as a field of bits of arbitrary size organised as
> "unsigned long" words.

We really do not need examples for the potential wreckage. Your explanation
that the code has implict assumptions about the maximum number of
interrupts per chip is sufficient. We all know what out of bound access can
cause.

> This patch renames irq_alloc_domain_generic_chips() to
> __irq_alloc_domain_generic_chips() and creates a macro to replace it.
> The macro uses MAYBE_BUILD_BUG_ON to check the irqs_per_chip parameter to
> stop compilation (if the compiler can resolve the parameter to a constant
> at compile time) or to warn during run-time, if the parameter given is
> bigger than 32.

There is no point in explaining the implementation in the changelog. It's
obvious from the patch itself.

I'll fix that up as well.

Thanks,

tglx

[PATCH v2 05/15] Use a local "dev" to avoid repetition of "rockchip->dev".

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   98 --
 1 file changed, 51 insertions(+), 47 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 63fb0ebc..ea75f35 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -380,6 +380,7 @@ static struct pci_ops rockchip_pcie_ops = {
  */
 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 {
+   struct device *dev = rockchip->dev;
int err;
u32 status;
unsigned long timeout;
@@ -388,31 +389,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
err = phy_init(rockchip->phy);
if (err < 0) {
-   dev_err(rockchip->dev, "fail to init phy, err %d\n", err);
+   dev_err(dev, "fail to init phy, err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->core_rst);
if (err) {
-   dev_err(rockchip->dev, "assert core_rst err %d\n", err);
+   dev_err(dev, "assert core_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
-   dev_err(rockchip->dev, "assert mgmt_rst err %d\n", err);
+   dev_err(dev, "assert mgmt_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
-   dev_err(rockchip->dev, "assert mgmt_sticky_rst err %d\n", err);
+   dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
return err;
}
 
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
-   dev_err(rockchip->dev, "assert pipe_rst err %d\n", err);
+   dev_err(dev, "assert pipe_rst err %d\n", err);
return err;
}
 
@@ -436,31 +437,31 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
err = phy_power_on(rockchip->phy);
if (err) {
-   dev_err(rockchip->dev, "fail to power on phy, err %d\n", err);
+   dev_err(dev, "fail to power on phy, err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->core_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert core_rst err %d\n", err);
+   dev_err(dev, "deassert core_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert mgmt_rst err %d\n", err);
+   dev_err(dev, "deassert mgmt_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert mgmt_sticky_rst err %d\n", 
err);
+   dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
return err;
}
 
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
-   dev_err(rockchip->dev, "deassert pipe_rst err %d\n", err);
+   dev_err(dev, "deassert pipe_rst err %d\n", err);
return err;
}
 
@@ -492,7 +493,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
  PCIE_CLIENT_LINK_STATUS_MASK) ==
  PCIE_CLIENT_LINK_STATUS_UP) {
-   dev_dbg(rockchip->dev, "PCIe link training gen1 
pass!\n");
+   dev_dbg(dev, "PCIe link training gen1 pass!\n");
break;
}
 
@@ -511,7 +512,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CLIENT_LINK_STATUS_MASK) ==
PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
if (err) {
-   dev_err(rockchip->dev, "PCIe link training gen1 
timeout!\n");
+   dev_err(dev, "PCIe link training gen1 timeout!\n");
return err;
}
}
@@ -532,7 +533,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 PCIE_CORE_PL_CONF_SPEED_MASK) ==
 PCIE_CORE_PL_CONF_SPEED_5G) {
-   dev_dbg(rockchip->dev, "PCIe link training gen2 
pass!\n");
+   dev_dbg(dev, "PCIe link training gen2 pass!\n");
break;
}
 
@@ -551,14 +552,14 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CORE_PL_CONF_SPEED_MASK) ==
PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
if (err)
-   

Re: [2/2] ath10k: use complete() instead complete_all()

[Kalle Valo]

Daniel Wagner  wrote:
> From: Daniel Wagner 
> 
> There is only one waiter for the completion, therefore there
> is no need to use complete_all(). Let's make that clear by
> using complete() instead of complete_all().
> 
> The usage pattern of the completion is:
> 
> waiter context  waker context
> 
> scan.started
> 
> 
> ath10k_start_scan()
>   lockdep_assert_held(conf_mutex)
>   auth10k_wmi_start_scan()
>   wait_for_completion_timeout(scan.started)
> 
>   ath10k_wmi_event_scan_start_failed()
> complete(scan.started)
> 
>   ath10k_wmi_event_scan_started()
> complete(scan.started)
> 
> scan.completed
> --
> 
> ath10k_scan_stop()
>   lockdep_assert_held(conf_mutex)
>   ath10k_wmi_stop_scan()
>   wait_for_completion_timeout(scan.completed)
> 
>   __ath10k_scan_finish()
> complete(scan.completed)
> 
> scan.on_channel
> ---
> 
> ath10k_remain_on_channel()
>   mutex_lock(conf_mutex)
>   ath10k_start_scan()
>   wait_for_completion_timeout(scan.on_channel)
> 
>   ath10k_wmi_event_scan_foreign_chan()
> complete(scan.on_channel)
> 
> offchan_tx_completed
> 
> 
> ath10k_offchan_tx_work()
>   mutex_lock(conf_mutex)
>   reinit_completion(offchan_tx_completed)
>   wait_for_completion_timeout(offchan_tx_completed)
> 
>   ath10k_report_offchain_tx()
> complete(offchan_tx_completed)
> 
> install_key_done
> 
> ath10k_install_key()
>   lockep_assert_held(conf_mutex)
>   reinit_completion(install_key_done)
>   wait_for_completion_timeout(install_key_done)
> 
>   ath10k_htt_t2h_msg_handler()
> complete(install_key_done)
> 
> vdev_setup_done
> ---
> 
> ath10k_monitor_vdev_start()
>   lockdep_assert_held(conf_mutex)
>reinit_completion(vdev_setup_done)
>   ath10k_vdev_setup_sync()
> wait_for_completion_timeout(vdev_setup_done)
> 
>   ath10k_wmi_event_vdev_start_resp()
> complete(vdev_setup_done)
> 
> ath10k_monitor_vdev_stop()
>   lockdep_assert_held(conf_mutex)
>   reinit_completion(vdev_setup_done()
>   ath10k_vdev_setup_sync()
> wait_for_completion_timeout(vdev_setup_done)
> 
>   ath10k_wmi_event_vdev_stopped()
>complete(vdev_setup_done)
> 
> thermal.wmi_sync
> 
> ath10k_thermal_show_temp()
>   mutex_lock(conf_mutex)
>   reinit_completion(thermal.wmi_sync)
>   wait_for_completion_timeout(thermal.wmi_sync)
> 
>   ath10k_thermal_event_temperature()
> complete(thermal.wmi_sync)
> 
> bss_survey_done
> ---
> ath10k_mac_update_bss_chan_survey
>   lockdep_assert_held(conf_mutex)
>   reinit_completion(bss_survey_done)
>   wait_for_completion_timeout(bss_survey_done)
> 
>   ath10k_wmi_event_pdev_bss_chan_info()
> complete(bss_survey_done)
> 
> All complete() calls happen while the conf_mutex is taken. That means
> at max one waiter is possible.
> 
> Signed-off-by: Daniel Wagner 

Thanks, 1 patch applied to ath-next branch of ath.git:

881ed54ecc13 ath10k: use complete() instead complete_all()

-- 
Sent by pwcli
https://patchwork.kernel.org/patch/9287731/

[PATCH 10/12] MIPS: Malta: Remove custom halt implementation

[Paul Burton]

The arch code will hang the machine with an infinite loop if the board
doesn't provide an impelementation of halt - let it, rather than
duplicating it.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-reset.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/arch/mips/mti-malta/malta-reset.c 
b/arch/mips/mti-malta/malta-reset.c
index 04d6b9c..dd6f62a 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -13,11 +13,6 @@
 #include 
 #include 
 
-static void mips_machine_halt(void)
-{
-   while (true);
-}
-
 static void mips_machine_power_off(void)
 {
mips_pm_suspend(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF);
@@ -28,7 +23,6 @@ static void mips_machine_power_off(void)
 
 static int __init mips_reboot_setup(void)
 {
-   _machine_halt = mips_machine_halt;
pm_power_off = mips_machine_power_off;
 
return 0;
-- 
2.9.3

[PATCH 11/12] power: reset: Add Intel PIIX4 poweroff driver

[Paul Burton]

Add a driver which allows powering off the system via an Intel PIIX4
southbridge, by entering the PIIX4 SOff state. This is useful on the
MIPS Malta development board, where it will power down the FPGA based
board until its ON/NMI button is pressed, or the QEMU implementation of
the MIPS Malta board where it will cause QEMU to exit.

Signed-off-by: Paul Burton 
---

 drivers/power/reset/Kconfig  |   9 +++
 drivers/power/reset/Makefile |   1 +
 drivers/power/reset/piix4-poweroff.c | 103 +++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/power/reset/piix4-poweroff.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index c74c3f6..b27ca50 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -104,6 +104,15 @@ config POWER_RESET_MSM
help
  Power off and restart support for Qualcomm boards.
 
+config POWER_RESET_PIIX4_POWEROFF
+   tristate "Intel PIIX4 power-off driver"
+   depends on MIPS && PCI
+   help
+ This driver supports powering off a system using the Intel PIIX4
+ southbridge, for example the MIPS Malta development board. The
+ southbridge SOff state is entered in response to a request to
+ power off the system.
+
 config POWER_RESET_LTC2952
bool "LTC2952 PowerPath power-off driver"
depends on OF_GPIO
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 1be307c..11dae3b 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
 obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
 obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
 obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
+obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
diff --git a/drivers/power/reset/piix4-poweroff.c 
b/drivers/power/reset/piix4-poweroff.c
new file mode 100644
index 000..bfa8bea
--- /dev/null
+++ b/drivers/power/reset/piix4-poweroff.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct pci_dev *pm_dev;
+static resource_size_t io_offset;
+
+enum piix4_pm_io_reg {
+   PIIX4_FUNC3IO_PMSTS = 0x00,
+#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS BIT(8)
+   PIIX4_FUNC3IO_PMCNTRL   = 0x04,
+#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN   BIT(13)
+#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10)
+};
+
+#define PIIX4_SUSPEND_MAGIC0x00120002
+
+static void piix4_poweroff(void)
+{
+   int spec_devid;
+   u16 sts;
+
+   /* Ensure the power button status is clear */
+   while (1) {
+   sts = inw(io_offset + PIIX4_FUNC3IO_PMSTS);
+   if (!(sts & PIIX4_FUNC3IO_PMSTS_PWRBTN_STS))
+   break;
+   outw(sts, io_offset + PIIX4_FUNC3IO_PMSTS);
+   }
+
+   /* Enable entry to suspend */
+   outw(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF | PIIX4_FUNC3IO_PMCNTRL_SUS_EN,
+io_offset + PIIX4_FUNC3IO_PMCNTRL);
+
+   /* If the special cycle occurs too soon this doesn't work... */
+   mdelay(10);
+
+   /*
+* The PIIX4 will enter the suspend state only after seeing a special
+* cycle with the correct magic data on the PCI bus. Generate that
+* cycle now.
+*/
+   spec_devid = PCI_DEVID(0, PCI_DEVFN(0x1f, 0x7));
+   pci_bus_write_config_dword(pm_dev->bus, spec_devid, 0,
+  PIIX4_SUSPEND_MAGIC);
+
+   /* Give the system some time to power down, then error */
+   mdelay(1000);
+   pr_emerg("Unable to poweroff system\n");
+}
+
+static int piix4_poweroff_probe(struct pci_dev *dev,
+   const struct pci_device_id *id)
+{
+   int res, io_region = PCI_BRIDGE_RESOURCES;
+
+   /* Request access to the PIIX4 PM IO registers */
+   res = pci_request_region(dev, io_region, "PIIX4 PM IO registers");
+   if (res) {
+   dev_err(>dev, "failed to request PM IO registers: %d\n",
+   res);
+   return res;
+   }
+
+   pm_dev = dev;
+   io_offset = pci_resource_start(dev, io_region);
+   pm_power_off = piix4_poweroff;
+
+   return 0;
+}
+
+static void piix4_poweroff_remove(struct pci_dev *dev)
+{
+   if (pm_power_off == 

[PATCH v2 02/15] Rename pcie_read() and pcie_write() to rockchip_pcie_read() and

[Bjorn Helgaas]

rockchip_pcie_write().
---
 drivers/pci/host/pcie-rockchip.c |   66 +++---
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a7006be..c9d0799 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,12 +200,12 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
 {
return readl(port->apb_base + reg);
 }
 
-static inline void pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
 {
writel(val, port->apb_base + reg);
 }
@@ -214,18 +214,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie_port *port)
 {
u32 status;
 
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
 {
u32 status;
 
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
 static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
@@ -417,7 +417,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
return err;
}
 
-   pcie_write(port,
+   rockchip_pcie_write(port,
   HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
 PCIE_CLIENT_CONF_ENABLE_MASK,
 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
@@ -471,13 +471,13 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 * reliable and enabling ASPM doesn't work.  This is a controller
 * bug we need to work around.
 */
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE +
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE +
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE +
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE +
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
/* Enable Gen1 training */
-   pcie_write(port,
+   rockchip_pcie_write(port,
   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
 PCIE_CLIENT_LINK_TRAIN_MASK,
 PCIE_CLIENT_LINK_TRAIN_SHIFT),
@@ -489,7 +489,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
timeout = jiffies + msecs_to_jiffies(500);
 
for (;;) {
-   status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+   status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
  PCIE_CLIENT_LINK_STATUS_MASK) ==
  PCIE_CLIENT_LINK_STATUS_UP) {
@@ -507,7 +507,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 
/* Double check gen1 training */
if (err) {
-   status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+   status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
PCIE_CLIENT_LINK_STATUS_MASK) ==
PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
@@ -521,15 +521,15 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 * Enable retrain for gen2. This should be configured only after
 * gen1 finished.
 */
-   status = pcie_read(port,
+   status = rockchip_pcie_read(port,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
status |= PCIE_CORE_LCSR_RETRAIN_LINK;
-   pcie_write(port, status,
+   rockchip_pcie_write(port, status,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
-   status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &

Re: [PATCH v2] mfd: arizona: Add DT options for max_channels_clocked and PDM speaker config

[Richard Fitzgerald]

On Fri, 2016-09-02 at 10:34 -0500, Rob Herring wrote:
> On Wed, Aug 31, 2016 at 10:25:43AM +0100, Richard Fitzgerald wrote:
> > This patch adds DT settings for the max_channels_clocked, spk_fmt and
> > spk_mute pdata.
> > 
> > Signed-off-by: Richard Fitzgerald 
> > ---
> >  Documentation/devicetree/bindings/mfd/arizona.txt | 11 
> 
> Binding looks fine, but...
> 
> >  drivers/mfd/arizona-core.c| 31 
> > +++
> >  2 files changed, 42 insertions(+)
> 
> > diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
> > index b95ff2d..36a9633 100644
> > --- a/drivers/mfd/arizona-core.c
> > +++ b/drivers/mfd/arizona-core.c
> > @@ -816,6 +816,37 @@ static int arizona_of_get_core_pdata(struct arizona 
> > *arizona)
> > count++;
> > }
> >  
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node,
> > +"wlf,max-channels-clocked",
> > +prop, cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->max_channels_clocked))
> > +   break;
> > +
> > +   pdata->max_channels_clocked[count] = val;
> > +   count++;
> > +   }
> 
> of_property_read_u32_array doesn't work for you?

No, it doesn't, because it doesn't read a variable-sized array.

> 
> > +
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node, "wlf,spk-fmt", prop,
> > +cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->spk_fmt))
> > +   break;
> > +
> > +   pdata->spk_fmt[count] = val;
> > +   count++;
> > +   }
> > +
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node, "wlf,spk-mute", prop,
> > +cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->spk_mute))
> > +   break;
> > +
> > +   pdata->spk_mute[count] = val;
> > +   count++;
> > +   }
> > +
> > return 0;
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majord...@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 11/15] Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index fe1b52f..88c16da 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -121,7 +121,7 @@
 
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
-#define  PCIE_CORE_RC_CONF_SCC_SHIFT   16
+#define  PCIE_RC_CONFIG_SCC_SHIFT  16
 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
 #define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
 #define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
@@ -545,7 +545,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
PCIE_RC_CONFIG_BASE);
rockchip_pcie_write(rockchip,
-   PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
+   PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
PCIE_RC_CONFIG_RID_CCR);
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 

[PATCH 08/12] MIPS: Malta: Probe pflash via DT

[Paul Burton]

Add the DT nodes required to probe the CFI compatible parallel monitor
flash found on the Malta development board, and remove the platform
code that was previously doing it. Delete the now-empty malta-platform.c
file. Adjust the Malta defconfigs that enable MTD & the pflash/CFI
driver to enable CONFIG_MTD_PHYSMAP_OF rather than CONFIG_MTD_PHYSMAP in
order to preserve their behaviour.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts| 25 
 arch/mips/configs/malta_defconfig   |  2 +-
 arch/mips/configs/malta_kvm_defconfig   |  2 +-
 arch/mips/configs/malta_kvm_guest_defconfig |  2 +-
 arch/mips/configs/maltaup_xpa_defconfig |  2 +-
 arch/mips/mti-malta/Makefile|  1 -
 arch/mips/mti-malta/malta-platform.c| 44 -
 7 files changed, 29 insertions(+), 49 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index ee43296..2e594ec 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -50,6 +50,31 @@
interrupts = ;
};
 
+   pflash@1e00 {
+   compatible = "intel,dt28f160", "cfi-flash";
+   reg = <0x1e00 0x40>;
+   bank-width = <4>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   yamon@0 {
+   label = "YAMON";
+   reg = <0x0 0x10>;
+   read-only;
+   };
+
+   user-fs@10 {
+   label = "User FS";
+   reg = <0x10 0x2e>;
+   };
+
+   board-config@3e {
+   label = "Board Config";
+   reg = <0x3e 0x2>;
+   read-only;
+   };
+   };
+
isa {
compatible = "isa";
#address-cells = <2>;
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index 5afb484..d5d4816 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -230,7 +230,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index 98f1387..ef6ef24 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -235,7 +235,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index 3b5d591..3a49a77 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -234,7 +234,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/maltaup_xpa_defconfig 
b/arch/mips/configs/maltaup_xpa_defconfig
index 7322157..62e05eb 100644
--- a/arch/mips/configs/maltaup_xpa_defconfig
+++ b/arch/mips/configs/maltaup_xpa_defconfig
@@ -231,7 +231,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 5827af7..0407774 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -11,7 +11,6 @@ obj-y += malta-dtshim.o
 obj-y  += malta-init.o
 obj-y  += malta-int.o
 obj-y  += malta-memory.o
-obj-y  += malta-platform.o
 obj-y  += malta-reset.o
 obj-y  += malta-setup.o
 obj-y  += malta-time.o
diff --git a/arch/mips/mti-malta/malta-platform.c 
b/arch/mips/mti-malta/malta-platform.c
index 6433a39..cc67dbf 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -25,11 +25,8 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
-#include 
 
 #define SMC_PORT(base, int)\
 {  \
@@ -67,49 +64,8 @@ static struct platform_device malta_uart8250_device = {
},
 };
 
-static struct mtd_partition malta_mtd_partitions[] = {
-   {
-   .name = 

[PATCH 07/12] MIPS: Malta: Probe RTC via DT

[Paul Burton]

Add the DT node required to probe the RTC, and remove the platform code
that was previously doing it.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts | 15 +++
 arch/mips/mti-malta/malta-platform.c | 21 -
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index af765af..ee43296 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -49,4 +49,19 @@
interrupt-parent = <>;
interrupts = ;
};
+
+   isa {
+   compatible = "isa";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   ranges = <1 0 0 0x1000>;
+
+   rtc: mc146818@70 {
+   compatible = "motorola,mc146818";
+   reg = <1 0x70 0x8>;
+
+   interrupt-parent = <>;
+   interrupts = <8>;
+   };
+   };
 };
diff --git a/arch/mips/mti-malta/malta-platform.c 
b/arch/mips/mti-malta/malta-platform.c
index e1dd1c1..6433a39 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -23,7 +23,6 @@
  */
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -68,25 +67,6 @@ static struct platform_device malta_uart8250_device = {
},
 };
 
-struct resource malta_rtc_resources[] = {
-   {
-   .start  = RTC_PORT(0),
-   .end= RTC_PORT(7),
-   .flags  = IORESOURCE_IO,
-   }, {
-   .start  = RTC_IRQ,
-   .end= RTC_IRQ,
-   .flags  = IORESOURCE_IRQ,
-   }
-};
-
-static struct platform_device malta_rtc_device = {
-   .name   = "rtc_cmos",
-   .id = -1,
-   .resource   = malta_rtc_resources,
-   .num_resources  = ARRAY_SIZE(malta_rtc_resources),
-};
-
 static struct mtd_partition malta_mtd_partitions[] = {
{
.name = "YAMON",
@@ -129,7 +109,6 @@ static struct platform_device malta_flash_device = {
 
 static struct platform_device *malta_devices[] __initdata = {
_uart8250_device,
-   _rtc_device,
_flash_device,
 };
 
-- 
2.9.3

[PATCH v2 08/15] Remove duplicate CSR definition.

[Bjorn Helgaas]

PCIE_RC_CONFIG_LCSR was the same as PCIE_RC_CONFIG_LCS.  Kept
PCIE_RC_CONFIG_LCS.

PCIE_CORE_LCSR_RETRAIN_LINK was inexplicably named differently and defined
separately.
---
 drivers/pci/host/pcie-rockchip.c |   27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index b204567..a2dd196 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -40,11 +40,12 @@
 #define PCIE_CLIENT_BASE   0x0
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
-#define PCIE_RC_CONFIG_LCSR0xd0
-#define  PCIE_RC_CONFIG_LCSR_LBMIE BIT(10)
-#define  PCIE_RC_CONFIG_LCSR_LABIE BIT(11)
-#define  PCIE_RC_CONFIG_LCSR_LBMS  BIT(30)
-#define  PCIE_RC_CONFIG_LCSR_LAMS  BIT(31)
+#define PCIE_RC_CONFIG_LCS 0xd0
+#define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
+#define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
+#define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
+#define  PCIE_RC_CONFIG_LCS_LBMS   BIT(30)
+#define  PCIE_RC_CONFIG_LCS_LAMS   BIT(31)
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_AXI_CONF_BASE0xc0
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
@@ -68,7 +69,6 @@
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
 #define PCIE_RC_CONFIG_RID_CCR 0x8
-#define PCIE_RC_CONFIG_LCS 0xd0
 #define PCIE_RC_BAR_CONF   0x300
 #define PCIE_CORE_OB_REGION_ADDR1  0x4
 #define PCIE_CORE_OB_REGION_DESC0  0x8
@@ -119,7 +119,6 @@
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
-#define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
 
 /*
  * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the
@@ -204,18 +203,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
-   status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
-   status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
 }
 
 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
@@ -506,7 +505,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 */
status = rockchip_pcie_read(rockchip,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
-   status |= PCIE_CORE_LCSR_RETRAIN_LINK;
+   status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
rockchip_pcie_write(rockchip, status,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 

[PATCH 12/12] MIPS: Malta: Use PIIX4 poweroff driver to power down

[Paul Burton]

Remove the platform code used to power down the system, instead relying
upon the new PIIX4 poweroff driver. This reduces the amount of platform
code required for the Malta board in preparation for allowing it to be
part of a more generic kernel.

Signed-off-by: Paul Burton 

---

 arch/mips/Kconfig   |  6 --
 arch/mips/configs/malta_defconfig   |  1 +
 arch/mips/configs/malta_kvm_defconfig   |  1 +
 arch/mips/configs/malta_kvm_guest_defconfig |  1 +
 arch/mips/configs/malta_qemu_32r6_defconfig |  1 +
 arch/mips/configs/maltaaprp_defconfig   |  1 +
 arch/mips/configs/maltasmvp_defconfig   |  1 +
 arch/mips/configs/maltasmvp_eva_defconfig   |  1 +
 arch/mips/configs/maltaup_defconfig |  1 +
 arch/mips/configs/maltaup_xpa_defconfig |  1 +
 arch/mips/mti-malta/Makefile|  2 -
 arch/mips/mti-malta/malta-pm.c  | 96 -
 arch/mips/mti-malta/malta-reset.c   | 30 -
 13 files changed, 9 insertions(+), 134 deletions(-)
 delete mode 100644 arch/mips/mti-malta/malta-pm.c
 delete mode 100644 arch/mips/mti-malta/malta-reset.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d875a5a..40e4b5d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1948,12 +1948,6 @@ config SYS_HAS_CPU_XLR
 config SYS_HAS_CPU_XLP
bool
 
-config MIPS_MALTA_PM
-   depends on MIPS_MALTA
-   depends on PCI
-   bool
-   default y
-
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index 58d43f3..f785767 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -319,6 +319,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index c8f7e28..fe1b941 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -332,6 +332,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index d2f54e5..a4ad822 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -332,6 +332,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig 
b/arch/mips/configs/malta_qemu_32r6_defconfig
index cbf37dd..e284b3d 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltaaprp_defconfig 
b/arch/mips/configs/maltaaprp_defconfig
index 35f6ba2..73dca90 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltasmvp_defconfig 
b/arch/mips/configs/maltasmvp_defconfig
index 900f145..b5ae55b 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -135,6 +135,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig 
b/arch/mips/configs/maltasmvp_eva_defconfig
index 8e2738b..c3c059c8 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -138,6 +138,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltaup_defconfig 
b/arch/mips/configs/maltaup_defconfig
index 6dc4e30..28749b5 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -132,6 +132,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 

[PATCH 6/6] ASoC: arizona: Add gating for source clocks of the FLLs

[Charles Keepax]

Whilst ultimately we would like to move all the clocking over to the
clock framework, as an intermediate step to get people going for now
enable the source clocks for FLLs as they are powered up.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 60 +-
 1 file changed, 54 insertions(+), 6 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index 2a019e9..780cf4f 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2244,6 +2244,42 @@ static int arizona_is_enabled_fll(struct arizona_fll 
*fll, int base)
return reg & ARIZONA_FLL1_ENA;
 }
 
+static int arizona_set_fll_clks(struct arizona_fll *fll, int base, bool ena)
+{
+   struct arizona *arizona = fll->arizona;
+   unsigned int val;
+   struct clk *clk;
+   int ret;
+
+   ret = regmap_read(arizona->regmap, base + 6, );
+   if (ret != 0) {
+   arizona_fll_err(fll, "Failed to read current source: %d\n",
+   ret);
+   return ret;
+   }
+
+   val &= ARIZONA_FLL1_CLK_REF_SRC_MASK;
+   val >>= ARIZONA_FLL1_CLK_REF_SRC_SHIFT;
+
+   switch (val) {
+   case ARIZONA_FLL_SRC_MCLK1:
+   clk = arizona->mclk[ARIZONA_MCLK1];
+   break;
+   case ARIZONA_FLL_SRC_MCLK2:
+   clk = arizona->mclk[ARIZONA_MCLK2];
+   break;
+   default:
+   return 0;
+   }
+
+   if (ena) {
+   return clk_prepare_enable(clk);
+   } else {
+   clk_disable_unprepare(clk);
+   return 0;
+   }
+}
+
 static int arizona_enable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
@@ -2266,6 +2302,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
udelay(32);
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
 ARIZONA_FLL1_GAIN_MASK, 0);
+
+   if (arizona_is_enabled_fll(fll, fll->base + 0x10) > 0)
+   arizona_set_fll_clks(fll, fll->base + 0x10, false);
+   arizona_set_fll_clks(fll, fll->base, false);
}
 
/*
@@ -2320,10 +2360,13 @@ static int arizona_enable_fll(struct arizona_fll *fll)
if (!already_enabled)
pm_runtime_get_sync(arizona->dev);
 
-   if (use_sync)
+   if (use_sync) {
+   arizona_set_fll_clks(fll, fll->base + 0x10, true);
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
 ARIZONA_FLL1_SYNC_ENA,
 ARIZONA_FLL1_SYNC_ENA);
+   }
+   arizona_set_fll_clks(fll, fll->base, true);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
 
@@ -2356,19 +2399,24 @@ static int arizona_enable_fll(struct arizona_fll *fll)
 static void arizona_disable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
-   bool change;
+   bool ref_change, sync_change;
 
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
regmap_update_bits_check(arizona->regmap, fll->base + 1,
-ARIZONA_FLL1_ENA, 0, );
-   regmap_update_bits(arizona->regmap, fll->base + 0x11,
-  ARIZONA_FLL1_SYNC_ENA, 0);
+ARIZONA_FLL1_ENA, 0, _change);
+   regmap_update_bits_check(arizona->regmap, fll->base + 0x11,
+ARIZONA_FLL1_SYNC_ENA, 0, _change);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_FREERUN, 0);
 
-   if (change)
+   if (sync_change)
+   arizona_set_fll_clks(fll, fll->base + 0x10, false);
+
+   if (ref_change) {
+   arizona_set_fll_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(arizona->dev);
+   }
 }
 
 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
-- 
2.1.4

[PATCH v2 00/15] PCI: rockchip: Cleanups against v10

[Bjorn Helgaas]

These are cleanups against 2098142ae87d, the current pci/host-rockchip
head in my tree.

Changes from v1:

  - Rework HIWORD_UPDATE
  - Remove duplicate CSR definitions
  - Move CSR block offset from read/write caller to CSR definition
  - Organize CSRs into logical blocks
  - Fix some inconsistent CSR names
  - Add names for registers at the base of CSR blocks

I was disappointed to find how disorganized the v10 CSR definitions were.
It was quite a hodgepodge.  I should have noticed that earlier, but as
penance, I tried to clean it up myself.

These are in git as pci/host-rockchip-wip.  Again, I intend to squash these
all into the single commit that adds the driver when I finally merge it.

---

Bjorn Helgaas (15):
  Remove unused symbols, unnecessary parens, other minor comments from
  Rename pcie_read() and pcie_write() to rockchip_pcie_read() and
  Always use "rockchip" as the pointer to per-device struct.
  Rename struct rockchip_pcie_port to struct rockchip_pcie.
  Use a local "dev" to avoid repetition of "rockchip->dev".
  Add comment about why 32-bit read/modify/write isn't safe.
  Simplify the confusing HIWORD_UPDATE scheme.
  Remove duplicate CSR definition.
  Move CSR bases into definition.
  Group related CSR definitions together.
  Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions.
  Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT
  The register at PCIE_CLIENT_BASE presumably has a name of its own.  Add a
  Simplify testing of link status and speed testing.
  Move msleeps to address Guenter's comments.


 drivers/pci/host/pcie-rockchip.c |  842 ++
 1 file changed, 391 insertions(+), 451 deletions(-)

[PATCH 3/6] ASoC: arizona: Avoid changing SYNC_ENA whilst the FLL_ENA is set

[Charles Keepax]

For best performance changing the synchroniser state whilst the FLL is
running should be avoided. As this has been done fairly regularly in
practice rather than hard preventing this, simply improve the FLL enable
sequence and give a warning if the user changes the synchroniser state.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index 463979f4..be24387 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2209,12 +2209,15 @@ static int arizona_enable_fll(struct arizona_fll *fll)
struct arizona *arizona = fll->arizona;
bool use_sync = false;
int already_enabled = arizona_is_enabled_fll(fll, fll->base);
+   int sync_enabled = arizona_is_enabled_fll(fll, fll->base + 0x10);
struct arizona_fll_cfg cfg;
int i;
unsigned int val;
 
if (already_enabled < 0)
return already_enabled;
+   if (sync_enabled < 0)
+   return sync_enabled;
 
if (already_enabled) {
/* Facilitate smooth refclk across the transition */
@@ -2259,6 +2262,9 @@ static int arizona_enable_fll(struct arizona_fll *fll)
return -EINVAL;
}
 
+   if (already_enabled && !!sync_enabled != use_sync)
+   arizona_fll_warn(fll, "Synchroniser changed on active FLL\n");
+
/*
 * Increase the bandwidth if we're not using a low frequency
 * sync source.
@@ -2274,12 +2280,12 @@ static int arizona_enable_fll(struct arizona_fll *fll)
if (!already_enabled)
pm_runtime_get_sync(arizona->dev);
 
-   regmap_update_bits_async(arizona->regmap, fll->base + 1,
-ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
if (use_sync)
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
 ARIZONA_FLL1_SYNC_ENA,
 ARIZONA_FLL1_SYNC_ENA);
+   regmap_update_bits_async(arizona->regmap, fll->base + 1,
+ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
 
if (already_enabled)
regmap_update_bits_async(arizona->regmap, fll->base + 1,
-- 
2.1.4

[PATCH v2 13/15] The register at PCIE_CLIENT_BASE presumably has a name of its own. Add a

[Bjorn Helgaas]

name for it and similar registers in other blocks.
---
 drivers/pci/host/pcie-rockchip.c |   31 +--
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 2a41439..a2610dd 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -38,7 +38,7 @@
 #include 
 
 /*
- * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16
+ * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
  * bits.  This allows atomic updates of the register without locking.
  */
 #define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
@@ -46,6 +46,7 @@
 #define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
 
 #define PCIE_CLIENT_BASE   0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
 #define  PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE(0x0001, 0x0001)
 #define  PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE(0x0002, 0x0002)
 #define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
@@ -87,6 +88,7 @@
PCIE_CLIENT_INT_PHY)
 
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
+#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
 #define  PCIE_CORE_PL_CONF_SPEED_5G0x1
 #define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
 #define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
@@ -120,6 +122,7 @@
 PCIE_CORE_INT_MMVC)
 
 #define PCIE_RC_CONFIG_BASE0xa0
+#define PCIE_RC_CONFIG_VENDOR  (PCIE_RC_CONFIG_BASE + 0x00)
 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
 #define  PCIE_RC_CONFIG_SCC_SHIFT  16
 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
@@ -131,6 +134,7 @@
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
 
 #define PCIE_CORE_AXI_CONF_BASE0xc0
+#define PCIE_CORE_OB_REGION_ADDR0  (PCIE_CORE_AXI_CONF_BASE + 0x0)
 #define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
 #define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
 #define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
@@ -140,7 +144,8 @@
 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
 
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
+#define PCIE_RP_IB_ADDR0   (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
+#define PCIE_RP_IB_ADDR1   (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
 
 /* Size of one AXI Region (not Region 0) */
 #define AXI_REGION_SIZEBIT(20)
@@ -419,7 +424,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
PCIE_CLIENT_MODE_RC |
PCIE_CLIENT_GEN_SEL_2,
-   PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONFIG);
 
err = phy_power_on(rockchip->phy);
if (err) {
@@ -462,7 +467,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
/* Enable Gen1 training */
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
-   PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONFIG);
 
gpiod_set_value(rockchip->ep_gpio, 1);
 
@@ -510,7 +515,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 PCIE_CORE_PL_CONF_SPEED_MASK) ==
 PCIE_CORE_PL_CONF_SPEED_5G) {
@@ -528,7 +533,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
/* Double check gen2 training */
if (err) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
PCIE_CORE_PL_CONF_SPEED_MASK) ==
PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
@@ -537,13 +542,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
}
 
/* Check the final link width from negotiated lane counter from MGMT */
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
   PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
 

[PATCH 12/12] MIPS: Malta: Use PIIX4 poweroff driver to power down

[Paul Burton]

Remove the platform code used to power down the system, instead relying
upon the new PIIX4 poweroff driver. This reduces the amount of platform
code required for the Malta board in preparation for allowing it to be
part of a more generic kernel.

Signed-off-by: Paul Burton 

---

 arch/mips/Kconfig   |  6 --
 arch/mips/configs/malta_defconfig   |  1 +
 arch/mips/configs/malta_kvm_defconfig   |  1 +
 arch/mips/configs/malta_kvm_guest_defconfig |  1 +
 arch/mips/configs/malta_qemu_32r6_defconfig |  1 +
 arch/mips/configs/maltaaprp_defconfig   |  1 +
 arch/mips/configs/maltasmvp_defconfig   |  1 +
 arch/mips/configs/maltasmvp_eva_defconfig   |  1 +
 arch/mips/configs/maltaup_defconfig |  1 +
 arch/mips/configs/maltaup_xpa_defconfig |  1 +
 arch/mips/mti-malta/Makefile|  2 -
 arch/mips/mti-malta/malta-pm.c  | 96 -
 arch/mips/mti-malta/malta-reset.c   | 30 -
 13 files changed, 9 insertions(+), 134 deletions(-)
 delete mode 100644 arch/mips/mti-malta/malta-pm.c
 delete mode 100644 arch/mips/mti-malta/malta-reset.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d875a5a..40e4b5d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1948,12 +1948,6 @@ config SYS_HAS_CPU_XLR
 config SYS_HAS_CPU_XLP
bool
 
-config MIPS_MALTA_PM
-   depends on MIPS_MALTA
-   depends on PCI
-   bool
-   default y
-
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index 58d43f3..f785767 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -319,6 +319,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index c8f7e28..fe1b941 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -332,6 +332,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index d2f54e5..a4ad822 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -332,6 +332,7 @@ CONFIG_LIBERTAS=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig 
b/arch/mips/configs/malta_qemu_32r6_defconfig
index cbf37dd..e284b3d 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltaaprp_defconfig 
b/arch/mips/configs/maltaaprp_defconfig
index 35f6ba2..73dca90 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltasmvp_defconfig 
b/arch/mips/configs/maltasmvp_defconfig
index 900f145..b5ae55b 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -135,6 +135,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig 
b/arch/mips/configs/maltasmvp_eva_defconfig
index 8e2738b..c3c059c8 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -138,6 +138,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
 CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltaup_defconfig 
b/arch/mips/configs/maltaup_defconfig
index 6dc4e30..28749b5 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -132,6 +132,7 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_POWER_RESET=y

[PATCH 6/6] ASoC: arizona: Add gating for source clocks of the FLLs

[Charles Keepax]

Whilst ultimately we would like to move all the clocking over to the
clock framework, as an intermediate step to get people going for now
enable the source clocks for FLLs as they are powered up.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 60 +-
 1 file changed, 54 insertions(+), 6 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index 2a019e9..780cf4f 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2244,6 +2244,42 @@ static int arizona_is_enabled_fll(struct arizona_fll 
*fll, int base)
return reg & ARIZONA_FLL1_ENA;
 }
 
+static int arizona_set_fll_clks(struct arizona_fll *fll, int base, bool ena)
+{
+   struct arizona *arizona = fll->arizona;
+   unsigned int val;
+   struct clk *clk;
+   int ret;
+
+   ret = regmap_read(arizona->regmap, base + 6, );
+   if (ret != 0) {
+   arizona_fll_err(fll, "Failed to read current source: %d\n",
+   ret);
+   return ret;
+   }
+
+   val &= ARIZONA_FLL1_CLK_REF_SRC_MASK;
+   val >>= ARIZONA_FLL1_CLK_REF_SRC_SHIFT;
+
+   switch (val) {
+   case ARIZONA_FLL_SRC_MCLK1:
+   clk = arizona->mclk[ARIZONA_MCLK1];
+   break;
+   case ARIZONA_FLL_SRC_MCLK2:
+   clk = arizona->mclk[ARIZONA_MCLK2];
+   break;
+   default:
+   return 0;
+   }
+
+   if (ena) {
+   return clk_prepare_enable(clk);
+   } else {
+   clk_disable_unprepare(clk);
+   return 0;
+   }
+}
+
 static int arizona_enable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
@@ -2266,6 +2302,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
udelay(32);
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
 ARIZONA_FLL1_GAIN_MASK, 0);
+
+   if (arizona_is_enabled_fll(fll, fll->base + 0x10) > 0)
+   arizona_set_fll_clks(fll, fll->base + 0x10, false);
+   arizona_set_fll_clks(fll, fll->base, false);
}
 
/*
@@ -2320,10 +2360,13 @@ static int arizona_enable_fll(struct arizona_fll *fll)
if (!already_enabled)
pm_runtime_get_sync(arizona->dev);
 
-   if (use_sync)
+   if (use_sync) {
+   arizona_set_fll_clks(fll, fll->base + 0x10, true);
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
 ARIZONA_FLL1_SYNC_ENA,
 ARIZONA_FLL1_SYNC_ENA);
+   }
+   arizona_set_fll_clks(fll, fll->base, true);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
 
@@ -2356,19 +2399,24 @@ static int arizona_enable_fll(struct arizona_fll *fll)
 static void arizona_disable_fll(struct arizona_fll *fll)
 {
struct arizona *arizona = fll->arizona;
-   bool change;
+   bool ref_change, sync_change;
 
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
regmap_update_bits_check(arizona->regmap, fll->base + 1,
-ARIZONA_FLL1_ENA, 0, );
-   regmap_update_bits(arizona->regmap, fll->base + 0x11,
-  ARIZONA_FLL1_SYNC_ENA, 0);
+ARIZONA_FLL1_ENA, 0, _change);
+   regmap_update_bits_check(arizona->regmap, fll->base + 0x11,
+ARIZONA_FLL1_SYNC_ENA, 0, _change);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
 ARIZONA_FLL1_FREERUN, 0);
 
-   if (change)
+   if (sync_change)
+   arizona_set_fll_clks(fll, fll->base + 0x10, false);
+
+   if (ref_change) {
+   arizona_set_fll_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(arizona->dev);
+   }
 }
 
 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
-- 
2.1.4

[PATCH v2 00/15] PCI: rockchip: Cleanups against v10

[Bjorn Helgaas]

These are cleanups against 2098142ae87d, the current pci/host-rockchip
head in my tree.

Changes from v1:

  - Rework HIWORD_UPDATE
  - Remove duplicate CSR definitions
  - Move CSR block offset from read/write caller to CSR definition
  - Organize CSRs into logical blocks
  - Fix some inconsistent CSR names
  - Add names for registers at the base of CSR blocks

I was disappointed to find how disorganized the v10 CSR definitions were.
It was quite a hodgepodge.  I should have noticed that earlier, but as
penance, I tried to clean it up myself.

These are in git as pci/host-rockchip-wip.  Again, I intend to squash these
all into the single commit that adds the driver when I finally merge it.

---

Bjorn Helgaas (15):
  Remove unused symbols, unnecessary parens, other minor comments from
  Rename pcie_read() and pcie_write() to rockchip_pcie_read() and
  Always use "rockchip" as the pointer to per-device struct.
  Rename struct rockchip_pcie_port to struct rockchip_pcie.
  Use a local "dev" to avoid repetition of "rockchip->dev".
  Add comment about why 32-bit read/modify/write isn't safe.
  Simplify the confusing HIWORD_UPDATE scheme.
  Remove duplicate CSR definition.
  Move CSR bases into definition.
  Group related CSR definitions together.
  Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions.
  Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT
  The register at PCIE_CLIENT_BASE presumably has a name of its own.  Add a
  Simplify testing of link status and speed testing.
  Move msleeps to address Guenter's comments.


 drivers/pci/host/pcie-rockchip.c |  842 ++
 1 file changed, 391 insertions(+), 451 deletions(-)

[PATCH 3/6] ASoC: arizona: Avoid changing SYNC_ENA whilst the FLL_ENA is set

[Charles Keepax]

For best performance changing the synchroniser state whilst the FLL is
running should be avoided. As this has been done fairly regularly in
practice rather than hard preventing this, simply improve the FLL enable
sequence and give a warning if the user changes the synchroniser state.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index 463979f4..be24387 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -2209,12 +2209,15 @@ static int arizona_enable_fll(struct arizona_fll *fll)
struct arizona *arizona = fll->arizona;
bool use_sync = false;
int already_enabled = arizona_is_enabled_fll(fll, fll->base);
+   int sync_enabled = arizona_is_enabled_fll(fll, fll->base + 0x10);
struct arizona_fll_cfg cfg;
int i;
unsigned int val;
 
if (already_enabled < 0)
return already_enabled;
+   if (sync_enabled < 0)
+   return sync_enabled;
 
if (already_enabled) {
/* Facilitate smooth refclk across the transition */
@@ -2259,6 +2262,9 @@ static int arizona_enable_fll(struct arizona_fll *fll)
return -EINVAL;
}
 
+   if (already_enabled && !!sync_enabled != use_sync)
+   arizona_fll_warn(fll, "Synchroniser changed on active FLL\n");
+
/*
 * Increase the bandwidth if we're not using a low frequency
 * sync source.
@@ -2274,12 +2280,12 @@ static int arizona_enable_fll(struct arizona_fll *fll)
if (!already_enabled)
pm_runtime_get_sync(arizona->dev);
 
-   regmap_update_bits_async(arizona->regmap, fll->base + 1,
-ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
if (use_sync)
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
 ARIZONA_FLL1_SYNC_ENA,
 ARIZONA_FLL1_SYNC_ENA);
+   regmap_update_bits_async(arizona->regmap, fll->base + 1,
+ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
 
if (already_enabled)
regmap_update_bits_async(arizona->regmap, fll->base + 1,
-- 
2.1.4

[PATCH v2 13/15] The register at PCIE_CLIENT_BASE presumably has a name of its own. Add a

[Bjorn Helgaas]

name for it and similar registers in other blocks.
---
 drivers/pci/host/pcie-rockchip.c |   31 +--
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 2a41439..a2610dd 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -38,7 +38,7 @@
 #include 
 
 /*
- * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16
+ * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
  * bits.  This allows atomic updates of the register without locking.
  */
 #define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
@@ -46,6 +46,7 @@
 #define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
 
 #define PCIE_CLIENT_BASE   0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
 #define  PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE(0x0001, 0x0001)
 #define  PCIE_CLIENT_LINK_TRAIN_ENABLE   HIWORD_UPDATE(0x0002, 0x0002)
 #define  PCIE_CLIENT_CONF_LANE_NUM(x)HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
@@ -87,6 +88,7 @@
PCIE_CLIENT_INT_PHY)
 
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
+#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
 #define  PCIE_CORE_PL_CONF_SPEED_5G0x1
 #define  PCIE_CORE_PL_CONF_SPEED_SHIFT 3
 #define  PCIE_CORE_PL_CONF_SPEED_MASK  0x3
@@ -120,6 +122,7 @@
 PCIE_CORE_INT_MMVC)
 
 #define PCIE_RC_CONFIG_BASE0xa0
+#define PCIE_RC_CONFIG_VENDOR  (PCIE_RC_CONFIG_BASE + 0x00)
 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
 #define  PCIE_RC_CONFIG_SCC_SHIFT  16
 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
@@ -131,6 +134,7 @@
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
 
 #define PCIE_CORE_AXI_CONF_BASE0xc0
+#define PCIE_CORE_OB_REGION_ADDR0  (PCIE_CORE_AXI_CONF_BASE + 0x0)
 #define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
 #define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
 #define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
@@ -140,7 +144,8 @@
 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
 
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
+#define PCIE_RP_IB_ADDR0   (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
+#define PCIE_RP_IB_ADDR1   (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
 
 /* Size of one AXI Region (not Region 0) */
 #define AXI_REGION_SIZEBIT(20)
@@ -419,7 +424,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
PCIE_CLIENT_MODE_RC |
PCIE_CLIENT_GEN_SEL_2,
-   PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONFIG);
 
err = phy_power_on(rockchip->phy);
if (err) {
@@ -462,7 +467,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
/* Enable Gen1 training */
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
-   PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONFIG);
 
gpiod_set_value(rockchip->ep_gpio, 1);
 
@@ -510,7 +515,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
 PCIE_CORE_PL_CONF_SPEED_MASK) ==
 PCIE_CORE_PL_CONF_SPEED_5G) {
@@ -528,7 +533,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 
/* Double check gen2 training */
if (err) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
PCIE_CORE_PL_CONF_SPEED_MASK) ==
PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
@@ -537,13 +542,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
}
 
/* Check the final link width from negotiated lane counter from MGMT */
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
status =  0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
   PCIE_CORE_PL_CONF_LANE_MASK);
dev_dbg(dev, "current link width is x%d\n", status);
 

[PATCH v2 02/15] Rename pcie_read() and pcie_write() to rockchip_pcie_read() and

[Bjorn Helgaas]

rockchip_pcie_write().
---
 drivers/pci/host/pcie-rockchip.c |   66 +++---
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a7006be..c9d0799 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,12 +200,12 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
 {
return readl(port->apb_base + reg);
 }
 
-static inline void pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
 {
writel(val, port->apb_base + reg);
 }
@@ -214,18 +214,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie_port *port)
 {
u32 status;
 
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
 {
u32 status;
 
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
 static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
@@ -417,7 +417,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
return err;
}
 
-   pcie_write(port,
+   rockchip_pcie_write(port,
   HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
 PCIE_CLIENT_CONF_ENABLE_MASK,
 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
@@ -471,13 +471,13 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 * reliable and enabling ASPM doesn't work.  This is a controller
 * bug we need to work around.
 */
-   status = pcie_read(port, PCIE_RC_CONFIG_BASE +
+   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE +
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-   pcie_write(port, status, PCIE_RC_CONFIG_BASE +
+   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE +
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
/* Enable Gen1 training */
-   pcie_write(port,
+   rockchip_pcie_write(port,
   HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
 PCIE_CLIENT_LINK_TRAIN_MASK,
 PCIE_CLIENT_LINK_TRAIN_SHIFT),
@@ -489,7 +489,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
timeout = jiffies + msecs_to_jiffies(500);
 
for (;;) {
-   status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+   status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
  PCIE_CLIENT_LINK_STATUS_MASK) ==
  PCIE_CLIENT_LINK_STATUS_UP) {
@@ -507,7 +507,7 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 
/* Double check gen1 training */
if (err) {
-   status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
+   status = rockchip_pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
PCIE_CLIENT_LINK_STATUS_MASK) ==
PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
@@ -521,15 +521,15 @@ static int rockchip_pcie_init_port(struct 
rockchip_pcie_port *port)
 * Enable retrain for gen2. This should be configured only after
 * gen1 finished.
 */
-   status = pcie_read(port,
+   status = rockchip_pcie_read(port,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
status |= PCIE_CORE_LCSR_RETRAIN_LINK;
-   pcie_write(port, status,
+   rockchip_pcie_write(port, status,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 
timeout = jiffies + msecs_to_jiffies(500);
for (;;) {
-   status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
+   status = rockchip_pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &

Re: [PATCH v2] mfd: arizona: Add DT options for max_channels_clocked and PDM speaker config

[Richard Fitzgerald]

On Fri, 2016-09-02 at 10:34 -0500, Rob Herring wrote:
> On Wed, Aug 31, 2016 at 10:25:43AM +0100, Richard Fitzgerald wrote:
> > This patch adds DT settings for the max_channels_clocked, spk_fmt and
> > spk_mute pdata.
> > 
> > Signed-off-by: Richard Fitzgerald 
> > ---
> >  Documentation/devicetree/bindings/mfd/arizona.txt | 11 
> 
> Binding looks fine, but...
> 
> >  drivers/mfd/arizona-core.c| 31 
> > +++
> >  2 files changed, 42 insertions(+)
> 
> > diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
> > index b95ff2d..36a9633 100644
> > --- a/drivers/mfd/arizona-core.c
> > +++ b/drivers/mfd/arizona-core.c
> > @@ -816,6 +816,37 @@ static int arizona_of_get_core_pdata(struct arizona 
> > *arizona)
> > count++;
> > }
> >  
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node,
> > +"wlf,max-channels-clocked",
> > +prop, cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->max_channels_clocked))
> > +   break;
> > +
> > +   pdata->max_channels_clocked[count] = val;
> > +   count++;
> > +   }
> 
> of_property_read_u32_array doesn't work for you?

No, it doesn't, because it doesn't read a variable-sized array.

> 
> > +
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node, "wlf,spk-fmt", prop,
> > +cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->spk_fmt))
> > +   break;
> > +
> > +   pdata->spk_fmt[count] = val;
> > +   count++;
> > +   }
> > +
> > +   count = 0;
> > +   of_property_for_each_u32(arizona->dev->of_node, "wlf,spk-mute", prop,
> > +cur, val) {
> > +   if (count == ARRAY_SIZE(pdata->spk_mute))
> > +   break;
> > +
> > +   pdata->spk_mute[count] = val;
> > +   count++;
> > +   }
> > +
> > return 0;
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majord...@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 11/15] Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index fe1b52f..88c16da 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -121,7 +121,7 @@
 
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
-#define  PCIE_CORE_RC_CONF_SCC_SHIFT   16
+#define  PCIE_RC_CONFIG_SCC_SHIFT  16
 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
 #define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
 #define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
@@ -545,7 +545,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
PCIE_RC_CONFIG_BASE);
rockchip_pcie_write(rockchip,
-   PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
+   PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
PCIE_RC_CONFIG_RID_CCR);
rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 

[PATCH 08/12] MIPS: Malta: Probe pflash via DT

[Paul Burton]

Add the DT nodes required to probe the CFI compatible parallel monitor
flash found on the Malta development board, and remove the platform
code that was previously doing it. Delete the now-empty malta-platform.c
file. Adjust the Malta defconfigs that enable MTD & the pflash/CFI
driver to enable CONFIG_MTD_PHYSMAP_OF rather than CONFIG_MTD_PHYSMAP in
order to preserve their behaviour.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts| 25 
 arch/mips/configs/malta_defconfig   |  2 +-
 arch/mips/configs/malta_kvm_defconfig   |  2 +-
 arch/mips/configs/malta_kvm_guest_defconfig |  2 +-
 arch/mips/configs/maltaup_xpa_defconfig |  2 +-
 arch/mips/mti-malta/Makefile|  1 -
 arch/mips/mti-malta/malta-platform.c| 44 -
 7 files changed, 29 insertions(+), 49 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index ee43296..2e594ec 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -50,6 +50,31 @@
interrupts = ;
};
 
+   pflash@1e00 {
+   compatible = "intel,dt28f160", "cfi-flash";
+   reg = <0x1e00 0x40>;
+   bank-width = <4>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   yamon@0 {
+   label = "YAMON";
+   reg = <0x0 0x10>;
+   read-only;
+   };
+
+   user-fs@10 {
+   label = "User FS";
+   reg = <0x10 0x2e>;
+   };
+
+   board-config@3e {
+   label = "Board Config";
+   reg = <0x3e 0x2>;
+   read-only;
+   };
+   };
+
isa {
compatible = "isa";
#address-cells = <2>;
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index 5afb484..d5d4816 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -230,7 +230,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index 98f1387..ef6ef24 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -235,7 +235,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index 3b5d591..3a49a77 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -234,7 +234,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/maltaup_xpa_defconfig 
b/arch/mips/configs/maltaup_xpa_defconfig
index 7322157..62e05eb 100644
--- a/arch/mips/configs/maltaup_xpa_defconfig
+++ b/arch/mips/configs/maltaup_xpa_defconfig
@@ -231,7 +231,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_UBI_GLUEBI=m
 CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 5827af7..0407774 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -11,7 +11,6 @@ obj-y += malta-dtshim.o
 obj-y  += malta-init.o
 obj-y  += malta-int.o
 obj-y  += malta-memory.o
-obj-y  += malta-platform.o
 obj-y  += malta-reset.o
 obj-y  += malta-setup.o
 obj-y  += malta-time.o
diff --git a/arch/mips/mti-malta/malta-platform.c 
b/arch/mips/mti-malta/malta-platform.c
index 6433a39..cc67dbf 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -25,11 +25,8 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
-#include 
 
 #define SMC_PORT(base, int)\
 {  \
@@ -67,49 +64,8 @@ static struct platform_device malta_uart8250_device = {
},
 };
 
-static struct mtd_partition malta_mtd_partitions[] = {
-   {
-   .name = "YAMON",
-   

[PATCH 07/12] MIPS: Malta: Probe RTC via DT

[Paul Burton]

Add the DT node required to probe the RTC, and remove the platform code
that was previously doing it.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts | 15 +++
 arch/mips/mti-malta/malta-platform.c | 21 -
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index af765af..ee43296 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -49,4 +49,19 @@
interrupt-parent = <>;
interrupts = ;
};
+
+   isa {
+   compatible = "isa";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   ranges = <1 0 0 0x1000>;
+
+   rtc: mc146818@70 {
+   compatible = "motorola,mc146818";
+   reg = <1 0x70 0x8>;
+
+   interrupt-parent = <>;
+   interrupts = <8>;
+   };
+   };
 };
diff --git a/arch/mips/mti-malta/malta-platform.c 
b/arch/mips/mti-malta/malta-platform.c
index e1dd1c1..6433a39 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -23,7 +23,6 @@
  */
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -68,25 +67,6 @@ static struct platform_device malta_uart8250_device = {
},
 };
 
-struct resource malta_rtc_resources[] = {
-   {
-   .start  = RTC_PORT(0),
-   .end= RTC_PORT(7),
-   .flags  = IORESOURCE_IO,
-   }, {
-   .start  = RTC_IRQ,
-   .end= RTC_IRQ,
-   .flags  = IORESOURCE_IRQ,
-   }
-};
-
-static struct platform_device malta_rtc_device = {
-   .name   = "rtc_cmos",
-   .id = -1,
-   .resource   = malta_rtc_resources,
-   .num_resources  = ARRAY_SIZE(malta_rtc_resources),
-};
-
 static struct mtd_partition malta_mtd_partitions[] = {
{
.name = "YAMON",
@@ -129,7 +109,6 @@ static struct platform_device malta_flash_device = {
 
 static struct platform_device *malta_devices[] __initdata = {
_uart8250_device,
-   _rtc_device,
_flash_device,
 };
 
-- 
2.9.3

[PATCH 11/12] power: reset: Add Intel PIIX4 poweroff driver

[Paul Burton]

Add a driver which allows powering off the system via an Intel PIIX4
southbridge, by entering the PIIX4 SOff state. This is useful on the
MIPS Malta development board, where it will power down the FPGA based
board until its ON/NMI button is pressed, or the QEMU implementation of
the MIPS Malta board where it will cause QEMU to exit.

Signed-off-by: Paul Burton 
---

 drivers/power/reset/Kconfig  |   9 +++
 drivers/power/reset/Makefile |   1 +
 drivers/power/reset/piix4-poweroff.c | 103 +++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/power/reset/piix4-poweroff.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index c74c3f6..b27ca50 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -104,6 +104,15 @@ config POWER_RESET_MSM
help
  Power off and restart support for Qualcomm boards.
 
+config POWER_RESET_PIIX4_POWEROFF
+   tristate "Intel PIIX4 power-off driver"
+   depends on MIPS && PCI
+   help
+ This driver supports powering off a system using the Intel PIIX4
+ southbridge, for example the MIPS Malta development board. The
+ southbridge SOff state is entered in response to a request to
+ power off the system.
+
 config POWER_RESET_LTC2952
bool "LTC2952 PowerPath power-off driver"
depends on OF_GPIO
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 1be307c..11dae3b 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
 obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
 obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
 obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
+obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
diff --git a/drivers/power/reset/piix4-poweroff.c 
b/drivers/power/reset/piix4-poweroff.c
new file mode 100644
index 000..bfa8bea
--- /dev/null
+++ b/drivers/power/reset/piix4-poweroff.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct pci_dev *pm_dev;
+static resource_size_t io_offset;
+
+enum piix4_pm_io_reg {
+   PIIX4_FUNC3IO_PMSTS = 0x00,
+#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS BIT(8)
+   PIIX4_FUNC3IO_PMCNTRL   = 0x04,
+#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN   BIT(13)
+#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10)
+};
+
+#define PIIX4_SUSPEND_MAGIC0x00120002
+
+static void piix4_poweroff(void)
+{
+   int spec_devid;
+   u16 sts;
+
+   /* Ensure the power button status is clear */
+   while (1) {
+   sts = inw(io_offset + PIIX4_FUNC3IO_PMSTS);
+   if (!(sts & PIIX4_FUNC3IO_PMSTS_PWRBTN_STS))
+   break;
+   outw(sts, io_offset + PIIX4_FUNC3IO_PMSTS);
+   }
+
+   /* Enable entry to suspend */
+   outw(PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF | PIIX4_FUNC3IO_PMCNTRL_SUS_EN,
+io_offset + PIIX4_FUNC3IO_PMCNTRL);
+
+   /* If the special cycle occurs too soon this doesn't work... */
+   mdelay(10);
+
+   /*
+* The PIIX4 will enter the suspend state only after seeing a special
+* cycle with the correct magic data on the PCI bus. Generate that
+* cycle now.
+*/
+   spec_devid = PCI_DEVID(0, PCI_DEVFN(0x1f, 0x7));
+   pci_bus_write_config_dword(pm_dev->bus, spec_devid, 0,
+  PIIX4_SUSPEND_MAGIC);
+
+   /* Give the system some time to power down, then error */
+   mdelay(1000);
+   pr_emerg("Unable to poweroff system\n");
+}
+
+static int piix4_poweroff_probe(struct pci_dev *dev,
+   const struct pci_device_id *id)
+{
+   int res, io_region = PCI_BRIDGE_RESOURCES;
+
+   /* Request access to the PIIX4 PM IO registers */
+   res = pci_request_region(dev, io_region, "PIIX4 PM IO registers");
+   if (res) {
+   dev_err(>dev, "failed to request PM IO registers: %d\n",
+   res);
+   return res;
+   }
+
+   pm_dev = dev;
+   io_offset = pci_resource_start(dev, io_region);
+   pm_power_off = piix4_poweroff;
+
+   return 0;
+}
+
+static void piix4_poweroff_remove(struct pci_dev *dev)
+{
+   if (pm_power_off == piix4_poweroff)
+   pm_power_off = 

[PATCH v2 08/15] Remove duplicate CSR definition.

[Bjorn Helgaas]

PCIE_RC_CONFIG_LCSR was the same as PCIE_RC_CONFIG_LCS.  Kept
PCIE_RC_CONFIG_LCS.

PCIE_CORE_LCSR_RETRAIN_LINK was inexplicably named differently and defined
separately.
---
 drivers/pci/host/pcie-rockchip.c |   27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index b204567..a2dd196 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -40,11 +40,12 @@
 #define PCIE_CLIENT_BASE   0x0
 #define PCIE_RC_CONFIG_BASE0xa0
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
-#define PCIE_RC_CONFIG_LCSR0xd0
-#define  PCIE_RC_CONFIG_LCSR_LBMIE BIT(10)
-#define  PCIE_RC_CONFIG_LCSR_LABIE BIT(11)
-#define  PCIE_RC_CONFIG_LCSR_LBMS  BIT(30)
-#define  PCIE_RC_CONFIG_LCSR_LAMS  BIT(31)
+#define PCIE_RC_CONFIG_LCS 0xd0
+#define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
+#define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
+#define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
+#define  PCIE_RC_CONFIG_LCS_LBMS   BIT(30)
+#define  PCIE_RC_CONFIG_LCS_LAMS   BIT(31)
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_AXI_CONF_BASE0xc0
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
@@ -68,7 +69,6 @@
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
 #define PCIE_RC_CONFIG_RID_CCR 0x8
-#define PCIE_RC_CONFIG_LCS 0xd0
 #define PCIE_RC_BAR_CONF   0x300
 #define PCIE_CORE_OB_REGION_ADDR1  0x4
 #define PCIE_CORE_OB_REGION_DESC0  0x8
@@ -119,7 +119,6 @@
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
-#define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
 
 /*
  * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the
@@ -204,18 +203,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
-   status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
-   status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
 }
 
 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
@@ -506,7 +505,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 */
status = rockchip_pcie_read(rockchip,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
-   status |= PCIE_CORE_LCSR_RETRAIN_LINK;
+   status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
rockchip_pcie_write(rockchip, status,
   PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
 

[PATCH v2 06/15] Add comment about why 32-bit read/modify/write isn't safe.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index ea75f35..c0c3ad5 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -282,6 +282,11 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie 
*rockchip,
 
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
+   /*
+* N.B. This read/modify/write isn't safe in general because it can
+* corrupt RW1C bits in adjacent registers.  But the hardware
+* doesn't support smaller writes.
+*/
tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
tmp |= val << ((where & 0x3) * 8);
writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);

[PATCH v2 06/15] Add comment about why 32-bit read/modify/write isn't safe.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index ea75f35..c0c3ad5 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -282,6 +282,11 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie 
*rockchip,
 
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
+   /*
+* N.B. This read/modify/write isn't safe in general because it can
+* corrupt RW1C bits in adjacent registers.  But the hardware
+* doesn't support smaller writes.
+*/
tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
tmp |= val << ((where & 0x3) * 8);
writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);

[PATCH 4/6] mfd: arizona: Add gating of external MCLKn clocks

[Charles Keepax]

From: Sylwester Nawrocki 

This patch adds requesting of the clocks supplied on MCLK1, MCLK2 pins,
gating of the 32k clock is added to the arizona_clk32k_enable(),
arizona_clk32k_disable() helpers.

It's a temporary change until the CODEC's clock controller gets exposed
through the clk API and is helpful for board configurations where the
MCLK clocks are not provided by always on oscillators.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Charles Keepax 
---
 drivers/mfd/arizona-core.c   | 30 --
 include/linux/mfd/arizona/core.h |  9 +
 2 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index e4f97b3..4fa0fae 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -49,7 +50,15 @@ int arizona_clk32k_enable(struct arizona *arizona)
case ARIZONA_32KZ_MCLK1:
ret = pm_runtime_get_sync(arizona->dev);
if (ret != 0)
-   goto out;
+   goto err_ref;
+   ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK1]);
+   if (ret != 0)
+   goto err_pm;
+   break;
+   case ARIZONA_32KZ_MCLK2:
+   ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK2]);
+   if (ret != 0)
+   goto err_ref;
break;
}
 
@@ -58,7 +67,9 @@ int arizona_clk32k_enable(struct arizona *arizona)
 ARIZONA_CLK_32K_ENA);
}
 
-out:
+err_pm:
+   pm_runtime_put_sync(arizona->dev);
+err_ref:
if (ret != 0)
arizona->clk32k_ref--;
 
@@ -83,6 +94,10 @@ int arizona_clk32k_disable(struct arizona *arizona)
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
pm_runtime_put_sync(arizona->dev);
+   clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK1]);
+   break;
+   case ARIZONA_32KZ_MCLK2:
+   clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK2]);
break;
}
}
@@ -1000,6 +1015,7 @@ static const struct mfd_cell wm8998_devs[] = {
 
 int arizona_dev_init(struct arizona *arizona)
 {
+   const char * const mclk_name[] = { "mclk1", "mclk2" };
struct device *dev = arizona->dev;
const char *type_name = NULL;
unsigned int reg, val, mask;
@@ -1016,6 +1032,16 @@ int arizona_dev_init(struct arizona *arizona)
else
arizona_of_get_core_pdata(arizona);
 
+   BUILD_BUG_ON(ARRAY_SIZE(arizona->mclk) != ARRAY_SIZE(mclk_name));
+   for (i = 0; i < ARRAY_SIZE(arizona->mclk); i++) {
+   arizona->mclk[i] = devm_clk_get(arizona->dev, mclk_name[i]);
+   if (IS_ERR(arizona->mclk[i])) {
+   dev_info(arizona->dev, "Failed to get %s: %ld\n",
+mclk_name[i], PTR_ERR(arizona->mclk[i]));
+   arizona->mclk[i] = NULL;
+   }
+   }
+
regcache_cache_only(arizona->regmap, true);
 
switch (arizona->type) {
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index 58ab4c0..b9909bb 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -13,6 +13,7 @@
 #ifndef _WM_ARIZONA_CORE_H
 #define _WM_ARIZONA_CORE_H
 
+#include 
 #include 
 #include 
 #include 
@@ -21,6 +22,12 @@
 
 #define ARIZONA_MAX_CORE_SUPPLIES 2
 
+enum {
+   ARIZONA_MCLK1,
+   ARIZONA_MCLK2,
+   ARIZONA_NUM_MCLK
+};
+
 enum arizona_type {
WM5102 = 1,
WM5110 = 2,
@@ -139,6 +146,8 @@ struct arizona {
struct mutex clk_lock;
int clk32k_ref;
 
+   struct clk *mclk[ARIZONA_NUM_MCLK];
+
bool ctrlif_error;
 
struct snd_soc_dapm_context *dapm;
-- 
2.1.4

[PATCH 5/6] ASoC: arizona: Add gating for clock when used for direct MCLK

[Charles Keepax]

Whilst ultimately we would like to move all the clocking over to the
clock framework, as an intermediate step to get people going for now
gating the source clocks for SYSCLK/ASYNCCLK when they are configured
to come directly from an MCLK pin.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 40 
 sound/soc/codecs/arizona.h |  2 ++
 sound/soc/codecs/cs47l24.c |  6 --
 sound/soc/codecs/wm5102.c  |  9 +++--
 sound/soc/codecs/wm5110.c  | 10 +++---
 sound/soc/codecs/wm8997.c  |  9 +++--
 sound/soc/codecs/wm8998.c  |  6 --
 7 files changed, 71 insertions(+), 11 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index be24387..2a019e9 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -1195,6 +1195,46 @@ static int arizona_set_opclk(struct snd_soc_codec 
*codec, unsigned int clk,
return -EINVAL;
 }
 
+int arizona_clk_ev(struct snd_soc_dapm_widget *w,
+  struct snd_kcontrol *kcontrol, int event)
+{
+   struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+   struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
+   unsigned int val;
+   int clk_idx;
+   int ret;
+
+   ret = regmap_read(arizona->regmap, w->reg, );
+   if (ret) {
+   dev_err(codec->dev, "Failed to check clock source: %d\n", ret);
+   return ret;
+   }
+
+   val = (val & ARIZONA_SYSCLK_SRC_MASK) >> ARIZONA_SYSCLK_SRC_SHIFT;
+
+   switch (val) {
+   case ARIZONA_CLK_SRC_MCLK1:
+   clk_idx = ARIZONA_MCLK1;
+   break;
+   case ARIZONA_CLK_SRC_MCLK2:
+   clk_idx = ARIZONA_MCLK2;
+   break;
+   default:
+   return 0;
+   }
+
+   switch (event) {
+   case SND_SOC_DAPM_PRE_PMU:
+   return clk_prepare_enable(arizona->mclk[clk_idx]);
+   case SND_SOC_DAPM_POST_PMD:
+   clk_disable_unprepare(arizona->mclk[clk_idx]);
+   return 0;
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL_GPL(arizona_clk_ev);
+
 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
   int source, unsigned int freq, int dir)
 {
diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h
index 69da1ef..1728771 100644
--- a/sound/soc/codecs/arizona.h
+++ b/sound/soc/codecs/arizona.h
@@ -272,6 +272,8 @@ extern int arizona_eq_coeff_put(struct snd_kcontrol 
*kcontrol,
 extern int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
  struct snd_ctl_elem_value *ucontrol);
 
+extern int arizona_clk_ev(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event);
 extern int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
  int source, unsigned int freq, int dir);
 
diff --git a/sound/soc/codecs/cs47l24.c b/sound/soc/codecs/cs47l24.c
index 257b152..5e8f979 100644
--- a/sound/soc/codecs/cs47l24.c
+++ b/sound/soc/codecs/cs47l24.c
@@ -335,9 +335,11 @@ static const struct snd_kcontrol_new 
cs47l24_aec_loopback_mux =
 
 static const struct snd_soc_dapm_widget cs47l24_dapm_widgets[] = {
 SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1,
-   ARIZONA_SYSCLK_ENA_SHIFT, 0, NULL, 0),
+   ARIZONA_SYSCLK_ENA_SHIFT, 0, arizona_clk_ev,
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
-   ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0),
+   ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index ed03ed27..a891344 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -607,6 +607,9 @@ static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
break;
+   case SND_SOC_DAPM_PRE_PMU:
+   case SND_SOC_DAPM_POST_PMD:
+   return arizona_clk_ev(w, kcontrol, event);
default:
return 0;
}
@@ -1077,9 +1080,11 @@ static const struct snd_kcontrol_new 
wm5102_aec_loopback_mux =
 static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = {
 SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
0, wm5102_sysclk_ev,
-   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 

[PATCH v2 12/15] Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT

[Bjorn Helgaas]

to match similar definitions.
---
 drivers/pci/host/pcie-rockchip.c |7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 88c16da..2a41439 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -56,8 +56,8 @@
 #define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
 #define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
-#define  ROCKCHIP_PCIE_RPIFR1_INTR_MASKGENMASK(8, 5)
-#define  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT   5
+#define  PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
+#define  PCIE_CLIENT_INTR_SHIFT5
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -679,8 +679,7 @@ static void rockchip_pcie_legacy_int_handler(struct 
irq_desc *desc)
chained_irq_enter(chip, desc);
 
reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
-   reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
-  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
+   reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
 
while (reg) {
hwirq = ffs(reg) - 1;

[PATCH v2 07/15] Simplify the confusing HIWORD_UPDATE scheme.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   70 +-
 1 file changed, 24 insertions(+), 46 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index c0c3ad5..b204567 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -115,36 +115,26 @@
  (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
   PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
 
-/*
-  * The higher 16-bit of this register is used for write protection
-  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
-  */
-#define HIWORD_UPDATE(val, mask, shift) \
-   ((val) << (shift) | (mask) << ((shift) + 16))
-
 #define RC_REGION_0_ADDR_TRANS_H   0x
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
 #define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
-#define PCIE_CLIENT_CONF_ENABLEBIT(0)
-#define PCIE_CLIENT_CONF_ENABLE_SHIFT  0
-#define PCIE_CLIENT_CONF_ENABLE_MASK   0x1
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE  1
-#define PCIE_CLIENT_LINK_TRAIN_SHIFT   1
-#define PCIE_CLIENT_LINK_TRAIN_MASK0x1
-#define PCIE_CLIENT_ARI_ENABLE BIT(0)
-#define PCIE_CLIENT_ARI_ENABLE_SHIFT   3
-#define PCIE_CLIENT_ARI_ENABLE_MASK0x1
-#define PCIE_CLIENT_CONF_LANE_NUM(x)   (x / 2)
-#define PCIE_CLIENT_CONF_LANE_NUM_SHIFT4
-#define PCIE_CLIENT_CONF_LANE_NUM_MASK 0x3
-#define PCIE_CLIENT_MODE_RCBIT(0)
-#define PCIE_CLIENT_MODE_SHIFT 6
-#define PCIE_CLIENT_MODE_MASK  0x1
-#define PCIE_CLIENT_GEN_SEL_2  1
-#define PCIE_CLIENT_GEN_SEL_SHIFT  7
-#define PCIE_CLIENT_GEN_SEL_MASK   0x1
+
+/*
+ * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the
+ * lower 16 bits.  This allows atomic updates of the register without
+ * locking.
+ */
+#define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
+
+#define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
+
+#define PCIE_CLIENT_CONF_ENABLEHIWORD_UPDATE(0x0001, 0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE  HIWORD_UPDATE(0x0002, 0x0002)
+#define PCIE_CLIENT_CONF_LANE_NUM(x)   HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
+#define PCIE_CLIENT_GEN_SEL_2  HIWORD_UPDATE(0x0040, 0x0040)
+
 #define PCIE_CLIENT_LINK_STATUS_UP 0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT  20
 #define PCIE_CLIENT_LINK_STATUS_MASK   0x3
@@ -423,22 +413,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
}
 
rockchip_pcie_write(rockchip,
-  HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
-PCIE_CLIENT_CONF_ENABLE_MASK,
-PCIE_CLIENT_CONF_ENABLE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes),
-PCIE_CLIENT_CONF_LANE_NUM_MASK,
-PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
-PCIE_CLIENT_MODE_MASK,
-PCIE_CLIENT_MODE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_ARI_ENABLE,
-PCIE_CLIENT_ARI_ENABLE_MASK,
-PCIE_CLIENT_ARI_ENABLE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_GEN_SEL_2,
-PCIE_CLIENT_GEN_SEL_MASK,
-PCIE_CLIENT_GEN_SEL_SHIFT),
-  PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONF_ENABLE |
+   PCIE_CLIENT_LINK_TRAIN_ENABLE |
+   PCIE_CLIENT_ARI_ENABLE |
+   PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
+   PCIE_CLIENT_MODE_RC |
+   PCIE_CLIENT_GEN_SEL_2,
+   PCIE_CLIENT_BASE);
 
err = phy_power_on(rockchip->phy);
if (err) {
@@ -482,11 +463,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
/* Enable Gen1 training */
-   rockchip_pcie_write(rockchip,
-  HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
-PCIE_CLIENT_LINK_TRAIN_MASK,
-PCIE_CLIENT_LINK_TRAIN_SHIFT),
-  PCIE_CLIENT_BASE);
+   rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+   PCIE_CLIENT_BASE);
 
gpiod_set_value(rockchip->ep_gpio, 1);
 

[PATCH v2 09/15] Move CSR bases into definition.

[Bjorn Helgaas]

Instead of this:

  #define PCIE_RC_CONFIG_LCS0xd0
  read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS);

do this:

  #define PCIE_RC_CONFIG_LCS(PCIE_RC_CONFIG_BASE + 0xd0)
  read(rockchip, PCIE_RC_CONFIG_LCS);

Mostly trivial, but rockchip_pcie_prog_ob_atu() and
rockchip_pcie_prog_ib_atu() are a little more complicated.
---
 drivers/pci/host/pcie-rockchip.c |  116 --
 1 file changed, 61 insertions(+), 55 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a2dd196..6edfce5 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -39,8 +39,8 @@
 
 #define PCIE_CLIENT_BASE   0x0
 #define PCIE_RC_CONFIG_BASE0xa0
-#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
-#define PCIE_RC_CONFIG_LCS 0xd0
+#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   (PCIE_RC_CONFIG_BASE + 0x90c)
+#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0x0d0)
 #define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
 #define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
 #define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
@@ -49,9 +49,9 @@
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_AXI_CONF_BASE0xc0
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_CLIENT_BASIC_STATUS1  0x48
-#define PCIE_CLIENT_INT_MASK   0x4c
-#define PCIE_CLIENT_INT_STATUS 0x50
+#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
+#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
+#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -68,18 +68,18 @@
 #define  PCIE_CLIENT_INT_PHY   BIT(2)
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
-#define PCIE_RC_CONFIG_RID_CCR 0x8
-#define PCIE_RC_BAR_CONF   0x300
-#define PCIE_CORE_OB_REGION_ADDR1  0x4
-#define PCIE_CORE_OB_REGION_DESC0  0x8
-#define PCIE_CORE_OB_REGION_DESC1  0xc
+#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
+#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 
0x300)
+#define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
+#define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
+#define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR  0xff00
 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_RP_IB_ADDR_TRANS  0x4
-#define PCIE_CORE_INT_MASK 0x900210
-#define PCIE_CORE_INT_STATUS   0x90020c
+#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 
0x4)
+#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 
0x210)
+#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 
0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
 #define  PCIE_CORE_INT_RRPEBIT(2)
@@ -194,7 +194,8 @@ static u32 rockchip_pcie_read(struct rockchip_pcie 
*rockchip, u32 reg)
return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
+   u32 reg)
 {
writel(val, rockchip->apb_base + reg);
 }
@@ -203,18 +204,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   rockchip_pcie_write(rockchip, 

[PATCH v2 03/15] Always use "rockchip" as the pointer to per-device struct.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |  488 +++---
 1 file changed, 244 insertions(+), 244 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index c9d0799..3cfb47a 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,56 +200,55 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
 {
-   return readl(port->apb_base + reg);
+   return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, 
u32 reg)
 {
-   writel(val, port->apb_base + reg);
+   writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
-   if (bus->number == pp->root_bus_nr && dev > 0)
+   if (bus->number == rockchip->root_bus_nr && dev > 0)
return 0;
 
/*
 * do not read more than one device on the bus directly attached
 * to RC's downstream side.
 */
-   if (bus->primary == pp->root_bus_nr && dev > 0)
+   if (bus->primary == rockchip->root_bus_nr && dev > 0)
return 0;
 
return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
-int where, int size,
-u32 *val)
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+int where, int size, u32 *val)
 {
-   void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
+   void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
 
if (!IS_ALIGNED((uintptr_t)addr, size)) {
*val = 0;
@@ -269,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct 
rockchip_pcie_port *pp,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
 int where, int size, u32 val)
 {
u32 mask, tmp, offset;
@@ -277,20 +276,20 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *pp,
offset = where & ~0x3;
 
if (size == 4) {
-   writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+   writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
return PCIBIOS_SUCCESSFUL;
}
 
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
-   tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
+   tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
tmp |= val << ((where & 0x3) * 8);
-   writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+   writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
 
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 *val)
 {
@@ -305,11 +304,11 @@ static int rockchip_pcie_rd_other_conf(struct 
rockchip_pcie_port *pp,
}

[PATCH 09/12] MIPS: Malta: Use syscon-reboot driver to reboot

[Paul Burton]

Make use of the generic syscon-reboot driver to reboot the Malta board,
reducing the amount of platform code it requires.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts| 12 
 arch/mips/configs/malta_defconfig   |  2 ++
 arch/mips/configs/malta_kvm_defconfig   |  2 ++
 arch/mips/configs/malta_kvm_guest_defconfig |  2 ++
 arch/mips/configs/malta_qemu_32r6_defconfig |  2 ++
 arch/mips/configs/maltaaprp_defconfig   |  2 ++
 arch/mips/configs/maltasmvp_defconfig   |  2 ++
 arch/mips/configs/maltasmvp_eva_defconfig   |  2 ++
 arch/mips/configs/maltaup_defconfig |  2 ++
 arch/mips/configs/maltaup_xpa_defconfig |  2 ++
 arch/mips/mti-malta/malta-reset.c   | 15 ++-
 11 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 2e594ec..71bd0da 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -75,6 +75,18 @@
};
};
 
+   fpga_regs: system-controller@1f00 {
+   compatible = "mti,malta-fpga", "syscon", "simple-mfd";
+   reg = <0x1f00 0x1000>;
+
+   reboot {
+   compatible = "syscon-reboot";
+   regmap = <_regs>;
+   offset = <0x500>;
+   mask = <0x4d>;
+   };
+   };
+
isa {
compatible = "isa";
#address-cells = <2>;
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index d5d4816..58d43f3 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -318,6 +318,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index ef6ef24..c8f7e28 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index 3a49a77..d2f54e5 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig 
b/arch/mips/configs/malta_qemu_32r6_defconfig
index 65f140e..cbf37dd 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
diff --git a/arch/mips/configs/maltaaprp_defconfig 
b/arch/mips/configs/maltaaprp_defconfig
index 799c433..35f6ba2 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltasmvp_defconfig 
b/arch/mips/configs/maltasmvp_defconfig
index ac0eb4d..900f145 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -134,6 +134,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig 
b/arch/mips/configs/maltasmvp_eva_defconfig
index 3184600..8e2738b 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -137,6 +137,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltaup_defconfig 
b/arch/mips/configs/maltaup_defconfig
index a79107d..6dc4e30 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -131,6 +131,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 

[PATCH 4/6] mfd: arizona: Add gating of external MCLKn clocks

[Charles Keepax]

From: Sylwester Nawrocki 

This patch adds requesting of the clocks supplied on MCLK1, MCLK2 pins,
gating of the 32k clock is added to the arizona_clk32k_enable(),
arizona_clk32k_disable() helpers.

It's a temporary change until the CODEC's clock controller gets exposed
through the clk API and is helpful for board configurations where the
MCLK clocks are not provided by always on oscillators.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Charles Keepax 
---
 drivers/mfd/arizona-core.c   | 30 --
 include/linux/mfd/arizona/core.h |  9 +
 2 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index e4f97b3..4fa0fae 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -49,7 +50,15 @@ int arizona_clk32k_enable(struct arizona *arizona)
case ARIZONA_32KZ_MCLK1:
ret = pm_runtime_get_sync(arizona->dev);
if (ret != 0)
-   goto out;
+   goto err_ref;
+   ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK1]);
+   if (ret != 0)
+   goto err_pm;
+   break;
+   case ARIZONA_32KZ_MCLK2:
+   ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK2]);
+   if (ret != 0)
+   goto err_ref;
break;
}
 
@@ -58,7 +67,9 @@ int arizona_clk32k_enable(struct arizona *arizona)
 ARIZONA_CLK_32K_ENA);
}
 
-out:
+err_pm:
+   pm_runtime_put_sync(arizona->dev);
+err_ref:
if (ret != 0)
arizona->clk32k_ref--;
 
@@ -83,6 +94,10 @@ int arizona_clk32k_disable(struct arizona *arizona)
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
pm_runtime_put_sync(arizona->dev);
+   clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK1]);
+   break;
+   case ARIZONA_32KZ_MCLK2:
+   clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK2]);
break;
}
}
@@ -1000,6 +1015,7 @@ static const struct mfd_cell wm8998_devs[] = {
 
 int arizona_dev_init(struct arizona *arizona)
 {
+   const char * const mclk_name[] = { "mclk1", "mclk2" };
struct device *dev = arizona->dev;
const char *type_name = NULL;
unsigned int reg, val, mask;
@@ -1016,6 +1032,16 @@ int arizona_dev_init(struct arizona *arizona)
else
arizona_of_get_core_pdata(arizona);
 
+   BUILD_BUG_ON(ARRAY_SIZE(arizona->mclk) != ARRAY_SIZE(mclk_name));
+   for (i = 0; i < ARRAY_SIZE(arizona->mclk); i++) {
+   arizona->mclk[i] = devm_clk_get(arizona->dev, mclk_name[i]);
+   if (IS_ERR(arizona->mclk[i])) {
+   dev_info(arizona->dev, "Failed to get %s: %ld\n",
+mclk_name[i], PTR_ERR(arizona->mclk[i]));
+   arizona->mclk[i] = NULL;
+   }
+   }
+
regcache_cache_only(arizona->regmap, true);
 
switch (arizona->type) {
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index 58ab4c0..b9909bb 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -13,6 +13,7 @@
 #ifndef _WM_ARIZONA_CORE_H
 #define _WM_ARIZONA_CORE_H
 
+#include 
 #include 
 #include 
 #include 
@@ -21,6 +22,12 @@
 
 #define ARIZONA_MAX_CORE_SUPPLIES 2
 
+enum {
+   ARIZONA_MCLK1,
+   ARIZONA_MCLK2,
+   ARIZONA_NUM_MCLK
+};
+
 enum arizona_type {
WM5102 = 1,
WM5110 = 2,
@@ -139,6 +146,8 @@ struct arizona {
struct mutex clk_lock;
int clk32k_ref;
 
+   struct clk *mclk[ARIZONA_NUM_MCLK];
+
bool ctrlif_error;
 
struct snd_soc_dapm_context *dapm;
-- 
2.1.4

[PATCH 5/6] ASoC: arizona: Add gating for clock when used for direct MCLK

[Charles Keepax]

Whilst ultimately we would like to move all the clocking over to the
clock framework, as an intermediate step to get people going for now
gating the source clocks for SYSCLK/ASYNCCLK when they are configured
to come directly from an MCLK pin.

Signed-off-by: Charles Keepax 
---
 sound/soc/codecs/arizona.c | 40 
 sound/soc/codecs/arizona.h |  2 ++
 sound/soc/codecs/cs47l24.c |  6 --
 sound/soc/codecs/wm5102.c  |  9 +++--
 sound/soc/codecs/wm5110.c  | 10 +++---
 sound/soc/codecs/wm8997.c  |  9 +++--
 sound/soc/codecs/wm8998.c  |  6 --
 7 files changed, 71 insertions(+), 11 deletions(-)

diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index be24387..2a019e9 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -1195,6 +1195,46 @@ static int arizona_set_opclk(struct snd_soc_codec 
*codec, unsigned int clk,
return -EINVAL;
 }
 
+int arizona_clk_ev(struct snd_soc_dapm_widget *w,
+  struct snd_kcontrol *kcontrol, int event)
+{
+   struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+   struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
+   unsigned int val;
+   int clk_idx;
+   int ret;
+
+   ret = regmap_read(arizona->regmap, w->reg, );
+   if (ret) {
+   dev_err(codec->dev, "Failed to check clock source: %d\n", ret);
+   return ret;
+   }
+
+   val = (val & ARIZONA_SYSCLK_SRC_MASK) >> ARIZONA_SYSCLK_SRC_SHIFT;
+
+   switch (val) {
+   case ARIZONA_CLK_SRC_MCLK1:
+   clk_idx = ARIZONA_MCLK1;
+   break;
+   case ARIZONA_CLK_SRC_MCLK2:
+   clk_idx = ARIZONA_MCLK2;
+   break;
+   default:
+   return 0;
+   }
+
+   switch (event) {
+   case SND_SOC_DAPM_PRE_PMU:
+   return clk_prepare_enable(arizona->mclk[clk_idx]);
+   case SND_SOC_DAPM_POST_PMD:
+   clk_disable_unprepare(arizona->mclk[clk_idx]);
+   return 0;
+   default:
+   return 0;
+   }
+}
+EXPORT_SYMBOL_GPL(arizona_clk_ev);
+
 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
   int source, unsigned int freq, int dir)
 {
diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h
index 69da1ef..1728771 100644
--- a/sound/soc/codecs/arizona.h
+++ b/sound/soc/codecs/arizona.h
@@ -272,6 +272,8 @@ extern int arizona_eq_coeff_put(struct snd_kcontrol 
*kcontrol,
 extern int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
  struct snd_ctl_elem_value *ucontrol);
 
+extern int arizona_clk_ev(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event);
 extern int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
  int source, unsigned int freq, int dir);
 
diff --git a/sound/soc/codecs/cs47l24.c b/sound/soc/codecs/cs47l24.c
index 257b152..5e8f979 100644
--- a/sound/soc/codecs/cs47l24.c
+++ b/sound/soc/codecs/cs47l24.c
@@ -335,9 +335,11 @@ static const struct snd_kcontrol_new 
cs47l24_aec_loopback_mux =
 
 static const struct snd_soc_dapm_widget cs47l24_dapm_widgets[] = {
 SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1,
-   ARIZONA_SYSCLK_ENA_SHIFT, 0, NULL, 0),
+   ARIZONA_SYSCLK_ENA_SHIFT, 0, arizona_clk_ev,
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
-   ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0),
+   ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
 SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index ed03ed27..a891344 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -607,6 +607,9 @@ static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
break;
+   case SND_SOC_DAPM_PRE_PMU:
+   case SND_SOC_DAPM_POST_PMD:
+   return arizona_clk_ev(w, kcontrol, event);
default:
return 0;
}
@@ -1077,9 +1080,11 @@ static const struct snd_kcontrol_new 
wm5102_aec_loopback_mux =
 static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = {
 SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
0, wm5102_sysclk_ev,
-   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
+   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
-  

[PATCH v2 12/15] Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT

[Bjorn Helgaas]

to match similar definitions.
---
 drivers/pci/host/pcie-rockchip.c |7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 88c16da..2a41439 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -56,8 +56,8 @@
 #define  PCIE_CLIENT_LINK_STATUS_MASK  0x3
 #define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
-#define  ROCKCHIP_PCIE_RPIFR1_INTR_MASKGENMASK(8, 5)
-#define  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT   5
+#define  PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
+#define  PCIE_CLIENT_INTR_SHIFT5
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -679,8 +679,7 @@ static void rockchip_pcie_legacy_int_handler(struct 
irq_desc *desc)
chained_irq_enter(chip, desc);
 
reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
-   reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
-  ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
+   reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
 
while (reg) {
hwirq = ffs(reg) - 1;

[PATCH v2 07/15] Simplify the confusing HIWORD_UPDATE scheme.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   70 +-
 1 file changed, 24 insertions(+), 46 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index c0c3ad5..b204567 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -115,36 +115,26 @@
  (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
   PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
 
-/*
-  * The higher 16-bit of this register is used for write protection
-  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
-  */
-#define HIWORD_UPDATE(val, mask, shift) \
-   ((val) << (shift) | (mask) << ((shift) + 16))
-
 #define RC_REGION_0_ADDR_TRANS_H   0x
 #define RC_REGION_0_ADDR_TRANS_L   0x
 #define RC_REGION_0_PASS_BITS  (25 - 1)
 #define MAX_AXI_WRAPPER_REGION_NUM 33
 #define PCIE_CORE_LCSR_RETRAIN_LINKBIT(5)
-#define PCIE_CLIENT_CONF_ENABLEBIT(0)
-#define PCIE_CLIENT_CONF_ENABLE_SHIFT  0
-#define PCIE_CLIENT_CONF_ENABLE_MASK   0x1
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE  1
-#define PCIE_CLIENT_LINK_TRAIN_SHIFT   1
-#define PCIE_CLIENT_LINK_TRAIN_MASK0x1
-#define PCIE_CLIENT_ARI_ENABLE BIT(0)
-#define PCIE_CLIENT_ARI_ENABLE_SHIFT   3
-#define PCIE_CLIENT_ARI_ENABLE_MASK0x1
-#define PCIE_CLIENT_CONF_LANE_NUM(x)   (x / 2)
-#define PCIE_CLIENT_CONF_LANE_NUM_SHIFT4
-#define PCIE_CLIENT_CONF_LANE_NUM_MASK 0x3
-#define PCIE_CLIENT_MODE_RCBIT(0)
-#define PCIE_CLIENT_MODE_SHIFT 6
-#define PCIE_CLIENT_MODE_MASK  0x1
-#define PCIE_CLIENT_GEN_SEL_2  1
-#define PCIE_CLIENT_GEN_SEL_SHIFT  7
-#define PCIE_CLIENT_GEN_SEL_MASK   0x1
+
+/*
+ * The upper 16 bits of the PCIE_CLIENT registers are a write mask for the
+ * lower 16 bits.  This allows atomic updates of the register without
+ * locking.
+ */
+#define HIWORD_UPDATE(mask, val)   ((mask << 16) | val)
+
+#define ENCODE_LANES(x)(((x >> 1) & 3) << 4)
+
+#define PCIE_CLIENT_CONF_ENABLEHIWORD_UPDATE(0x0001, 0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE  HIWORD_UPDATE(0x0002, 0x0002)
+#define PCIE_CLIENT_CONF_LANE_NUM(x)   HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
+#define PCIE_CLIENT_GEN_SEL_2  HIWORD_UPDATE(0x0040, 0x0040)
+
 #define PCIE_CLIENT_LINK_STATUS_UP 0x3
 #define PCIE_CLIENT_LINK_STATUS_SHIFT  20
 #define PCIE_CLIENT_LINK_STATUS_MASK   0x3
@@ -423,22 +413,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
}
 
rockchip_pcie_write(rockchip,
-  HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
-PCIE_CLIENT_CONF_ENABLE_MASK,
-PCIE_CLIENT_CONF_ENABLE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes),
-PCIE_CLIENT_CONF_LANE_NUM_MASK,
-PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
-PCIE_CLIENT_MODE_MASK,
-PCIE_CLIENT_MODE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_ARI_ENABLE,
-PCIE_CLIENT_ARI_ENABLE_MASK,
-PCIE_CLIENT_ARI_ENABLE_SHIFT) |
-  HIWORD_UPDATE(PCIE_CLIENT_GEN_SEL_2,
-PCIE_CLIENT_GEN_SEL_MASK,
-PCIE_CLIENT_GEN_SEL_SHIFT),
-  PCIE_CLIENT_BASE);
+   PCIE_CLIENT_CONF_ENABLE |
+   PCIE_CLIENT_LINK_TRAIN_ENABLE |
+   PCIE_CLIENT_ARI_ENABLE |
+   PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
+   PCIE_CLIENT_MODE_RC |
+   PCIE_CLIENT_GEN_SEL_2,
+   PCIE_CLIENT_BASE);
 
err = phy_power_on(rockchip->phy);
if (err) {
@@ -482,11 +463,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
 PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
/* Enable Gen1 training */
-   rockchip_pcie_write(rockchip,
-  HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
-PCIE_CLIENT_LINK_TRAIN_MASK,
-PCIE_CLIENT_LINK_TRAIN_SHIFT),
-  PCIE_CLIENT_BASE);
+   rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
+   PCIE_CLIENT_BASE);
 
gpiod_set_value(rockchip->ep_gpio, 1);
 

[PATCH v2 09/15] Move CSR bases into definition.

[Bjorn Helgaas]

Instead of this:

  #define PCIE_RC_CONFIG_LCS0xd0
  read(rockchip, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCS);

do this:

  #define PCIE_RC_CONFIG_LCS(PCIE_RC_CONFIG_BASE + 0xd0)
  read(rockchip, PCIE_RC_CONFIG_LCS);

Mostly trivial, but rockchip_pcie_prog_ob_atu() and
rockchip_pcie_prog_ib_atu() are a little more complicated.
---
 drivers/pci/host/pcie-rockchip.c |  116 --
 1 file changed, 61 insertions(+), 55 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a2dd196..6edfce5 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -39,8 +39,8 @@
 
 #define PCIE_CLIENT_BASE   0x0
 #define PCIE_RC_CONFIG_BASE0xa0
-#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   0x90c
-#define PCIE_RC_CONFIG_LCS 0xd0
+#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2   (PCIE_RC_CONFIG_BASE + 0x90c)
+#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0x0d0)
 #define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK   BIT(5)
 #define  PCIE_RC_CONFIG_LCS_LBMIE  BIT(10)
 #define  PCIE_RC_CONFIG_LCS_LABIE  BIT(11)
@@ -49,9 +49,9 @@
 #define PCIE_CORE_CTRL_MGMT_BASE   0x90
 #define PCIE_CORE_AXI_CONF_BASE0xc0
 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
-#define PCIE_CLIENT_BASIC_STATUS1  0x48
-#define PCIE_CLIENT_INT_MASK   0x4c
-#define PCIE_CLIENT_INT_STATUS 0x50
+#define PCIE_CLIENT_BASIC_STATUS1  (PCIE_CLIENT_BASE + 0x48)
+#define PCIE_CLIENT_INT_MASK   (PCIE_CLIENT_BASE + 0x4c)
+#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
 #define  PCIE_CLIENT_INT_LEGACY_DONE   BIT(15)
 #define  PCIE_CLIENT_INT_MSG   BIT(14)
 #define  PCIE_CLIENT_INT_HOT_RST   BIT(13)
@@ -68,18 +68,18 @@
 #define  PCIE_CLIENT_INT_PHY   BIT(2)
 #define  PCIE_CLIENT_INT_HOT_PLUG  BIT(1)
 #define  PCIE_CLIENT_INT_PWR_STCG  BIT(0)
-#define PCIE_RC_CONFIG_RID_CCR 0x8
-#define PCIE_RC_BAR_CONF   0x300
-#define PCIE_CORE_OB_REGION_ADDR1  0x4
-#define PCIE_CORE_OB_REGION_DESC0  0x8
-#define PCIE_CORE_OB_REGION_DESC1  0xc
+#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
+#define PCIE_RC_BAR_CONF   (PCIE_CORE_CTRL_MGMT_BASE + 
0x300)
+#define PCIE_CORE_OB_REGION_ADDR1  (PCIE_CORE_AXI_CONF_BASE + 0x4)
+#define PCIE_CORE_OB_REGION_DESC0  (PCIE_CORE_AXI_CONF_BASE + 0x8)
+#define PCIE_CORE_OB_REGION_DESC1  (PCIE_CORE_AXI_CONF_BASE + 0xc)
 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR  0xff00
 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR  0xff00
-#define PCIE_RP_IB_ADDR_TRANS  0x4
-#define PCIE_CORE_INT_MASK 0x900210
-#define PCIE_CORE_INT_STATUS   0x90020c
+#define PCIE_RP_IB_ADDR_TRANS  (PCIE_CORE_AXI_INBOUND_BASE + 
0x4)
+#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 
0x210)
+#define PCIE_CORE_INT_STATUS   (PCIE_CORE_CTRL_MGMT_BASE + 
0x20c)
 #define  PCIE_CORE_INT_PRFPE   BIT(0)
 #define  PCIE_CORE_INT_CRFPE   BIT(1)
 #define  PCIE_CORE_INT_RRPEBIT(2)
@@ -194,7 +194,8 @@ static u32 rockchip_pcie_read(struct rockchip_pcie 
*rockchip, u32 reg)
return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
+   u32 reg)
 {
writel(val, rockchip->apb_base + reg);
 }
@@ -203,18 +204,18 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
 }
 
 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
-   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCS);
+   rockchip_pcie_write(rockchip, 

[PATCH v2 03/15] Always use "rockchip" as the pointer to per-device struct.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |  488 +++---
 1 file changed, 244 insertions(+), 244 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index c9d0799..3cfb47a 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -200,56 +200,55 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *port, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
 {
-   return readl(port->apb_base + reg);
+   return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *port, u32 val, u32 
reg)
+static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, 
u32 reg)
 {
-   writel(val, port->apb_base + reg);
+   writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
-   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
 {
u32 status;
 
-   status = rockchip_pcie_read(port, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
-   rockchip_pcie_write(port, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
+   rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
-   if (bus->number == pp->root_bus_nr && dev > 0)
+   if (bus->number == rockchip->root_bus_nr && dev > 0)
return 0;
 
/*
 * do not read more than one device on the bus directly attached
 * to RC's downstream side.
 */
-   if (bus->primary == pp->root_bus_nr && dev > 0)
+   if (bus->primary == rockchip->root_bus_nr && dev > 0)
return 0;
 
return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
-int where, int size,
-u32 *val)
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+int where, int size, u32 *val)
 {
-   void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
+   void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
 
if (!IS_ALIGNED((uintptr_t)addr, size)) {
*val = 0;
@@ -269,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct 
rockchip_pcie_port *pp,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
 int where, int size, u32 val)
 {
u32 mask, tmp, offset;
@@ -277,20 +276,20 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *pp,
offset = where & ~0x3;
 
if (size == 4) {
-   writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+   writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
return PCIBIOS_SUCCESSFUL;
}
 
mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 
-   tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
+   tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
tmp |= val << ((where & 0x3) * 8);
-   writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
+   writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
 
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 *val)
 {
@@ -305,11 +304,11 @@ static int rockchip_pcie_rd_other_conf(struct 
rockchip_pcie_port *pp,
}

[PATCH 09/12] MIPS: Malta: Use syscon-reboot driver to reboot

[Paul Burton]

Make use of the generic syscon-reboot driver to reboot the Malta board,
reducing the amount of platform code it requires.

Signed-off-by: Paul Burton 
---

 arch/mips/boot/dts/mti/malta.dts| 12 
 arch/mips/configs/malta_defconfig   |  2 ++
 arch/mips/configs/malta_kvm_defconfig   |  2 ++
 arch/mips/configs/malta_kvm_guest_defconfig |  2 ++
 arch/mips/configs/malta_qemu_32r6_defconfig |  2 ++
 arch/mips/configs/maltaaprp_defconfig   |  2 ++
 arch/mips/configs/maltasmvp_defconfig   |  2 ++
 arch/mips/configs/maltasmvp_eva_defconfig   |  2 ++
 arch/mips/configs/maltaup_defconfig |  2 ++
 arch/mips/configs/maltaup_xpa_defconfig |  2 ++
 arch/mips/mti-malta/malta-reset.c   | 15 ++-
 11 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 2e594ec..71bd0da 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -75,6 +75,18 @@
};
};
 
+   fpga_regs: system-controller@1f00 {
+   compatible = "mti,malta-fpga", "syscon", "simple-mfd";
+   reg = <0x1f00 0x1000>;
+
+   reboot {
+   compatible = "syscon-reboot";
+   regmap = <_regs>;
+   offset = <0x500>;
+   mask = <0x4d>;
+   };
+   };
+
isa {
compatible = "isa";
#address-cells = <2>;
diff --git a/arch/mips/configs/malta_defconfig 
b/arch/mips/configs/malta_defconfig
index d5d4816..58d43f3 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -318,6 +318,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_defconfig 
b/arch/mips/configs/malta_kvm_defconfig
index ef6ef24..c8f7e28 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig 
b/arch/mips/configs/malta_kvm_guest_defconfig
index 3a49a77..d2f54e5 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
 # CONFIG_SERIO_I8042 is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig 
b/arch/mips/configs/malta_qemu_32r6_defconfig
index 65f140e..cbf37dd 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
diff --git a/arch/mips/configs/maltaaprp_defconfig 
b/arch/mips/configs/maltaaprp_defconfig
index 799c433..35f6ba2 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltasmvp_defconfig 
b/arch/mips/configs/maltasmvp_defconfig
index ac0eb4d..900f145 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -134,6 +134,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig 
b/arch/mips/configs/maltasmvp_eva_defconfig
index 3184600..8e2738b 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -137,6 +137,8 @@ CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
diff --git a/arch/mips/configs/maltaup_defconfig 
b/arch/mips/configs/maltaup_defconfig
index a79107d..6dc4e30 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -131,6 +131,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 

[PATCH v2 15/15] Move msleeps to address Guenter's comments.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   35 +++
 1 file changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e33d2f7..d293a62 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -481,24 +481,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
break;
}
 
-   msleep(20);
-
-   if (!time_before(jiffies, timeout)) {
-   err = -ETIMEDOUT;
-   break;
-   }
-   }
-
-   /* Double check gen1 training */
-   if (err) {
-   status = rockchip_pcie_read(rockchip,
-   PCIE_CLIENT_BASIC_STATUS1);
-   err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
-  PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
-   if (err) {
+   if (time_after(jiffies, timeout)) {
dev_err(dev, "PCIe link training gen1 timeout!\n");
-   return err;
+   return -ETIMEDOUT;
}
+
+   msleep(20);
}
 
/*
@@ -518,21 +506,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
break;
}
 
-   msleep(20);
-
-   if (!time_before(jiffies, timeout)) {
-   err = -ETIMEDOUT;
+   if (time_after(jiffies, timeout)) {
+   dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
break;
}
-   }
 
-   /* Double check gen2 training */
-   if (err) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
-  PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
-   if (err)
-   dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
+   msleep(20);
}
 
/* Check the final link width from negotiated lane counter from MGMT */

[PATCH v2 04/15] Rename struct rockchip_pcie_port to struct rockchip_pcie.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   46 +++---
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 3cfb47a..63fb0ebc 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -178,7 +178,7 @@
PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
PCIE_CLIENT_INT_PHY)
 
-struct rockchip_pcie_port {
+struct rockchip_pcie {
void__iomem *reg_base;  /* DT axi-base */
void__iomem *apb_base;  /* DT apb-base */
struct  phy *phy;
@@ -200,17 +200,17 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
 {
return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, 
u32 reg)
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 
reg)
 {
writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
@@ -219,7 +219,7 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie_port *rockchip)
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
@@ -228,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct 
rockchip_pcie_port *rockchip)
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
@@ -245,7 +245,7 @@ static int rockchip_pcie_valid_device(struct 
rockchip_pcie_port *rockchip,
return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
 int where, int size, u32 *val)
 {
void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
@@ -268,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
 int where, int size, u32 val)
 {
u32 mask, tmp, offset;
@@ -289,7 +289,7 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 *val)
 {
@@ -316,7 +316,7 @@ static int rockchip_pcie_rd_other_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 val)
 {
@@ -342,7 +342,7 @@ static int rockchip_pcie_wr_other_conf(struct 
rockchip_pcie_port *rockchip,
 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 int size, u32 *val)
 {
-   struct rockchip_pcie_port *rockchip = bus->sysdata;
+   struct rockchip_pcie *rockchip = bus->sysdata;
 
if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
*val = 0x;
@@ -358,7 +358,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 int where, int size, u32 val)
 {
-   struct rockchip_pcie_port *rockchip = bus->sysdata;
+   struct rockchip_pcie *rockchip = bus->sysdata;
 
if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -378,7 +378,7 @@ static struct pci_ops rockchip_pcie_ops = {
  * rockchip_pcie_init_port - Initialize hardware
  * @rockchip: PCIe port information
  */
-static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip)
+static 

[PATCH v2 15/15] Move msleeps to address Guenter's comments.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   35 +++
 1 file changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e33d2f7..d293a62 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -481,24 +481,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
break;
}
 
-   msleep(20);
-
-   if (!time_before(jiffies, timeout)) {
-   err = -ETIMEDOUT;
-   break;
-   }
-   }
-
-   /* Double check gen1 training */
-   if (err) {
-   status = rockchip_pcie_read(rockchip,
-   PCIE_CLIENT_BASIC_STATUS1);
-   err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
-  PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
-   if (err) {
+   if (time_after(jiffies, timeout)) {
dev_err(dev, "PCIe link training gen1 timeout!\n");
-   return err;
+   return -ETIMEDOUT;
}
+
+   msleep(20);
}
 
/*
@@ -518,21 +506,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
break;
}
 
-   msleep(20);
-
-   if (!time_before(jiffies, timeout)) {
-   err = -ETIMEDOUT;
+   if (time_after(jiffies, timeout)) {
+   dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
break;
}
-   }
 
-   /* Double check gen2 training */
-   if (err) {
-   status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-   err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
-  PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
-   if (err)
-   dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
+   msleep(20);
}
 
/* Check the final link width from negotiated lane counter from MGMT */

[PATCH v2 04/15] Rename struct rockchip_pcie_port to struct rockchip_pcie.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   46 +++---
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 3cfb47a..63fb0ebc 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -178,7 +178,7 @@
PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
PCIE_CLIENT_INT_PHY)
 
-struct rockchip_pcie_port {
+struct rockchip_pcie {
void__iomem *reg_base;  /* DT axi-base */
void__iomem *apb_base;  /* DT apb-base */
struct  phy *phy;
@@ -200,17 +200,17 @@ struct rockchip_pcie_port {
struct  irq_domain *irq_domain;
 };
 
-static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg)
+static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
 {
return readl(rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, 
u32 reg)
+static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 
reg)
 {
writel(val, rockchip->apb_base + reg);
 }
 
-static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
@@ -219,7 +219,7 @@ static void rockchip_pcie_enable_bw_int(struct 
rockchip_pcie_port *rockchip)
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip)
+static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
 {
u32 status;
 
@@ -228,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct 
rockchip_pcie_port *rockchip)
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + 
PCIE_RC_CONFIG_LCSR);
 }
 
-static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
  struct pci_bus *bus, int dev)
 {
/* access only one slot on each root port */
@@ -245,7 +245,7 @@ static int rockchip_pcie_valid_device(struct 
rockchip_pcie_port *rockchip,
return 1;
 }
 
-static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
 int where, int size, u32 *val)
 {
void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
@@ -268,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
 int where, int size, u32 val)
 {
u32 mask, tmp, offset;
@@ -289,7 +289,7 @@ static int rockchip_pcie_wr_own_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 *val)
 {
@@ -316,7 +316,7 @@ static int rockchip_pcie_rd_other_conf(struct 
rockchip_pcie_port *rockchip,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip,
+static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
   struct pci_bus *bus, u32 devfn,
   int where, int size, u32 val)
 {
@@ -342,7 +342,7 @@ static int rockchip_pcie_wr_other_conf(struct 
rockchip_pcie_port *rockchip,
 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 int size, u32 *val)
 {
-   struct rockchip_pcie_port *rockchip = bus->sysdata;
+   struct rockchip_pcie *rockchip = bus->sysdata;
 
if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
*val = 0x;
@@ -358,7 +358,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 
devfn, int where,
 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 int where, int size, u32 val)
 {
-   struct rockchip_pcie_port *rockchip = bus->sysdata;
+   struct rockchip_pcie *rockchip = bus->sysdata;
 
if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -378,7 +378,7 @@ static struct pci_ops rockchip_pcie_ops = {
  * rockchip_pcie_init_port - Initialize hardware
  * @rockchip: PCIe port information
  */
-static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip)
+static 

[PATCH 01/12] irqchip: i8259: Add domain before mapping parent irq

[Paul Burton]

Mapping the parent IRQ will use a virq number which may conflict with
the hardcoded I8259A_IRQ_BASE..I8259A_IRQ_BASE+15 range that the i8259
driver expects to be free. If this occurs then we'll hit errors when
adding the i8259 IRQ domain, since one of its virq numbers will already
be in use.

Avoid this by adding the i8259 domain before mapping the parent IRQ,
such that the i8259 virq numbers become used before the parent interrupt
controller gets a chance to use any of them.

Signed-off-by: Paul Burton 
---

 drivers/irqchip/irq-i8259.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 6b304eb..85897fd 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -370,13 +370,15 @@ int __init i8259_of_init(struct device_node *node, struct 
device_node *parent)
struct irq_domain *domain;
unsigned int parent_irq;
 
+   domain = __init_i8259_irqs(node);
+
parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq) {
pr_err("Failed to map i8259 parent IRQ\n");
+   irq_domain_remove(domain);
return -ENODEV;
}
 
-   domain = __init_i8259_irqs(node);
irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
 domain);
return 0;
-- 
2.9.3

[PATCH 00/12] Partial MIPS Malta DT conversion

[Paul Burton]

This series begins converting the MIPS Malta board to use device tree to
probe its various devices & peripherals, with the eventual goal of
including Malta support in generic kernels.

In terms of use the only change should be that kernels will
automatically make use of more than 256MB DDR when built for 64 bit, or
32 bit with highmem enabled.

The series leaves Malta with a significant amount less platform code and
thus closer to being ready for inclusion in a generic MIPS kernel.

Applies atop v4.8-rc4.

Paul Burton (12):
  irqchip: i8259: Add domain before mapping parent irq
  irqchip: i8259: Allow platforms to override poll function
  irqchip: i8259: Remove unused i8259A_irq_pending
  MIPS: Malta: Allow PCI devices DMA to lower 2GB physical
  MIPS: Malta: Use all available DDR by default
  MIPS: Malta: Probe interrupt controllers via DT
  MIPS: Malta: Probe RTC via DT
  MIPS: Malta: Probe pflash via DT
  MIPS: Malta: Use syscon-reboot driver to reboot
  MIPS: Malta: Remove custom halt implementation
  power: reset: Add Intel PIIX4 poweroff driver
  MIPS: Malta: Use PIIX4 poweroff driver to power down

 arch/mips/Kconfig   |   7 +-
 arch/mips/boot/dts/mti/malta.dts|  93 ++
 arch/mips/configs/malta_defconfig   |   5 +-
 arch/mips/configs/malta_kvm_defconfig   |   5 +-
 arch/mips/configs/malta_kvm_guest_defconfig |   5 +-
 arch/mips/configs/malta_qemu_32r6_defconfig |   3 +
 arch/mips/configs/maltaaprp_defconfig   |   3 +
 arch/mips/configs/maltasmvp_defconfig   |   3 +
 arch/mips/configs/maltasmvp_eva_defconfig   |   3 +
 arch/mips/configs/maltaup_defconfig |   3 +
 arch/mips/configs/maltaup_xpa_defconfig |   5 +-
 arch/mips/include/asm/i8259.h   |  12 +-
 arch/mips/mti-malta/Makefile|   3 -
 arch/mips/mti-malta/malta-dtshim.c  | 187 +++-
 arch/mips/mti-malta/malta-init.c|  17 ++-
 arch/mips/mti-malta/malta-int.c |  96 +-
 arch/mips/mti-malta/malta-platform.c|  65 --
 arch/mips/mti-malta/malta-pm.c  |  96 --
 arch/mips/mti-malta/malta-reset.c   |  47 ---
 drivers/irqchip/irq-i8259.c |  30 ++---
 drivers/power/reset/Kconfig |   9 ++
 drivers/power/reset/Makefile|   1 +
 drivers/power/reset/piix4-poweroff.c| 103 +++
 23 files changed, 452 insertions(+), 349 deletions(-)
 delete mode 100644 arch/mips/mti-malta/malta-pm.c
 delete mode 100644 arch/mips/mti-malta/malta-reset.c
 create mode 100644 drivers/power/reset/piix4-poweroff.c

-- 
2.9.3

[PATCH 06/12] MIPS: Malta: Probe interrupt controllers via DT

[Paul Burton]

Probe the CPU, GIC & i8259 interrupt controllers present in the Malta
system using device tree. This enables interrupts to be provided to
devices using device tree as they are moved over to being probed using
it.

Since Malta is very configurable it's unknown whether a GIC will be
present at compile time. In order to support both cases the
malta_dt_shim code is added in order to detect whether a GIC is present,
adjusting the DT to route interrupts correctly and nop out the GIC node
if no GIC is found.

Signed-off-by: Paul Burton 
---

 arch/mips/Kconfig  |  1 +
 arch/mips/boot/dts/mti/malta.dts   | 41 
 arch/mips/mti-malta/malta-dtshim.c | 78 +++
 arch/mips/mti-malta/malta-int.c| 96 ++
 4 files changed, 125 insertions(+), 91 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2638856..d875a5a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_RELOCATABLE
select USE_OF
+   select LIBFDT
select ZONE_DMA32 if 64BIT
select BUILTIN_DTB
select LIBFDT
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index b18c466..af765af 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -1,5 +1,8 @@
 /dts-v1/;
 
+#include 
+#include 
+
 /memreserve/ 0x 0x1000;/* YAMON exception vectors */
 /memreserve/ 0x1000 0x000ef000;/* YAMON */
 /memreserve/ 0x000f 0x0001;/* PIIX4 ISA memory */
@@ -8,4 +11,42 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,malta";
+
+   cpu_intc: interrupt-controller {
+   compatible = "mti,cpu-interrupt-controller";
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   };
+
+   gic: interrupt-controller@1bdc {
+   compatible = "mti,gic";
+   reg = <0x1bdc 0x2>;
+
+   interrupt-controller;
+   #interrupt-cells = <3>;
+
+   /*
+* Declare the interrupt-parent even though the mti,gic
+* binding doesn't require it, such that the kernel can
+* figure out that cpu_intc is the root interrupt
+* controller & should be probed first.
+*/
+   interrupt-parent = <_intc>;
+
+   timer {
+   compatible = "mti,gic-timer";
+   interrupts = ;
+   };
+   };
+
+   i8259: interrupt-controller@20 {
+   compatible = "intel,i8259";
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = ;
+   };
 };
diff --git a/arch/mips/mti-malta/malta-dtshim.c 
b/arch/mips/mti-malta/malta-dtshim.c
index 5d37b7e..c398582 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -16,6 +16,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 
 #define ROCIT_REG_BASE 0x1f403000
@@ -225,6 +228,80 @@ static void __init append_memory(void *fdt, int root_off)
panic("Unable to set linux,usable-memory property: %d", err);
 }
 
+static void __init remove_gic(void *fdt)
+{
+   int err, gic_off, i8259_off, cpu_off;
+   void __iomem *biu_base;
+   uint32_t cpu_phandle, sc_cfg;
+
+   /* if we have a CM which reports a GIC is present, leave the DT alone */
+   err = mips_cm_probe();
+   if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
+   return;
+
+   if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
+   /*
+* On systems using the RocIT system controller a GIC may be
+* present without a CM. Detect whether that is the case.
+*/
+   biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
+   MSC01_BIU_ADDRSPACE_SZ);
+   sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
+   if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) {
+   /* enable the GIC at the system controller level */
+   sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF);
+   __raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
+   return;
+   }
+   }
+
+   gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
+   if (gic_off < 0) {
+   pr_warn("malta-dtshim: unable to find DT GIC node: %d\n",
+   gic_off);
+   return;
+   }
+
+   err = fdt_nop_node(fdt, gic_off);
+   if (err)
+   pr_warn("malta-dtshim: unable to nop GIC node\n");
+
+   i8259_off = 

Re: [PATCH] drm/tegra: Expose color key and plane blending controls to userspace

[Thierry Reding]

On Fri, Sep 02, 2016 at 05:32:19PM +0200, Thierry Reding wrote:
> On Fri, Sep 02, 2016 at 12:33:42PM +0300, Dmitry Osipenko wrote:
> > Chromakey is a simple way of video overlay overlap implementation. This
> > patch adds 2 new IOCTL's: first - sets color key and is common across of
> > all Tegra SoC's, second - sets plane blending controls and allows to
> > utilize the color key, this one is exclusive to Tegra20/30.
> > 
> > Signed-off-by: Dmitry Osipenko 
> > ---
> >  drivers/gpu/drm/tegra/dc.c   | 150 +---
> >  drivers/gpu/drm/tegra/dc.h   |   6 ++
> >  drivers/gpu/drm/tegra/drm.c  | 159 
> > +++
> >  drivers/gpu/drm/tegra/drm.h  |  14 
> >  include/uapi/drm/tegra_drm.h |  34 +
> >  5 files changed, 337 insertions(+), 26 deletions(-)
> 
> I think these are really nice features to have, but these would need to
> be exposed as properties, rather than custom driver-specific IOCTLs. It
> seems to me like the colorkey feature could be implemented in much the
> same way as in the Armada, RCar and Nouveau drivers.
> 
> As for the blending options, I think they should be exposed in terms of
> the zpos property, to allow generic userspace to make use of them. Also
> can you explain why this needs to be exclusive to Tegra20 and Tegra30?

Ah... I just realized that the blending interface changed on Tegra124.
All the more reason to expose this more generically, that way we can
hide the differences between a property and support the same interface
across all generations of Tegra.

Also see this:


https://chromium.googlesource.com/chromiumos/third_party/kernel/+/de9295aabdb7f80555c9b77b29ac77bcdac3280b

Thierry


signature.asc
Description: PGP signature

[PATCH 04/12] MIPS: Malta: Allow PCI devices DMA to lower 2GB physical

[Paul Burton]

Set the PCI_BAR0 register in all configurations such that PCI devices
can perform DMA to all of the bottom 2GB of the physical address space.
This is imperfect if we make use of the legacy Malta memory map, but it
is an improvement on the inconsistent values setup before.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-init.c | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index dc2c521..0f3b881 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -242,23 +243,19 @@ mips_pci_controller:
  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 #endif
-#ifndef CONFIG_EVA
-   /* Fix up target memory mapping.  */
-   MSC_READ(MSC01_PCI_BAR0, mask);
-   MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
-#else
+
/*
 * Setup the Malta max (2GB) memory for PCI DMA in host bridge
-* in transparent addressing mode, starting from 0x8000.
+* in transparent addressing mode.
 */
-   mask = PHYS_OFFSET | (1<<3);
+   mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
MSC_WRITE(MSC01_PCI_BAR0, mask);
-
-   mask = PHYS_OFFSET;
MSC_WRITE(MSC01_PCI_HEAD4, mask);
+
+   mask &= MSC01_PCI_BAR0_SIZE_MSK;
MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
-#endif
+
/* Don't handle target retries indefinitely.  */
if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
MSC01_PCI_CFG_MAXRTRY_MSK)
-- 
2.9.3

[PATCH 02/12] irqchip: i8259: Allow platforms to override poll function

[Paul Burton]

The default i8259 polling function (i8259_irq) is nicely generic but is
fairly costly. Platforms often provide an alternative means of polling
for an i8259 interrupt, and when using the i8259 without device tree
have typically just chained its parent interrupt to their own handler
function. In order to allow for platform-specific polling functions to
be used in cases where the driver is probed via device tree, provide an
i8259_set_poll function that accepts a pointer to an alternative poll
function that will override the default.

Signed-off-by: Paul Burton 
---

 arch/mips/include/asm/i8259.h | 11 +++
 drivers/irqchip/irq-i8259.c   |  8 +++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index a7fbcd6..b27fcc4 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -43,6 +43,17 @@ extern void make_8259A_irq(unsigned int irq);
 extern void init_i8259_irqs(void);
 extern int i8259_of_init(struct device_node *node, struct device_node *parent);
 
+/**
+ * i8159_set_poll() - Override the i8259 polling function
+ * @poll: pointer to platform-specific polling function
+ *
+ * Call this to override the generic i8259 polling function, which directly
+ * accesses i8259 registers, with a platform specific one which may be faster
+ * in cases where hardware provides a more optimal means of polling for an
+ * interrupt.
+ */
+extern void i8259_set_poll(int (*poll)(void));
+
 /*
  * Do the traditional i8259 interrupt polling thing.  This is for the few
  * cases where no better interrupt acknowledge method is available and we
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 85897fd..1f4a344 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -38,6 +38,7 @@ static void disable_8259A_irq(struct irq_data *d);
 static void enable_8259A_irq(struct irq_data *d);
 static void mask_and_ack_8259A(struct irq_data *d);
 static void init_8259A(int auto_eoi);
+static int (*i8259_poll)(void) = i8259_irq;
 
 static struct irq_chip i8259A_chip = {
.name   = "XT-PIC",
@@ -51,6 +52,11 @@ static struct irq_chip i8259A_chip = {
  * 8259A PIC functions to handle ISA devices:
  */
 
+void i8259_set_poll(int (*poll)(void))
+{
+   i8259_poll = poll;
+}
+
 /*
  * This contains the irq mask for both 8259A irq controllers,
  */
@@ -355,7 +361,7 @@ void __init init_i8259_irqs(void)
 static void i8259_irq_dispatch(struct irq_desc *desc)
 {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
-   int hwirq = i8259_irq();
+   int hwirq = i8259_poll();
unsigned int irq;
 
if (hwirq < 0)
-- 
2.9.3

[PATCH 03/12] irqchip: i8259: Remove unused i8259A_irq_pending

[Paul Burton]

The i8259A_irq_pending function is unused. Remove the dead code.

Signed-off-by: Paul Burton 
---

 arch/mips/include/asm/i8259.h |  1 -
 drivers/irqchip/irq-i8259.c   | 18 --
 2 files changed, 19 deletions(-)

diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index b27fcc4..32229c7 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -37,7 +37,6 @@
 
 extern raw_spinlock_t i8259A_lock;
 
-extern int i8259A_irq_pending(unsigned int irq);
 extern void make_8259A_irq(unsigned int irq);
 
 extern void init_i8259_irqs(void);
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 1f4a344..1aec12c 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -95,24 +95,6 @@ static void enable_8259A_irq(struct irq_data *d)
raw_spin_unlock_irqrestore(_lock, flags);
 }
 
-int i8259A_irq_pending(unsigned int irq)
-{
-   unsigned int mask;
-   unsigned long flags;
-   int ret;
-
-   irq -= I8259A_IRQ_BASE;
-   mask = 1 << irq;
-   raw_spin_lock_irqsave(_lock, flags);
-   if (irq < 8)
-   ret = inb(PIC_MASTER_CMD) & mask;
-   else
-   ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
-   raw_spin_unlock_irqrestore(_lock, flags);
-
-   return ret;
-}
-
 void make_8259A_irq(unsigned int irq)
 {
disable_irq_nosync(irq);
-- 
2.9.3

[PATCH 05/12] MIPS: Malta: Use all available DDR by default

[Paul Burton]

Malta boards can have more than 256MB DDR available, but we have
previously only made use of up to 256MB (ie. the DDR accessible via
kseg0) by default, without the user manually specifying mem= kernel
parameters. This patch causes all available DDR, as reported by the
bootloader via the ememsize or memsize environment variables or
optionally on the command line, to be used when possible without the
user needing to manually provide the memory ranges.

Malta now has 2 subtly different memory maps which have to be taken into
account when setting this up. The original memory map (referred to by
the code as v1) has up to 2GB of DDR aliased in both the upper & lower
halves of the 32 bit physical address space, with a 256MB I/O region
obscuring 0x1000-0x1fff only in the lower alias. The revised v2
memory map is flat with up to 4GB DDR starting from 0x0, and the I/O
region obscures 256MB of DDR which becomes inacessible. The memory map
in use is indicated by a register provided by the rocit2 system
controller, which is checked in order to set up the kernels memory
ranges accordingly.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-dtshim.c | 109 +++--
 1 file changed, 103 insertions(+), 6 deletions(-)

diff --git a/arch/mips/mti-malta/malta-dtshim.c 
b/arch/mips/mti-malta/malta-dtshim.c
index 151f488..5d37b7e 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -13,18 +13,63 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+#define ROCIT_REG_BASE 0x1f403000
+#define ROCIT_CONFIG_GEN1  (ROCIT_REG_BASE + 0x04)
+#define  ROCIT_CONFIG_GEN1_MEMMAP_SHIFT8
+#define  ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
+
 static unsigned char fdt_buf[16 << 10] __initdata;
 
 /* determined physical memory size, not overridden by command line args
 */
 extern unsigned long physical_memsize;
 
-#define MAX_MEM_ARRAY_ENTRIES 1
+enum mem_map {
+   MEM_MAP_V1 = 0,
+   MEM_MAP_V2,
+};
+
+#define MAX_MEM_ARRAY_ENTRIES 2
+
+static __init int malta_scon(void)
+{
+   int scon = MIPS_REVISION_SCONID;
+
+   if (scon != MIPS_REVISION_SCON_OTHER)
+   return scon;
+
+   switch (MIPS_REVISION_CORID) {
+   case MIPS_REVISION_CORID_QED_RM5261:
+   case MIPS_REVISION_CORID_CORE_LV:
+   case MIPS_REVISION_CORID_CORE_FPGA:
+   case MIPS_REVISION_CORID_CORE_FPGAR2:
+   return MIPS_REVISION_SCON_GT64120;
+
+   case MIPS_REVISION_CORID_CORE_EMUL_BON:
+   case MIPS_REVISION_CORID_BONITO64:
+   case MIPS_REVISION_CORID_CORE_20K:
+   return MIPS_REVISION_SCON_BONITO;
+
+   case MIPS_REVISION_CORID_CORE_MSC:
+   case MIPS_REVISION_CORID_CORE_FPGA2:
+   case MIPS_REVISION_CORID_CORE_24K:
+   return MIPS_REVISION_SCON_SOCIT;
+
+   case MIPS_REVISION_CORID_CORE_FPGA3:
+   case MIPS_REVISION_CORID_CORE_FPGA4:
+   case MIPS_REVISION_CORID_CORE_FPGA5:
+   case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+   default:
+   return MIPS_REVISION_SCON_ROCIT;
+   }
+}
 
-static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
+static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size,
+enum mem_map map)
 {
unsigned long size_preio;
unsigned entries;
@@ -39,11 +84,47 @@ static unsigned __init gen_fdt_mem_array(__be32 *mem_array, 
unsigned long size)
 * DDR but limits it to 2GB.
 */
mem_array[1] = cpu_to_be32(size);
+   goto done;
+   }
+
+   size_preio = min_t(unsigned long, size, SZ_256M);
+   mem_array[1] = cpu_to_be32(size_preio);
+   size -= size_preio;
+   if (!size)
+   goto done;
+
+   if (map == MEM_MAP_V2) {
+   /*
+* We have a flat 32 bit physical memory map with DDR filling
+* all 4GB of the memory map, apart from the I/O region which
+* obscures 256MB from 0x1000-0x1fff.
+*
+* Therefore we discard the 256MB behind the I/O region.
+*/
+   if (size <= SZ_256M)
+   goto done;
+   size -= SZ_256M;
+
+   /* Make use of the memory following the I/O region */
+   entries++;
+   mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_512M);
+   mem_array[3] = cpu_to_be32(size);
} else {
-   size_preio = min_t(unsigned long, size, SZ_256M);
-   mem_array[1] = cpu_to_be32(size_preio);
+   /*
+* We have a 32 bit physical memory map with a 2GB DDR region
+* aliased in the upper & lower halves of it. The I/O region
+* obscures 256MB from 0x1000-0x1fff in the low alias
+  

Re: [PATCH] drm/tegra: Expose color key and plane blending controls to userspace

[Thierry Reding]

On Fri, Sep 02, 2016 at 05:32:19PM +0200, Thierry Reding wrote:
> On Fri, Sep 02, 2016 at 12:33:42PM +0300, Dmitry Osipenko wrote:
> > Chromakey is a simple way of video overlay overlap implementation. This
> > patch adds 2 new IOCTL's: first - sets color key and is common across of
> > all Tegra SoC's, second - sets plane blending controls and allows to
> > utilize the color key, this one is exclusive to Tegra20/30.
> > 
> > Signed-off-by: Dmitry Osipenko 
> > ---
> >  drivers/gpu/drm/tegra/dc.c   | 150 +---
> >  drivers/gpu/drm/tegra/dc.h   |   6 ++
> >  drivers/gpu/drm/tegra/drm.c  | 159 
> > +++
> >  drivers/gpu/drm/tegra/drm.h  |  14 
> >  include/uapi/drm/tegra_drm.h |  34 +
> >  5 files changed, 337 insertions(+), 26 deletions(-)
> 
> I think these are really nice features to have, but these would need to
> be exposed as properties, rather than custom driver-specific IOCTLs. It
> seems to me like the colorkey feature could be implemented in much the
> same way as in the Armada, RCar and Nouveau drivers.
> 
> As for the blending options, I think they should be exposed in terms of
> the zpos property, to allow generic userspace to make use of them. Also
> can you explain why this needs to be exclusive to Tegra20 and Tegra30?

Ah... I just realized that the blending interface changed on Tegra124.
All the more reason to expose this more generically, that way we can
hide the differences between a property and support the same interface
across all generations of Tegra.

Also see this:


https://chromium.googlesource.com/chromiumos/third_party/kernel/+/de9295aabdb7f80555c9b77b29ac77bcdac3280b

Thierry


signature.asc
Description: PGP signature

[PATCH 04/12] MIPS: Malta: Allow PCI devices DMA to lower 2GB physical

[Paul Burton]

Set the PCI_BAR0 register in all configurations such that PCI devices
can perform DMA to all of the bottom 2GB of the physical address space.
This is imperfect if we make use of the legacy Malta memory map, but it
is an improvement on the inconsistent values setup before.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-init.c | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index dc2c521..0f3b881 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -242,23 +243,19 @@ mips_pci_controller:
  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 #endif
-#ifndef CONFIG_EVA
-   /* Fix up target memory mapping.  */
-   MSC_READ(MSC01_PCI_BAR0, mask);
-   MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
-#else
+
/*
 * Setup the Malta max (2GB) memory for PCI DMA in host bridge
-* in transparent addressing mode, starting from 0x8000.
+* in transparent addressing mode.
 */
-   mask = PHYS_OFFSET | (1<<3);
+   mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
MSC_WRITE(MSC01_PCI_BAR0, mask);
-
-   mask = PHYS_OFFSET;
MSC_WRITE(MSC01_PCI_HEAD4, mask);
+
+   mask &= MSC01_PCI_BAR0_SIZE_MSK;
MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
-#endif
+
/* Don't handle target retries indefinitely.  */
if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
MSC01_PCI_CFG_MAXRTRY_MSK)
-- 
2.9.3

[PATCH 02/12] irqchip: i8259: Allow platforms to override poll function

[Paul Burton]

The default i8259 polling function (i8259_irq) is nicely generic but is
fairly costly. Platforms often provide an alternative means of polling
for an i8259 interrupt, and when using the i8259 without device tree
have typically just chained its parent interrupt to their own handler
function. In order to allow for platform-specific polling functions to
be used in cases where the driver is probed via device tree, provide an
i8259_set_poll function that accepts a pointer to an alternative poll
function that will override the default.

Signed-off-by: Paul Burton 
---

 arch/mips/include/asm/i8259.h | 11 +++
 drivers/irqchip/irq-i8259.c   |  8 +++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index a7fbcd6..b27fcc4 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -43,6 +43,17 @@ extern void make_8259A_irq(unsigned int irq);
 extern void init_i8259_irqs(void);
 extern int i8259_of_init(struct device_node *node, struct device_node *parent);
 
+/**
+ * i8159_set_poll() - Override the i8259 polling function
+ * @poll: pointer to platform-specific polling function
+ *
+ * Call this to override the generic i8259 polling function, which directly
+ * accesses i8259 registers, with a platform specific one which may be faster
+ * in cases where hardware provides a more optimal means of polling for an
+ * interrupt.
+ */
+extern void i8259_set_poll(int (*poll)(void));
+
 /*
  * Do the traditional i8259 interrupt polling thing.  This is for the few
  * cases where no better interrupt acknowledge method is available and we
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 85897fd..1f4a344 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -38,6 +38,7 @@ static void disable_8259A_irq(struct irq_data *d);
 static void enable_8259A_irq(struct irq_data *d);
 static void mask_and_ack_8259A(struct irq_data *d);
 static void init_8259A(int auto_eoi);
+static int (*i8259_poll)(void) = i8259_irq;
 
 static struct irq_chip i8259A_chip = {
.name   = "XT-PIC",
@@ -51,6 +52,11 @@ static struct irq_chip i8259A_chip = {
  * 8259A PIC functions to handle ISA devices:
  */
 
+void i8259_set_poll(int (*poll)(void))
+{
+   i8259_poll = poll;
+}
+
 /*
  * This contains the irq mask for both 8259A irq controllers,
  */
@@ -355,7 +361,7 @@ void __init init_i8259_irqs(void)
 static void i8259_irq_dispatch(struct irq_desc *desc)
 {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
-   int hwirq = i8259_irq();
+   int hwirq = i8259_poll();
unsigned int irq;
 
if (hwirq < 0)
-- 
2.9.3

[PATCH 01/12] irqchip: i8259: Add domain before mapping parent irq

[Paul Burton]

Mapping the parent IRQ will use a virq number which may conflict with
the hardcoded I8259A_IRQ_BASE..I8259A_IRQ_BASE+15 range that the i8259
driver expects to be free. If this occurs then we'll hit errors when
adding the i8259 IRQ domain, since one of its virq numbers will already
be in use.

Avoid this by adding the i8259 domain before mapping the parent IRQ,
such that the i8259 virq numbers become used before the parent interrupt
controller gets a chance to use any of them.

Signed-off-by: Paul Burton 
---

 drivers/irqchip/irq-i8259.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 6b304eb..85897fd 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -370,13 +370,15 @@ int __init i8259_of_init(struct device_node *node, struct 
device_node *parent)
struct irq_domain *domain;
unsigned int parent_irq;
 
+   domain = __init_i8259_irqs(node);
+
parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq) {
pr_err("Failed to map i8259 parent IRQ\n");
+   irq_domain_remove(domain);
return -ENODEV;
}
 
-   domain = __init_i8259_irqs(node);
irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
 domain);
return 0;
-- 
2.9.3

[PATCH 00/12] Partial MIPS Malta DT conversion

[Paul Burton]

This series begins converting the MIPS Malta board to use device tree to
probe its various devices & peripherals, with the eventual goal of
including Malta support in generic kernels.

In terms of use the only change should be that kernels will
automatically make use of more than 256MB DDR when built for 64 bit, or
32 bit with highmem enabled.

The series leaves Malta with a significant amount less platform code and
thus closer to being ready for inclusion in a generic MIPS kernel.

Applies atop v4.8-rc4.

Paul Burton (12):
  irqchip: i8259: Add domain before mapping parent irq
  irqchip: i8259: Allow platforms to override poll function
  irqchip: i8259: Remove unused i8259A_irq_pending
  MIPS: Malta: Allow PCI devices DMA to lower 2GB physical
  MIPS: Malta: Use all available DDR by default
  MIPS: Malta: Probe interrupt controllers via DT
  MIPS: Malta: Probe RTC via DT
  MIPS: Malta: Probe pflash via DT
  MIPS: Malta: Use syscon-reboot driver to reboot
  MIPS: Malta: Remove custom halt implementation
  power: reset: Add Intel PIIX4 poweroff driver
  MIPS: Malta: Use PIIX4 poweroff driver to power down

 arch/mips/Kconfig   |   7 +-
 arch/mips/boot/dts/mti/malta.dts|  93 ++
 arch/mips/configs/malta_defconfig   |   5 +-
 arch/mips/configs/malta_kvm_defconfig   |   5 +-
 arch/mips/configs/malta_kvm_guest_defconfig |   5 +-
 arch/mips/configs/malta_qemu_32r6_defconfig |   3 +
 arch/mips/configs/maltaaprp_defconfig   |   3 +
 arch/mips/configs/maltasmvp_defconfig   |   3 +
 arch/mips/configs/maltasmvp_eva_defconfig   |   3 +
 arch/mips/configs/maltaup_defconfig |   3 +
 arch/mips/configs/maltaup_xpa_defconfig |   5 +-
 arch/mips/include/asm/i8259.h   |  12 +-
 arch/mips/mti-malta/Makefile|   3 -
 arch/mips/mti-malta/malta-dtshim.c  | 187 +++-
 arch/mips/mti-malta/malta-init.c|  17 ++-
 arch/mips/mti-malta/malta-int.c |  96 +-
 arch/mips/mti-malta/malta-platform.c|  65 --
 arch/mips/mti-malta/malta-pm.c  |  96 --
 arch/mips/mti-malta/malta-reset.c   |  47 ---
 drivers/irqchip/irq-i8259.c |  30 ++---
 drivers/power/reset/Kconfig |   9 ++
 drivers/power/reset/Makefile|   1 +
 drivers/power/reset/piix4-poweroff.c| 103 +++
 23 files changed, 452 insertions(+), 349 deletions(-)
 delete mode 100644 arch/mips/mti-malta/malta-pm.c
 delete mode 100644 arch/mips/mti-malta/malta-reset.c
 create mode 100644 drivers/power/reset/piix4-poweroff.c

-- 
2.9.3

[PATCH 06/12] MIPS: Malta: Probe interrupt controllers via DT

[Paul Burton]

Probe the CPU, GIC & i8259 interrupt controllers present in the Malta
system using device tree. This enables interrupts to be provided to
devices using device tree as they are moved over to being probed using
it.

Since Malta is very configurable it's unknown whether a GIC will be
present at compile time. In order to support both cases the
malta_dt_shim code is added in order to detect whether a GIC is present,
adjusting the DT to route interrupts correctly and nop out the GIC node
if no GIC is found.

Signed-off-by: Paul Burton 
---

 arch/mips/Kconfig  |  1 +
 arch/mips/boot/dts/mti/malta.dts   | 41 
 arch/mips/mti-malta/malta-dtshim.c | 78 +++
 arch/mips/mti-malta/malta-int.c| 96 ++
 4 files changed, 125 insertions(+), 91 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2638856..d875a5a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -478,6 +478,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_RELOCATABLE
select USE_OF
+   select LIBFDT
select ZONE_DMA32 if 64BIT
select BUILTIN_DTB
select LIBFDT
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index b18c466..af765af 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -1,5 +1,8 @@
 /dts-v1/;
 
+#include 
+#include 
+
 /memreserve/ 0x 0x1000;/* YAMON exception vectors */
 /memreserve/ 0x1000 0x000ef000;/* YAMON */
 /memreserve/ 0x000f 0x0001;/* PIIX4 ISA memory */
@@ -8,4 +11,42 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,malta";
+
+   cpu_intc: interrupt-controller {
+   compatible = "mti,cpu-interrupt-controller";
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   };
+
+   gic: interrupt-controller@1bdc {
+   compatible = "mti,gic";
+   reg = <0x1bdc 0x2>;
+
+   interrupt-controller;
+   #interrupt-cells = <3>;
+
+   /*
+* Declare the interrupt-parent even though the mti,gic
+* binding doesn't require it, such that the kernel can
+* figure out that cpu_intc is the root interrupt
+* controller & should be probed first.
+*/
+   interrupt-parent = <_intc>;
+
+   timer {
+   compatible = "mti,gic-timer";
+   interrupts = ;
+   };
+   };
+
+   i8259: interrupt-controller@20 {
+   compatible = "intel,i8259";
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = ;
+   };
 };
diff --git a/arch/mips/mti-malta/malta-dtshim.c 
b/arch/mips/mti-malta/malta-dtshim.c
index 5d37b7e..c398582 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -16,6 +16,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 
 #define ROCIT_REG_BASE 0x1f403000
@@ -225,6 +228,80 @@ static void __init append_memory(void *fdt, int root_off)
panic("Unable to set linux,usable-memory property: %d", err);
 }
 
+static void __init remove_gic(void *fdt)
+{
+   int err, gic_off, i8259_off, cpu_off;
+   void __iomem *biu_base;
+   uint32_t cpu_phandle, sc_cfg;
+
+   /* if we have a CM which reports a GIC is present, leave the DT alone */
+   err = mips_cm_probe();
+   if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
+   return;
+
+   if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
+   /*
+* On systems using the RocIT system controller a GIC may be
+* present without a CM. Detect whether that is the case.
+*/
+   biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
+   MSC01_BIU_ADDRSPACE_SZ);
+   sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
+   if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) {
+   /* enable the GIC at the system controller level */
+   sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF);
+   __raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
+   return;
+   }
+   }
+
+   gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
+   if (gic_off < 0) {
+   pr_warn("malta-dtshim: unable to find DT GIC node: %d\n",
+   gic_off);
+   return;
+   }
+
+   err = fdt_nop_node(fdt, gic_off);
+   if (err)
+   pr_warn("malta-dtshim: unable to nop GIC node\n");
+
+   i8259_off = fdt_node_offset_by_compatible(fdt, -1, 

[PATCH 03/12] irqchip: i8259: Remove unused i8259A_irq_pending

[Paul Burton]

The i8259A_irq_pending function is unused. Remove the dead code.

Signed-off-by: Paul Burton 
---

 arch/mips/include/asm/i8259.h |  1 -
 drivers/irqchip/irq-i8259.c   | 18 --
 2 files changed, 19 deletions(-)

diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index b27fcc4..32229c7 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -37,7 +37,6 @@
 
 extern raw_spinlock_t i8259A_lock;
 
-extern int i8259A_irq_pending(unsigned int irq);
 extern void make_8259A_irq(unsigned int irq);
 
 extern void init_i8259_irqs(void);
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 1f4a344..1aec12c 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -95,24 +95,6 @@ static void enable_8259A_irq(struct irq_data *d)
raw_spin_unlock_irqrestore(_lock, flags);
 }
 
-int i8259A_irq_pending(unsigned int irq)
-{
-   unsigned int mask;
-   unsigned long flags;
-   int ret;
-
-   irq -= I8259A_IRQ_BASE;
-   mask = 1 << irq;
-   raw_spin_lock_irqsave(_lock, flags);
-   if (irq < 8)
-   ret = inb(PIC_MASTER_CMD) & mask;
-   else
-   ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
-   raw_spin_unlock_irqrestore(_lock, flags);
-
-   return ret;
-}
-
 void make_8259A_irq(unsigned int irq)
 {
disable_irq_nosync(irq);
-- 
2.9.3

[PATCH 05/12] MIPS: Malta: Use all available DDR by default

[Paul Burton]

Malta boards can have more than 256MB DDR available, but we have
previously only made use of up to 256MB (ie. the DDR accessible via
kseg0) by default, without the user manually specifying mem= kernel
parameters. This patch causes all available DDR, as reported by the
bootloader via the ememsize or memsize environment variables or
optionally on the command line, to be used when possible without the
user needing to manually provide the memory ranges.

Malta now has 2 subtly different memory maps which have to be taken into
account when setting this up. The original memory map (referred to by
the code as v1) has up to 2GB of DDR aliased in both the upper & lower
halves of the 32 bit physical address space, with a 256MB I/O region
obscuring 0x1000-0x1fff only in the lower alias. The revised v2
memory map is flat with up to 4GB DDR starting from 0x0, and the I/O
region obscures 256MB of DDR which becomes inacessible. The memory map
in use is indicated by a register provided by the rocit2 system
controller, which is checked in order to set up the kernels memory
ranges accordingly.

Signed-off-by: Paul Burton 
---

 arch/mips/mti-malta/malta-dtshim.c | 109 +++--
 1 file changed, 103 insertions(+), 6 deletions(-)

diff --git a/arch/mips/mti-malta/malta-dtshim.c 
b/arch/mips/mti-malta/malta-dtshim.c
index 151f488..5d37b7e 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -13,18 +13,63 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+#define ROCIT_REG_BASE 0x1f403000
+#define ROCIT_CONFIG_GEN1  (ROCIT_REG_BASE + 0x04)
+#define  ROCIT_CONFIG_GEN1_MEMMAP_SHIFT8
+#define  ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
+
 static unsigned char fdt_buf[16 << 10] __initdata;
 
 /* determined physical memory size, not overridden by command line args
 */
 extern unsigned long physical_memsize;
 
-#define MAX_MEM_ARRAY_ENTRIES 1
+enum mem_map {
+   MEM_MAP_V1 = 0,
+   MEM_MAP_V2,
+};
+
+#define MAX_MEM_ARRAY_ENTRIES 2
+
+static __init int malta_scon(void)
+{
+   int scon = MIPS_REVISION_SCONID;
+
+   if (scon != MIPS_REVISION_SCON_OTHER)
+   return scon;
+
+   switch (MIPS_REVISION_CORID) {
+   case MIPS_REVISION_CORID_QED_RM5261:
+   case MIPS_REVISION_CORID_CORE_LV:
+   case MIPS_REVISION_CORID_CORE_FPGA:
+   case MIPS_REVISION_CORID_CORE_FPGAR2:
+   return MIPS_REVISION_SCON_GT64120;
+
+   case MIPS_REVISION_CORID_CORE_EMUL_BON:
+   case MIPS_REVISION_CORID_BONITO64:
+   case MIPS_REVISION_CORID_CORE_20K:
+   return MIPS_REVISION_SCON_BONITO;
+
+   case MIPS_REVISION_CORID_CORE_MSC:
+   case MIPS_REVISION_CORID_CORE_FPGA2:
+   case MIPS_REVISION_CORID_CORE_24K:
+   return MIPS_REVISION_SCON_SOCIT;
+
+   case MIPS_REVISION_CORID_CORE_FPGA3:
+   case MIPS_REVISION_CORID_CORE_FPGA4:
+   case MIPS_REVISION_CORID_CORE_FPGA5:
+   case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+   default:
+   return MIPS_REVISION_SCON_ROCIT;
+   }
+}
 
-static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
+static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size,
+enum mem_map map)
 {
unsigned long size_preio;
unsigned entries;
@@ -39,11 +84,47 @@ static unsigned __init gen_fdt_mem_array(__be32 *mem_array, 
unsigned long size)
 * DDR but limits it to 2GB.
 */
mem_array[1] = cpu_to_be32(size);
+   goto done;
+   }
+
+   size_preio = min_t(unsigned long, size, SZ_256M);
+   mem_array[1] = cpu_to_be32(size_preio);
+   size -= size_preio;
+   if (!size)
+   goto done;
+
+   if (map == MEM_MAP_V2) {
+   /*
+* We have a flat 32 bit physical memory map with DDR filling
+* all 4GB of the memory map, apart from the I/O region which
+* obscures 256MB from 0x1000-0x1fff.
+*
+* Therefore we discard the 256MB behind the I/O region.
+*/
+   if (size <= SZ_256M)
+   goto done;
+   size -= SZ_256M;
+
+   /* Make use of the memory following the I/O region */
+   entries++;
+   mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_512M);
+   mem_array[3] = cpu_to_be32(size);
} else {
-   size_preio = min_t(unsigned long, size, SZ_256M);
-   mem_array[1] = cpu_to_be32(size_preio);
+   /*
+* We have a 32 bit physical memory map with a 2GB DDR region
+* aliased in the upper & lower halves of it. The I/O region
+* obscures 256MB from 0x1000-0x1fff in the low alias
+* but the 

Re: [PATCH] generic: Add the exception case checking routine for ppi interrupt

[Marc Zyngier]

On 02/09/16 14:08, Thomas Gleixner wrote:
> On Thu, 1 Sep 2016, Marc Zyngier wrote:
>> On 01/09/16 09:15, majun (F) wrote:
>> Well, this issue goes way beyond the hack you wanted to add to the
>> generic code, and it should probably be addressed in the GIC code
>> itself, as an implementation specific workaround. Without knowing the
>> details of the erratum, it is difficult to think of that would be
>> required. I can come up with something like this:
>>
>>  irqnr = gic_read_iar();
>>  if (unlikely(!is_enabled(irqnr))) {
>>  gic_write_eoir(irqnr);
>>  if (static_key_true(_deactivate))
>>  gic_write_dir(irqnr);
>>  set_pending(irqnr);
>>  continue;
>>  }
>>
>> Performance will suffer (an extra MMIO access on the fast path). If LPIs
>> are also affected, then the ITS code also needs to be involved, and
>> that's not going to be pretty either. This code will have to be enabled
>> at runtime, and handled like other erratum we have in this code.
> 
> So that's certainly a required workaround at the gic level. Though I really
> think that we should make handle_percpu_devid_irq robust against a spurious
> interrupt.
> 
>>  void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
>>  {
>> -struct irq_chip *chip = irq_desc_get_chip(desc);
>> -struct irqaction *action = desc->action;
>> -void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
>> +struct irq_chip *chip = NULL;
>> +struct irqaction *action;
>> +void *dev_id;
>>  irqreturn_t res;
>>  
>> +action = desc->action;
>> +
>> +/* Unexpected interrupt in some execption case
>> + * we just send eoi to end this interrupt
>> + */
>> +if (unlikely(!action)) {
>> +mask_irq(desc);
> 
> This is wrong. mask_irq() does not work for percpu interrupts. Aside of that
> this completely lacks any debug information which tells us that there is
> something wrong in the system. I'm going to apply the patch below for
> robustness sake.
> 
> Thanks,
> 
>   tglx
> 
> 8<--
> Subject: genirq: Robustify handle_percpu_devid_irq()
> From: Thomas Gleixner 
> Date: Fri, 02 Sep 2016 14:45:19 +0200
> 
> The percpu_devid handler is not robust against spurious interrupts. If a
> spurious interrupt happens and no action is installed then the handler crashes
> with a NULL pointer dereference.
> 
> Add a sanity check for this and log the wreckage once in dmesg.
> 
> Reported-by: Majun 
> Signed-off-by: Thomas Gleixner 

Looks fine to me.

Acked-by: Marc Zyngier 

M.
-- 
Jazz is not dead. It just smells funny...

Re: [writeback] 8bc4ad9498: INFO: suspicious RCU usage. ]

[Jens Axboe]

On 09/02/2016 09:36 AM, Paul E. McKenney wrote:

On Fri, Sep 02, 2016 at 10:56:22AM -0400, Tejun Heo wrote:

(cc'ing Paul, hi!)

Hello,

On Thu, Sep 01, 2016 at 02:13:34PM -0600, Jens Axboe wrote:

On 09/01/2016 04:21 AM, kernel test robot wrote:

[7.323356] cdrom: Uniform CD-ROM driver Revision: 3.20
[7.334239]
[7.337256] ===
[7.340532] [ INFO: suspicious RCU usage. ]
[7.342419] 4.8.0-rc4-8-g8bc4ad9 #1 Not tainted
[7.347065] ---
[7.350132] include/linux/cgroup.h:435 suspicious rcu_dereference_check() 
usage!


Lockdep does not believe that any locks are held, correct?


Which is correct, the queue lock has been dropped at this point.


[7.410074] Call Trace:
[7.411328]  [] dump_stack+0x82/0xb8
[7.413982]  [] lockdep_rcu_suspicious+0xf7/0x100
[7.415828]  [] bio_blkcg+0x89/0x93
[7.417336]  [] check_blkcg_changed+0x58/0x1b8
[7.428722]  [] cfq_set_request+0xd1/0x2a3
[7.439690]  [] elv_set_request+0x1f/0x24
[7.442157]  [] get_request+0x38f/0x77f
[7.447449]  [] blk_get_request+0x65/0xa8
[7.449868]  [] ide_cd_queue_pc+0x76/0x19d
[7.453757]  [] cdrom_check_status+0x51/0x53
[7.455372]  [] ide_cdrom_check_events_real+0x20/0x3f
[7.457294]  [] cdrom_update_events+0x18/0x21
[7.458987]  [] cdrom_check_events+0x12/0x1f
[7.460713]  [] idecd_check_events+0x1c/0x1e
[7.462393]  [] disk_check_events+0x47/0x103
[7.464129]  [] disk_events_workfn+0x1c/0x1e
[7.465844]  [] process_one_work+0x272/0x4ee
[7.467462]  [] worker_thread+0x1eb/0x2c9


The warning is from

#define task_css_set_check(task, __c)   \
rcu_dereference_check((task)->cgroups,   \
lockdep_is_held(_mutex) ||   \
lockdep_is_held(_set_lock) ||   \
((task)->flags & PF_EXITING) || (__c))

which is used by bio_blkcg() which is called by the following code in
check_blkcg_changed().

rcu_read_lock();
serial_nr = bio_blkcg(bio)->css.serial_nr;
rcu_read_unlock();

So, I have no idea.  It looks like rcu_dereference_check() is being
called with rcu read locked but still triggering suspicious RCU usage
warning.


Perhaps there is an rcu_read_unlock() somewhere on the code path?


The code hasn't changed for quite a while now, so it's also really
weird that it's triggering now.  Paul, does anything ring a bell?


I have not see something like this recently.


The question is if it's really new, or just re-triggering because the
writeback branch changes that function? It's further down though, so
can't impact the RCU section. And the writeback changes don't have any
RCU code in them...


--
Jens Axboe

Re: [writeback] 8bc4ad9498: INFO: suspicious RCU usage. ]

[Jens Axboe]

On 09/02/2016 09:36 AM, Paul E. McKenney wrote:

On Fri, Sep 02, 2016 at 10:56:22AM -0400, Tejun Heo wrote:

(cc'ing Paul, hi!)

Hello,

On Thu, Sep 01, 2016 at 02:13:34PM -0600, Jens Axboe wrote:

On 09/01/2016 04:21 AM, kernel test robot wrote:

[7.323356] cdrom: Uniform CD-ROM driver Revision: 3.20
[7.334239]
[7.337256] ===
[7.340532] [ INFO: suspicious RCU usage. ]
[7.342419] 4.8.0-rc4-8-g8bc4ad9 #1 Not tainted
[7.347065] ---
[7.350132] include/linux/cgroup.h:435 suspicious rcu_dereference_check() 
usage!


Lockdep does not believe that any locks are held, correct?


Which is correct, the queue lock has been dropped at this point.


[7.410074] Call Trace:
[7.411328]  [] dump_stack+0x82/0xb8
[7.413982]  [] lockdep_rcu_suspicious+0xf7/0x100
[7.415828]  [] bio_blkcg+0x89/0x93
[7.417336]  [] check_blkcg_changed+0x58/0x1b8
[7.428722]  [] cfq_set_request+0xd1/0x2a3
[7.439690]  [] elv_set_request+0x1f/0x24
[7.442157]  [] get_request+0x38f/0x77f
[7.447449]  [] blk_get_request+0x65/0xa8
[7.449868]  [] ide_cd_queue_pc+0x76/0x19d
[7.453757]  [] cdrom_check_status+0x51/0x53
[7.455372]  [] ide_cdrom_check_events_real+0x20/0x3f
[7.457294]  [] cdrom_update_events+0x18/0x21
[7.458987]  [] cdrom_check_events+0x12/0x1f
[7.460713]  [] idecd_check_events+0x1c/0x1e
[7.462393]  [] disk_check_events+0x47/0x103
[7.464129]  [] disk_events_workfn+0x1c/0x1e
[7.465844]  [] process_one_work+0x272/0x4ee
[7.467462]  [] worker_thread+0x1eb/0x2c9


The warning is from

#define task_css_set_check(task, __c)   \
rcu_dereference_check((task)->cgroups,   \
lockdep_is_held(_mutex) ||   \
lockdep_is_held(_set_lock) ||   \
((task)->flags & PF_EXITING) || (__c))

which is used by bio_blkcg() which is called by the following code in
check_blkcg_changed().

rcu_read_lock();
serial_nr = bio_blkcg(bio)->css.serial_nr;
rcu_read_unlock();

So, I have no idea.  It looks like rcu_dereference_check() is being
called with rcu read locked but still triggering suspicious RCU usage
warning.


Perhaps there is an rcu_read_unlock() somewhere on the code path?


The code hasn't changed for quite a while now, so it's also really
weird that it's triggering now.  Paul, does anything ring a bell?


I have not see something like this recently.


The question is if it's really new, or just re-triggering because the
writeback branch changes that function? It's further down though, so
can't impact the RCU section. And the writeback changes don't have any
RCU code in them...


--
Jens Axboe

Re: [PATCH] generic: Add the exception case checking routine for ppi interrupt

[Marc Zyngier]

On 02/09/16 14:08, Thomas Gleixner wrote:
> On Thu, 1 Sep 2016, Marc Zyngier wrote:
>> On 01/09/16 09:15, majun (F) wrote:
>> Well, this issue goes way beyond the hack you wanted to add to the
>> generic code, and it should probably be addressed in the GIC code
>> itself, as an implementation specific workaround. Without knowing the
>> details of the erratum, it is difficult to think of that would be
>> required. I can come up with something like this:
>>
>>  irqnr = gic_read_iar();
>>  if (unlikely(!is_enabled(irqnr))) {
>>  gic_write_eoir(irqnr);
>>  if (static_key_true(_deactivate))
>>  gic_write_dir(irqnr);
>>  set_pending(irqnr);
>>  continue;
>>  }
>>
>> Performance will suffer (an extra MMIO access on the fast path). If LPIs
>> are also affected, then the ITS code also needs to be involved, and
>> that's not going to be pretty either. This code will have to be enabled
>> at runtime, and handled like other erratum we have in this code.
> 
> So that's certainly a required workaround at the gic level. Though I really
> think that we should make handle_percpu_devid_irq robust against a spurious
> interrupt.
> 
>>  void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
>>  {
>> -struct irq_chip *chip = irq_desc_get_chip(desc);
>> -struct irqaction *action = desc->action;
>> -void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
>> +struct irq_chip *chip = NULL;
>> +struct irqaction *action;
>> +void *dev_id;
>>  irqreturn_t res;
>>  
>> +action = desc->action;
>> +
>> +/* Unexpected interrupt in some execption case
>> + * we just send eoi to end this interrupt
>> + */
>> +if (unlikely(!action)) {
>> +mask_irq(desc);
> 
> This is wrong. mask_irq() does not work for percpu interrupts. Aside of that
> this completely lacks any debug information which tells us that there is
> something wrong in the system. I'm going to apply the patch below for
> robustness sake.
> 
> Thanks,
> 
>   tglx
> 
> 8<--
> Subject: genirq: Robustify handle_percpu_devid_irq()
> From: Thomas Gleixner 
> Date: Fri, 02 Sep 2016 14:45:19 +0200
> 
> The percpu_devid handler is not robust against spurious interrupts. If a
> spurious interrupt happens and no action is installed then the handler crashes
> with a NULL pointer dereference.
> 
> Add a sanity check for this and log the wreckage once in dmesg.
> 
> Reported-by: Majun 
> Signed-off-by: Thomas Gleixner 

Looks fine to me.

Acked-by: Marc Zyngier 

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v5 2/4] ARM: dts: rockchip: update compatible strings for Rockchip efuse

[Heiko Stübner]

Am Donnerstag, 1. September 2016, 20:16:55 schrieb Finley Xiao:
> Signed-off-by: Finley Xiao 
> Reviewed-by: Heiko Stuebner 

due to the new compatible values, this would cause a regression (existing 
functionality breaking) when used without the efuse change, so I've put this 
patch into a branch for 4.10 with Doug's review, so that the code change is 
definitly existing by then.


Heiko

Re: [PATCH v5 2/4] ARM: dts: rockchip: update compatible strings for Rockchip efuse

[Heiko Stübner]

Am Donnerstag, 1. September 2016, 20:16:55 schrieb Finley Xiao:
> Signed-off-by: Finley Xiao 
> Reviewed-by: Heiko Stuebner 

due to the new compatible values, this would cause a regression (existing 
functionality breaking) when used without the efuse change, so I've put this 
patch into a branch for 4.10 with Doug's review, so that the code change is 
definitly existing by then.


Heiko