Re: [PATCH v3] powerpc/mm: Implemented default_hugepagesz verification for powerpc

[Aneesh Kumar K.V]

Victor Aoqui  writes:

> Implemented default hugepage size verification (default_hugepagesz=)
> in order to allow allocation of defined number of pages (hugepages=)
> only for supported hugepage sizes.
>
> Signed-off-by: Victor Aoqui 

I am still not sure about this. With current upstream we get

 PCI: Probing PCI hardware 
 PCI: Probing PCI hardware done 
  
 HugeTLB: unsupported default_hugepagesz 2097152. Reverting to 16777216 
  
 HugeTLB registered 16.0 MiB page size, pre-allocated 0 pages   
  
 HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages  

That warning is added by

d715cf804a0318e83c75c0a7abd1a4b9ce13e8da

Which should be good enough right ?

-aneesh

Re: [PATCH v3] powerpc/mm: Implemented default_hugepagesz verification for powerpc

[Aneesh Kumar K.V]

Victor Aoqui  writes:

> Implemented default hugepage size verification (default_hugepagesz=)
> in order to allow allocation of defined number of pages (hugepages=)
> only for supported hugepage sizes.
>
> Signed-off-by: Victor Aoqui 

I am still not sure about this. With current upstream we get

 PCI: Probing PCI hardware 
 PCI: Probing PCI hardware done 
  
 HugeTLB: unsupported default_hugepagesz 2097152. Reverting to 16777216 
  
 HugeTLB registered 16.0 MiB page size, pre-allocated 0 pages   
  
 HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages  

That warning is added by

d715cf804a0318e83c75c0a7abd1a4b9ce13e8da

Which should be good enough right ?

-aneesh

Re: [PATCH v2 17/25] mtd: nand: qcom: add BAM DMA descriptor handling

[Archit Taneja]

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA flag is dependent upon the type of channel.

2. For ADM DMA, the descriptor is being formed for every DMA
request so its sgl count will be always 1 while in BAM DMA, the
clubbing of descriptor is being done to increase throughput.

3. ADM uses only one channel while in BAM, data descriptors
will be submitted to tx channel (for write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.


Reviewed-by: Archit Taneja 



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 143 ++
  1 file changed, 130 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index fc29c97..589108b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -209,14 +209,23 @@ struct bam_transaction {
   * This data type corresponds to the nand dma descriptor
   * @list - list for desc_info
   * @dir - DMA transfer direction
- * @sgl - sgl which will be used for single sgl dma descriptor
+ * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used 
by
+ *   ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
   * @dma_desc - low level dma engine descriptor
   */
  struct desc_info {
struct list_head node;
  
  	enum dma_data_direction dir;

-   struct scatterlist sgl;
+   union {
+   struct scatterlist adm_sgl;
+   struct {
+   struct scatterlist *bam_sgl;
+   int sgl_cnt;
+   };
+   };
struct dma_async_tx_descriptor *dma_desc;
  };
  
@@ -580,9 +589,77 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)

nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
  }
  
-static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,

-int reg_off, const void *vaddr, int size,
-bool flow_control)
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+ struct dma_chan *chan,
+ unsigned long flags)
+{
+   struct desc_info *desc;
+   struct scatterlist *sgl;
+   unsigned int sgl_cnt;
+   int ret;
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+   enum dma_transfer_direction dir_eng;
+   struct dma_async_tx_descriptor *dma_desc;
+
+   desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+   if (!desc)
+   return -ENOMEM;
+
+   if (chan == nandc->cmd_chan) {
+   sgl = _txn->cmd_sgl[bam_txn->cmd_sgl_start];
+   sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+   bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+   dir_eng = DMA_MEM_TO_DEV;
+   desc->dir = DMA_TO_DEVICE;
+   } else if (chan == nandc->tx_chan) {
+   sgl = _txn->data_sgl[bam_txn->tx_sgl_start];
+   sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+   bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+   dir_eng = DMA_MEM_TO_DEV;
+   desc->dir = DMA_TO_DEVICE;
+   } else {
+   sgl = _txn->data_sgl[bam_txn->rx_sgl_start];
+   sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+   bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+   desc->dir = DMA_FROM_DEVICE;
+   dir_eng = DMA_DEV_TO_MEM;
+   }
+
+   sg_mark_end(sgl + sgl_cnt - 1);
+   ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+   if (ret == 0) {
+   dev_err(nandc->dev, "failure in mapping desc\n");
+   kfree(desc);
+   return -ENOMEM;
+   }
+
+   desc->sgl_cnt = sgl_cnt;
+   desc->bam_sgl = sgl;
+
+   dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+  flags);
+
+   if (!dma_desc) {
+   dev_err(nandc->dev, "failure in prep desc\n");
+   kfree(desc);
+   return -EINVAL;
+   }
+
+   desc->dma_desc = dma_desc;
+
+   list_add_tail(>node, >desc_list);
+
+   return 0;
+}
+
+static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+int reg_off, const void *vaddr, int size,
+bool 

Re: [PATCH v2 17/25] mtd: nand: qcom: add BAM DMA descriptor handling

[Archit Taneja]

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA flag is dependent upon the type of channel.

2. For ADM DMA, the descriptor is being formed for every DMA
request so its sgl count will be always 1 while in BAM DMA, the
clubbing of descriptor is being done to increase throughput.

3. ADM uses only one channel while in BAM, data descriptors
will be submitted to tx channel (for write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.


Reviewed-by: Archit Taneja 



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 143 ++
  1 file changed, 130 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index fc29c97..589108b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -209,14 +209,23 @@ struct bam_transaction {
   * This data type corresponds to the nand dma descriptor
   * @list - list for desc_info
   * @dir - DMA transfer direction
- * @sgl - sgl which will be used for single sgl dma descriptor
+ * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used 
by
+ *   ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
   * @dma_desc - low level dma engine descriptor
   */
  struct desc_info {
struct list_head node;
  
  	enum dma_data_direction dir;

-   struct scatterlist sgl;
+   union {
+   struct scatterlist adm_sgl;
+   struct {
+   struct scatterlist *bam_sgl;
+   int sgl_cnt;
+   };
+   };
struct dma_async_tx_descriptor *dma_desc;
  };
  
@@ -580,9 +589,77 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)

nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
  }
  
-static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,

-int reg_off, const void *vaddr, int size,
-bool flow_control)
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+ struct dma_chan *chan,
+ unsigned long flags)
+{
+   struct desc_info *desc;
+   struct scatterlist *sgl;
+   unsigned int sgl_cnt;
+   int ret;
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+   enum dma_transfer_direction dir_eng;
+   struct dma_async_tx_descriptor *dma_desc;
+
+   desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+   if (!desc)
+   return -ENOMEM;
+
+   if (chan == nandc->cmd_chan) {
+   sgl = _txn->cmd_sgl[bam_txn->cmd_sgl_start];
+   sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+   bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+   dir_eng = DMA_MEM_TO_DEV;
+   desc->dir = DMA_TO_DEVICE;
+   } else if (chan == nandc->tx_chan) {
+   sgl = _txn->data_sgl[bam_txn->tx_sgl_start];
+   sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+   bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+   dir_eng = DMA_MEM_TO_DEV;
+   desc->dir = DMA_TO_DEVICE;
+   } else {
+   sgl = _txn->data_sgl[bam_txn->rx_sgl_start];
+   sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+   bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+   desc->dir = DMA_FROM_DEVICE;
+   dir_eng = DMA_DEV_TO_MEM;
+   }
+
+   sg_mark_end(sgl + sgl_cnt - 1);
+   ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+   if (ret == 0) {
+   dev_err(nandc->dev, "failure in mapping desc\n");
+   kfree(desc);
+   return -ENOMEM;
+   }
+
+   desc->sgl_cnt = sgl_cnt;
+   desc->bam_sgl = sgl;
+
+   dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+  flags);
+
+   if (!dma_desc) {
+   dev_err(nandc->dev, "failure in prep desc\n");
+   kfree(desc);
+   return -EINVAL;
+   }
+
+   desc->dma_desc = dma_desc;
+
+   list_add_tail(>node, >desc_list);
+
+   return 0;
+}
+
+static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+int reg_off, const void *vaddr, int size,
+bool flow_control)
  {
struct desc_info 

[PATCH v4 1/2] dt-bindings: gpio: davinci: Add keystone-k2g compatible

[Keerthy]

The patch adds keystone-k2g compatible, specific properties and
an example. The patch also adds the details of supported SoCs
for each compatible.

Signed-off-by: Keerthy 
Acked-by: Rob Herring 
---

Changes in v4:

  * Changed documentation links.
  * Added Rob's Ack.
  * Replaced keystone-k2g with 66AK2G
  * Corrected the $Subject
  * Changed compatible to ti,k2g-gpio

Changes in v3:

  * Added details about family of SoCs corresponding to compatibles.

 .../devicetree/bindings/gpio/gpio-davinci.txt  | 91 +-
 1 file changed, 89 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 
b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 5079ba7..5ad08b2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
 Davinci/Keystone GPIO controller bindings
 
 Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+   "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+   66AK2E SoCs
+   "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
 
 - reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
 - ti,ngpio: The number of GPIO pins supported.
 
 - ti,davinci-gpio-unbanked: The number of GPIOs that have an individual 
interrupt
-line to processor.
+   line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+  the appropriate clock bindings consumer usage in,
+
+  Documentation/devicetree/bindings/clock/keystone-gate.txt
+for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+  Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
 
 The GPIO controller also acts as an interrupt controller. It uses the default
 two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
 };
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+   compatible = "ti,keystone-gpio";
+   reg = <0x0260bf00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   /* HW Interrupts mapped to GPIO pins */
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   clocks = <>;
+   clock-names = "gpio";
+   ti,ngpio = <32>;
+   ti,davinci-gpio-unbanked = <32>;
+};
-- 
1.9.1

[PATCH v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
functional. 9 banks with 16 gpios making a total of 144. The second
instance has only the GPIO0:GPIO67 functional and rest are marked
reserved.

Signed-off-by: Keerthy 
Acked-by: Linus Walleij 
---

Changes in v4:

  * Couple of rephrasing in the commit log.
  * Changed compatible to ti,k2g-gpio.

Changes in v2:

  * Split the documentation part into a separate patch.

 arch/arm/boot/dts/keystone-k2g.dtsi | 42 +
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa..4eb1ba8 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 
 / {
compatible = "ti,k2g","ti,keystone";
@@ -168,5 +169,46 @@
#reset-cells = <2>;
};
};
+
+   gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+   };
+
+   gpio1: gpio@260a000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x0260a000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <68>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001c 0x0>;
+   clock-names = "gpio";
+   };
};
 };
-- 
1.9.1

[PATCH v4 1/2] dt-bindings: gpio: davinci: Add keystone-k2g compatible

[Keerthy]

The patch adds keystone-k2g compatible, specific properties and
an example. The patch also adds the details of supported SoCs
for each compatible.

Signed-off-by: Keerthy 
Acked-by: Rob Herring 
---

Changes in v4:

  * Changed documentation links.
  * Added Rob's Ack.
  * Replaced keystone-k2g with 66AK2G
  * Corrected the $Subject
  * Changed compatible to ti,k2g-gpio

Changes in v3:

  * Added details about family of SoCs corresponding to compatibles.

 .../devicetree/bindings/gpio/gpio-davinci.txt  | 91 +-
 1 file changed, 89 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 
b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 5079ba7..5ad08b2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
 Davinci/Keystone GPIO controller bindings
 
 Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+   "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+   66AK2E SoCs
+   "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
 
 - reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
 - ti,ngpio: The number of GPIO pins supported.
 
 - ti,davinci-gpio-unbanked: The number of GPIOs that have an individual 
interrupt
-line to processor.
+   line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+  the appropriate clock bindings consumer usage in,
+
+  Documentation/devicetree/bindings/clock/keystone-gate.txt
+for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+  Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
 
 The GPIO controller also acts as an interrupt controller. It uses the default
 two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
 };
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+   compatible = "ti,keystone-gpio";
+   reg = <0x0260bf00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   /* HW Interrupts mapped to GPIO pins */
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   clocks = <>;
+   clock-names = "gpio";
+   ti,ngpio = <32>;
+   ti,davinci-gpio-unbanked = <32>;
+};
-- 
1.9.1

[PATCH v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
functional. 9 banks with 16 gpios making a total of 144. The second
instance has only the GPIO0:GPIO67 functional and rest are marked
reserved.

Signed-off-by: Keerthy 
Acked-by: Linus Walleij 
---

Changes in v4:

  * Couple of rephrasing in the commit log.
  * Changed compatible to ti,k2g-gpio.

Changes in v2:

  * Split the documentation part into a separate patch.

 arch/arm/boot/dts/keystone-k2g.dtsi | 42 +
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa..4eb1ba8 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 
 / {
compatible = "ti,k2g","ti,keystone";
@@ -168,5 +169,46 @@
#reset-cells = <2>;
};
};
+
+   gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+   };
+
+   gpio1: gpio@260a000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x0260a000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <68>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001c 0x0>;
+   clock-names = "gpio";
+   };
};
 };
-- 
1.9.1

Re: [v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

On Friday 04 August 2017 11:15 AM, Keerthy wrote:
> 66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
> functional. 9 banks with 16 gpios making a total of 144. The second
> instance has only the GPIO0:GPIO67 functional and rest are marked
> reserved.

I will send with the $subject fixed please ignore this.


> 
> Signed-off-by: Keerthy 
> Acked-by: Linus Walleij 
> ---
> 
> Changes in v4:
> 
>   * Couple of rephrasing in the commit log.
>   * Changed compatible to ti,k2g-gpio.
> 
> Changes in v2:
> 
>   * Split the documentation part into a separate patch.
> 
>  arch/arm/boot/dts/keystone-k2g.dtsi | 42 
> +
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
> b/arch/arm/boot/dts/keystone-k2g.dtsi
> index bf4d1fa..4eb1ba8 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -15,6 +15,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  / {
>   compatible = "ti,k2g","ti,keystone";
> @@ -168,5 +169,46 @@
>   #reset-cells = <2>;
>   };
>   };
> +
> + gpio0: gpio@2603000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x02603000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <144>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001b 0x0>;
> + clock-names = "gpio";
> + };
> +
> + gpio1: gpio@260a000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x0260a000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <68>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001c 0x0>;
> + clock-names = "gpio";
> + };
>   };
>  };
> 

Re: [v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

On Friday 04 August 2017 11:15 AM, Keerthy wrote:
> 66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
> functional. 9 banks with 16 gpios making a total of 144. The second
> instance has only the GPIO0:GPIO67 functional and rest are marked
> reserved.

I will send with the $subject fixed please ignore this.


> 
> Signed-off-by: Keerthy 
> Acked-by: Linus Walleij 
> ---
> 
> Changes in v4:
> 
>   * Couple of rephrasing in the commit log.
>   * Changed compatible to ti,k2g-gpio.
> 
> Changes in v2:
> 
>   * Split the documentation part into a separate patch.
> 
>  arch/arm/boot/dts/keystone-k2g.dtsi | 42 
> +
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
> b/arch/arm/boot/dts/keystone-k2g.dtsi
> index bf4d1fa..4eb1ba8 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -15,6 +15,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  / {
>   compatible = "ti,k2g","ti,keystone";
> @@ -168,5 +169,46 @@
>   #reset-cells = <2>;
>   };
>   };
> +
> + gpio0: gpio@2603000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x02603000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <144>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001b 0x0>;
> + clock-names = "gpio";
> + };
> +
> + gpio1: gpio@260a000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x0260a000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <68>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001c 0x0>;
> + clock-names = "gpio";
> + };
>   };
>  };
> 

[v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
functional. 9 banks with 16 gpios making a total of 144. The second
instance has only the GPIO0:GPIO67 functional and rest are marked
reserved.

Signed-off-by: Keerthy 
Acked-by: Linus Walleij 
---

Changes in v4:

  * Couple of rephrasing in the commit log.
  * Changed compatible to ti,k2g-gpio.

Changes in v2:

  * Split the documentation part into a separate patch.

 arch/arm/boot/dts/keystone-k2g.dtsi | 42 +
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa..4eb1ba8 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 
 / {
compatible = "ti,k2g","ti,keystone";
@@ -168,5 +169,46 @@
#reset-cells = <2>;
};
};
+
+   gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+   };
+
+   gpio1: gpio@260a000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x0260a000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <68>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001c 0x0>;
+   clock-names = "gpio";
+   };
};
 };
-- 
1.9.1

[v4 1/2] dt-bindings: gpio: davinci: Add keystone-k2g compatible

[Keerthy]

The patch adds keystone-k2g compatible, specific properties and
an example. The patch also adds the details of supported SoCs
for each compatible.

Signed-off-by: Keerthy 
Acked-by: Rob Herring 
---

Changes in v4:

  * Changed documentation links.
  * Added Rob's Ack.
  * Replaced keystone-k2g with 66AK2G
  * Corrected the $Subject
  * Changed compatible to ti,k2g-gpio

Changes in v3:

  * Added details about family of SoCs corresponding to compatibles.

 .../devicetree/bindings/gpio/gpio-davinci.txt  | 91 +-
 1 file changed, 89 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 
b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 5079ba7..5ad08b2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
 Davinci/Keystone GPIO controller bindings
 
 Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+   "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+   66AK2E SoCs
+   "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
 
 - reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
 - ti,ngpio: The number of GPIO pins supported.
 
 - ti,davinci-gpio-unbanked: The number of GPIOs that have an individual 
interrupt
-line to processor.
+   line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+  the appropriate clock bindings consumer usage in,
+
+  Documentation/devicetree/bindings/clock/keystone-gate.txt
+for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+  Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
 
 The GPIO controller also acts as an interrupt controller. It uses the default
 two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
 };
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+   compatible = "ti,keystone-gpio";
+   reg = <0x0260bf00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   /* HW Interrupts mapped to GPIO pins */
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   clocks = <>;
+   clock-names = "gpio";
+   ti,ngpio = <32>;
+   ti,davinci-gpio-unbanked = <32>;
+};
-- 
1.9.1

[v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
functional. 9 banks with 16 gpios making a total of 144. The second
instance has only the GPIO0:GPIO67 functional and rest are marked
reserved.

Signed-off-by: Keerthy 
Acked-by: Linus Walleij 
---

Changes in v4:

  * Couple of rephrasing in the commit log.
  * Changed compatible to ti,k2g-gpio.

Changes in v2:

  * Split the documentation part into a separate patch.

 arch/arm/boot/dts/keystone-k2g.dtsi | 42 +
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa..4eb1ba8 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 
 / {
compatible = "ti,k2g","ti,keystone";
@@ -168,5 +169,46 @@
#reset-cells = <2>;
};
};
+
+   gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+   };
+
+   gpio1: gpio@260a000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x0260a000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <68>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001c 0x0>;
+   clock-names = "gpio";
+   };
};
 };
-- 
1.9.1

[v4 1/2] dt-bindings: gpio: davinci: Add keystone-k2g compatible

[Keerthy]

The patch adds keystone-k2g compatible, specific properties and
an example. The patch also adds the details of supported SoCs
for each compatible.

Signed-off-by: Keerthy 
Acked-by: Rob Herring 
---

Changes in v4:

  * Changed documentation links.
  * Added Rob's Ack.
  * Replaced keystone-k2g with 66AK2G
  * Corrected the $Subject
  * Changed compatible to ti,k2g-gpio

Changes in v3:

  * Added details about family of SoCs corresponding to compatibles.

 .../devicetree/bindings/gpio/gpio-davinci.txt  | 91 +-
 1 file changed, 89 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 
b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 5079ba7..5ad08b2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
 Davinci/Keystone GPIO controller bindings
 
 Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+   "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+   66AK2E SoCs
+   "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
 
 - reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
 - ti,ngpio: The number of GPIO pins supported.
 
 - ti,davinci-gpio-unbanked: The number of GPIOs that have an individual 
interrupt
-line to processor.
+   line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+  the appropriate clock bindings consumer usage in,
+
+  Documentation/devicetree/bindings/clock/keystone-gate.txt
+for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+  Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
 
 The GPIO controller also acts as an interrupt controller. It uses the default
 two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
 };
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+   compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+   reg = <0x02603000 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <144>;
+   ti,davinci-gpio-unbanked = <0>;
+   clocks = <_clks 0x001b 0x0>;
+   clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+   compatible = "ti,keystone-gpio";
+   reg = <0x0260bf00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   /* HW Interrupts mapped to GPIO pins */
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   clocks = <>;
+   clock-names = "gpio";
+   ti,ngpio = <32>;
+   ti,davinci-gpio-unbanked = <32>;
+};
-- 
1.9.1

Re: [v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

On Friday 04 August 2017 11:15 AM, Keerthy wrote:
> 66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
> functional. 9 banks with 16 gpios making a total of 144. The second
> instance has only the GPIO0:GPIO67 functional and rest are marked
> reserved.

Oops. I will send with the $subject fixed please ignore this.

> 
> Signed-off-by: Keerthy 
> Acked-by: Linus Walleij 
> ---
> 
> Changes in v4:
> 
>   * Couple of rephrasing in the commit log.
>   * Changed compatible to ti,k2g-gpio.
> 
> Changes in v2:
> 
>   * Split the documentation part into a separate patch.
> 
>  arch/arm/boot/dts/keystone-k2g.dtsi | 42 
> +
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
> b/arch/arm/boot/dts/keystone-k2g.dtsi
> index bf4d1fa..4eb1ba8 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -15,6 +15,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  / {
>   compatible = "ti,k2g","ti,keystone";
> @@ -168,5 +169,46 @@
>   #reset-cells = <2>;
>   };
>   };
> +
> + gpio0: gpio@2603000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x02603000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <144>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001b 0x0>;
> + clock-names = "gpio";
> + };
> +
> + gpio1: gpio@260a000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x0260a000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <68>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001c 0x0>;
> + clock-names = "gpio";
> + };
>   };
>  };
> 

Re: [v4 2/2] ARM: dts: keystone-k2g: Add gpio nodes

[Keerthy]

On Friday 04 August 2017 11:15 AM, Keerthy wrote:
> 66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
> functional. 9 banks with 16 gpios making a total of 144. The second
> instance has only the GPIO0:GPIO67 functional and rest are marked
> reserved.

Oops. I will send with the $subject fixed please ignore this.

> 
> Signed-off-by: Keerthy 
> Acked-by: Linus Walleij 
> ---
> 
> Changes in v4:
> 
>   * Couple of rephrasing in the commit log.
>   * Changed compatible to ti,k2g-gpio.
> 
> Changes in v2:
> 
>   * Split the documentation part into a separate patch.
> 
>  arch/arm/boot/dts/keystone-k2g.dtsi | 42 
> +
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi 
> b/arch/arm/boot/dts/keystone-k2g.dtsi
> index bf4d1fa..4eb1ba8 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -15,6 +15,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  / {
>   compatible = "ti,k2g","ti,keystone";
> @@ -168,5 +169,46 @@
>   #reset-cells = <2>;
>   };
>   };
> +
> + gpio0: gpio@2603000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x02603000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <144>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001b 0x0>;
> + clock-names = "gpio";
> + };
> +
> + gpio1: gpio@260a000 {
> + compatible = "ti,k2g-gpio", "ti,keystone-gpio";
> + reg = <0x0260a000 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <68>;
> + ti,davinci-gpio-unbanked = <0>;
> + clocks = <_clks 0x001c 0x0>;
> + clock-names = "gpio";
> + };
>   };
>  };
> 

[PATCH] samples/bpf: Fix cross compiler error with bpf sample

[Joel Fernandes]

When cross-compiling the bpf sample map_perf_test for aarch64, I find that
__NR_getpgrp is undefined. This causes build errors. Fix it by allowing the
deprecated syscall in the sample.

Signed-off-by: Joel Fernandes 
---
 samples/bpf/map_perf_test_user.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/samples/bpf/map_perf_test_user.c b/samples/bpf/map_perf_test_user.c
index 1a8894b5ac51..6e6fc7121640 100644
--- a/samples/bpf/map_perf_test_user.c
+++ b/samples/bpf/map_perf_test_user.c
@@ -8,7 +8,9 @@
 #include 
 #include 
 #include 
+#define __ARCH_WANT_SYSCALL_DEPRECATED
 #include 
+#undef __ARCH_WANT_SYSCALL_DEPRECATED
 #include 
 #include 
 #include 
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

[PATCH] samples/bpf: Fix cross compiler error with bpf sample

[Joel Fernandes]

When cross-compiling the bpf sample map_perf_test for aarch64, I find that
__NR_getpgrp is undefined. This causes build errors. Fix it by allowing the
deprecated syscall in the sample.

Signed-off-by: Joel Fernandes 
---
 samples/bpf/map_perf_test_user.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/samples/bpf/map_perf_test_user.c b/samples/bpf/map_perf_test_user.c
index 1a8894b5ac51..6e6fc7121640 100644
--- a/samples/bpf/map_perf_test_user.c
+++ b/samples/bpf/map_perf_test_user.c
@@ -8,7 +8,9 @@
 #include 
 #include 
 #include 
+#define __ARCH_WANT_SYSCALL_DEPRECATED
 #include 
+#undef __ARCH_WANT_SYSCALL_DEPRECATED
 #include 
 #include 
 #include 
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

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---
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Re: Gift-

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for claims.

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---
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Re: strace-4.18 test suite oopses sparc64 4.12 and 4.13-rc kernels

[Sam Ravnborg]

Hi Davem.

On Thu, Aug 03, 2017 at 02:57:48PM -0700, David Miller wrote:
> From: Mikael Pettersson 
> Date: Thu, 3 Aug 2017 22:02:57 +0200
> 
> > With that in place the kernel booted fine.
> > When I then ran the `poll' strace test binary, the OOPS was replaced by:
> > 
> > [  140.589913] _copy_from_user(fff000123c8dfa7c,   (null), 240) res 
> > 240
> > [  140.753162] _copy_from_user(fff000123c8dfa7c, f7e4a000, 8) res 8
> > [  140.824155] _copy_from_user(fff000123c8dfa7c, f7e49ff8, 16) res 
> > 18442240552407530112
> > 
> > That last `res' doesn't look good.
> 
> Please test this patch:
> 
> diff --git a/arch/sparc/lib/U3memcpy.S b/arch/sparc/lib/U3memcpy.S
> index 54f9870..5a8cb37 100644
> --- a/arch/sparc/lib/U3memcpy.S
> +++ b/arch/sparc/lib/U3memcpy.S
> @@ -145,13 +145,13 @@ ENDPROC(U3_retl_o2_plus_GS_plus_0x08)
>  ENTRY(U3_retl_o2_and_7_plus_GS)
>   and %o2, 7, %o2
>   retl
> -  add%o2, GLOBAL_SPARE, %o2
> +  add%o2, GLOBAL_SPARE, %o0
>  ENDPROC(U3_retl_o2_and_7_plus_GS)
>  ENTRY(U3_retl_o2_and_7_plus_GS_plus_8)
>   add GLOBAL_SPARE, 8, GLOBAL_SPARE
>   and %o2, 7, %o2
>   retl
> -  add%o2, GLOBAL_SPARE, %o2
> +  add%o2, GLOBAL_SPARE, %o0
>  ENDPROC(U3_retl_o2_and_7_plus_GS_plus_8)
>  #endif
>  
Patch looks obviously correct, and I am a bit irritated that
I did not see this myself.
Reviewed-by: Sam Ravnborg 

I will send another patch that fixes/adds a few comments to the same file.

Sam

Re: strace-4.18 test suite oopses sparc64 4.12 and 4.13-rc kernels

[Sam Ravnborg]

Hi Davem.

On Thu, Aug 03, 2017 at 02:57:48PM -0700, David Miller wrote:
> From: Mikael Pettersson 
> Date: Thu, 3 Aug 2017 22:02:57 +0200
> 
> > With that in place the kernel booted fine.
> > When I then ran the `poll' strace test binary, the OOPS was replaced by:
> > 
> > [  140.589913] _copy_from_user(fff000123c8dfa7c,   (null), 240) res 
> > 240
> > [  140.753162] _copy_from_user(fff000123c8dfa7c, f7e4a000, 8) res 8
> > [  140.824155] _copy_from_user(fff000123c8dfa7c, f7e49ff8, 16) res 
> > 18442240552407530112
> > 
> > That last `res' doesn't look good.
> 
> Please test this patch:
> 
> diff --git a/arch/sparc/lib/U3memcpy.S b/arch/sparc/lib/U3memcpy.S
> index 54f9870..5a8cb37 100644
> --- a/arch/sparc/lib/U3memcpy.S
> +++ b/arch/sparc/lib/U3memcpy.S
> @@ -145,13 +145,13 @@ ENDPROC(U3_retl_o2_plus_GS_plus_0x08)
>  ENTRY(U3_retl_o2_and_7_plus_GS)
>   and %o2, 7, %o2
>   retl
> -  add%o2, GLOBAL_SPARE, %o2
> +  add%o2, GLOBAL_SPARE, %o0
>  ENDPROC(U3_retl_o2_and_7_plus_GS)
>  ENTRY(U3_retl_o2_and_7_plus_GS_plus_8)
>   add GLOBAL_SPARE, 8, GLOBAL_SPARE
>   and %o2, 7, %o2
>   retl
> -  add%o2, GLOBAL_SPARE, %o2
> +  add%o2, GLOBAL_SPARE, %o0
>  ENDPROC(U3_retl_o2_and_7_plus_GS_plus_8)
>  #endif
>  
Patch looks obviously correct, and I am a bit irritated that
I did not see this myself.
Reviewed-by: Sam Ravnborg 

I will send another patch that fixes/adds a few comments to the same file.

Sam

[PATCH 4/5] scsi/esp_scsi: Avoid sending ABORT TASK SET messages

[Finn Thain]

If an LLD aborts a task set, it should complete the affected commands
with the appropriate result code. In a couple of cases esp_scsi doesn't
do so.

When the initiator receives an unhandled message, just respond by sending
a MESSAGE REJECT instead of ABORT TASK SET, and thus avoid the issue.

OTOH, a MESSAGE REJECT sent by a target can be taken as an indication
that the initiator messed up somehow. It isn't always possible to abort
correctly, so just fall back on a SCSI bus reset, which will complete the
affected commands with the appropriate result code.

For example, certain Apple (Sony) CD-ROM drives, when the non-existent
LUN 1 is scanned, can't handle the INQUIRY command. The problem is not
detected until the initiator gets a MESSAGE REJECT. Whenever esp_scsi
sees that message, it raises ATN and sends ABORT TASK SET -- but
neglects to complete the failed scmd.

The target then goes into DATA OUT phase (probably bogus), while the ESP
device goes into disconnected mode (surprising, given the bus phase).
The next Transfer Information command from esp_scsi then causes
an Invalid Command interrupt because that command is not valid when in
disconnected mode:

mac_esp: using PDMA for controller 0
mac_esp mac_esp.0: esp0: regs[50f1:(null)] irq[19]
mac_esp mac_esp.0: esp0: is a ESP236, 16 MHz (ccf=4), SCSI ID 7
scsi host0: esp
scsi 0:0:0:0: Direct-Access SEAGATE  ST318416N0010 PQ: 0 ANSI: 3
scsi target0:0:0: Beginning Domain Validation
scsi target0:0:0: asynchronous
scsi target0:0:0: Domain Validation skipping write tests
scsi target0:0:0: Ending Domain Validation
scsi 0:0:3:0: CD-ROMSONY CD-ROM CDU-8003A 1.9a PQ: 0 ANSI: 2 CCS
scsi target0:0:3: Beginning Domain Validation
scsi target0:0:3: FAST-5 SCSI 2.0 MB/s ST (500 ns, offset 15)
scsi target0:0:3: Domain Validation skipping write tests
scsi target0:0:3: Ending Domain Validation
scsi host0: unexpected IREG 40
scsi host0: Dumping command log
scsi host0: ent[2] CMD val[c2] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[3] CMD val[00] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[4] EVENT val[0d] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[5] EVENT val[03] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0d]
scsi host0: ent[6] CMD val[90] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[03]
scsi host0: ent[7] EVENT val[05] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[03]
scsi host0: ent[8] EVENT val[0d] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[05]
scsi host0: ent[9] CMD val[01] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[10] CMD val[11] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[11] EVENT val[0b] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[12] CMD val[12] sreg[97] seqreg[cc] sreg2[00] ireg[08] ss[00] 
event[0b]
scsi host0: ent[13] EVENT val[0c] sreg[97] seqreg[cc] sreg2[00] ireg[08] ss[00] 
event[0b]
scsi host0: ent[14] CMD val[44] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[00] 
event[0c]
scsi host0: ent[15] CMD val[01] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[16] CMD val[c2] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[17] CMD val[00] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[18] EVENT val[0d] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[19] EVENT val[06] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0d]
scsi host0: ent[20] CMD val[01] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[06]
scsi host0: ent[21] CMD val[10] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[06]
scsi host0: ent[22] CMD val[1a] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[23] CMD val[12] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[24] EVENT val[0d] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[25] EVENT val[09] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[26] CMD val[01] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[27] CMD val[10] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[28] EVENT val[0a] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[29] EVENT val[0d] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[0a]
scsi host0: ent[30] EVENT val[04] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[0d]
scsi host0: ent[31] CMD val[01] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi host0: ent[0] CMD val[90] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi host0: ent[1] EVENT val[05] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi target0:0:3: FAST-5 SCSI 2.0 MB/s ST (500 ns, offset 15)
scsi target0:0:0: asynchronous
sr 0:0:3:0: [sr0] scsi-1 drive
cdrom: Uniform CD-ROM driver Revision: 3.20
sd 

[PATCH 4/5] scsi/esp_scsi: Avoid sending ABORT TASK SET messages

[Finn Thain]

If an LLD aborts a task set, it should complete the affected commands
with the appropriate result code. In a couple of cases esp_scsi doesn't
do so.

When the initiator receives an unhandled message, just respond by sending
a MESSAGE REJECT instead of ABORT TASK SET, and thus avoid the issue.

OTOH, a MESSAGE REJECT sent by a target can be taken as an indication
that the initiator messed up somehow. It isn't always possible to abort
correctly, so just fall back on a SCSI bus reset, which will complete the
affected commands with the appropriate result code.

For example, certain Apple (Sony) CD-ROM drives, when the non-existent
LUN 1 is scanned, can't handle the INQUIRY command. The problem is not
detected until the initiator gets a MESSAGE REJECT. Whenever esp_scsi
sees that message, it raises ATN and sends ABORT TASK SET -- but
neglects to complete the failed scmd.

The target then goes into DATA OUT phase (probably bogus), while the ESP
device goes into disconnected mode (surprising, given the bus phase).
The next Transfer Information command from esp_scsi then causes
an Invalid Command interrupt because that command is not valid when in
disconnected mode:

mac_esp: using PDMA for controller 0
mac_esp mac_esp.0: esp0: regs[50f1:(null)] irq[19]
mac_esp mac_esp.0: esp0: is a ESP236, 16 MHz (ccf=4), SCSI ID 7
scsi host0: esp
scsi 0:0:0:0: Direct-Access SEAGATE  ST318416N0010 PQ: 0 ANSI: 3
scsi target0:0:0: Beginning Domain Validation
scsi target0:0:0: asynchronous
scsi target0:0:0: Domain Validation skipping write tests
scsi target0:0:0: Ending Domain Validation
scsi 0:0:3:0: CD-ROMSONY CD-ROM CDU-8003A 1.9a PQ: 0 ANSI: 2 CCS
scsi target0:0:3: Beginning Domain Validation
scsi target0:0:3: FAST-5 SCSI 2.0 MB/s ST (500 ns, offset 15)
scsi target0:0:3: Domain Validation skipping write tests
scsi target0:0:3: Ending Domain Validation
scsi host0: unexpected IREG 40
scsi host0: Dumping command log
scsi host0: ent[2] CMD val[c2] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[3] CMD val[00] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[4] EVENT val[0d] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[5] EVENT val[03] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[0d]
scsi host0: ent[6] CMD val[90] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[03]
scsi host0: ent[7] EVENT val[05] sreg[91] seqreg[04] sreg2[00] ireg[18] ss[00] 
event[03]
scsi host0: ent[8] EVENT val[0d] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[05]
scsi host0: ent[9] CMD val[01] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[10] CMD val[11] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[11] EVENT val[0b] sreg[93] seqreg[cc] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[12] CMD val[12] sreg[97] seqreg[cc] sreg2[00] ireg[08] ss[00] 
event[0b]
scsi host0: ent[13] EVENT val[0c] sreg[97] seqreg[cc] sreg2[00] ireg[08] ss[00] 
event[0b]
scsi host0: ent[14] CMD val[44] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[00] 
event[0c]
scsi host0: ent[15] CMD val[01] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[16] CMD val[c2] sreg[90] seqreg[cc] sreg2[00] ireg[20] ss[01] 
event[0c]
scsi host0: ent[17] CMD val[00] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[18] EVENT val[0d] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0c]
scsi host0: ent[19] EVENT val[06] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[0d]
scsi host0: ent[20] CMD val[01] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[06]
scsi host0: ent[21] CMD val[10] sreg[87] seqreg[02] sreg2[00] ireg[18] ss[00] 
event[06]
scsi host0: ent[22] CMD val[1a] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[23] CMD val[12] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[24] EVENT val[0d] sreg[87] seqreg[ca] sreg2[00] ireg[08] ss[00] 
event[06]
scsi host0: ent[25] EVENT val[09] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[0d]
scsi host0: ent[26] CMD val[01] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[27] CMD val[10] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[28] EVENT val[0a] sreg[86] seqreg[ca] sreg2[00] ireg[10] ss[00] 
event[09]
scsi host0: ent[29] EVENT val[0d] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[0a]
scsi host0: ent[30] EVENT val[04] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[0d]
scsi host0: ent[31] CMD val[01] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi host0: ent[0] CMD val[90] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi host0: ent[1] EVENT val[05] sreg[80] seqreg[ca] sreg2[00] ireg[20] ss[00] 
event[04]
scsi target0:0:3: FAST-5 SCSI 2.0 MB/s ST (500 ns, offset 15)
scsi target0:0:0: asynchronous
sr 0:0:3:0: [sr0] scsi-1 drive
cdrom: Uniform CD-ROM driver Revision: 3.20
sd 

[PATCH 3/5] scsi/esp_scsi: Clean up control flow and dead code

[Finn Thain]

This patch improves readability. There are no functional changes.

Since this touches on a questionable ESP_INTR_DC conditional, add some
commentary to help others who may (as I did) find themselves chasing an
"Invalid Command" error after the device flags this condition.

This cleanup also eliminates a warning from "make W=1":
drivers/scsi/esp_scsi.c: In function 'esp_finish_select':
drivers/scsi/esp_scsi.c:1233:5: warning: variable 'orig_select_state' set but 
not used [-Wunused-but-set-variable]
  u8 orig_select_state;

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/esp_scsi.c | 40 ++--
 drivers/scsi/esp_scsi.h |  1 -
 2 files changed, 14 insertions(+), 27 deletions(-)

diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index 71cb05b1c3eb..93fef2b3d357 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -597,14 +597,12 @@ static int esp_alloc_lun_tag(struct esp_cmd_entry *ent,
 
lp->non_tagged_cmd = ent;
return 0;
-   } else {
-   /* Tagged command, see if blocked by a
-* non-tagged one.
-*/
-   if (lp->non_tagged_cmd || lp->hold)
-   return -EBUSY;
}
 
+   /* Tagged command. Check that it isn't blocked by a non-tagged one. */
+   if (lp->non_tagged_cmd || lp->hold)
+   return -EBUSY;
+
BUG_ON(lp->tagged_cmds[ent->orig_tag[1]]);
 
lp->tagged_cmds[ent->orig_tag[1]] = ent;
@@ -1210,12 +1208,6 @@ static int esp_reconnect(struct esp *esp)
 
esp->active_cmd = ent;
 
-   if (ent->flags & ESP_CMD_FLAG_ABORT) {
-   esp->msg_out[0] = ABORT_TASK_SET;
-   esp->msg_out_len = 1;
-   scsi_esp_cmd(esp, ESP_CMD_SATN);
-   }
-
esp_event(esp, ESP_EVENT_CHECK_PHASE);
esp_restore_pointers(esp, ent);
esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
@@ -1230,9 +1222,6 @@ static int esp_finish_select(struct esp *esp)
 {
struct esp_cmd_entry *ent;
struct scsi_cmnd *cmd;
-   u8 orig_select_state;
-
-   orig_select_state = esp->select_state;
 
/* No longer selecting.  */
esp->select_state = ESP_SELECT_NONE;
@@ -1745,7 +1734,6 @@ static int esp_process_event(struct esp *esp)
return 0;
}
goto again;
-   break;
 
case ESP_EVENT_DATA_IN:
write = 1;
@@ -1956,12 +1944,14 @@ static int esp_process_event(struct esp *esp)
} else {
if (esp->msg_out_len > 1)
esp->ops->dma_invalidate(esp);
-   }
 
-   if (!(esp->ireg & ESP_INTR_DC)) {
-   if (esp->rev != FASHME)
+   /* XXX if the chip went into disconnected mode,
+* we can't run the phase state machine anyway.
+*/
+   if (!(esp->ireg & ESP_INTR_DC))
scsi_esp_cmd(esp, ESP_CMD_NULL);
}
+
esp_event(esp, ESP_EVENT_CHECK_PHASE);
goto again;
case ESP_EVENT_MSGIN:
@@ -2022,7 +2012,6 @@ static int esp_process_event(struct esp *esp)
}
esp_schedule_reset(esp);
return 0;
-   break;
 
case ESP_EVENT_RESET:
scsi_esp_cmd(esp, ESP_CMD_RS);
@@ -2033,7 +2022,6 @@ static int esp_process_event(struct esp *esp)
 "Unexpected event %x, resetting\n", esp->event);
esp_schedule_reset(esp);
return 0;
-   break;
}
return 1;
 }
@@ -2170,14 +2158,14 @@ static void __esp_interrupt(struct esp *esp)
 
esp_schedule_reset(esp);
} else {
-   if (!(esp->ireg & ESP_INTR_RSEL)) {
-   /* Some combination of FDONE, BSERV, DC.  */
-   if (esp->select_state != ESP_SELECT_NONE)
-   intr_done = esp_finish_select(esp);
-   } else if (esp->ireg & ESP_INTR_RSEL) {
+   if (esp->ireg & ESP_INTR_RSEL) {
if (esp->active_cmd)
(void) esp_finish_select(esp);
intr_done = esp_reconnect(esp);
+   } else {
+   /* Some combination of FDONE, BSERV, DC. */
+   if (esp->select_state != ESP_SELECT_NONE)
+   intr_done = esp_finish_select(esp);
}
}
while (!intr_done)
diff --git a/drivers/scsi/esp_scsi.h b/drivers/scsi/esp_scsi.h
index 84dcbe4a6268..7e8932ae91f8 100644
--- a/drivers/scsi/esp_scsi.h
+++ b/drivers/scsi/esp_scsi.h
@@ -281,7 +281,6 @@ struct esp_cmd_entry {
 
u8  

[PATCH 3/5] scsi/esp_scsi: Clean up control flow and dead code

[Finn Thain]

This patch improves readability. There are no functional changes.

Since this touches on a questionable ESP_INTR_DC conditional, add some
commentary to help others who may (as I did) find themselves chasing an
"Invalid Command" error after the device flags this condition.

This cleanup also eliminates a warning from "make W=1":
drivers/scsi/esp_scsi.c: In function 'esp_finish_select':
drivers/scsi/esp_scsi.c:1233:5: warning: variable 'orig_select_state' set but 
not used [-Wunused-but-set-variable]
  u8 orig_select_state;

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/esp_scsi.c | 40 ++--
 drivers/scsi/esp_scsi.h |  1 -
 2 files changed, 14 insertions(+), 27 deletions(-)

diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index 71cb05b1c3eb..93fef2b3d357 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -597,14 +597,12 @@ static int esp_alloc_lun_tag(struct esp_cmd_entry *ent,
 
lp->non_tagged_cmd = ent;
return 0;
-   } else {
-   /* Tagged command, see if blocked by a
-* non-tagged one.
-*/
-   if (lp->non_tagged_cmd || lp->hold)
-   return -EBUSY;
}
 
+   /* Tagged command. Check that it isn't blocked by a non-tagged one. */
+   if (lp->non_tagged_cmd || lp->hold)
+   return -EBUSY;
+
BUG_ON(lp->tagged_cmds[ent->orig_tag[1]]);
 
lp->tagged_cmds[ent->orig_tag[1]] = ent;
@@ -1210,12 +1208,6 @@ static int esp_reconnect(struct esp *esp)
 
esp->active_cmd = ent;
 
-   if (ent->flags & ESP_CMD_FLAG_ABORT) {
-   esp->msg_out[0] = ABORT_TASK_SET;
-   esp->msg_out_len = 1;
-   scsi_esp_cmd(esp, ESP_CMD_SATN);
-   }
-
esp_event(esp, ESP_EVENT_CHECK_PHASE);
esp_restore_pointers(esp, ent);
esp->flags |= ESP_FLAG_QUICKIRQ_CHECK;
@@ -1230,9 +1222,6 @@ static int esp_finish_select(struct esp *esp)
 {
struct esp_cmd_entry *ent;
struct scsi_cmnd *cmd;
-   u8 orig_select_state;
-
-   orig_select_state = esp->select_state;
 
/* No longer selecting.  */
esp->select_state = ESP_SELECT_NONE;
@@ -1745,7 +1734,6 @@ static int esp_process_event(struct esp *esp)
return 0;
}
goto again;
-   break;
 
case ESP_EVENT_DATA_IN:
write = 1;
@@ -1956,12 +1944,14 @@ static int esp_process_event(struct esp *esp)
} else {
if (esp->msg_out_len > 1)
esp->ops->dma_invalidate(esp);
-   }
 
-   if (!(esp->ireg & ESP_INTR_DC)) {
-   if (esp->rev != FASHME)
+   /* XXX if the chip went into disconnected mode,
+* we can't run the phase state machine anyway.
+*/
+   if (!(esp->ireg & ESP_INTR_DC))
scsi_esp_cmd(esp, ESP_CMD_NULL);
}
+
esp_event(esp, ESP_EVENT_CHECK_PHASE);
goto again;
case ESP_EVENT_MSGIN:
@@ -2022,7 +2012,6 @@ static int esp_process_event(struct esp *esp)
}
esp_schedule_reset(esp);
return 0;
-   break;
 
case ESP_EVENT_RESET:
scsi_esp_cmd(esp, ESP_CMD_RS);
@@ -2033,7 +2022,6 @@ static int esp_process_event(struct esp *esp)
 "Unexpected event %x, resetting\n", esp->event);
esp_schedule_reset(esp);
return 0;
-   break;
}
return 1;
 }
@@ -2170,14 +2158,14 @@ static void __esp_interrupt(struct esp *esp)
 
esp_schedule_reset(esp);
} else {
-   if (!(esp->ireg & ESP_INTR_RSEL)) {
-   /* Some combination of FDONE, BSERV, DC.  */
-   if (esp->select_state != ESP_SELECT_NONE)
-   intr_done = esp_finish_select(esp);
-   } else if (esp->ireg & ESP_INTR_RSEL) {
+   if (esp->ireg & ESP_INTR_RSEL) {
if (esp->active_cmd)
(void) esp_finish_select(esp);
intr_done = esp_reconnect(esp);
+   } else {
+   /* Some combination of FDONE, BSERV, DC. */
+   if (esp->select_state != ESP_SELECT_NONE)
+   intr_done = esp_finish_select(esp);
}
}
while (!intr_done)
diff --git a/drivers/scsi/esp_scsi.h b/drivers/scsi/esp_scsi.h
index 84dcbe4a6268..7e8932ae91f8 100644
--- a/drivers/scsi/esp_scsi.h
+++ b/drivers/scsi/esp_scsi.h
@@ -281,7 +281,6 @@ struct esp_cmd_entry {
 
u8  flags;
 #define ESP_CMD_FLAG_WRITE 0x01 /* 

[PATCH 5/5] scsi/esp_scsi: Always clear msg_out_len after MESSAGE OUT phase

[Finn Thain]

After sending a message, always clear esp->msg_out_len. Otherwise,
eh_abort_handler may subsequently fail to send an ABORT TASK SET
message.

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/esp_scsi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index 4d1e08a87274..c3fc34b9964d 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -1951,6 +1951,8 @@ static int esp_process_event(struct esp *esp)
scsi_esp_cmd(esp, ESP_CMD_NULL);
}
 
+   esp->msg_out_len = 0;
+
esp_event(esp, ESP_EVENT_CHECK_PHASE);
goto again;
case ESP_EVENT_MSGIN:
-- 
2.13.0

[PATCH 5/5] scsi/esp_scsi: Always clear msg_out_len after MESSAGE OUT phase

[Finn Thain]

After sending a message, always clear esp->msg_out_len. Otherwise,
eh_abort_handler may subsequently fail to send an ABORT TASK SET
message.

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/esp_scsi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index 4d1e08a87274..c3fc34b9964d 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -1951,6 +1951,8 @@ static int esp_process_event(struct esp *esp)
scsi_esp_cmd(esp, ESP_CMD_NULL);
}
 
+   esp->msg_out_len = 0;
+
esp_event(esp, ESP_EVENT_CHECK_PHASE);
goto again;
case ESP_EVENT_MSGIN:
-- 
2.13.0

[PATCH 0/5] esp_scsi, mac_esp: Various fixes and cleanups

[Finn Thain]

This series has been tested on m68k Macs (ESP236 equivalent).

Some more testing with different targets and devices (FAS236 etc)
might be nice. Being that the esp_scsi fixes are on error paths,
more review may actually be more valuable than more testing...


Finn Thain (5):
  scsi/mac_esp: Avoid type warning from sparse
  scsi/mac_esp: Fix PIO transfers for MESSAGE IN phase
  scsi/esp_scsi: Clean up control flow and dead code
  scsi/esp_scsi: Avoid sending ABORT TASK SET messages
  scsi/esp_scsi: Always clear msg_out_len after MESSAGE OUT phase

 drivers/scsi/esp_scsi.c | 53 +
 drivers/scsi/esp_scsi.h |  1 -
 drivers/scsi/mac_esp.c  | 37 +-
 3 files changed, 42 insertions(+), 49 deletions(-)

-- 
2.13.0

[PATCH 0/5] esp_scsi, mac_esp: Various fixes and cleanups

[Finn Thain]

This series has been tested on m68k Macs (ESP236 equivalent).

Some more testing with different targets and devices (FAS236 etc)
might be nice. Being that the esp_scsi fixes are on error paths,
more review may actually be more valuable than more testing...


Finn Thain (5):
  scsi/mac_esp: Avoid type warning from sparse
  scsi/mac_esp: Fix PIO transfers for MESSAGE IN phase
  scsi/esp_scsi: Clean up control flow and dead code
  scsi/esp_scsi: Avoid sending ABORT TASK SET messages
  scsi/esp_scsi: Always clear msg_out_len after MESSAGE OUT phase

 drivers/scsi/esp_scsi.c | 53 +
 drivers/scsi/esp_scsi.h |  1 -
 drivers/scsi/mac_esp.c  | 37 +-
 3 files changed, 42 insertions(+), 49 deletions(-)

-- 
2.13.0

[PATCH 1/5] scsi/mac_esp: Avoid type warning from sparse

[Finn Thain]

Avoid the following warning from "make C=1":

  CHECK   drivers/scsi/mac_esp.c
drivers/scsi/mac_esp.c:357:30: warning: incorrect type in initializer 
(different address spaces)
drivers/scsi/mac_esp.c:357:30:expected unsigned char [usertype] *fifo
drivers/scsi/mac_esp.c:357:30:got void [noderef] *

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/mac_esp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
index cdb61eaa2d1f..253142f3cf6f 100644
--- a/drivers/scsi/mac_esp.c
+++ b/drivers/scsi/mac_esp.c
@@ -348,7 +348,7 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 addr, 
u32 esp_count,
 u32 dma_count, int write, u8 cmd)
 {
struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
-   u8 *fifo = esp->regs + ESP_FDATA * 16;
+   u8 __iomem *fifo = esp->regs + ESP_FDATA * 16;
 
cmd &= ~ESP_CMD_DMA;
mep->error = 0;
-- 
2.13.0

[PATCH 1/5] scsi/mac_esp: Avoid type warning from sparse

[Finn Thain]

Avoid the following warning from "make C=1":

  CHECK   drivers/scsi/mac_esp.c
drivers/scsi/mac_esp.c:357:30: warning: incorrect type in initializer 
(different address spaces)
drivers/scsi/mac_esp.c:357:30:expected unsigned char [usertype] *fifo
drivers/scsi/mac_esp.c:357:30:got void [noderef] *

Tested-by: Stan Johnson 
Signed-off-by: Finn Thain 
---
 drivers/scsi/mac_esp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
index cdb61eaa2d1f..253142f3cf6f 100644
--- a/drivers/scsi/mac_esp.c
+++ b/drivers/scsi/mac_esp.c
@@ -348,7 +348,7 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 addr, 
u32 esp_count,
 u32 dma_count, int write, u8 cmd)
 {
struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
-   u8 *fifo = esp->regs + ESP_FDATA * 16;
+   u8 __iomem *fifo = esp->regs + ESP_FDATA * 16;
 
cmd &= ~ESP_CMD_DMA;
mep->error = 0;
-- 
2.13.0

[PATCH 2/5] scsi/mac_esp: Fix PIO transfers for MESSAGE IN phase

[Finn Thain]

When in MESSAGE IN phase, the ESP device does not automatically
acknowledge each byte that is transferred by PIO. The mac_esp driver
neglects to explicitly ack them, which causes a timeout during messages
larger than one byte (e.g. tag bytes during reconnect). Fix this with an
ESP_CMD_MOK command after each byte.

The MESSAGE IN phase is also different in that each byte transferred
raises ESP_INTR_FDONE. So don't exit the transfer loop for this interrupt,
for this phase.

That resolves the "Reconnect IRQ2 timeout" error on those Macs which use
PIO transfers instead of PDMA. This patch also improves on the weak tests
for unexpected interrupts and phase changes during PIO transfers.

Tested-by: Stan Johnson 
Fixes: 02507a80b35e ("[PATCH] [SCSI] mac_esp: fix PIO mode, take 2")
Signed-off-by: Finn Thain 
---
 drivers/scsi/mac_esp.c | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
index 253142f3cf6f..eb551f3cc471 100644
--- a/drivers/scsi/mac_esp.c
+++ b/drivers/scsi/mac_esp.c
@@ -349,25 +349,23 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
 {
struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
u8 __iomem *fifo = esp->regs + ESP_FDATA * 16;
+   u8 phase = esp->sreg & ESP_STAT_PMASK;
 
cmd &= ~ESP_CMD_DMA;
mep->error = 0;
 
if (write) {
+   u8 *dst = (u8 *)addr;
+   u8 mask = ~(phase == ESP_MIP ? ESP_INTR_FDONE : ESP_INTR_BSERV);
+
scsi_esp_cmd(esp, cmd);
 
while (1) {
-   unsigned int n;
-
-   n = mac_esp_wait_for_fifo(esp);
-   if (!n)
+   if (!mac_esp_wait_for_fifo(esp))
break;
 
-   if (n > esp_count)
-   n = esp_count;
-   esp_count -= n;
-
-   MAC_ESP_PIO_LOOP("%2@,%0@+", n);
+   *dst++ = esp_read8(ESP_FDATA);
+   --esp_count;
 
if (!esp_count)
break;
@@ -375,14 +373,17 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
if (mac_esp_wait_for_intr(esp))
break;
 
-   if (((esp->sreg & ESP_STAT_PMASK) != ESP_DIP) &&
-   ((esp->sreg & ESP_STAT_PMASK) != ESP_MIP))
+   if ((esp->sreg & ESP_STAT_PMASK) != phase)
break;
 
esp->ireg = esp_read8(ESP_INTRPT);
-   if ((esp->ireg & (ESP_INTR_DC | ESP_INTR_BSERV)) !=
-   ESP_INTR_BSERV)
+   if (esp->ireg & mask) {
+   mep->error = 1;
break;
+   }
+
+   if (phase == ESP_MIP)
+   scsi_esp_cmd(esp, ESP_CMD_MOK);
 
scsi_esp_cmd(esp, ESP_CMD_TI);
}
@@ -402,14 +403,14 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
if (mac_esp_wait_for_intr(esp))
break;
 
-   if (((esp->sreg & ESP_STAT_PMASK) != ESP_DOP) &&
-   ((esp->sreg & ESP_STAT_PMASK) != ESP_MOP))
+   if ((esp->sreg & ESP_STAT_PMASK) != phase)
break;
 
esp->ireg = esp_read8(ESP_INTRPT);
-   if ((esp->ireg & (ESP_INTR_DC | ESP_INTR_BSERV)) !=
-   ESP_INTR_BSERV)
+   if (esp->ireg & ~ESP_INTR_BSERV) {
+   mep->error = 1;
break;
+   }
 
n = MAC_ESP_FIFO_SIZE -
(esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES);
-- 
2.13.0

Re: [PATCH v2 16/25] mtd: nand: qcom: allocate BAM transaction

[Archit Taneja]

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for it be


What does 'base layer' here mean?


allocated during probe time and before every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from BAM
transaction.


Could you also mention in the commit message that the size of the
buffer used for BAM transactions is calculated based on the NAND device
with the maximum page size, among all the devices connected to the
controller.



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 114 ++
  1 file changed, 114 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f49c3da..fc29c97 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
  #include 
  #include 
  #include 
+#include 
  
  /* NANDc reg offsets */

  #define   NAND_FLASH_CMD  0x00
@@ -172,6 +173,45 @@
  #define   ECC_BCH_4BITBIT(2)
  #define   ECC_BCH_8BITBIT(3)
  
+#define QPIC_PER_CW_CMD_ELEMENTS	32

+#define QPIC_PER_CW_CMD_SGL32
+#define QPIC_PER_CW_DATA_SGL   8
+
+/*
+ * This data type corresponds to the BAM transaction which will be used for all
+ * NAND transfers.
+ * @bam_ce - the array of bam command elements
+ * @cmd_sgl - sgl for nand bam command pipe
+ * @data_sgl - sgl for nand bam consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl request
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *for current sgl. It will be used for size calculation
+ *for current sgl
+ * @cmd_sgl_pos - current index in command sgl.
+ * @tx_sgl_pos - current index in data sgl for tx.
+ * @rx_sgl_pos - current index in data sgl for rx.
+ */
+struct bam_transaction {
+   struct bam_cmd_element *bam_ce;
+   struct scatterlist *cmd_sgl;
+   struct scatterlist *data_sgl;
+   u32 bam_ce_pos;
+   u32 bam_ce_start;
+   u32 cmd_sgl_pos;
+   u32 cmd_sgl_start;
+   u32 tx_sgl_pos;
+   u32 tx_sgl_start;
+   u32 rx_sgl_pos;
+   u32 rx_sgl_start;
+};
+
+/*
+ * This data type corresponds to the nand dma descriptor
+ * @list - list for desc_info
+ * @dir - DMA transfer direction
+ * @sgl - sgl which will be used for single sgl dma descriptor
+ * @dma_desc - low level dma engine descriptor
+ */
  struct desc_info {
struct list_head node;
  
@@ -238,6 +278,8 @@ struct nandc_regs {

   * @cmd1/vld: some fixed controller register values
   * @props:properties of current NAND controller IP,
   *initialized via DT match data
+ * @max_cwperpage: maximum qpic codeword required. calcualted


s/calcualted/calculated

Thanks,
Archit


+ * from all nand device pagesize
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -265,11 +307,13 @@ struct qcom_nand_controller {
};
  
  	struct list_head desc_list;

+   struct bam_transaction *bam_txn;
  
  	u8		*data_buffer;

int buf_size;
int buf_count;
int buf_start;
+   unsigned intmax_cwperpage;
  
  	__le32 *reg_read_buf;

dma_addr_t reg_read_buf_phys;
@@ -342,6 +386,50 @@ struct qcom_props {
bool is_bam;
  };
  
+/* Frees the BAM transaction memory */

+static void free_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   devm_kfree(nandc->dev, bam_txn);
+}
+
+/* Allocates and Initializes the BAM transaction */
+static struct bam_transaction *
+alloc_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn;
+   size_t bam_txn_size;
+   unsigned int num_cw = nandc->max_cwperpage;
+   void *bam_txn_buf;
+
+   bam_txn_size =
+   sizeof(*bam_txn) + num_cw *
+   ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+   (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+   (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+
+   bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+   if (!bam_txn_buf)
+   return NULL;
+
+   bam_txn = bam_txn_buf;
+   bam_txn_buf += sizeof(*bam_txn);
+
+   bam_txn->bam_ce = bam_txn_buf;
+   bam_txn_buf +=
+   sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
+   bam_txn->cmd_sgl = 

[PATCH 2/5] scsi/mac_esp: Fix PIO transfers for MESSAGE IN phase

[Finn Thain]

When in MESSAGE IN phase, the ESP device does not automatically
acknowledge each byte that is transferred by PIO. The mac_esp driver
neglects to explicitly ack them, which causes a timeout during messages
larger than one byte (e.g. tag bytes during reconnect). Fix this with an
ESP_CMD_MOK command after each byte.

The MESSAGE IN phase is also different in that each byte transferred
raises ESP_INTR_FDONE. So don't exit the transfer loop for this interrupt,
for this phase.

That resolves the "Reconnect IRQ2 timeout" error on those Macs which use
PIO transfers instead of PDMA. This patch also improves on the weak tests
for unexpected interrupts and phase changes during PIO transfers.

Tested-by: Stan Johnson 
Fixes: 02507a80b35e ("[PATCH] [SCSI] mac_esp: fix PIO mode, take 2")
Signed-off-by: Finn Thain 
---
 drivers/scsi/mac_esp.c | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/scsi/mac_esp.c b/drivers/scsi/mac_esp.c
index 253142f3cf6f..eb551f3cc471 100644
--- a/drivers/scsi/mac_esp.c
+++ b/drivers/scsi/mac_esp.c
@@ -349,25 +349,23 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
 {
struct mac_esp_priv *mep = MAC_ESP_GET_PRIV(esp);
u8 __iomem *fifo = esp->regs + ESP_FDATA * 16;
+   u8 phase = esp->sreg & ESP_STAT_PMASK;
 
cmd &= ~ESP_CMD_DMA;
mep->error = 0;
 
if (write) {
+   u8 *dst = (u8 *)addr;
+   u8 mask = ~(phase == ESP_MIP ? ESP_INTR_FDONE : ESP_INTR_BSERV);
+
scsi_esp_cmd(esp, cmd);
 
while (1) {
-   unsigned int n;
-
-   n = mac_esp_wait_for_fifo(esp);
-   if (!n)
+   if (!mac_esp_wait_for_fifo(esp))
break;
 
-   if (n > esp_count)
-   n = esp_count;
-   esp_count -= n;
-
-   MAC_ESP_PIO_LOOP("%2@,%0@+", n);
+   *dst++ = esp_read8(ESP_FDATA);
+   --esp_count;
 
if (!esp_count)
break;
@@ -375,14 +373,17 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
if (mac_esp_wait_for_intr(esp))
break;
 
-   if (((esp->sreg & ESP_STAT_PMASK) != ESP_DIP) &&
-   ((esp->sreg & ESP_STAT_PMASK) != ESP_MIP))
+   if ((esp->sreg & ESP_STAT_PMASK) != phase)
break;
 
esp->ireg = esp_read8(ESP_INTRPT);
-   if ((esp->ireg & (ESP_INTR_DC | ESP_INTR_BSERV)) !=
-   ESP_INTR_BSERV)
+   if (esp->ireg & mask) {
+   mep->error = 1;
break;
+   }
+
+   if (phase == ESP_MIP)
+   scsi_esp_cmd(esp, ESP_CMD_MOK);
 
scsi_esp_cmd(esp, ESP_CMD_TI);
}
@@ -402,14 +403,14 @@ static void mac_esp_send_pio_cmd(struct esp *esp, u32 
addr, u32 esp_count,
if (mac_esp_wait_for_intr(esp))
break;
 
-   if (((esp->sreg & ESP_STAT_PMASK) != ESP_DOP) &&
-   ((esp->sreg & ESP_STAT_PMASK) != ESP_MOP))
+   if ((esp->sreg & ESP_STAT_PMASK) != phase)
break;
 
esp->ireg = esp_read8(ESP_INTRPT);
-   if ((esp->ireg & (ESP_INTR_DC | ESP_INTR_BSERV)) !=
-   ESP_INTR_BSERV)
+   if (esp->ireg & ~ESP_INTR_BSERV) {
+   mep->error = 1;
break;
+   }
 
n = MAC_ESP_FIFO_SIZE -
(esp_read8(ESP_FFLAGS) & ESP_FF_FBYTES);
-- 
2.13.0

Re: [PATCH v2 16/25] mtd: nand: qcom: allocate BAM transaction

[Archit Taneja]

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for it be


What does 'base layer' here mean?


allocated during probe time and before every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from BAM
transaction.


Could you also mention in the commit message that the size of the
buffer used for BAM transactions is calculated based on the NAND device
with the maximum page size, among all the devices connected to the
controller.



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 114 ++
  1 file changed, 114 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f49c3da..fc29c97 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
  #include 
  #include 
  #include 
+#include 
  
  /* NANDc reg offsets */

  #define   NAND_FLASH_CMD  0x00
@@ -172,6 +173,45 @@
  #define   ECC_BCH_4BITBIT(2)
  #define   ECC_BCH_8BITBIT(3)
  
+#define QPIC_PER_CW_CMD_ELEMENTS	32

+#define QPIC_PER_CW_CMD_SGL32
+#define QPIC_PER_CW_DATA_SGL   8
+
+/*
+ * This data type corresponds to the BAM transaction which will be used for all
+ * NAND transfers.
+ * @bam_ce - the array of bam command elements
+ * @cmd_sgl - sgl for nand bam command pipe
+ * @data_sgl - sgl for nand bam consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl request
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *for current sgl. It will be used for size calculation
+ *for current sgl
+ * @cmd_sgl_pos - current index in command sgl.
+ * @tx_sgl_pos - current index in data sgl for tx.
+ * @rx_sgl_pos - current index in data sgl for rx.
+ */
+struct bam_transaction {
+   struct bam_cmd_element *bam_ce;
+   struct scatterlist *cmd_sgl;
+   struct scatterlist *data_sgl;
+   u32 bam_ce_pos;
+   u32 bam_ce_start;
+   u32 cmd_sgl_pos;
+   u32 cmd_sgl_start;
+   u32 tx_sgl_pos;
+   u32 tx_sgl_start;
+   u32 rx_sgl_pos;
+   u32 rx_sgl_start;
+};
+
+/*
+ * This data type corresponds to the nand dma descriptor
+ * @list - list for desc_info
+ * @dir - DMA transfer direction
+ * @sgl - sgl which will be used for single sgl dma descriptor
+ * @dma_desc - low level dma engine descriptor
+ */
  struct desc_info {
struct list_head node;
  
@@ -238,6 +278,8 @@ struct nandc_regs {

   * @cmd1/vld: some fixed controller register values
   * @props:properties of current NAND controller IP,
   *initialized via DT match data
+ * @max_cwperpage: maximum qpic codeword required. calcualted


s/calcualted/calculated

Thanks,
Archit


+ * from all nand device pagesize
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -265,11 +307,13 @@ struct qcom_nand_controller {
};
  
  	struct list_head desc_list;

+   struct bam_transaction *bam_txn;
  
  	u8		*data_buffer;

int buf_size;
int buf_count;
int buf_start;
+   unsigned intmax_cwperpage;
  
  	__le32 *reg_read_buf;

dma_addr_t reg_read_buf_phys;
@@ -342,6 +386,50 @@ struct qcom_props {
bool is_bam;
  };
  
+/* Frees the BAM transaction memory */

+static void free_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   devm_kfree(nandc->dev, bam_txn);
+}
+
+/* Allocates and Initializes the BAM transaction */
+static struct bam_transaction *
+alloc_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn;
+   size_t bam_txn_size;
+   unsigned int num_cw = nandc->max_cwperpage;
+   void *bam_txn_buf;
+
+   bam_txn_size =
+   sizeof(*bam_txn) + num_cw *
+   ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+   (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+   (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+
+   bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+   if (!bam_txn_buf)
+   return NULL;
+
+   bam_txn = bam_txn_buf;
+   bam_txn_buf += sizeof(*bam_txn);
+
+   bam_txn->bam_ce = bam_txn_buf;
+   bam_txn_buf +=
+   sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
+   bam_txn->cmd_sgl = bam_txn_buf;
+   

Re: [v5 09/15] sparc64: optimized struct page zeroing

[Sam Ravnborg]

Hi Pavel.

On Thu, Aug 03, 2017 at 05:23:47PM -0400, Pavel Tatashin wrote:
> Add an optimized mm_zero_struct_page(), so struct page's are zeroed without
> calling memset(). We do eight regular stores, thus avoid cost of membar.

The commit message does no longer reflect the implementation,
and should be updated.

> 
> Signed-off-by: Pavel Tatashin 
> Reviewed-by: Steven Sistare 
> Reviewed-by: Daniel Jordan 
> Reviewed-by: Bob Picco 
> ---
>  arch/sparc/include/asm/pgtable_64.h | 32 
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/sparc/include/asm/pgtable_64.h 
> b/arch/sparc/include/asm/pgtable_64.h
> index 6fbd931f0570..be47537e84c5 100644
> --- a/arch/sparc/include/asm/pgtable_64.h
> +++ b/arch/sparc/include/asm/pgtable_64.h
> @@ -230,6 +230,38 @@ extern unsigned long _PAGE_ALL_SZ_BITS;
>  extern struct page *mem_map_zero;
>  #define ZERO_PAGE(vaddr) (mem_map_zero)
>  
> +/* This macro must be updated when the size of struct page grows above 80
> + * or reduces below 64.
> + * The idea that compiler optimizes out switch() statement, and only
> + * leaves clrx instructions or memset() call.
> + */
> +#define  mm_zero_struct_page(pp) do {
> \
> + unsigned long *_pp = (void *)(pp);  \
> + \
> + /* Check that struct page is 8-byte aligned */  \
> + BUILD_BUG_ON(sizeof(struct page) & 7);  \
Would also be good to catch if sizeof > 80 so we do not silently
migrate to the suboptimal version (silent at build time).
Can you at build time catch if size is no any of: 64, 72, 80
and simplify the below a little?

Sam

Re: [v5 09/15] sparc64: optimized struct page zeroing

[Sam Ravnborg]

Hi Pavel.

On Thu, Aug 03, 2017 at 05:23:47PM -0400, Pavel Tatashin wrote:
> Add an optimized mm_zero_struct_page(), so struct page's are zeroed without
> calling memset(). We do eight regular stores, thus avoid cost of membar.

The commit message does no longer reflect the implementation,
and should be updated.

> 
> Signed-off-by: Pavel Tatashin 
> Reviewed-by: Steven Sistare 
> Reviewed-by: Daniel Jordan 
> Reviewed-by: Bob Picco 
> ---
>  arch/sparc/include/asm/pgtable_64.h | 32 
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/sparc/include/asm/pgtable_64.h 
> b/arch/sparc/include/asm/pgtable_64.h
> index 6fbd931f0570..be47537e84c5 100644
> --- a/arch/sparc/include/asm/pgtable_64.h
> +++ b/arch/sparc/include/asm/pgtable_64.h
> @@ -230,6 +230,38 @@ extern unsigned long _PAGE_ALL_SZ_BITS;
>  extern struct page *mem_map_zero;
>  #define ZERO_PAGE(vaddr) (mem_map_zero)
>  
> +/* This macro must be updated when the size of struct page grows above 80
> + * or reduces below 64.
> + * The idea that compiler optimizes out switch() statement, and only
> + * leaves clrx instructions or memset() call.
> + */
> +#define  mm_zero_struct_page(pp) do {
> \
> + unsigned long *_pp = (void *)(pp);  \
> + \
> + /* Check that struct page is 8-byte aligned */  \
> + BUILD_BUG_ON(sizeof(struct page) & 7);  \
Would also be good to catch if sizeof > 80 so we do not silently
migrate to the suboptimal version (silent at build time).
Can you at build time catch if size is no any of: 64, 72, 80
and simplify the below a little?

Sam

Re: [PATCH net-next] net: dsa: User per-cpu 64-bit statistics

[Eric Dumazet]

On Thu, 2017-08-03 at 21:33 -0700, Florian Fainelli wrote:
> During testing with a background iperf pushing 1Gbit/sec worth of
> traffic and having both ifconfig and ethtool collect statistics, we
> could see quite frequent deadlocks. Convert the often accessed DSA slave
> network devices statistics to per-cpu 64-bit statistics to remove these
> deadlocks and provide fast efficient statistics updates.
> 

This seems to be a bug fix, it would be nice to get a proper tag like :

Fixes: f613ed665bb3 ("net: dsa: Add support for 64-bit statistics")

Problem here is that if multiple cpus can call dsa_switch_rcv() at the
same time, then u64_stats_update_begin() contract is not respected.

include/linux/u64_stats_sync.h states :

 * Usage :
 *
 * Stats producer (writer) should use following template granted it already got
 * an exclusive access to counters (a lock is already taken, or per cpu
 * data is used [in a non preemptable context])
 *
 *   spin_lock_bh(...) or other synchronization to get exclusive access
 *   ...
 *   u64_stats_update_begin(>syncp);

Re: [PATCH net-next] net: dsa: User per-cpu 64-bit statistics

[Eric Dumazet]

On Thu, 2017-08-03 at 21:33 -0700, Florian Fainelli wrote:
> During testing with a background iperf pushing 1Gbit/sec worth of
> traffic and having both ifconfig and ethtool collect statistics, we
> could see quite frequent deadlocks. Convert the often accessed DSA slave
> network devices statistics to per-cpu 64-bit statistics to remove these
> deadlocks and provide fast efficient statistics updates.
> 

This seems to be a bug fix, it would be nice to get a proper tag like :

Fixes: f613ed665bb3 ("net: dsa: Add support for 64-bit statistics")

Problem here is that if multiple cpus can call dsa_switch_rcv() at the
same time, then u64_stats_update_begin() contract is not respected.

include/linux/u64_stats_sync.h states :

 * Usage :
 *
 * Stats producer (writer) should use following template granted it already got
 * an exclusive access to counters (a lock is already taken, or per cpu
 * data is used [in a non preemptable context])
 *
 *   spin_lock_bh(...) or other synchronization to get exclusive access
 *   ...
 *   u64_stats_update_begin(>syncp);

[PATCH BUGFIX/IMPROVEMENT V2 1/2] block,bfq: refactor device-idling logic

[Paolo Valente]

The logic that decides whether to idle the device is scattered across
three functions. Almost all of the logic is in the function
bfq_bfqq_may_idle, but (1) part of the decision is made in
bfq_update_idle_window, and (2) the function bfq_bfqq_must_idle may
switch off idling regardless of the output of bfq_bfqq_may_idle. In
addition, both bfq_update_idle_window and bfq_bfqq_must_idle make
their decisions as a function of parameters that are used, for similar
purposes, also in bfq_bfqq_may_idle. This commit addresses these
issues by moving all the logic into bfq_bfqq_may_idle.

Signed-off-by: Paolo Valente 
---
 block/bfq-iosched.c | 117 +++-
 block/bfq-iosched.h |  12 +++---
 2 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index 436b6ca..ccdc9e6 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -128,7 +128,7 @@ BFQ_BFQQ_FNS(busy);
 BFQ_BFQQ_FNS(wait_request);
 BFQ_BFQQ_FNS(non_blocking_wait_rq);
 BFQ_BFQQ_FNS(fifo_expire);
-BFQ_BFQQ_FNS(idle_window);
+BFQ_BFQQ_FNS(has_short_ttime);
 BFQ_BFQQ_FNS(sync);
 BFQ_BFQQ_FNS(IO_bound);
 BFQ_BFQQ_FNS(in_large_burst);
@@ -731,10 +731,10 @@ bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct 
bfq_data *bfqd,
unsigned int old_wr_coeff = bfqq->wr_coeff;
bool busy = bfq_already_existing && bfq_bfqq_busy(bfqq);
 
-   if (bic->saved_idle_window)
-   bfq_mark_bfqq_idle_window(bfqq);
+   if (bic->saved_has_short_ttime)
+   bfq_mark_bfqq_has_short_ttime(bfqq);
else
-   bfq_clear_bfqq_idle_window(bfqq);
+   bfq_clear_bfqq_has_short_ttime(bfqq);
 
if (bic->saved_IO_bound)
bfq_mark_bfqq_IO_bound(bfqq);
@@ -2012,7 +2012,7 @@ static void bfq_bfqq_save_state(struct bfq_queue *bfqq)
return;
 
bic->saved_ttime = bfqq->ttime;
-   bic->saved_idle_window = bfq_bfqq_idle_window(bfqq);
+   bic->saved_has_short_ttime = bfq_bfqq_has_short_ttime(bfqq);
bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
bic->was_in_burst_list = !hlist_unhashed(>burst_list_node);
@@ -3038,8 +3038,8 @@ void bfq_bfqq_expire(struct bfq_data *bfqd,
}
 
bfq_log_bfqq(bfqd, bfqq,
-   "expire (%d, slow %d, num_disp %d, idle_win %d)", reason,
-   slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq));
+   "expire (%d, slow %d, num_disp %d, short_ttime %d)", reason,
+   slow, bfqq->dispatched, bfq_bfqq_has_short_ttime(bfqq));
 
/*
 * Increase, decrease or leave budget unchanged according to
@@ -3122,6 +3122,18 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
return true;
 
/*
+* Idling is performed only if slice_idle > 0. In addition, we
+* do not idle if
+* (a) bfqq is async
+* (b) bfqq is in the idle io prio class: in this case we do
+* not idle because we want to minimize the bandwidth that
+* queues in this class can steal to higher-priority queues
+*/
+   if (bfqd->bfq_slice_idle == 0 || !bfq_bfqq_sync(bfqq) ||
+   bfq_class_idle(bfqq))
+   return false;
+
+   /*
 * The next variable takes into account the cases where idling
 * boosts the throughput.
 *
@@ -3142,7 +3154,7 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
 */
idling_boosts_thr = !bfqd->hw_tag ||
(!blk_queue_nonrot(bfqd->queue) && bfq_bfqq_IO_bound(bfqq) &&
-bfq_bfqq_idle_window(bfqq));
+bfq_bfqq_has_short_ttime(bfqq));
 
/*
 * The value of the next variable,
@@ -3313,16 +3325,13 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
asymmetric_scenario && !bfq_bfqq_in_large_burst(bfqq);
 
/*
-* We have now all the components we need to compute the return
-* value of the function, which is true only if both the following
-* conditions hold:
-* 1) bfqq is sync, because idling make sense only for sync queues;
-* 2) idling either boosts the throughput (without issues), or
-*is necessary to preserve service guarantees.
+* We have now all the components we need to compute the
+* return value of the function, which is true only if idling
+* either boosts the throughput (without issues), or is
+* necessary to preserve service guarantees.
 */
-   return bfq_bfqq_sync(bfqq) &&
-   (idling_boosts_thr_without_issues ||
-idling_needed_for_service_guarantees);
+   return idling_boosts_thr_without_issues ||
+   idling_needed_for_service_guarantees;
 }
 
 /*
@@ -3338,10 +3347,7 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
  */
 static 

[PATCH BUGFIX/IMPROVEMENT V2 0/2] block, bfq: improve and refactor throughput-boosting logic

[Paolo Valente]

Hi,
these two patches improve throughput-boosting logic in two
aspects. The first patch refactors the parts of the device-idling
logic, related to throughput boosting, that are still scattered across
the source file bfq-iosched.c. The patch concetrates all the logic in
one function. The second patch fixes/improves device idling for
flash-based devices that have no internal queueing of I/O requests.

The contribution in the first patch has been triggered by that in the
second patch: finding the change made by the second patch has been
more difficult than it had to be, because the logic that decides
whether to idle the device is scattered across three functions.

The second patch provides a significant throghput boost, for random
I/O with flash-based non-queueing devices. For example, on a HiKey
board, throughput increases by up to 125%, growing, e.g., from 6.9MB/s
to 15.6MB/s with two or three random readers in parallel.

Thanks,
Paolo

Paolo Valente (2):
  block,bfq: refactor device-idling logic
  block, bfq: boost throughput with flash-based non-queueing devices

 block/bfq-iosched.c | 144 
 block/bfq-iosched.h |  12 ++---
 2 files changed, 85 insertions(+), 71 deletions(-)

--
2.10.0

[PATCH BUGFIX/IMPROVEMENT V2 1/2] block,bfq: refactor device-idling logic

[Paolo Valente]

The logic that decides whether to idle the device is scattered across
three functions. Almost all of the logic is in the function
bfq_bfqq_may_idle, but (1) part of the decision is made in
bfq_update_idle_window, and (2) the function bfq_bfqq_must_idle may
switch off idling regardless of the output of bfq_bfqq_may_idle. In
addition, both bfq_update_idle_window and bfq_bfqq_must_idle make
their decisions as a function of parameters that are used, for similar
purposes, also in bfq_bfqq_may_idle. This commit addresses these
issues by moving all the logic into bfq_bfqq_may_idle.

Signed-off-by: Paolo Valente 
---
 block/bfq-iosched.c | 117 +++-
 block/bfq-iosched.h |  12 +++---
 2 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index 436b6ca..ccdc9e6 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -128,7 +128,7 @@ BFQ_BFQQ_FNS(busy);
 BFQ_BFQQ_FNS(wait_request);
 BFQ_BFQQ_FNS(non_blocking_wait_rq);
 BFQ_BFQQ_FNS(fifo_expire);
-BFQ_BFQQ_FNS(idle_window);
+BFQ_BFQQ_FNS(has_short_ttime);
 BFQ_BFQQ_FNS(sync);
 BFQ_BFQQ_FNS(IO_bound);
 BFQ_BFQQ_FNS(in_large_burst);
@@ -731,10 +731,10 @@ bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct 
bfq_data *bfqd,
unsigned int old_wr_coeff = bfqq->wr_coeff;
bool busy = bfq_already_existing && bfq_bfqq_busy(bfqq);
 
-   if (bic->saved_idle_window)
-   bfq_mark_bfqq_idle_window(bfqq);
+   if (bic->saved_has_short_ttime)
+   bfq_mark_bfqq_has_short_ttime(bfqq);
else
-   bfq_clear_bfqq_idle_window(bfqq);
+   bfq_clear_bfqq_has_short_ttime(bfqq);
 
if (bic->saved_IO_bound)
bfq_mark_bfqq_IO_bound(bfqq);
@@ -2012,7 +2012,7 @@ static void bfq_bfqq_save_state(struct bfq_queue *bfqq)
return;
 
bic->saved_ttime = bfqq->ttime;
-   bic->saved_idle_window = bfq_bfqq_idle_window(bfqq);
+   bic->saved_has_short_ttime = bfq_bfqq_has_short_ttime(bfqq);
bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
bic->was_in_burst_list = !hlist_unhashed(>burst_list_node);
@@ -3038,8 +3038,8 @@ void bfq_bfqq_expire(struct bfq_data *bfqd,
}
 
bfq_log_bfqq(bfqd, bfqq,
-   "expire (%d, slow %d, num_disp %d, idle_win %d)", reason,
-   slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq));
+   "expire (%d, slow %d, num_disp %d, short_ttime %d)", reason,
+   slow, bfqq->dispatched, bfq_bfqq_has_short_ttime(bfqq));
 
/*
 * Increase, decrease or leave budget unchanged according to
@@ -3122,6 +3122,18 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
return true;
 
/*
+* Idling is performed only if slice_idle > 0. In addition, we
+* do not idle if
+* (a) bfqq is async
+* (b) bfqq is in the idle io prio class: in this case we do
+* not idle because we want to minimize the bandwidth that
+* queues in this class can steal to higher-priority queues
+*/
+   if (bfqd->bfq_slice_idle == 0 || !bfq_bfqq_sync(bfqq) ||
+   bfq_class_idle(bfqq))
+   return false;
+
+   /*
 * The next variable takes into account the cases where idling
 * boosts the throughput.
 *
@@ -3142,7 +3154,7 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
 */
idling_boosts_thr = !bfqd->hw_tag ||
(!blk_queue_nonrot(bfqd->queue) && bfq_bfqq_IO_bound(bfqq) &&
-bfq_bfqq_idle_window(bfqq));
+bfq_bfqq_has_short_ttime(bfqq));
 
/*
 * The value of the next variable,
@@ -3313,16 +3325,13 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
asymmetric_scenario && !bfq_bfqq_in_large_burst(bfqq);
 
/*
-* We have now all the components we need to compute the return
-* value of the function, which is true only if both the following
-* conditions hold:
-* 1) bfqq is sync, because idling make sense only for sync queues;
-* 2) idling either boosts the throughput (without issues), or
-*is necessary to preserve service guarantees.
+* We have now all the components we need to compute the
+* return value of the function, which is true only if idling
+* either boosts the throughput (without issues), or is
+* necessary to preserve service guarantees.
 */
-   return bfq_bfqq_sync(bfqq) &&
-   (idling_boosts_thr_without_issues ||
-idling_needed_for_service_guarantees);
+   return idling_boosts_thr_without_issues ||
+   idling_needed_for_service_guarantees;
 }
 
 /*
@@ -3338,10 +3347,7 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
  */
 static bool 

[PATCH BUGFIX/IMPROVEMENT V2 0/2] block, bfq: improve and refactor throughput-boosting logic

[Paolo Valente]

Hi,
these two patches improve throughput-boosting logic in two
aspects. The first patch refactors the parts of the device-idling
logic, related to throughput boosting, that are still scattered across
the source file bfq-iosched.c. The patch concetrates all the logic in
one function. The second patch fixes/improves device idling for
flash-based devices that have no internal queueing of I/O requests.

The contribution in the first patch has been triggered by that in the
second patch: finding the change made by the second patch has been
more difficult than it had to be, because the logic that decides
whether to idle the device is scattered across three functions.

The second patch provides a significant throghput boost, for random
I/O with flash-based non-queueing devices. For example, on a HiKey
board, throughput increases by up to 125%, growing, e.g., from 6.9MB/s
to 15.6MB/s with two or three random readers in parallel.

Thanks,
Paolo

Paolo Valente (2):
  block,bfq: refactor device-idling logic
  block, bfq: boost throughput with flash-based non-queueing devices

 block/bfq-iosched.c | 144 
 block/bfq-iosched.h |  12 ++---
 2 files changed, 85 insertions(+), 71 deletions(-)

--
2.10.0

[PATCH BUGFIX/IMPROVEMENT V2 2/2] block, bfq: boost throughput with flash-based non-queueing devices

[Paolo Valente]

When a queue associated with a process remains empty, there are cases
where throughput gets boosted if the device is idled to await the
arrival of a new I/O request for that queue. Currently, BFQ assumes
that one of these cases is when the device has no internal queueing
(regardless of the properties of the I/O being served). Unfortunately,
this condition has proved to be too general. So, this commit refines it
as "the device has no internal queueing and is rotational".

This refinement provides a significant throughput boost with random
I/O, on flash-based storage without internal queueing. For example, on
a HiKey board, throughput increases by up to 125%, growing, e.g., from
6.9MB/s to 15.6MB/s with two or three random readers in parallel.

Signed-off-by: Paolo Valente 
Signed-off-by: Luca Miccio 
---
 block/bfq-iosched.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index ccdc9e6..509f399 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -3114,7 +3114,10 @@ static bool bfq_may_expire_for_budg_timeout(struct 
bfq_queue *bfqq)
 static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
 {
struct bfq_data *bfqd = bfqq->bfqd;
-   bool idling_boosts_thr, idling_boosts_thr_without_issues,
+   bool rot_without_queueing =
+   !blk_queue_nonrot(bfqd->queue) && !bfqd->hw_tag,
+   bfqq_sequential_and_IO_bound,
+   idling_boosts_thr, idling_boosts_thr_without_issues,
idling_needed_for_service_guarantees,
asymmetric_scenario;
 
@@ -3133,28 +3136,34 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
bfq_class_idle(bfqq))
return false;
 
+   bfqq_sequential_and_IO_bound = !BFQQ_SEEKY(bfqq) &&
+   bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_has_short_ttime(bfqq);
+
/*
 * The next variable takes into account the cases where idling
 * boosts the throughput.
 *
 * The value of the variable is computed considering, first, that
 * idling is virtually always beneficial for the throughput if:
-* (a) the device is not NCQ-capable, or
-* (b) regardless of the presence of NCQ, the device is rotational
-* and the request pattern for bfqq is I/O-bound and sequential.
+* (a) the device is not NCQ-capable and rotational, or
+* (b) regardless of the presence of NCQ, the device is rotational and
+* the request pattern for bfqq is I/O-bound and sequential, or
+* (c) regardless of whether it is rotational, the device is
+* not NCQ-capable and the request pattern for bfqq is
+* I/O-bound and sequential.
 *
 * Secondly, and in contrast to the above item (b), idling an
 * NCQ-capable flash-based device would not boost the
 * throughput even with sequential I/O; rather it would lower
 * the throughput in proportion to how fast the device
 * is. Accordingly, the next variable is true if any of the
-* above conditions (a) and (b) is true, and, in particular,
-* happens to be false if bfqd is an NCQ-capable flash-based
-* device.
+* above conditions (a), (b) or (c) is true, and, in
+* particular, happens to be false if bfqd is an NCQ-capable
+* flash-based device.
 */
-   idling_boosts_thr = !bfqd->hw_tag ||
-   (!blk_queue_nonrot(bfqd->queue) && bfq_bfqq_IO_bound(bfqq) &&
-bfq_bfqq_has_short_ttime(bfqq));
+   idling_boosts_thr = rot_without_queueing ||
+   ((!blk_queue_nonrot(bfqd->queue) || !bfqd->hw_tag) &&
+bfqq_sequential_and_IO_bound);
 
/*
 * The value of the next variable,
-- 
2.10.0

[PATCH BUGFIX/IMPROVEMENT V2 2/2] block, bfq: boost throughput with flash-based non-queueing devices

[Paolo Valente]

When a queue associated with a process remains empty, there are cases
where throughput gets boosted if the device is idled to await the
arrival of a new I/O request for that queue. Currently, BFQ assumes
that one of these cases is when the device has no internal queueing
(regardless of the properties of the I/O being served). Unfortunately,
this condition has proved to be too general. So, this commit refines it
as "the device has no internal queueing and is rotational".

This refinement provides a significant throughput boost with random
I/O, on flash-based storage without internal queueing. For example, on
a HiKey board, throughput increases by up to 125%, growing, e.g., from
6.9MB/s to 15.6MB/s with two or three random readers in parallel.

Signed-off-by: Paolo Valente 
Signed-off-by: Luca Miccio 
---
 block/bfq-iosched.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index ccdc9e6..509f399 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -3114,7 +3114,10 @@ static bool bfq_may_expire_for_budg_timeout(struct 
bfq_queue *bfqq)
 static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
 {
struct bfq_data *bfqd = bfqq->bfqd;
-   bool idling_boosts_thr, idling_boosts_thr_without_issues,
+   bool rot_without_queueing =
+   !blk_queue_nonrot(bfqd->queue) && !bfqd->hw_tag,
+   bfqq_sequential_and_IO_bound,
+   idling_boosts_thr, idling_boosts_thr_without_issues,
idling_needed_for_service_guarantees,
asymmetric_scenario;
 
@@ -3133,28 +3136,34 @@ static bool bfq_bfqq_may_idle(struct bfq_queue *bfqq)
bfq_class_idle(bfqq))
return false;
 
+   bfqq_sequential_and_IO_bound = !BFQQ_SEEKY(bfqq) &&
+   bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_has_short_ttime(bfqq);
+
/*
 * The next variable takes into account the cases where idling
 * boosts the throughput.
 *
 * The value of the variable is computed considering, first, that
 * idling is virtually always beneficial for the throughput if:
-* (a) the device is not NCQ-capable, or
-* (b) regardless of the presence of NCQ, the device is rotational
-* and the request pattern for bfqq is I/O-bound and sequential.
+* (a) the device is not NCQ-capable and rotational, or
+* (b) regardless of the presence of NCQ, the device is rotational and
+* the request pattern for bfqq is I/O-bound and sequential, or
+* (c) regardless of whether it is rotational, the device is
+* not NCQ-capable and the request pattern for bfqq is
+* I/O-bound and sequential.
 *
 * Secondly, and in contrast to the above item (b), idling an
 * NCQ-capable flash-based device would not boost the
 * throughput even with sequential I/O; rather it would lower
 * the throughput in proportion to how fast the device
 * is. Accordingly, the next variable is true if any of the
-* above conditions (a) and (b) is true, and, in particular,
-* happens to be false if bfqd is an NCQ-capable flash-based
-* device.
+* above conditions (a), (b) or (c) is true, and, in
+* particular, happens to be false if bfqd is an NCQ-capable
+* flash-based device.
 */
-   idling_boosts_thr = !bfqd->hw_tag ||
-   (!blk_queue_nonrot(bfqd->queue) && bfq_bfqq_IO_bound(bfqq) &&
-bfq_bfqq_has_short_ttime(bfqq));
+   idling_boosts_thr = rot_without_queueing ||
+   ((!blk_queue_nonrot(bfqd->queue) || !bfqd->hw_tag) &&
+bfqq_sequential_and_IO_bound);
 
/*
 * The value of the next variable,
-- 
2.10.0

Re: [V3 1/2] phy: ralink-usb: add driver for Mediatek/Ralink

[Kishon Vijay Abraham I]

On Thursday 03 August 2017 04:02 PM, Harvey Hunt wrote:
> From: John Crispin 
> 
> Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
> The driver is trivial and only sets up power and host mode.
> 
> Signed-off-by: John Crispin 
> Signed-off-by: Harvey Hunt 
> Cc: linux-kernel@vger.kernel.org 
> Cc: linux-media...@lists.infradead.org 
> ---
> Changes in V3
> * Separate DT bindings
> * Update Kconfig text
> * Modify John's email address
> * Rebase onto v4.13-rc3
> 
> Changes in V2
> * remove refcounting
> * drop empty functions
> * dont use static globals
> * use explicit compatible strings
> 
>  drivers/phy/Kconfig  |   8 ++
>  drivers/phy/Makefile |   1 +
>  drivers/phy/phy-ralink-usb.c | 175 
> +++
>  3 files changed, 184 insertions(+)
>  create mode 100644 drivers/phy/phy-ralink-usb.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index c1807d4..79f966a 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
>   help
> Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
>  
> +config PHY_RALINK_USB
> + tristate "Ralink USB PHY driver"
> + select GENERIC_PHY
> + depends on RALINK

depends on RALINK || COMPILE_TEST?

Thanks
Kishon

Re: [V3 1/2] phy: ralink-usb: add driver for Mediatek/Ralink

[Kishon Vijay Abraham I]

On Thursday 03 August 2017 04:02 PM, Harvey Hunt wrote:
> From: John Crispin 
> 
> Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
> The driver is trivial and only sets up power and host mode.
> 
> Signed-off-by: John Crispin 
> Signed-off-by: Harvey Hunt 
> Cc: linux-kernel@vger.kernel.org 
> Cc: linux-media...@lists.infradead.org 
> ---
> Changes in V3
> * Separate DT bindings
> * Update Kconfig text
> * Modify John's email address
> * Rebase onto v4.13-rc3
> 
> Changes in V2
> * remove refcounting
> * drop empty functions
> * dont use static globals
> * use explicit compatible strings
> 
>  drivers/phy/Kconfig  |   8 ++
>  drivers/phy/Makefile |   1 +
>  drivers/phy/phy-ralink-usb.c | 175 
> +++
>  3 files changed, 184 insertions(+)
>  create mode 100644 drivers/phy/phy-ralink-usb.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index c1807d4..79f966a 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
>   help
> Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
>  
> +config PHY_RALINK_USB
> + tristate "Ralink USB PHY driver"
> + select GENERIC_PHY
> + depends on RALINK

depends on RALINK || COMPILE_TEST?

Thanks
Kishon

Re: [PATCH v2 2/4] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Kishon Vijay Abraham I]

Hi,

On Wednesday 26 July 2017 11:36 AM, Jiancheng Xue wrote:
> From: Pengcheng Li 
> 
> Add inno-usb2-phy driver for hi3798cv200 SoC.
> 
> Signed-off-by: Pengcheng Li 
> Signed-off-by: Jiancheng Xue 
> ---
>  drivers/phy/hisilicon/Kconfig  |  11 +-
>  drivers/phy/hisilicon/Makefile |   1 +
>  drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 236 
> +
>  3 files changed, 247 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> 
> diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
> index 6164c4c..6a675c5 100644
> --- a/drivers/phy/hisilicon/Kconfig
> +++ b/drivers/phy/hisilicon/Kconfig
> @@ -8,9 +8,18 @@ config PHY_HI6220_USB
>   select MFD_SYSCON
>   help
> Enable this to support the HISILICON HI6220 USB PHY.
> -
  ^^
not related to $patch.
> To compile this driver as a module, choose M here.
>  
> +config PHY_HISI_INNO_USB2
> +   tristate "HiSilicon INNO USB2 PHY support"
> +   depends on (ARCH_HISI) || COMPILE_TEST
> +   select GENERIC_PHY
> +   select MFD_SYSCON
> +   help
> + Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
> + USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
> + USB host port to accept one USB device.
> +
>  config PHY_HIX5HD2_SATA
>   tristate "HIX5HD2 SATA PHY Driver"
>   depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
> diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
> index 541b348..e6c9794 100644
> --- a/drivers/phy/hisilicon/Makefile
> +++ b/drivers/phy/hisilicon/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o
> +obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o
>  obj-$(CONFIG_PHY_HIX5HD2_SATA)   += phy-hix5hd2-sata.o
> diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c 
> b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> new file mode 100644
> index 000..7edf4a3
> --- /dev/null
> +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> @@ -0,0 +1,236 @@
> +/*
> + * HiSilicon INNO USB2 PHY Driver.
> + *
> + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define INNO_PHY_PORT_NUM2
> +#define REF_CLK_STABLE_TIME  100 /* unit:us */
> +#define UTMI_CLK_STABLE_TIME 200 /* unit:us */
> +#define TEST_CLK_STABLE_TIME 2   /* unit:ms */
> +#define PHY_CLK_STABLE_TIME  2   /* unit:ms */
> +#define UTMI_RST_COMPLETE_TIME   2   /* unit:ms */
> +#define TEST_RST_COMPLETE_TIME   100 /* unit:us */
> +#define POR_RST_COMPLETE_TIME300 /* unit:us */
> +#define PHY_TEST_DATAGENMASK(7, 0)
> +#define PHY_TEST_ADDRGENMASK(15, 8)
> +#define PHY_TEST_PORTGENMASK(18, 16)
> +#define PHY_TEST_WRENBIT(21)
> +#define PHY_TEST_CLK BIT(22) /* rising edge active */
> +#define PHY_TEST_RST BIT(23) /* low active */
> +#define PHY_CLK_ENABLE   BIT(2)
> +
> +struct hisi_inno_phy_priv {
> + struct regmap *syscon;
> + u32 reg;
> + struct clk *ref_clk;
> + struct reset_control *por_rst;
> + struct reset_control *test_rst;
> + struct reset_control *utmi_rst[INNO_PHY_PORT_NUM];
> + u32 port_num;
> +};
> +
> +static void hisi_inno_phy_write_reg(struct regmap *syscon,
> + u32 reg, u8 port, u32 addr, u32 data)
> +{
> + u32 value;
> +
> + value = (data & PHY_TEST_DATA)
> + | ((addr << 8) & PHY_TEST_ADDR)
> + | ((port << 16) & PHY_TEST_PORT)
> + | PHY_TEST_WREN | PHY_TEST_RST;
> + regmap_write(syscon, reg, value);
> + value |= PHY_TEST_CLK;
> + regmap_write(syscon, reg, value);
> + value &= ~PHY_TEST_CLK;
> + regmap_write(syscon, reg, value);
> +}
> +
> +static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
> +{
> + /* The phy clk is controlled by the port0 register 0x06. */
> + hisi_inno_phy_write_reg(priv->syscon,
> + priv->reg, 0, 0x06, PHY_CLK_ENABLE);
> + msleep(PHY_CLK_STABLE_TIME);
> +}
> +
> +static int 

Re: [PATCH v2 2/4] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Kishon Vijay Abraham I]

Hi,

On Wednesday 26 July 2017 11:36 AM, Jiancheng Xue wrote:
> From: Pengcheng Li 
> 
> Add inno-usb2-phy driver for hi3798cv200 SoC.
> 
> Signed-off-by: Pengcheng Li 
> Signed-off-by: Jiancheng Xue 
> ---
>  drivers/phy/hisilicon/Kconfig  |  11 +-
>  drivers/phy/hisilicon/Makefile |   1 +
>  drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 236 
> +
>  3 files changed, 247 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> 
> diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
> index 6164c4c..6a675c5 100644
> --- a/drivers/phy/hisilicon/Kconfig
> +++ b/drivers/phy/hisilicon/Kconfig
> @@ -8,9 +8,18 @@ config PHY_HI6220_USB
>   select MFD_SYSCON
>   help
> Enable this to support the HISILICON HI6220 USB PHY.
> -
  ^^
not related to $patch.
> To compile this driver as a module, choose M here.
>  
> +config PHY_HISI_INNO_USB2
> +   tristate "HiSilicon INNO USB2 PHY support"
> +   depends on (ARCH_HISI) || COMPILE_TEST
> +   select GENERIC_PHY
> +   select MFD_SYSCON
> +   help
> + Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
> + USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
> + USB host port to accept one USB device.
> +
>  config PHY_HIX5HD2_SATA
>   tristate "HIX5HD2 SATA PHY Driver"
>   depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
> diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
> index 541b348..e6c9794 100644
> --- a/drivers/phy/hisilicon/Makefile
> +++ b/drivers/phy/hisilicon/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o
> +obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o
>  obj-$(CONFIG_PHY_HIX5HD2_SATA)   += phy-hix5hd2-sata.o
> diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c 
> b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> new file mode 100644
> index 000..7edf4a3
> --- /dev/null
> +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> @@ -0,0 +1,236 @@
> +/*
> + * HiSilicon INNO USB2 PHY Driver.
> + *
> + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define INNO_PHY_PORT_NUM2
> +#define REF_CLK_STABLE_TIME  100 /* unit:us */
> +#define UTMI_CLK_STABLE_TIME 200 /* unit:us */
> +#define TEST_CLK_STABLE_TIME 2   /* unit:ms */
> +#define PHY_CLK_STABLE_TIME  2   /* unit:ms */
> +#define UTMI_RST_COMPLETE_TIME   2   /* unit:ms */
> +#define TEST_RST_COMPLETE_TIME   100 /* unit:us */
> +#define POR_RST_COMPLETE_TIME300 /* unit:us */
> +#define PHY_TEST_DATAGENMASK(7, 0)
> +#define PHY_TEST_ADDRGENMASK(15, 8)
> +#define PHY_TEST_PORTGENMASK(18, 16)
> +#define PHY_TEST_WRENBIT(21)
> +#define PHY_TEST_CLK BIT(22) /* rising edge active */
> +#define PHY_TEST_RST BIT(23) /* low active */
> +#define PHY_CLK_ENABLE   BIT(2)
> +
> +struct hisi_inno_phy_priv {
> + struct regmap *syscon;
> + u32 reg;
> + struct clk *ref_clk;
> + struct reset_control *por_rst;
> + struct reset_control *test_rst;
> + struct reset_control *utmi_rst[INNO_PHY_PORT_NUM];
> + u32 port_num;
> +};
> +
> +static void hisi_inno_phy_write_reg(struct regmap *syscon,
> + u32 reg, u8 port, u32 addr, u32 data)
> +{
> + u32 value;
> +
> + value = (data & PHY_TEST_DATA)
> + | ((addr << 8) & PHY_TEST_ADDR)
> + | ((port << 16) & PHY_TEST_PORT)
> + | PHY_TEST_WREN | PHY_TEST_RST;
> + regmap_write(syscon, reg, value);
> + value |= PHY_TEST_CLK;
> + regmap_write(syscon, reg, value);
> + value &= ~PHY_TEST_CLK;
> + regmap_write(syscon, reg, value);
> +}
> +
> +static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
> +{
> + /* The phy clk is controlled by the port0 register 0x06. */
> + hisi_inno_phy_write_reg(priv->syscon,
> + priv->reg, 0, 0x06, PHY_CLK_ENABLE);
> + msleep(PHY_CLK_STABLE_TIME);
> +}
> +
> +static int hisi_inno_phy_init(struct phy *phy)
> +{
> + struct hisi_inno_phy_priv 

Re: [PATCH v2 15/25] mtd: nand: qcom: DMA mapping support for register read buffer

[Archit Taneja]

Hi,

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
descriptor will contain the dma address of the register read
buffer.


It isn't entirely clear from the commit message why we can't use
the existing code with QPIC NAND. A bit of background would help.
Can you consider adding something like this:

"On QPIC NAND, which uses BAM DMA, we read the controller registers
by preparing a BAM command descriptor. This descriptor requires the
the a) controller register address and b) the DMA address in which we
want to store the value read back from the controller register. Therefore,
it's required that we also map our register read buffer for DMA (using
dma_map_single). We use the returned DMA address for preparing
entries in our command descriptor."



This patch adds the DMA mapping support for register read buffer.
This buffer will be DMA mapped during allocation time. Before
starting of any operation, this buffer will be synced for device
operation and after operation completion, it will be synced for
CPU.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 40 
  1 file changed, 40 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -229,6 +229,7 @@ struct nandc_regs {
   *by upper layers directly
   * @buf_size/count/start: markers for chip->read_buf/write_buf functions
   * @reg_read_buf: local buffer for reading back registers via DMA
+ * @reg_read_buf_phys: contains dma address for register read buffer


Maybe we should rename this as reg_read_dma since it is dma_addr_t ?

Looks good otherwise.

Thanks,
Archit


   * @reg_read_pos: marker for data read in reg_read_buf
   *
   * @regs: a contiguous chunk of memory for DMA register
@@ -271,6 +272,7 @@ struct qcom_nand_controller {
int buf_start;
  
  	__le32 *reg_read_buf;

+   dma_addr_t reg_read_buf_phys;
int reg_read_pos;
  
  	struct nandc_regs *regs;

@@ -363,6 +365,24 @@ static inline void nandc_write(struct qcom_nand_controller 
*nandc, int offset,
iowrite32(val, nandc->base + offset);
  }
  
+static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,

+ bool is_cpu)
+{
+   if (!nandc->props->is_bam)
+   return;
+
+   if (is_cpu)
+   dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_buf_phys,
+   MAX_REG_RD *
+   sizeof(*nandc->reg_read_buf),
+   DMA_FROM_DEVICE);
+   else
+   dma_sync_single_for_device(nandc->dev, nandc->reg_read_buf_phys,
+  MAX_REG_RD *
+  sizeof(*nandc->reg_read_buf),
+  DMA_FROM_DEVICE);
+}
+
  static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
  {
switch (offset) {
@@ -847,6 +867,7 @@ static void free_descs(struct qcom_nand_controller *nandc)
  static void clear_read_regs(struct qcom_nand_controller *nandc)
  {
nandc->reg_read_pos = 0;
+   nandc_read_buffer_sync(nandc, false);
  }
  
  static void pre_command(struct qcom_nand_host *host, int command)

@@ -876,6 +897,7 @@ static void parse_erase_write_errors(struct qcom_nand_host 
*host, int command)
int i;
  
  	num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;

+   nandc_read_buffer_sync(nandc, true);
  
  	for (i = 0; i < num_cw; i++) {

u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
@@ -897,6 +919,7 @@ static void post_command(struct qcom_nand_host *host, int 
command)
  
  	switch (command) {

case NAND_CMD_READID:
+   nandc_read_buffer_sync(nandc, true);
memcpy(nandc->data_buffer, nandc->reg_read_buf,
   nandc->buf_count);
break;
@@ -1060,6 +1083,7 @@ static int parse_read_errors(struct qcom_nand_host *host, 
u8 *data_buf,
int i;
  
  	buf = (struct read_stats *)nandc->reg_read_buf;

+   nandc_read_buffer_sync(nandc, true);
  
  	for (i = 0; i < ecc->steps; i++, buf++) {

u32 flash, buffer, erased_cw;
@@ -1996,6 +2020,16 @@ static int qcom_nandc_alloc(struct qcom_nand_controller 
*nandc)
return -ENOMEM;
  
  	if (nandc->props->is_bam) {

+   nandc->reg_read_buf_phys =
+   dma_map_single(nandc->dev, nandc->reg_read_buf,
+   

Re: [PATCH v2 15/25] mtd: nand: qcom: DMA mapping support for register read buffer

[Archit Taneja]

Hi,

On 07/19/2017 05:18 PM, Abhishek Sahu wrote:

The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
descriptor will contain the dma address of the register read
buffer.


It isn't entirely clear from the commit message why we can't use
the existing code with QPIC NAND. A bit of background would help.
Can you consider adding something like this:

"On QPIC NAND, which uses BAM DMA, we read the controller registers
by preparing a BAM command descriptor. This descriptor requires the
the a) controller register address and b) the DMA address in which we
want to store the value read back from the controller register. Therefore,
it's required that we also map our register read buffer for DMA (using
dma_map_single). We use the returned DMA address for preparing
entries in our command descriptor."



This patch adds the DMA mapping support for register read buffer.
This buffer will be DMA mapped during allocation time. Before
starting of any operation, this buffer will be synced for device
operation and after operation completion, it will be synced for
CPU.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 40 
  1 file changed, 40 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -229,6 +229,7 @@ struct nandc_regs {
   *by upper layers directly
   * @buf_size/count/start: markers for chip->read_buf/write_buf functions
   * @reg_read_buf: local buffer for reading back registers via DMA
+ * @reg_read_buf_phys: contains dma address for register read buffer


Maybe we should rename this as reg_read_dma since it is dma_addr_t ?

Looks good otherwise.

Thanks,
Archit


   * @reg_read_pos: marker for data read in reg_read_buf
   *
   * @regs: a contiguous chunk of memory for DMA register
@@ -271,6 +272,7 @@ struct qcom_nand_controller {
int buf_start;
  
  	__le32 *reg_read_buf;

+   dma_addr_t reg_read_buf_phys;
int reg_read_pos;
  
  	struct nandc_regs *regs;

@@ -363,6 +365,24 @@ static inline void nandc_write(struct qcom_nand_controller 
*nandc, int offset,
iowrite32(val, nandc->base + offset);
  }
  
+static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,

+ bool is_cpu)
+{
+   if (!nandc->props->is_bam)
+   return;
+
+   if (is_cpu)
+   dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_buf_phys,
+   MAX_REG_RD *
+   sizeof(*nandc->reg_read_buf),
+   DMA_FROM_DEVICE);
+   else
+   dma_sync_single_for_device(nandc->dev, nandc->reg_read_buf_phys,
+  MAX_REG_RD *
+  sizeof(*nandc->reg_read_buf),
+  DMA_FROM_DEVICE);
+}
+
  static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
  {
switch (offset) {
@@ -847,6 +867,7 @@ static void free_descs(struct qcom_nand_controller *nandc)
  static void clear_read_regs(struct qcom_nand_controller *nandc)
  {
nandc->reg_read_pos = 0;
+   nandc_read_buffer_sync(nandc, false);
  }
  
  static void pre_command(struct qcom_nand_host *host, int command)

@@ -876,6 +897,7 @@ static void parse_erase_write_errors(struct qcom_nand_host 
*host, int command)
int i;
  
  	num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;

+   nandc_read_buffer_sync(nandc, true);
  
  	for (i = 0; i < num_cw; i++) {

u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
@@ -897,6 +919,7 @@ static void post_command(struct qcom_nand_host *host, int 
command)
  
  	switch (command) {

case NAND_CMD_READID:
+   nandc_read_buffer_sync(nandc, true);
memcpy(nandc->data_buffer, nandc->reg_read_buf,
   nandc->buf_count);
break;
@@ -1060,6 +1083,7 @@ static int parse_read_errors(struct qcom_nand_host *host, 
u8 *data_buf,
int i;
  
  	buf = (struct read_stats *)nandc->reg_read_buf;

+   nandc_read_buffer_sync(nandc, true);
  
  	for (i = 0; i < ecc->steps; i++, buf++) {

u32 flash, buffer, erased_cw;
@@ -1996,6 +2020,16 @@ static int qcom_nandc_alloc(struct qcom_nand_controller 
*nandc)
return -ENOMEM;
  
  	if (nandc->props->is_bam) {

+   nandc->reg_read_buf_phys =
+   dma_map_single(nandc->dev, nandc->reg_read_buf,
+  

Re: [PATCH 0/2] PCI: dwc: convert remaining dbi read/writes to dw_pcie_readX_dbi/dw_pcie_writeX_dbi

[Kishon Vijay Abraham I]

On Friday 04 August 2017 01:42 AM, Bjorn Helgaas wrote:
> Adding Kishon & Pratyush for real this time.
> 
> On Wed, Aug 02, 2017 at 04:32:56PM -0500, Bjorn Helgaas wrote:
>> [+cc Kishon, Pratyush]
>>
>> On Fri, Jul 14, 2017 at 02:07:33PM +0200, Niklas Cassel wrote:
>>> Since the introduction of the dw_pcie_readX_dbi/dw_pcie_writeX_dbi macros,
>>> most dw_pcie_read(pci->dbi_base, ..)/dw_pcie_write(pci->dbi_base, ..) calls
>>> have been converted to dw_pcie_readX_dbi/dw_pcie_writeX_dbi calls.
>>> Convert the remaining calls.
>>>
>>> Niklas Cassel (2):
>>>   PCI: dwc: dra7xx: utilize dw_pcie_readX_dbi/dw_pcie_writeX_dbi macros
>>>   PCI: dwc: spear13xx: utilize dw_pcie_readX_dbi/dw_pcie_writeX_dbi
>>> macros
>>>
>>>  drivers/pci/dwc/pci-dra7xx.c | 14 ++
>>>  drivers/pci/dwc/pcie-spear13xx.c | 22 ++
>>>  2 files changed, 16 insertions(+), 20 deletions(-)
>>
>> Waiting for ack from maintainers (cc'd).

Tested this in dra7xx
Acked-by: Kishon Vijay Abraham I 

Re: [PATCH 0/2] PCI: dwc: convert remaining dbi read/writes to dw_pcie_readX_dbi/dw_pcie_writeX_dbi

[Kishon Vijay Abraham I]

On Friday 04 August 2017 01:42 AM, Bjorn Helgaas wrote:
> Adding Kishon & Pratyush for real this time.
> 
> On Wed, Aug 02, 2017 at 04:32:56PM -0500, Bjorn Helgaas wrote:
>> [+cc Kishon, Pratyush]
>>
>> On Fri, Jul 14, 2017 at 02:07:33PM +0200, Niklas Cassel wrote:
>>> Since the introduction of the dw_pcie_readX_dbi/dw_pcie_writeX_dbi macros,
>>> most dw_pcie_read(pci->dbi_base, ..)/dw_pcie_write(pci->dbi_base, ..) calls
>>> have been converted to dw_pcie_readX_dbi/dw_pcie_writeX_dbi calls.
>>> Convert the remaining calls.
>>>
>>> Niklas Cassel (2):
>>>   PCI: dwc: dra7xx: utilize dw_pcie_readX_dbi/dw_pcie_writeX_dbi macros
>>>   PCI: dwc: spear13xx: utilize dw_pcie_readX_dbi/dw_pcie_writeX_dbi
>>> macros
>>>
>>>  drivers/pci/dwc/pci-dra7xx.c | 14 ++
>>>  drivers/pci/dwc/pcie-spear13xx.c | 22 ++
>>>  2 files changed, 16 insertions(+), 20 deletions(-)
>>
>> Waiting for ack from maintainers (cc'd).

Tested this in dra7xx
Acked-by: Kishon Vijay Abraham I 

Re: [PATCH 2/2] fsnotify: use method copy_dname copying filename

[Al Viro]

On Fri, Aug 04, 2017 at 11:58:41AM +0800, 林守磊 wrote:
> Hi all
> 
> I sent this patch two months ago, then I found CVE from this link last night
> 
> http://seclists.org/oss-sec/2017/q3/240
> 
> which not only references this patch, but also provides a upstream fix
> 
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49d31c2f389acfe83417083e1208422b4091cd9
> 
> I was wondering why @viro hadn't noticed this mail (And @viro fixed
> this). I'm new here and nobody,
> trying to do my best to help the this linux community. I was looking
> forword to your reply, because some
> insufficiency may exists in my work, I'd like to learn from you guys
> 
> Thanks and humble enough to wait your reply

Fair enough.  As for the reasons why allocation of name copy is a bad idea,
consider this: only short (embedded) names get overwritten on rename.
External ones (i.e. anything longer than 32 bytes or so) are unmodified
until freed.  And their lifetime is controlled by a refcount, so we can
trivially get a guaranteed to be stable name in that case - all it takes
is bumping the refcount and the name _will_ stay around until we drop
the reference.  So we are left with the case of short names and that
is trivial to deal with - 32-byte array is small enough, so we can bloody
well have it on caller's stack and copy the (short) name there.
That approach avoids all the headache with allocation, allocation failure
handling, etc.  Stack footprint is not much higher (especially compared
to how much idiotify and friends stomp on the stack) and it's obviously
cheaper - we only copy the name in short case and we never go into
allocator.  And it's just as easy to use as "make a dynamic copy" variant
of API...

Al, still buried in packing boxes at the moment...

Re: [PATCH 2/2] fsnotify: use method copy_dname copying filename

[Al Viro]

On Fri, Aug 04, 2017 at 11:58:41AM +0800, 林守磊 wrote:
> Hi all
> 
> I sent this patch two months ago, then I found CVE from this link last night
> 
> http://seclists.org/oss-sec/2017/q3/240
> 
> which not only references this patch, but also provides a upstream fix
> 
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49d31c2f389acfe83417083e1208422b4091cd9
> 
> I was wondering why @viro hadn't noticed this mail (And @viro fixed
> this). I'm new here and nobody,
> trying to do my best to help the this linux community. I was looking
> forword to your reply, because some
> insufficiency may exists in my work, I'd like to learn from you guys
> 
> Thanks and humble enough to wait your reply

Fair enough.  As for the reasons why allocation of name copy is a bad idea,
consider this: only short (embedded) names get overwritten on rename.
External ones (i.e. anything longer than 32 bytes or so) are unmodified
until freed.  And their lifetime is controlled by a refcount, so we can
trivially get a guaranteed to be stable name in that case - all it takes
is bumping the refcount and the name _will_ stay around until we drop
the reference.  So we are left with the case of short names and that
is trivial to deal with - 32-byte array is small enough, so we can bloody
well have it on caller's stack and copy the (short) name there.
That approach avoids all the headache with allocation, allocation failure
handling, etc.  Stack footprint is not much higher (especially compared
to how much idiotify and friends stomp on the stack) and it's obviously
cheaper - we only copy the name in short case and we never go into
allocator.  And it's just as easy to use as "make a dynamic copy" variant
of API...

Al, still buried in packing boxes at the moment...

Re: [PATCH v5 3/4] sched/deadline: Add support for SD_PREFER_SIBLING on find_later_rq()

[Byungchul Park]

On Thu, Aug 03, 2017 at 02:03:34PM +0200, Peter Zijlstra wrote:
> This one I'm not sure on..  at the very least we should exclude all of
> the prefer sibling domain when we do the next domain, and if there are
> multiple prefer sibling levels, we should only pick the first
> fallback_cpu -- there is no point is overriding it with a possible CPU
> further away.

I agree.

> I implemented that below -- although the find_cpu() function is really
> rather horrible.
> 
> But still this isn't quite right, because when we consider this for SMT
> (as was the intent here) we'll happily occupy a full sibling core over
> finding an empty one.
> 
> Now, the problem is that actually doing the right thing quickly ends up
> very expensive, we'd have to scan the entire cache domain at least once,
> so maybe this is good enough.. no idea :/
> 
> 
> ---
> --- a/kernel/sched/deadline.c
> +++ b/kernel/sched/deadline.c
> @@ -1793,12 +1793,35 @@ static struct task_struct *pick_earliest
>  
>  static DEFINE_PER_CPU(cpumask_var_t, local_cpu_mask_dl);
>  
> +/*
> + * Find the first cpu in: mask & sd & ~prefer
  ^
Yes, I missed it.

> + */
> +static int find_cpu(const struct cpumask *mask,
> + const struct sched_domain *sd,
> + const struct sched_domain *prefer)
> +{
> + const struct cpumask *sds = sched_domain_span(sd);
> + const struct cpumask *ps  = prefer ? sched_domain_span(prefer) : NULL;
> + int cpu = -1;
> +
> + while ((cpu = cpumask_next(cpu, mask)) < nr_cpu_ids) {
> + if (!cpumask_test_cpu(cpu, sds))
> + continue;
> + if (ps && cpumask_test_cpu(cpu, ps))
> + continue;
> + break;
> + }
> +
> + return cpu;
> +}
> +
>  static int find_later_rq(struct task_struct *task)
>  {
> - struct sched_domain *sd;
> + struct sched_domain *sd, *prefer = NULL;
>   struct cpumask *later_mask = 
> this_cpu_cpumask_var_ptr(local_cpu_mask_dl);
>   int this_cpu = smp_processor_id();
>   int cpu = task_cpu(task);
> + int fallback_cpu = -1;
>  
>   /* Make sure the mask is initialized first */
>   if (unlikely(!later_mask))
> @@ -1850,8 +1873,7 @@ static int find_later_rq(struct task_str
>   return this_cpu;
>   }
>  
> - best_cpu = cpumask_first_and(later_mask,
> - sched_domain_span(sd));
> + best_cpu = find_cpu(later_mask, sd, prefer);
>   /*
>* Last chance: if a cpu being in both later_mask
>* and current sd span is valid, that becomes our
> @@ -1859,6 +1881,17 @@ static int find_later_rq(struct task_str
>* already under consideration through later_mask.
>*/
>   if (best_cpu < nr_cpu_ids) {
> + /*
> +  * If current domain is SD_PREFER_SIBLING
> +  * flaged, we have to get more chances to
> +  * check other siblings.
> +  */
> + if (sd->flags & SD_PREFER_SIBLING) {
> + prefer = sd;
> + if (fallback_cpu == -1)
^
 I like the 'if' statement.
 I should have done this.

> + fallback_cpu = best_cpu;
> + continue;
> + }
>   rcu_read_unlock();
>   return best_cpu;
>   }

Thank you.

Re: [PATCH v5 3/4] sched/deadline: Add support for SD_PREFER_SIBLING on find_later_rq()

[Byungchul Park]

On Thu, Aug 03, 2017 at 02:03:34PM +0200, Peter Zijlstra wrote:
> This one I'm not sure on..  at the very least we should exclude all of
> the prefer sibling domain when we do the next domain, and if there are
> multiple prefer sibling levels, we should only pick the first
> fallback_cpu -- there is no point is overriding it with a possible CPU
> further away.

I agree.

> I implemented that below -- although the find_cpu() function is really
> rather horrible.
> 
> But still this isn't quite right, because when we consider this for SMT
> (as was the intent here) we'll happily occupy a full sibling core over
> finding an empty one.
> 
> Now, the problem is that actually doing the right thing quickly ends up
> very expensive, we'd have to scan the entire cache domain at least once,
> so maybe this is good enough.. no idea :/
> 
> 
> ---
> --- a/kernel/sched/deadline.c
> +++ b/kernel/sched/deadline.c
> @@ -1793,12 +1793,35 @@ static struct task_struct *pick_earliest
>  
>  static DEFINE_PER_CPU(cpumask_var_t, local_cpu_mask_dl);
>  
> +/*
> + * Find the first cpu in: mask & sd & ~prefer
  ^
Yes, I missed it.

> + */
> +static int find_cpu(const struct cpumask *mask,
> + const struct sched_domain *sd,
> + const struct sched_domain *prefer)
> +{
> + const struct cpumask *sds = sched_domain_span(sd);
> + const struct cpumask *ps  = prefer ? sched_domain_span(prefer) : NULL;
> + int cpu = -1;
> +
> + while ((cpu = cpumask_next(cpu, mask)) < nr_cpu_ids) {
> + if (!cpumask_test_cpu(cpu, sds))
> + continue;
> + if (ps && cpumask_test_cpu(cpu, ps))
> + continue;
> + break;
> + }
> +
> + return cpu;
> +}
> +
>  static int find_later_rq(struct task_struct *task)
>  {
> - struct sched_domain *sd;
> + struct sched_domain *sd, *prefer = NULL;
>   struct cpumask *later_mask = 
> this_cpu_cpumask_var_ptr(local_cpu_mask_dl);
>   int this_cpu = smp_processor_id();
>   int cpu = task_cpu(task);
> + int fallback_cpu = -1;
>  
>   /* Make sure the mask is initialized first */
>   if (unlikely(!later_mask))
> @@ -1850,8 +1873,7 @@ static int find_later_rq(struct task_str
>   return this_cpu;
>   }
>  
> - best_cpu = cpumask_first_and(later_mask,
> - sched_domain_span(sd));
> + best_cpu = find_cpu(later_mask, sd, prefer);
>   /*
>* Last chance: if a cpu being in both later_mask
>* and current sd span is valid, that becomes our
> @@ -1859,6 +1881,17 @@ static int find_later_rq(struct task_str
>* already under consideration through later_mask.
>*/
>   if (best_cpu < nr_cpu_ids) {
> + /*
> +  * If current domain is SD_PREFER_SIBLING
> +  * flaged, we have to get more chances to
> +  * check other siblings.
> +  */
> + if (sd->flags & SD_PREFER_SIBLING) {
> + prefer = sd;
> + if (fallback_cpu == -1)
^
 I like the 'if' statement.
 I should have done this.

> + fallback_cpu = best_cpu;
> + continue;
> + }
>   rcu_read_unlock();
>   return best_cpu;
>   }

Thank you.

Re: [PATCH] cpufreq: dt: Add rk3328 compatible to use generic cpufreq driver

[Viresh Kumar]

On 04-08-17, 09:52, Finley Xiao wrote:
> This patch adds the rk3328 compatible string for supporting
> the generic cpufreq driver on RK3328.
> 
> Signed-off-by: Finley Xiao 
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
> b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 096aea7..13c0c47 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -76,6 +76,7 @@ static const struct of_device_id machines[] __initconst = {
>   { .compatible = "rockchip,rk3188", },
>   { .compatible = "rockchip,rk3228", },
>   { .compatible = "rockchip,rk3288", },
> + { .compatible = "rockchip,rk3328", },
>   { .compatible = "rockchip,rk3366", },
>   { .compatible = "rockchip,rk3368", },
>   { .compatible = "rockchip,rk3399", },

Acked-by: Viresh Kumar 

-- 
viresh

Re: [PATCH] cpufreq: dt: Add rk3328 compatible to use generic cpufreq driver

[Viresh Kumar]

On 04-08-17, 09:52, Finley Xiao wrote:
> This patch adds the rk3328 compatible string for supporting
> the generic cpufreq driver on RK3328.
> 
> Signed-off-by: Finley Xiao 
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
> b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 096aea7..13c0c47 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -76,6 +76,7 @@ static const struct of_device_id machines[] __initconst = {
>   { .compatible = "rockchip,rk3188", },
>   { .compatible = "rockchip,rk3228", },
>   { .compatible = "rockchip,rk3288", },
> + { .compatible = "rockchip,rk3328", },
>   { .compatible = "rockchip,rk3366", },
>   { .compatible = "rockchip,rk3368", },
>   { .compatible = "rockchip,rk3399", },

Acked-by: Viresh Kumar 

-- 
viresh

[PATCH 01/11] drm: i915: i915_oa_kblgt2: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_kblgt2.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c 
b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
index 87dbd0a..c9b6751 100644
--- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
@@ -2412,7 +2412,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "f8d677e9-ff6f-4df1-9310-0334c6efacce",
.attrs =  attrs_render_basic,
 };
@@ -2434,7 +2434,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "e17fc42a-e614-41b6-90c4-1074841a6c77",
.attrs =  attrs_compute_basic,
 };
@@ -2456,7 +2456,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "d7a17a3a-ca71-40d2-a919-ace80d50633f",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2478,7 +2478,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "57b59202-172b-477a-87de-33f85572c589",
.attrs =  attrs_memory_reads,
 };
@@ -2500,7 +2500,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0",
.attrs =  attrs_memory_writes,
 };
@@ -2522,7 +2522,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "4af0400a-81c3-47db-a6b6-deddbd75680e",
.attrs =  attrs_compute_extended,
 };
@@ -2544,7 +2544,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "0e22f995-79ca-4f67-83ab-e9d9772488d8",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2566,7 +2566,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2588,7 +2588,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2",
.attrs =  attrs_l3_1,
 };
@@ -2610,7 +2610,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "2f8e32e4-5956-46e2-af31-c8ea95887332",
.attrs =  attrs_l3_2,
 };
@@ -2632,7 +2632,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "ca046aad-b5fb-4101-adce-6473ee6e5b14",
.attrs =  attrs_l3_3,
 };
@@ -2654,7 +2654,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2676,7 +2676,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af",
.attrs =  attrs_sampler,
 };
@@ -2698,7 +2698,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 01/11] drm: i915: i915_oa_kblgt2: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_kblgt2.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c 
b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
index 87dbd0a..c9b6751 100644
--- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
@@ -2412,7 +2412,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "f8d677e9-ff6f-4df1-9310-0334c6efacce",
.attrs =  attrs_render_basic,
 };
@@ -2434,7 +2434,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "e17fc42a-e614-41b6-90c4-1074841a6c77",
.attrs =  attrs_compute_basic,
 };
@@ -2456,7 +2456,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "d7a17a3a-ca71-40d2-a919-ace80d50633f",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2478,7 +2478,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "57b59202-172b-477a-87de-33f85572c589",
.attrs =  attrs_memory_reads,
 };
@@ -2500,7 +2500,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0",
.attrs =  attrs_memory_writes,
 };
@@ -2522,7 +2522,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "4af0400a-81c3-47db-a6b6-deddbd75680e",
.attrs =  attrs_compute_extended,
 };
@@ -2544,7 +2544,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "0e22f995-79ca-4f67-83ab-e9d9772488d8",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2566,7 +2566,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2588,7 +2588,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2",
.attrs =  attrs_l3_1,
 };
@@ -2610,7 +2610,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "2f8e32e4-5956-46e2-af31-c8ea95887332",
.attrs =  attrs_l3_2,
 };
@@ -2632,7 +2632,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "ca046aad-b5fb-4101-adce-6473ee6e5b14",
.attrs =  attrs_l3_3,
 };
@@ -2654,7 +2654,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2676,7 +2676,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af",
.attrs =  attrs_sampler,
 };
@@ -2698,7 +2698,7 @@ int i915_oa_select_metric_set_kblgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const 

[PATCH 02/11] drm: i915: i915_oa_bdw: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_bdw.c | 44 +++---
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c 
b/drivers/gpu/drm/i915/i915_oa_bdw.c
index d4462c2..90c96c2 100644
--- a/drivers/gpu/drm/i915/i915_oa_bdw.c
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.c
@@ -4669,7 +4669,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
.attrs =  attrs_render_basic,
 };
@@ -4691,7 +4691,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "35fbc9b2-a891-40a6-a38d-022bb7057552",
.attrs =  attrs_compute_basic,
 };
@@ -4713,7 +4713,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "233d0544-fff7-4281-8291-e02f222aff72",
.attrs =  attrs_render_pipe_profile,
 };
@@ -4735,7 +4735,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c",
.attrs =  attrs_memory_reads,
 };
@@ -4757,7 +4757,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c",
.attrs =  attrs_memory_writes,
 };
@@ -4779,7 +4779,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "e99ccaca-821c-4df9-97a7-96bdb7204e43",
.attrs =  attrs_compute_extended,
 };
@@ -4801,7 +4801,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "27a364dc-8225-4ecb-b607-d6f1925598d9",
.attrs =  attrs_compute_l3_cache,
 };
@@ -4823,7 +4823,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_data_port_reads_coalescing = {
+static const struct attribute_group group_data_port_reads_coalescing = {
.name = "857fc630-2f09-4804-85f1-084adfadd5ab",
.attrs =  attrs_data_port_reads_coalescing,
 };
@@ -4845,7 +4845,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_data_port_writes_coalescing = {
+static const struct attribute_group group_data_port_writes_coalescing = {
.name = "343ebc99-4a55-414c-8c17-d8e259cf5e20",
.attrs =  attrs_data_port_writes_coalescing,
 };
@@ -4867,7 +4867,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e",
.attrs =  attrs_hdc_and_sf,
 };
@@ -4889,7 +4889,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b",
.attrs =  attrs_l3_1,
 };
@@ -4911,7 +4911,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a",
.attrs =  attrs_l3_2,
 };
@@ -4933,7 +4933,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c",
.attrs =  attrs_l3_3,
 };
@@ -4955,7 +4955,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 02/11] drm: i915: i915_oa_bdw: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_bdw.c | 44 +++---
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c 
b/drivers/gpu/drm/i915/i915_oa_bdw.c
index d4462c2..90c96c2 100644
--- a/drivers/gpu/drm/i915/i915_oa_bdw.c
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.c
@@ -4669,7 +4669,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
.attrs =  attrs_render_basic,
 };
@@ -4691,7 +4691,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "35fbc9b2-a891-40a6-a38d-022bb7057552",
.attrs =  attrs_compute_basic,
 };
@@ -4713,7 +4713,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "233d0544-fff7-4281-8291-e02f222aff72",
.attrs =  attrs_render_pipe_profile,
 };
@@ -4735,7 +4735,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c",
.attrs =  attrs_memory_reads,
 };
@@ -4757,7 +4757,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c",
.attrs =  attrs_memory_writes,
 };
@@ -4779,7 +4779,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "e99ccaca-821c-4df9-97a7-96bdb7204e43",
.attrs =  attrs_compute_extended,
 };
@@ -4801,7 +4801,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "27a364dc-8225-4ecb-b607-d6f1925598d9",
.attrs =  attrs_compute_l3_cache,
 };
@@ -4823,7 +4823,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_data_port_reads_coalescing = {
+static const struct attribute_group group_data_port_reads_coalescing = {
.name = "857fc630-2f09-4804-85f1-084adfadd5ab",
.attrs =  attrs_data_port_reads_coalescing,
 };
@@ -4845,7 +4845,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_data_port_writes_coalescing = {
+static const struct attribute_group group_data_port_writes_coalescing = {
.name = "343ebc99-4a55-414c-8c17-d8e259cf5e20",
.attrs =  attrs_data_port_writes_coalescing,
 };
@@ -4867,7 +4867,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e",
.attrs =  attrs_hdc_and_sf,
 };
@@ -4889,7 +4889,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b",
.attrs =  attrs_l3_1,
 };
@@ -4911,7 +4911,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a",
.attrs =  attrs_l3_2,
 };
@@ -4933,7 +4933,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c",
.attrs =  attrs_l3_3,
 };
@@ -4955,7 +4955,7 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_4 = {
+static const struct 

[PATCH 05/11] drm: i915: i915_oa_glk: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_glk.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c 
b/drivers/gpu/drm/i915/i915_oa_glk.c
index 2f356d5..a8eea3a 100644
--- a/drivers/gpu/drm/i915/i915_oa_glk.c
+++ b/drivers/gpu/drm/i915/i915_oa_glk.c
@@ -2119,7 +2119,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68",
.attrs =  attrs_render_basic,
 };
@@ -2141,7 +2141,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "814285f6-354d-41d2-ba49-e24e622714a0",
.attrs =  attrs_compute_basic,
 };
@@ -2163,7 +2163,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "07d397a6-b3e6-49f6-9433-a4f293d55978",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2185,7 +2185,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "1a356946-5428-450b-a2f0-89f8783a302d",
.attrs =  attrs_memory_reads,
 };
@@ -2207,7 +2207,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9",
.attrs =  attrs_memory_writes,
 };
@@ -2229,7 +2229,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "bc9bcff2-459a-4cbc-986d-a84b077153f3",
.attrs =  attrs_compute_extended,
 };
@@ -2251,7 +2251,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "88ec931f-5b4a-453a-9db6-a61232b6143d",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2273,7 +2273,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "530d176d-2a18-4014-adf8-1500c6c60835",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2295,7 +2295,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d",
.attrs =  attrs_l3_1,
 };
@@ -2317,7 +2317,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "6617623e-ca73-4791-b2b7-ddedd0846a0c",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2339,7 +2339,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0",
.attrs =  attrs_sampler,
 };
@@ -2361,7 +2361,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83",
.attrs =  attrs_tdl_1,
 };
@@ -2383,7 +2383,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d",
.attrs =  attrs_tdl_2,
 };
@@ -2405,7 +2405,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extra = {
+static const struct attribute_group 

[PATCH 05/11] drm: i915: i915_oa_glk: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_glk.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c 
b/drivers/gpu/drm/i915/i915_oa_glk.c
index 2f356d5..a8eea3a 100644
--- a/drivers/gpu/drm/i915/i915_oa_glk.c
+++ b/drivers/gpu/drm/i915/i915_oa_glk.c
@@ -2119,7 +2119,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68",
.attrs =  attrs_render_basic,
 };
@@ -2141,7 +2141,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "814285f6-354d-41d2-ba49-e24e622714a0",
.attrs =  attrs_compute_basic,
 };
@@ -2163,7 +2163,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "07d397a6-b3e6-49f6-9433-a4f293d55978",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2185,7 +2185,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "1a356946-5428-450b-a2f0-89f8783a302d",
.attrs =  attrs_memory_reads,
 };
@@ -2207,7 +2207,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9",
.attrs =  attrs_memory_writes,
 };
@@ -2229,7 +2229,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "bc9bcff2-459a-4cbc-986d-a84b077153f3",
.attrs =  attrs_compute_extended,
 };
@@ -2251,7 +2251,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "88ec931f-5b4a-453a-9db6-a61232b6143d",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2273,7 +2273,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "530d176d-2a18-4014-adf8-1500c6c60835",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2295,7 +2295,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d",
.attrs =  attrs_l3_1,
 };
@@ -2317,7 +2317,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "6617623e-ca73-4791-b2b7-ddedd0846a0c",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2339,7 +2339,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0",
.attrs =  attrs_sampler,
 };
@@ -2361,7 +2361,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83",
.attrs =  attrs_tdl_1,
 };
@@ -2383,7 +2383,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d",
.attrs =  attrs_tdl_2,
 };
@@ -2405,7 +2405,7 @@ int i915_oa_select_metric_set_glk(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extra = {
+static const struct attribute_group group_compute_extra = {
   

[PATCH 03/11] drm: i915: i915_oa_bxt: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_bxt.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c 
b/drivers/gpu/drm/i915/i915_oa_bxt.c
index 93864d8..db80045 100644
--- a/drivers/gpu/drm/i915/i915_oa_bxt.c
+++ b/drivers/gpu/drm/i915/i915_oa_bxt.c
@@ -2207,7 +2207,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
.attrs =  attrs_render_basic,
 };
@@ -2229,7 +2229,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "012d72cf-82a9-4d25-8ddf-74076fd30797",
.attrs =  attrs_compute_basic,
 };
@@ -2251,7 +2251,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "ce416533-e49e-4211-80af-ec513590a914",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2273,7 +2273,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "398e2452-18d7-42d0-b241-e4d0a9148ada",
.attrs =  attrs_memory_reads,
 };
@@ -2295,7 +2295,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5",
.attrs =  attrs_memory_writes,
 };
@@ -2317,7 +2317,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49",
.attrs =  attrs_compute_extended,
 };
@@ -2339,7 +2339,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2361,7 +2361,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2383,7 +2383,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "00ad5a41-7eab-4f7a-9103-49d411c67219",
.attrs =  attrs_l3_1,
 };
@@ -2405,7 +2405,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2427,7 +2427,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "8364e2a8-af63-40af-b0d5-42969a255654",
.attrs =  attrs_sampler,
 };
@@ -2449,7 +2449,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92",
.attrs =  attrs_tdl_1,
 };
@@ -2471,7 +2471,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "d260f03f-b34d-4b49-a44e-436819117332",
.attrs =  attrs_tdl_2,
 };
@@ -2493,7 +2493,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extra = {
+static const struct attribute_group 

[PATCH 03/11] drm: i915: i915_oa_bxt: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_bxt.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c 
b/drivers/gpu/drm/i915/i915_oa_bxt.c
index 93864d8..db80045 100644
--- a/drivers/gpu/drm/i915/i915_oa_bxt.c
+++ b/drivers/gpu/drm/i915/i915_oa_bxt.c
@@ -2207,7 +2207,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
.attrs =  attrs_render_basic,
 };
@@ -2229,7 +2229,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "012d72cf-82a9-4d25-8ddf-74076fd30797",
.attrs =  attrs_compute_basic,
 };
@@ -2251,7 +2251,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "ce416533-e49e-4211-80af-ec513590a914",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2273,7 +2273,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "398e2452-18d7-42d0-b241-e4d0a9148ada",
.attrs =  attrs_memory_reads,
 };
@@ -2295,7 +2295,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5",
.attrs =  attrs_memory_writes,
 };
@@ -2317,7 +2317,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49",
.attrs =  attrs_compute_extended,
 };
@@ -2339,7 +2339,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2361,7 +2361,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2383,7 +2383,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "00ad5a41-7eab-4f7a-9103-49d411c67219",
.attrs =  attrs_l3_1,
 };
@@ -2405,7 +2405,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2427,7 +2427,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "8364e2a8-af63-40af-b0d5-42969a255654",
.attrs =  attrs_sampler,
 };
@@ -2449,7 +2449,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92",
.attrs =  attrs_tdl_1,
 };
@@ -2471,7 +2471,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "d260f03f-b34d-4b49-a44e-436819117332",
.attrs =  attrs_tdl_2,
 };
@@ -2493,7 +2493,7 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extra = {
+static const struct attribute_group group_compute_extra = {
   

[PATCH 07/11] drm: i915: i915_oa_kblgt3: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_kblgt3.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c 
b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
index 6ed0925..f234801 100644
--- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
@@ -2461,7 +2461,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "0286c920-2f6d-493b-b22d-7a5280df43de",
.attrs =  attrs_render_basic,
 };
@@ -2483,7 +2483,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2",
.attrs =  attrs_compute_basic,
 };
@@ -2505,7 +2505,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "c7c735f3-ce58-45cf-aa04-30b183f1faff",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2527,7 +2527,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "96ec2219-040b-428a-856a-6bc03363a057",
.attrs =  attrs_memory_reads,
 };
@@ -2549,7 +2549,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "03372b64-4996-4d3b-aa18-790e75eeb9c2",
.attrs =  attrs_memory_writes,
 };
@@ -2571,7 +2571,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150",
.attrs =  attrs_compute_extended,
 };
@@ -2593,7 +2593,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "2ce0911a-27fc-4887-96f0-11084fa807c3",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2615,7 +2615,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2637,7 +2637,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "4e93d156-9b39-4268-8544-a8e0480806d7",
.attrs =  attrs_l3_1,
 };
@@ -2659,7 +2659,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "de1bec86-ca92-4b43-89fa-147653221cc0",
.attrs =  attrs_l3_2,
 };
@@ -2681,7 +2681,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef",
.attrs =  attrs_l3_3,
 };
@@ -2703,7 +2703,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2725,7 +2725,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda",
.attrs =  attrs_sampler,
 };
@@ -2747,7 +2747,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 07/11] drm: i915: i915_oa_kblgt3: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_kblgt3.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c 
b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
index 6ed0925..f234801 100644
--- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
@@ -2461,7 +2461,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "0286c920-2f6d-493b-b22d-7a5280df43de",
.attrs =  attrs_render_basic,
 };
@@ -2483,7 +2483,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2",
.attrs =  attrs_compute_basic,
 };
@@ -2505,7 +2505,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "c7c735f3-ce58-45cf-aa04-30b183f1faff",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2527,7 +2527,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "96ec2219-040b-428a-856a-6bc03363a057",
.attrs =  attrs_memory_reads,
 };
@@ -2549,7 +2549,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "03372b64-4996-4d3b-aa18-790e75eeb9c2",
.attrs =  attrs_memory_writes,
 };
@@ -2571,7 +2571,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150",
.attrs =  attrs_compute_extended,
 };
@@ -2593,7 +2593,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "2ce0911a-27fc-4887-96f0-11084fa807c3",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2615,7 +2615,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2637,7 +2637,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "4e93d156-9b39-4268-8544-a8e0480806d7",
.attrs =  attrs_l3_1,
 };
@@ -2659,7 +2659,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "de1bec86-ca92-4b43-89fa-147653221cc0",
.attrs =  attrs_l3_2,
 };
@@ -2681,7 +2681,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef",
.attrs =  attrs_l3_3,
 };
@@ -2703,7 +2703,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2725,7 +2725,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda",
.attrs =  attrs_sampler,
 };
@@ -2747,7 +2747,7 @@ int i915_oa_select_metric_set_kblgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const 

[PATCH 09/11] drm: i915: i915_oa_sklgt3: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt3.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
index 7765e22..e26f300 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
@@ -2460,7 +2460,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "4616d450-2393-4836-8146-53c5ed84d359",
.attrs =  attrs_render_basic,
 };
@@ -2482,7 +2482,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58",
.attrs =  attrs_compute_basic,
 };
@@ -2504,7 +2504,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2526,7 +2526,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767",
.attrs =  attrs_memory_reads,
 };
@@ -2548,7 +2548,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14",
.attrs =  attrs_memory_writes,
 };
@@ -2570,7 +2570,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "52435e0b-f188-42ea-8680-21a56ee20dee",
.attrs =  attrs_compute_extended,
 };
@@ -2592,7 +2592,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "27076eeb-49f3-4fed-8423-c66506005c63",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2614,7 +2614,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "8071b409-c39a-4674-94d7-32962ecfb512",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2636,7 +2636,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed",
.attrs =  attrs_l3_1,
 };
@@ -2658,7 +2658,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "25dc828e-1d2d-426e-9546-a1d4233cdf16",
.attrs =  attrs_l3_2,
 };
@@ -2680,7 +2680,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf",
.attrs =  attrs_l3_3,
 };
@@ -2702,7 +2702,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2724,7 +2724,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6",
.attrs =  attrs_sampler,
 };
@@ -2746,7 +2746,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 11/11] drm: i915: i915_sysfs: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_sysfs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 1eef3fa..3fe3e56 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -96,7 +96,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group rc6_attr_group = {
+static const struct attribute_group rc6_attr_group = {
.name = power_group_name,
.attrs =  rc6_attrs
 };
@@ -107,7 +107,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group rc6p_attr_group = {
+static const struct attribute_group rc6p_attr_group = {
.name = power_group_name,
.attrs =  rc6p_attrs
 };
@@ -117,7 +117,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group media_rc6_attr_group = {
+static const struct attribute_group media_rc6_attr_group = {
.name = power_group_name,
.attrs =  media_rc6_attrs
 };
-- 
1.9.1

[PATCH 10/11] drm: i915: i915_oa_sklgt4: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt4.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
index 9ddab43..0671899 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
@@ -2514,7 +2514,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "bad77c24-cc64-480d-99bf-e7b740713800",
.attrs =  attrs_render_basic,
 };
@@ -2536,7 +2536,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "7277228f-e7f3-4743-945a-6a2049d11377",
.attrs =  attrs_compute_basic,
 };
@@ -2558,7 +2558,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "463c668c-3f60-49b6-8f85-d995b635b3b2",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2580,7 +2580,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
.attrs =  attrs_memory_reads,
 };
@@ -2602,7 +2602,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "055f256d-4052-467c-8dec-6064a4806433",
.attrs =  attrs_memory_writes,
 };
@@ -2624,7 +2624,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "753972d4-87cd-4460-824d-754463ac5054",
.attrs =  attrs_compute_extended,
 };
@@ -2646,7 +2646,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2668,7 +2668,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2690,7 +2690,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
.attrs =  attrs_l3_1,
 };
@@ -2712,7 +2712,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
.attrs =  attrs_l3_2,
 };
@@ -2734,7 +2734,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "1988315f-0a26-44df-acb0-df7ec86b1456",
.attrs =  attrs_l3_3,
 };
@@ -2756,7 +2756,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2778,7 +2778,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
.attrs =  attrs_sampler,
 };
@@ -2800,7 +2800,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 09/11] drm: i915: i915_oa_sklgt3: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt3.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
index 7765e22..e26f300 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
@@ -2460,7 +2460,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "4616d450-2393-4836-8146-53c5ed84d359",
.attrs =  attrs_render_basic,
 };
@@ -2482,7 +2482,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58",
.attrs =  attrs_compute_basic,
 };
@@ -2504,7 +2504,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2526,7 +2526,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767",
.attrs =  attrs_memory_reads,
 };
@@ -2548,7 +2548,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14",
.attrs =  attrs_memory_writes,
 };
@@ -2570,7 +2570,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "52435e0b-f188-42ea-8680-21a56ee20dee",
.attrs =  attrs_compute_extended,
 };
@@ -2592,7 +2592,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "27076eeb-49f3-4fed-8423-c66506005c63",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2614,7 +2614,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "8071b409-c39a-4674-94d7-32962ecfb512",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2636,7 +2636,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed",
.attrs =  attrs_l3_1,
 };
@@ -2658,7 +2658,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "25dc828e-1d2d-426e-9546-a1d4233cdf16",
.attrs =  attrs_l3_2,
 };
@@ -2680,7 +2680,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf",
.attrs =  attrs_l3_3,
 };
@@ -2702,7 +2702,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2724,7 +2724,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6",
.attrs =  attrs_sampler,
 };
@@ -2746,7 +2746,7 @@ int i915_oa_select_metric_set_sklgt3(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const 

[PATCH 11/11] drm: i915: i915_sysfs: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_sysfs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 1eef3fa..3fe3e56 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -96,7 +96,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group rc6_attr_group = {
+static const struct attribute_group rc6_attr_group = {
.name = power_group_name,
.attrs =  rc6_attrs
 };
@@ -107,7 +107,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group rc6p_attr_group = {
+static const struct attribute_group rc6p_attr_group = {
.name = power_group_name,
.attrs =  rc6p_attrs
 };
@@ -117,7 +117,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
NULL
 };
 
-static struct attribute_group media_rc6_attr_group = {
+static const struct attribute_group media_rc6_attr_group = {
.name = power_group_name,
.attrs =  media_rc6_attrs
 };
-- 
1.9.1

[PATCH 10/11] drm: i915: i915_oa_sklgt4: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt4.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
index 9ddab43..0671899 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
@@ -2514,7 +2514,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "bad77c24-cc64-480d-99bf-e7b740713800",
.attrs =  attrs_render_basic,
 };
@@ -2536,7 +2536,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "7277228f-e7f3-4743-945a-6a2049d11377",
.attrs =  attrs_compute_basic,
 };
@@ -2558,7 +2558,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "463c668c-3f60-49b6-8f85-d995b635b3b2",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2580,7 +2580,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
.attrs =  attrs_memory_reads,
 };
@@ -2602,7 +2602,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "055f256d-4052-467c-8dec-6064a4806433",
.attrs =  attrs_memory_writes,
 };
@@ -2624,7 +2624,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "753972d4-87cd-4460-824d-754463ac5054",
.attrs =  attrs_compute_extended,
 };
@@ -2646,7 +2646,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b",
.attrs =  attrs_compute_l3_cache,
 };
@@ -2668,7 +2668,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2690,7 +2690,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
.attrs =  attrs_l3_1,
 };
@@ -2712,7 +2712,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
.attrs =  attrs_l3_2,
 };
@@ -2734,7 +2734,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "1988315f-0a26-44df-acb0-df7ec86b1456",
.attrs =  attrs_l3_3,
 };
@@ -2756,7 +2756,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2778,7 +2778,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
.attrs =  attrs_sampler,
 };
@@ -2800,7 +2800,7 @@ int i915_oa_select_metric_set_sklgt4(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const 

[PATCH 06/11] drm: i915: i915_oa_hsw: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_hsw.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c 
b/drivers/gpu/drm/i915/i915_oa_hsw.c
index 10f169f..93fbe33 100644
--- a/drivers/gpu/drm/i915/i915_oa_hsw.c
+++ b/drivers/gpu/drm/i915/i915_oa_hsw.c
@@ -668,7 +668,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212",
.attrs =  attrs_render_basic,
 };
@@ -690,7 +690,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b",
.attrs =  attrs_compute_basic,
 };
@@ -712,7 +712,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "3865be28-6982-49fe-9494-e4d1b4795413",
.attrs =  attrs_compute_extended,
 };
@@ -734,7 +734,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "bb5ed49b-2497-4095-94f6-26ba294db88a",
.attrs =  attrs_memory_reads,
 };
@@ -756,7 +756,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "3358d639-9b5f-45ab-976d-9b08cbfc6240",
.attrs =  attrs_memory_writes,
 };
@@ -778,7 +778,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_balance = {
+static const struct attribute_group group_sampler_balance = {
.name = "bc274488-b4b6-40c7-90da-b77d7ad16189",
.attrs =  attrs_sampler_balance,
 };
-- 
1.9.1

[PATCH 04/11] drm: i915: i915_oa_chv: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_chv.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c 
b/drivers/gpu/drm/i915/i915_oa_chv.c
index aa6bece..85c6c36 100644
--- a/drivers/gpu/drm/i915/i915_oa_chv.c
+++ b/drivers/gpu/drm/i915/i915_oa_chv.c
@@ -2422,7 +2422,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb",
.attrs =  attrs_render_basic,
 };
@@ -2444,7 +2444,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "f522a89c-ecd1-4522-8331-3383c54af5f5",
.attrs =  attrs_compute_basic,
 };
@@ -2466,7 +2466,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "a9ccc03d-a943-4e6b-9cd6-13e063075927",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2488,7 +2488,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2510,7 +2510,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
.attrs =  attrs_l3_1,
 };
@@ -2532,7 +2532,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
.attrs =  attrs_l3_2,
 };
@@ -2554,7 +2554,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
.attrs =  attrs_l3_3,
 };
@@ -2576,7 +2576,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_4 = {
+static const struct attribute_group group_l3_4 = {
.name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
.attrs =  attrs_l3_4,
 };
@@ -2598,7 +2598,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2620,7 +2620,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_1 = {
+static const struct attribute_group group_sampler_1 = {
.name = "71148d78-baf5-474f-878a-e23158d0265d",
.attrs =  attrs_sampler_1,
 };
@@ -2642,7 +2642,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_2 = {
+static const struct attribute_group group_sampler_2 = {
.name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
.attrs =  attrs_sampler_2,
 };
@@ -2664,7 +2664,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
.attrs =  attrs_tdl_1,
 };
@@ -2686,7 +2686,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
.attrs =  attrs_tdl_2,
 };
@@ -2708,7 +2708,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_test_oa = {
+static const struct attribute_group group_test_oa = {
.name = "4a534b07-cba3-414d-8d60-874830e883aa",
.attrs =  attrs_test_oa,
 };
-- 

[PATCH 06/11] drm: i915: i915_oa_hsw: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_hsw.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c 
b/drivers/gpu/drm/i915/i915_oa_hsw.c
index 10f169f..93fbe33 100644
--- a/drivers/gpu/drm/i915/i915_oa_hsw.c
+++ b/drivers/gpu/drm/i915/i915_oa_hsw.c
@@ -668,7 +668,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212",
.attrs =  attrs_render_basic,
 };
@@ -690,7 +690,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b",
.attrs =  attrs_compute_basic,
 };
@@ -712,7 +712,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "3865be28-6982-49fe-9494-e4d1b4795413",
.attrs =  attrs_compute_extended,
 };
@@ -734,7 +734,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "bb5ed49b-2497-4095-94f6-26ba294db88a",
.attrs =  attrs_memory_reads,
 };
@@ -756,7 +756,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "3358d639-9b5f-45ab-976d-9b08cbfc6240",
.attrs =  attrs_memory_writes,
 };
@@ -778,7 +778,7 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_balance = {
+static const struct attribute_group group_sampler_balance = {
.name = "bc274488-b4b6-40c7-90da-b77d7ad16189",
.attrs =  attrs_sampler_balance,
 };
-- 
1.9.1

[PATCH 04/11] drm: i915: i915_oa_chv: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_chv.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c 
b/drivers/gpu/drm/i915/i915_oa_chv.c
index aa6bece..85c6c36 100644
--- a/drivers/gpu/drm/i915/i915_oa_chv.c
+++ b/drivers/gpu/drm/i915/i915_oa_chv.c
@@ -2422,7 +2422,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb",
.attrs =  attrs_render_basic,
 };
@@ -2444,7 +2444,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "f522a89c-ecd1-4522-8331-3383c54af5f5",
.attrs =  attrs_compute_basic,
 };
@@ -2466,7 +2466,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "a9ccc03d-a943-4e6b-9cd6-13e063075927",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2488,7 +2488,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
.attrs =  attrs_hdc_and_sf,
 };
@@ -2510,7 +2510,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
.attrs =  attrs_l3_1,
 };
@@ -2532,7 +2532,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
.attrs =  attrs_l3_2,
 };
@@ -2554,7 +2554,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
.attrs =  attrs_l3_3,
 };
@@ -2576,7 +2576,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_4 = {
+static const struct attribute_group group_l3_4 = {
.name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
.attrs =  attrs_l3_4,
 };
@@ -2598,7 +2598,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -2620,7 +2620,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_1 = {
+static const struct attribute_group group_sampler_1 = {
.name = "71148d78-baf5-474f-878a-e23158d0265d",
.attrs =  attrs_sampler_1,
 };
@@ -2642,7 +2642,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler_2 = {
+static const struct attribute_group group_sampler_2 = {
.name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
.attrs =  attrs_sampler_2,
 };
@@ -2664,7 +2664,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const struct attribute_group group_tdl_1 = {
.name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
.attrs =  attrs_tdl_1,
 };
@@ -2686,7 +2686,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_2 = {
+static const struct attribute_group group_tdl_2 = {
.name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
.attrs =  attrs_tdl_2,
 };
@@ -2708,7 +2708,7 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private 
*dev_priv)
NULL,
 };
 
-static struct attribute_group group_test_oa = {
+static const struct attribute_group group_test_oa = {
.name = "4a534b07-cba3-414d-8d60-874830e883aa",
.attrs =  attrs_test_oa,
 };
-- 
1.9.1

[PATCH 08/11] drm: i915: i915_oa_sklgt2: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt2.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
index 1268bed..80e6054 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
@@ -2900,7 +2900,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "f519e481-24d2-4d42-87c9-3fdd12c00202",
.attrs =  attrs_render_basic,
 };
@@ -2922,7 +2922,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "fe47b29d-ae51-423e-bff4-27d965a95b60",
.attrs =  attrs_compute_basic,
 };
@@ -2944,7 +2944,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2966,7 +2966,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "9bc436dd-6130-4add-affc-283eb6eaa864",
.attrs =  attrs_memory_reads,
 };
@@ -2988,7 +2988,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "2ea0da8f-3527-4669-9d9d-13099a7435bf",
.attrs =  attrs_memory_writes,
 };
@@ -3010,7 +3010,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "d97d16af-028b-4cd1-a672-6210cb5513dd",
.attrs =  attrs_compute_extended,
 };
@@ -3032,7 +3032,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "9fb22842-e708-43f7-9752-e0e41670c39e",
.attrs =  attrs_compute_l3_cache,
 };
@@ -3054,7 +3054,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "5378e2a1-4248-4188-a4ae-da25a794c603",
.attrs =  attrs_hdc_and_sf,
 };
@@ -3076,7 +3076,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "f42cdd6a-b000-42cb-870f-5eb423a7f514",
.attrs =  attrs_l3_1,
 };
@@ -3098,7 +3098,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "b9bf2423-d88c-4a7b-a051-627611d00dcc",
.attrs =  attrs_l3_2,
 };
@@ -3120,7 +3120,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "2414a93d-d84f-406e-99c0-472161194b40",
.attrs =  attrs_l3_3,
 };
@@ -3142,7 +3142,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -3164,7 +3164,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1",
.attrs =  attrs_sampler,
 };
@@ -3186,7 +3186,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group 

[PATCH 08/11] drm: i915: i915_oa_sklgt2: constify attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/i915/i915_oa_sklgt2.c | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c 
b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
index 1268bed..80e6054 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
@@ -2900,7 +2900,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_basic = {
+static const struct attribute_group group_render_basic = {
.name = "f519e481-24d2-4d42-87c9-3fdd12c00202",
.attrs =  attrs_render_basic,
 };
@@ -2922,7 +2922,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_basic = {
+static const struct attribute_group group_compute_basic = {
.name = "fe47b29d-ae51-423e-bff4-27d965a95b60",
.attrs =  attrs_compute_basic,
 };
@@ -2944,7 +2944,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_render_pipe_profile = {
+static const struct attribute_group group_render_pipe_profile = {
.name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774",
.attrs =  attrs_render_pipe_profile,
 };
@@ -2966,7 +2966,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_reads = {
+static const struct attribute_group group_memory_reads = {
.name = "9bc436dd-6130-4add-affc-283eb6eaa864",
.attrs =  attrs_memory_reads,
 };
@@ -2988,7 +2988,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_memory_writes = {
+static const struct attribute_group group_memory_writes = {
.name = "2ea0da8f-3527-4669-9d9d-13099a7435bf",
.attrs =  attrs_memory_writes,
 };
@@ -3010,7 +3010,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_extended = {
+static const struct attribute_group group_compute_extended = {
.name = "d97d16af-028b-4cd1-a672-6210cb5513dd",
.attrs =  attrs_compute_extended,
 };
@@ -3032,7 +3032,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_compute_l3_cache = {
+static const struct attribute_group group_compute_l3_cache = {
.name = "9fb22842-e708-43f7-9752-e0e41670c39e",
.attrs =  attrs_compute_l3_cache,
 };
@@ -3054,7 +3054,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_hdc_and_sf = {
+static const struct attribute_group group_hdc_and_sf = {
.name = "5378e2a1-4248-4188-a4ae-da25a794c603",
.attrs =  attrs_hdc_and_sf,
 };
@@ -3076,7 +3076,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_1 = {
+static const struct attribute_group group_l3_1 = {
.name = "f42cdd6a-b000-42cb-870f-5eb423a7f514",
.attrs =  attrs_l3_1,
 };
@@ -3098,7 +3098,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_2 = {
+static const struct attribute_group group_l3_2 = {
.name = "b9bf2423-d88c-4a7b-a051-627611d00dcc",
.attrs =  attrs_l3_2,
 };
@@ -3120,7 +3120,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_l3_3 = {
+static const struct attribute_group group_l3_3 = {
.name = "2414a93d-d84f-406e-99c0-472161194b40",
.attrs =  attrs_l3_3,
 };
@@ -3142,7 +3142,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_rasterizer_and_pixel_backend = {
+static const struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5",
.attrs =  attrs_rasterizer_and_pixel_backend,
 };
@@ -3164,7 +3164,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_sampler = {
+static const struct attribute_group group_sampler = {
.name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1",
.attrs =  attrs_sampler,
 };
@@ -3186,7 +3186,7 @@ int i915_oa_select_metric_set_sklgt2(struct 
drm_i915_private *dev_priv)
NULL,
 };
 
-static struct attribute_group group_tdl_1 = {
+static const 

[PATCH 00/11] constify i915 attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Arvind Yadav (11):
  [PATCH 01/11] drm: i915: i915_oa_kblgt2: constify attribute_group structures.
  [PATCH 02/11] drm: i915: i915_oa_bdw: constify attribute_group structures.
  [PATCH 03/11] drm: i915: i915_oa_bxt: constify attribute_group structures.
  [PATCH 04/11] drm: i915: i915_oa_chv: constify attribute_group structures.
  [PATCH 05/11] drm: i915: i915_oa_glk: constify attribute_group structures.
  [PATCH 06/11] drm: i915: i915_oa_hsw: constify attribute_group structures.
  [PATCH 07/11] drm: i915: i915_oa_kblgt3: constify attribute_group structures.
  [PATCH 08/11] drm: i915: i915_oa_sklgt2: constify attribute_group structures.
  [PATCH 09/11] drm: i915: i915_oa_sklgt3: constify attribute_group structures.
  [PATCH 10/11] drm: i915: i915_oa_sklgt4: constify attribute_group structures.
  [PATCH 11/11] drm: i915: i915_sysfs: constify attribute_group structures.

 drivers/gpu/drm/i915/i915_oa_bdw.c| 44 +--
 drivers/gpu/drm/i915/i915_oa_bxt.c| 30 
 drivers/gpu/drm/i915/i915_oa_chv.c| 28 +++---
 drivers/gpu/drm/i915/i915_oa_glk.c| 30 
 drivers/gpu/drm/i915/i915_oa_hsw.c| 12 +-
 drivers/gpu/drm/i915/i915_oa_kblgt2.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_kblgt3.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt2.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt3.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt4.c | 36 ++--
 drivers/gpu/drm/i915/i915_sysfs.c |  6 ++---
 11 files changed, 165 insertions(+), 165 deletions(-)

-- 
1.9.1

[PATCH 00/11] constify i915 attribute_group structures.

[Arvind Yadav]

attribute_group are not supposed to change at runtime. All functions
working with attribute_group provided by  work with
const attribute_group. So mark the non-const structs as const.

Arvind Yadav (11):
  [PATCH 01/11] drm: i915: i915_oa_kblgt2: constify attribute_group structures.
  [PATCH 02/11] drm: i915: i915_oa_bdw: constify attribute_group structures.
  [PATCH 03/11] drm: i915: i915_oa_bxt: constify attribute_group structures.
  [PATCH 04/11] drm: i915: i915_oa_chv: constify attribute_group structures.
  [PATCH 05/11] drm: i915: i915_oa_glk: constify attribute_group structures.
  [PATCH 06/11] drm: i915: i915_oa_hsw: constify attribute_group structures.
  [PATCH 07/11] drm: i915: i915_oa_kblgt3: constify attribute_group structures.
  [PATCH 08/11] drm: i915: i915_oa_sklgt2: constify attribute_group structures.
  [PATCH 09/11] drm: i915: i915_oa_sklgt3: constify attribute_group structures.
  [PATCH 10/11] drm: i915: i915_oa_sklgt4: constify attribute_group structures.
  [PATCH 11/11] drm: i915: i915_sysfs: constify attribute_group structures.

 drivers/gpu/drm/i915/i915_oa_bdw.c| 44 +--
 drivers/gpu/drm/i915/i915_oa_bxt.c| 30 
 drivers/gpu/drm/i915/i915_oa_chv.c| 28 +++---
 drivers/gpu/drm/i915/i915_oa_glk.c| 30 
 drivers/gpu/drm/i915/i915_oa_hsw.c| 12 +-
 drivers/gpu/drm/i915/i915_oa_kblgt2.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_kblgt3.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt2.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt3.c | 36 ++--
 drivers/gpu/drm/i915/i915_oa_sklgt4.c | 36 ++--
 drivers/gpu/drm/i915/i915_sysfs.c |  6 ++---
 11 files changed, 165 insertions(+), 165 deletions(-)

-- 
1.9.1

Re: [PATCH 4.12 00/31] 4.12.5-stable review

[Guenter Roeck]

On 08/03/2017 04:17 PM, Greg Kroah-Hartman wrote:

This is the start of the stable review cycle for the 4.12.5 release.
There are 31 patches in this series, all will be posted as a response
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Sat Aug  5 23:17:23 UTC 2017.
Anything received after that time might be too late.



Build results:
total: 145 pass: 145 fail: 0
Qemu test results:
total: 122 pass: 122 fail: 0

Details are available at http://kerneltests.org/builders.

Guenter

Re: [PATCH 4.12 00/31] 4.12.5-stable review

[Guenter Roeck]

On 08/03/2017 04:17 PM, Greg Kroah-Hartman wrote:

This is the start of the stable review cycle for the 4.12.5 release.
There are 31 patches in this series, all will be posted as a response
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Sat Aug  5 23:17:23 UTC 2017.
Anything received after that time might be too late.



Build results:
total: 145 pass: 145 fail: 0
Qemu test results:
total: 122 pass: 122 fail: 0

Details are available at http://kerneltests.org/builders.

Guenter

[PATCH] pinctrl: add __rcu annotations to fix sparse warnings

[Masahiro Yamada]

Sparse reports "warning: incorrect type in assignment (different
address spaces)".

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/core.c   | 2 +-
 drivers/pinctrl/pinmux.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 89b9ca77daea..60f82c67b92d 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -686,7 +686,7 @@ EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group);
 static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
 {
struct radix_tree_iter iter;
-   void **slot;
+   void __rcu **slot;
 
radix_tree_for_each_slot(slot, >pin_group_tree, , 0)
radix_tree_delete(>pin_group_tree, iter.index);
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 36d5da9dc587..55502fc4479c 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -833,7 +833,7 @@ EXPORT_SYMBOL_GPL(pinmux_generic_remove_function);
 void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
 {
struct radix_tree_iter iter;
-   void **slot;
+   void __rcu **slot;
 
radix_tree_for_each_slot(slot, >pin_function_tree, , 0)
radix_tree_delete(>pin_function_tree, iter.index);
-- 
2.7.4

[PATCH] pinctrl: add __rcu annotations to fix sparse warnings

[Masahiro Yamada]

Sparse reports "warning: incorrect type in assignment (different
address spaces)".

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/core.c   | 2 +-
 drivers/pinctrl/pinmux.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 89b9ca77daea..60f82c67b92d 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -686,7 +686,7 @@ EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group);
 static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
 {
struct radix_tree_iter iter;
-   void **slot;
+   void __rcu **slot;
 
radix_tree_for_each_slot(slot, >pin_group_tree, , 0)
radix_tree_delete(>pin_group_tree, iter.index);
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 36d5da9dc587..55502fc4479c 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -833,7 +833,7 @@ EXPORT_SYMBOL_GPL(pinmux_generic_remove_function);
 void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
 {
struct radix_tree_iter iter;
-   void **slot;
+   void __rcu **slot;
 
radix_tree_for_each_slot(slot, >pin_function_tree, , 0)
radix_tree_delete(>pin_function_tree, iter.index);
-- 
2.7.4

[PATCH] pinctrl: nomadik: fix incorrect type in return expression

[Masahiro Yamada]

Sparse reports "warning: incorrect type in return expression (different
address spaces)" because nmk_gpio_populate_chip() is supposed to return
(struct nmk_gpio_chip *) whereas devm_ioremap_resource() returns
(void __iomem *).  ERR_CAST() is needed to fix the warning.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c 
b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index d318ca055489..a53f1a9b1ed2 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -1078,7 +1078,7 @@ static struct nmk_gpio_chip 
*nmk_gpio_populate_chip(struct device_node *np,
res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(>dev, res);
if (IS_ERR(base))
-   return base;
+   return ERR_CAST(base);
nmk_chip->addr = base;
 
clk = clk_get(_pdev->dev, NULL);
-- 
2.7.4

[PATCH] pinctrl: nomadik: fix incorrect type in return expression

[Masahiro Yamada]

Sparse reports "warning: incorrect type in return expression (different
address spaces)" because nmk_gpio_populate_chip() is supposed to return
(struct nmk_gpio_chip *) whereas devm_ioremap_resource() returns
(void __iomem *).  ERR_CAST() is needed to fix the warning.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c 
b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index d318ca055489..a53f1a9b1ed2 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -1078,7 +1078,7 @@ static struct nmk_gpio_chip 
*nmk_gpio_populate_chip(struct device_node *np,
res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(>dev, res);
if (IS_ERR(base))
-   return base;
+   return ERR_CAST(base);
nmk_chip->addr = base;
 
clk = clk_get(_pdev->dev, NULL);
-- 
2.7.4

[PATCH] pinctrl: sirf: add static to local data

[Masahiro Yamada]

Detected by sparse.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/sirf/pinctrl-atlas7.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c 
b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 1efa315a7dbe..b3de1eb04ec1 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -549,7 +549,7 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
PINCTRL_PIN(163, "jtag_trstn"),
 };
 
-struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
+static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
/* The Configuration of IOC_RTC Pads */
PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
@@ -1002,7 +1002,7 @@ static const unsigned int vi_vip1_high8bit_pins[] = { 82, 
83, 84, 103, 104,
105, 106, 107, 102, 97, 98, };
 
 /* definition of pin group table */
-struct atlas7_pin_group altas7_pin_groups[] = {
+static struct atlas7_pin_group altas7_pin_groups[] = {
GROUP("gnss_gpio_grp", gnss_gpio_pins),
GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
@@ -4764,7 +4764,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
_vip1_high8bit_grp_mux),
 };
 
-struct atlas7_pinctrl_data atlas7_ioc_data = {
+static struct atlas7_pinctrl_data atlas7_ioc_data = {
.pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
.pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
.grps = (struct atlas7_pin_group *)altas7_pin_groups,
-- 
2.7.4

[PATCH] pinctrl: sirf: add static to local data

[Masahiro Yamada]

Detected by sparse.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/sirf/pinctrl-atlas7.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c 
b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 1efa315a7dbe..b3de1eb04ec1 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -549,7 +549,7 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
PINCTRL_PIN(163, "jtag_trstn"),
 };
 
-struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
+static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
/* The Configuration of IOC_RTC Pads */
PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
@@ -1002,7 +1002,7 @@ static const unsigned int vi_vip1_high8bit_pins[] = { 82, 
83, 84, 103, 104,
105, 106, 107, 102, 97, 98, };
 
 /* definition of pin group table */
-struct atlas7_pin_group altas7_pin_groups[] = {
+static struct atlas7_pin_group altas7_pin_groups[] = {
GROUP("gnss_gpio_grp", gnss_gpio_pins),
GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
@@ -4764,7 +4764,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
_vip1_high8bit_grp_mux),
 };
 
-struct atlas7_pinctrl_data atlas7_ioc_data = {
+static struct atlas7_pinctrl_data atlas7_ioc_data = {
.pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
.pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
.grps = (struct atlas7_pin_group *)altas7_pin_groups,
-- 
2.7.4

[PATCH] pinctrl: armada-37xx: add static to local data

[Masahiro Yamada]

Detected by sparse.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index f024e25787fc..0b263b90a9a8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -179,14 +179,14 @@ static struct armada_37xx_pin_group 
armada_37xx_sb_groups[] = {
PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
 };
 
-const struct armada_37xx_pin_data armada_37xx_pin_nb = {
+static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
.nr_pins = 36,
.name = "GPIO1",
.groups = armada_37xx_nb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
 };
 
-const struct armada_37xx_pin_data armada_37xx_pin_sb = {
+static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.nr_pins = 29,
.name = "GPIO2",
.groups = armada_37xx_sb_groups,
-- 
2.7.4

[PATCH] pinctrl: armada-37xx: add static to local data

[Masahiro Yamada]

Detected by sparse.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index f024e25787fc..0b263b90a9a8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -179,14 +179,14 @@ static struct armada_37xx_pin_group 
armada_37xx_sb_groups[] = {
PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
 };
 
-const struct armada_37xx_pin_data armada_37xx_pin_nb = {
+static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
.nr_pins = 36,
.name = "GPIO1",
.groups = armada_37xx_nb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
 };
 
-const struct armada_37xx_pin_data armada_37xx_pin_sb = {
+static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.nr_pins = 29,
.name = "GPIO2",
.groups = armada_37xx_sb_groups,
-- 
2.7.4

[PATCH net-next] net: dsa: User per-cpu 64-bit statistics

[Florian Fainelli]

During testing with a background iperf pushing 1Gbit/sec worth of
traffic and having both ifconfig and ethtool collect statistics, we
could see quite frequent deadlocks. Convert the often accessed DSA slave
network devices statistics to per-cpu 64-bit statistics to remove these
deadlocks and provide fast efficient statistics updates.

Signed-off-by: Florian Fainelli 
---
 net/dsa/dsa.c  | 10 +---
 net/dsa/dsa_priv.h |  2 +-
 net/dsa/slave.c| 72 +++---
 3 files changed, 59 insertions(+), 25 deletions(-)

diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 0ba842c08dd3..a91e520e735f 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -190,6 +190,7 @@ static int dsa_switch_rcv(struct sk_buff *skb, struct 
net_device *dev,
 {
struct dsa_switch_tree *dst = dev->dsa_ptr;
struct sk_buff *nskb = NULL;
+   struct pcpu_sw_netstats *s;
struct dsa_slave_priv *p;
 
if (unlikely(dst == NULL)) {
@@ -213,10 +214,11 @@ static int dsa_switch_rcv(struct sk_buff *skb, struct 
net_device *dev,
skb->pkt_type = PACKET_HOST;
skb->protocol = eth_type_trans(skb, skb->dev);
 
-   u64_stats_update_begin(>stats64.syncp);
-   p->stats64.rx_packets++;
-   p->stats64.rx_bytes += skb->len;
-   u64_stats_update_end(>stats64.syncp);
+   s = this_cpu_ptr(p->stats64);
+   u64_stats_update_begin(>syncp);
+   s->rx_packets++;
+   s->rx_bytes += skb->len;
+   u64_stats_update_end(>syncp);
 
netif_receive_skb(skb);
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 7aa0656296c2..306cff229def 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -77,7 +77,7 @@ struct dsa_slave_priv {
struct sk_buff *(*xmit)(struct sk_buff *skb,
struct net_device *dev);
 
-   struct pcpu_sw_netstats stats64;
+   struct pcpu_sw_netstats *stats64;
 
/* DSA port data, such as switch, port index, etc. */
struct dsa_port *dp;
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index e196562035b1..605444ced06c 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -352,12 +352,14 @@ static inline netdev_tx_t dsa_netpoll_send_skb(struct 
dsa_slave_priv *p,
 static netdev_tx_t dsa_slave_xmit(struct sk_buff *skb, struct net_device *dev)
 {
struct dsa_slave_priv *p = netdev_priv(dev);
+   struct pcpu_sw_netstats *s;
struct sk_buff *nskb;
 
-   u64_stats_update_begin(>stats64.syncp);
-   p->stats64.tx_packets++;
-   p->stats64.tx_bytes += skb->len;
-   u64_stats_update_end(>stats64.syncp);
+   s = this_cpu_ptr(p->stats64);
+   u64_stats_update_begin(>syncp);
+   s->tx_packets++;
+   s->tx_bytes += skb->len;
+   u64_stats_update_end(>syncp);
 
/* Transmit function may have to reallocate the original SKB,
 * in which case it must have freed it. Only free it here on error.
@@ -596,15 +598,26 @@ static void dsa_slave_get_ethtool_stats(struct net_device 
*dev,
 {
struct dsa_slave_priv *p = netdev_priv(dev);
struct dsa_switch *ds = p->dp->ds;
+   struct pcpu_sw_netstats *s;
unsigned int start;
-
-   do {
-   start = u64_stats_fetch_begin_irq(>stats64.syncp);
-   data[0] = p->stats64.tx_packets;
-   data[1] = p->stats64.tx_bytes;
-   data[2] = p->stats64.rx_packets;
-   data[3] = p->stats64.rx_bytes;
-   } while (u64_stats_fetch_retry_irq(>stats64.syncp, start));
+   int i;
+
+   for_each_possible_cpu(i) {
+   u64 tx_packets, tx_bytes, rx_packets, rx_bytes;
+
+   s = per_cpu_ptr(p->stats64, i);
+   do {
+   start = u64_stats_fetch_begin_irq(>syncp);
+   tx_packets = s->tx_packets;
+   tx_bytes = s->tx_bytes;
+   rx_packets = s->rx_packets;
+   rx_bytes = s->rx_bytes;
+   } while (u64_stats_fetch_retry_irq(>syncp, start));
+   data[0] += tx_packets;
+   data[1] += tx_bytes;
+   data[2] += rx_packets;
+   data[3] += rx_bytes;
+   }
if (ds->ops->get_ethtool_stats)
ds->ops->get_ethtool_stats(ds, p->dp->index, data + 4);
 }
@@ -879,16 +892,28 @@ static void dsa_slave_get_stats64(struct net_device *dev,
  struct rtnl_link_stats64 *stats)
 {
struct dsa_slave_priv *p = netdev_priv(dev);
+   struct pcpu_sw_netstats *s;
unsigned int start;
+   int i;
 
netdev_stats_to_stats64(stats, >stats);
-   do {
-   start = u64_stats_fetch_begin_irq(>stats64.syncp);
-   stats->tx_packets = p->stats64.tx_packets;
-   stats->tx_bytes = p->stats64.tx_bytes;
-   stats->rx_packets = p->stats64.rx_packets;
-   stats->rx_bytes 

[PATCH net-next] net: dsa: User per-cpu 64-bit statistics

[Florian Fainelli]

During testing with a background iperf pushing 1Gbit/sec worth of
traffic and having both ifconfig and ethtool collect statistics, we
could see quite frequent deadlocks. Convert the often accessed DSA slave
network devices statistics to per-cpu 64-bit statistics to remove these
deadlocks and provide fast efficient statistics updates.

Signed-off-by: Florian Fainelli 
---
 net/dsa/dsa.c  | 10 +---
 net/dsa/dsa_priv.h |  2 +-
 net/dsa/slave.c| 72 +++---
 3 files changed, 59 insertions(+), 25 deletions(-)

diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 0ba842c08dd3..a91e520e735f 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -190,6 +190,7 @@ static int dsa_switch_rcv(struct sk_buff *skb, struct 
net_device *dev,
 {
struct dsa_switch_tree *dst = dev->dsa_ptr;
struct sk_buff *nskb = NULL;
+   struct pcpu_sw_netstats *s;
struct dsa_slave_priv *p;
 
if (unlikely(dst == NULL)) {
@@ -213,10 +214,11 @@ static int dsa_switch_rcv(struct sk_buff *skb, struct 
net_device *dev,
skb->pkt_type = PACKET_HOST;
skb->protocol = eth_type_trans(skb, skb->dev);
 
-   u64_stats_update_begin(>stats64.syncp);
-   p->stats64.rx_packets++;
-   p->stats64.rx_bytes += skb->len;
-   u64_stats_update_end(>stats64.syncp);
+   s = this_cpu_ptr(p->stats64);
+   u64_stats_update_begin(>syncp);
+   s->rx_packets++;
+   s->rx_bytes += skb->len;
+   u64_stats_update_end(>syncp);
 
netif_receive_skb(skb);
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 7aa0656296c2..306cff229def 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -77,7 +77,7 @@ struct dsa_slave_priv {
struct sk_buff *(*xmit)(struct sk_buff *skb,
struct net_device *dev);
 
-   struct pcpu_sw_netstats stats64;
+   struct pcpu_sw_netstats *stats64;
 
/* DSA port data, such as switch, port index, etc. */
struct dsa_port *dp;
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index e196562035b1..605444ced06c 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -352,12 +352,14 @@ static inline netdev_tx_t dsa_netpoll_send_skb(struct 
dsa_slave_priv *p,
 static netdev_tx_t dsa_slave_xmit(struct sk_buff *skb, struct net_device *dev)
 {
struct dsa_slave_priv *p = netdev_priv(dev);
+   struct pcpu_sw_netstats *s;
struct sk_buff *nskb;
 
-   u64_stats_update_begin(>stats64.syncp);
-   p->stats64.tx_packets++;
-   p->stats64.tx_bytes += skb->len;
-   u64_stats_update_end(>stats64.syncp);
+   s = this_cpu_ptr(p->stats64);
+   u64_stats_update_begin(>syncp);
+   s->tx_packets++;
+   s->tx_bytes += skb->len;
+   u64_stats_update_end(>syncp);
 
/* Transmit function may have to reallocate the original SKB,
 * in which case it must have freed it. Only free it here on error.
@@ -596,15 +598,26 @@ static void dsa_slave_get_ethtool_stats(struct net_device 
*dev,
 {
struct dsa_slave_priv *p = netdev_priv(dev);
struct dsa_switch *ds = p->dp->ds;
+   struct pcpu_sw_netstats *s;
unsigned int start;
-
-   do {
-   start = u64_stats_fetch_begin_irq(>stats64.syncp);
-   data[0] = p->stats64.tx_packets;
-   data[1] = p->stats64.tx_bytes;
-   data[2] = p->stats64.rx_packets;
-   data[3] = p->stats64.rx_bytes;
-   } while (u64_stats_fetch_retry_irq(>stats64.syncp, start));
+   int i;
+
+   for_each_possible_cpu(i) {
+   u64 tx_packets, tx_bytes, rx_packets, rx_bytes;
+
+   s = per_cpu_ptr(p->stats64, i);
+   do {
+   start = u64_stats_fetch_begin_irq(>syncp);
+   tx_packets = s->tx_packets;
+   tx_bytes = s->tx_bytes;
+   rx_packets = s->rx_packets;
+   rx_bytes = s->rx_bytes;
+   } while (u64_stats_fetch_retry_irq(>syncp, start));
+   data[0] += tx_packets;
+   data[1] += tx_bytes;
+   data[2] += rx_packets;
+   data[3] += rx_bytes;
+   }
if (ds->ops->get_ethtool_stats)
ds->ops->get_ethtool_stats(ds, p->dp->index, data + 4);
 }
@@ -879,16 +892,28 @@ static void dsa_slave_get_stats64(struct net_device *dev,
  struct rtnl_link_stats64 *stats)
 {
struct dsa_slave_priv *p = netdev_priv(dev);
+   struct pcpu_sw_netstats *s;
unsigned int start;
+   int i;
 
netdev_stats_to_stats64(stats, >stats);
-   do {
-   start = u64_stats_fetch_begin_irq(>stats64.syncp);
-   stats->tx_packets = p->stats64.tx_packets;
-   stats->tx_bytes = p->stats64.tx_bytes;
-   stats->rx_packets = p->stats64.rx_packets;
-   stats->rx_bytes = 

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

[Chen-Yu Tsai]

On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng  wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai  写到:
>>Hi,
>>
>>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng  wrote:
>>> From: Jernej Skrabec 
>>>
>>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>>set.
>>>
>>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>>
>>> Signed-off-by: Jernej Skrabec 
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> index b1127e8629d9..2ebb3d865b01 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>>"avs",  "osc24M",
>>>
>>>  static const char * const hdmi_parents[] = { "pll-video" };
>>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>>> -0x150, 0, 4, 24, 2, BIT(31), 0);
>>> +0x150, 0, 4, 24, 2, BIT(31),
>>CLK_SET_RATE_PARENT);
>>
>>Line is longer than 80 characters.
>>
>>This looks independent enough so I've merged this for 4.14 with the
>>offending line wrapped and the following tag added:
>>
>>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>
> Please don't merge this now until Jernej send it.

(Dropped Rob, devicetree and dri mailing lists)

Hi Jernej,

Is it OK if we take this patch for the next release? Or rather,
if there anything blocking this patch?

Thanks
ChenYu

>
>>
>>ChenYu
>>
>>>
>>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
>>>   0x154, BIT(31), 0);
>>> --
>>> 2.13.0
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>Groups "linux-sunxi" group.
>>> To unsubscribe from this group and stop receiving emails from it,
>>send an email to linux-sunxi+unsubscr...@googlegroups.com.
>>> For more options, visit https://groups.google.com/d/optout.
>
> --
> You received this message because you are subscribed to the Google Groups 
> "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to linux-sunxi+unsubscr...@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

[Chen-Yu Tsai]

On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng  wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai  写到:
>>Hi,
>>
>>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng  wrote:
>>> From: Jernej Skrabec 
>>>
>>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>>set.
>>>
>>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>>
>>> Signed-off-by: Jernej Skrabec 
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> index b1127e8629d9..2ebb3d865b01 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>>"avs",  "osc24M",
>>>
>>>  static const char * const hdmi_parents[] = { "pll-video" };
>>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>>> -0x150, 0, 4, 24, 2, BIT(31), 0);
>>> +0x150, 0, 4, 24, 2, BIT(31),
>>CLK_SET_RATE_PARENT);
>>
>>Line is longer than 80 characters.
>>
>>This looks independent enough so I've merged this for 4.14 with the
>>offending line wrapped and the following tag added:
>>
>>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>
> Please don't merge this now until Jernej send it.

(Dropped Rob, devicetree and dri mailing lists)

Hi Jernej,

Is it OK if we take this patch for the next release? Or rather,
if there anything blocking this patch?

Thanks
ChenYu

>
>>
>>ChenYu
>>
>>>
>>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
>>>   0x154, BIT(31), 0);
>>> --
>>> 2.13.0
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>Groups "linux-sunxi" group.
>>> To unsubscribe from this group and stop receiving emails from it,
>>send an email to linux-sunxi+unsubscr...@googlegroups.com.
>>> For more options, visit https://groups.google.com/d/optout.
>
> --
> You received this message because you are subscribed to the Google Groups 
> "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to linux-sunxi+unsubscr...@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

Re: [linux-sunxi] [PATCH] drm/panel: simple: Fix width and height for Olimex LCD-OLinuXino-4.3TS

[Chen-Yu Tsai]

On Thu, Jul 20, 2017 at 6:29 PM, Jonathan Liu  wrote:
> The physical size of the panel is 105.5 (W) x 67.2 (H) x 4.05 (D) mm
> but the active display area is 95.04 (W) x 53.856 (H) mm.
>
> The width and height should be set to the active display area.
>
> Signed-off-by: Jonathan Liu 

You probably want:

Fixes: cf5c9e6dc70d ("drm/panel: simple: Add timings for the Olimex
  LCD-OLinuXino-4.3TS")

Otherwise,

Reviewed-by: Chen-Yu Tsai 

against the panel datasheet linked from Olimex's product page.
This should probably go in through drm-misc?

Re: [linux-sunxi] [PATCH] drm/panel: simple: Fix width and height for Olimex LCD-OLinuXino-4.3TS

[Chen-Yu Tsai]

On Thu, Jul 20, 2017 at 6:29 PM, Jonathan Liu  wrote:
> The physical size of the panel is 105.5 (W) x 67.2 (H) x 4.05 (D) mm
> but the active display area is 95.04 (W) x 53.856 (H) mm.
>
> The width and height should be set to the active display area.
>
> Signed-off-by: Jonathan Liu 

You probably want:

Fixes: cf5c9e6dc70d ("drm/panel: simple: Add timings for the Olimex
  LCD-OLinuXino-4.3TS")

Otherwise,

Reviewed-by: Chen-Yu Tsai 

against the panel datasheet linked from Olimex's product page.
This should probably go in through drm-misc?