Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Boqun Feng]

On Wed, Aug 16, 2017 at 02:05:06PM +0900, Byungchul Park wrote:
> On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > > I see...
> > > 
> > > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be 
> > > released
> > > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > > Task   C : acquired of lock#3 -> wait for completion of barr->done
> > 
> > >From the stack trace below, this barr->done is for flush_work() in
> > lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> > 
> > > Worker D : wait for wfc.work to be released -> will complete barr->done
> > 
> > and this barr->done is for work "wfc.work".
> > 
> > So those two barr->done could not be the same instance, IIUC. Therefore
> > the deadlock case is not possible.
> > 
> > The problem here is all barr->done instances are initialized at
> > insert_wq_barrier() and they belongs to the same lock class, to fix
> 
> I'm not sure this caused the lockdep warning but, if they belongs to the
> same class even though they couldn't be the same instance as you said, I
> also think that is another problem and should be fixed.
> 

My point was more like this is a false positive case, which we should
avoid as hard as we can, because this very case doesn't look like a
deadlock to me.

Maybe the pattern above does exist in current kernel, but we need to
guide/adjust lockdep to find the real case showing it's happening.

Regards,
Boqun

> > this, we need to differ barr->done with different lock classes based on
> > the corresponding works.
> > 
> > How about the this(only compilation test):
> > 
> > ->8
> > diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> > index e86733a8b344..d14067942088 100644
> > --- a/kernel/workqueue.c
> > +++ b/kernel/workqueue.c
> > @@ -2431,6 +2431,27 @@ struct wq_barrier {
> > struct task_struct  *task;  /* purely informational */
> >  };
> >  
> > +#ifdef CONFIG_LOCKDEP_COMPLETE
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> > \
> > +  "(complete)" #barr,  
> > \
> > +  (target)->lockdep_map.key, 1);   
> > \
> > +   __init_completion(>done); 
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#else
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   init_completion(>done);   
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#endif
> > +
> >  static void wq_barrier_func(struct work_struct *work)
> >  {
> > struct wq_barrier *barr = container_of(work, struct wq_barrier, work);
> > @@ -2474,10 +2495,7 @@ static void insert_wq_barrier(struct pool_workqueue 
> > *pwq,
> >  * checks and call back into the fixup functions where we
> >  * might deadlock.
> >  */
> > -   INIT_WORK_ONSTACK(>work, wq_barrier_func);
> > -   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(>work));
> > -   init_completion(>done);
> > -   barr->task = current;
> > +   INIT_WQ_BARRIER_ONSTACK(barr, wq_barrier_func, target);
> >  
> > /*
> >  * If @target is currently being executed, schedule the


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Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Boqun Feng]

On Wed, Aug 16, 2017 at 02:05:06PM +0900, Byungchul Park wrote:
> On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > > I see...
> > > 
> > > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be 
> > > released
> > > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > > Task   C : acquired of lock#3 -> wait for completion of barr->done
> > 
> > >From the stack trace below, this barr->done is for flush_work() in
> > lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> > 
> > > Worker D : wait for wfc.work to be released -> will complete barr->done
> > 
> > and this barr->done is for work "wfc.work".
> > 
> > So those two barr->done could not be the same instance, IIUC. Therefore
> > the deadlock case is not possible.
> > 
> > The problem here is all barr->done instances are initialized at
> > insert_wq_barrier() and they belongs to the same lock class, to fix
> 
> I'm not sure this caused the lockdep warning but, if they belongs to the
> same class even though they couldn't be the same instance as you said, I
> also think that is another problem and should be fixed.
> 

My point was more like this is a false positive case, which we should
avoid as hard as we can, because this very case doesn't look like a
deadlock to me.

Maybe the pattern above does exist in current kernel, but we need to
guide/adjust lockdep to find the real case showing it's happening.

Regards,
Boqun

> > this, we need to differ barr->done with different lock classes based on
> > the corresponding works.
> > 
> > How about the this(only compilation test):
> > 
> > ->8
> > diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> > index e86733a8b344..d14067942088 100644
> > --- a/kernel/workqueue.c
> > +++ b/kernel/workqueue.c
> > @@ -2431,6 +2431,27 @@ struct wq_barrier {
> > struct task_struct  *task;  /* purely informational */
> >  };
> >  
> > +#ifdef CONFIG_LOCKDEP_COMPLETE
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> > \
> > +  "(complete)" #barr,  
> > \
> > +  (target)->lockdep_map.key, 1);   
> > \
> > +   __init_completion(>done); 
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#else
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   init_completion(>done);   
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#endif
> > +
> >  static void wq_barrier_func(struct work_struct *work)
> >  {
> > struct wq_barrier *barr = container_of(work, struct wq_barrier, work);
> > @@ -2474,10 +2495,7 @@ static void insert_wq_barrier(struct pool_workqueue 
> > *pwq,
> >  * checks and call back into the fixup functions where we
> >  * might deadlock.
> >  */
> > -   INIT_WORK_ONSTACK(>work, wq_barrier_func);
> > -   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(>work));
> > -   init_completion(>done);
> > -   barr->task = current;
> > +   INIT_WQ_BARRIER_ONSTACK(barr, wq_barrier_func, target);
> >  
> > /*
> >  * If @target is currently being executed, schedule the


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Re: [virtio-dev] [PATCH v13 0/5] Virtio-balloon Enhancement

[Adam Tao]

On Thu, Aug 03, 2017 at 02:38:14PM +0800, Wei Wang wrote:
> This patch series enhances the existing virtio-balloon with the following
> new features:
> 1) fast ballooning: transfer ballooned pages between the guest and host in
> chunks using sgs, instead of one by one; and
> 2) free_page_vq: a new virtqueue to report guest free pages to the host.
> 
Hi wei,
The reason we add the new vq for the migration feature is based on
what(original design based on inflate and deflate vq)?
I am wondering if we add new feature in the future do we still need to add new 
type
of vq?
Do we need to add one command queue for the common purpose(including
different type of requests except the in/deflate ones)?
Thanks
Adam
> The second feature can be used to accelerate live migration of VMs. Here
> are some details:
> 
> Live migration needs to transfer the VM's memory from the source machine
> to the destination round by round. For the 1st round, all the VM's memory
> is transferred. From the 2nd round, only the pieces of memory that were
> written by the guest (after the 1st round) are transferred. One method
> that is popularly used by the hypervisor to track which part of memory is
> written is to write-protect all the guest memory.
> 
> The second feature  enables the optimization of the 1st round memory
> transfer - the hypervisor can skip the transfer of guest free pages in the
> 1st round. It is not concerned that the memory pages are used after they
> are given to the hypervisor as a hint of the free pages, because they will
> be tracked by the hypervisor and transferred in the next round if they are
> used and written.
> 
> Change Log:
> v12->v13:
> 1) mm: use a callback function to handle the the free page blocks from the
> report function. This avoids exposing the zone internal to a kernel module.
> 2) virtio-balloon: send balloon pages or a free page block using a single sg
> each time. This has the benefits of simpler implementation with no new APIs.
> 3) virtio-balloon: the free_page_vq is used to report free pages only (no
> multiple usages interleaving)
> 4) virtio-balloon: Balloon pages and free page blocks are sent via input sgs,
> and the completion signal to the host is sent via an output sg.
> 
> v11->v12:
> 1) xbitmap: use the xbitmap from Matthew Wilcox to record ballooned pages.
> 2) virtio-ring: enable the driver to build up a desc chain using vring desc.
> 3) virtio-ring: Add locking to the existing START_USE() and END_USE() macro
> to lock/unlock the vq when a vq operation starts/ends.
> 4) virtio-ring: add virtqueue_kick_sync() and virtqueue_kick_async()
> 5) virtio-balloon: describe chunks of ballooned pages and free pages blocks
> directly using one or more chains of desc from the vq.
> 
> v10->v11:
> 1) virtio_balloon: use vring_desc to describe a chunk;
> 2) virtio_ring: support to add an indirect desc table to virtqueue;
> 3)  virtio_balloon: use cmdq to report guest memory statistics.
> 
> v9->v10:
> 1) mm: put report_unused_page_block() under CONFIG_VIRTIO_BALLOON;
> 2) virtio-balloon: add virtballoon_validate();
> 3) virtio-balloon: msg format change;
> 4) virtio-balloon: move miscq handling to a task on system_freezable_wq;
> 5) virtio-balloon: code cleanup.
> 
> v8->v9:
> 1) Split the two new features, VIRTIO_BALLOON_F_BALLOON_CHUNKS and
> VIRTIO_BALLOON_F_MISC_VQ, which were mixed together in the previous
> implementation;
> 2) Simpler function to get the free page block.
> 
> v7->v8:
> 1) Use only one chunk format, instead of two.
> 2) re-write the virtio-balloon implementation patch.
> 3) commit changes
> 4) patch re-org
> 
> Matthew Wilcox (1):
>   Introduce xbitmap
> 
> Wei Wang (4):
>   xbitmap: add xb_find_next_bit() and xb_zero()
>   virtio-balloon: VIRTIO_BALLOON_F_SG
>   mm: support reporting free page blocks
>   virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_VQ
> 
>  drivers/virtio/virtio_balloon.c | 302 
> +++-
>  include/linux/mm.h  |   7 +
>  include/linux/mmzone.h  |   5 +
>  include/linux/radix-tree.h  |   2 +
>  include/linux/xbitmap.h |  53 +++
>  include/uapi/linux/virtio_balloon.h |   2 +
>  lib/radix-tree.c| 167 +++-
>  mm/page_alloc.c | 109 +
>  8 files changed, 609 insertions(+), 38 deletions(-)
>  create mode 100644 include/linux/xbitmap.h
> 
> -- 
> 2.7.4
> 
> 
> -
> To unsubscribe, e-mail: virtio-dev-unsubscr...@lists.oasis-open.org
> For additional commands, e-mail: virtio-dev-h...@lists.oasis-open.org

Re: [virtio-dev] [PATCH v13 0/5] Virtio-balloon Enhancement

[Adam Tao]

On Thu, Aug 03, 2017 at 02:38:14PM +0800, Wei Wang wrote:
> This patch series enhances the existing virtio-balloon with the following
> new features:
> 1) fast ballooning: transfer ballooned pages between the guest and host in
> chunks using sgs, instead of one by one; and
> 2) free_page_vq: a new virtqueue to report guest free pages to the host.
> 
Hi wei,
The reason we add the new vq for the migration feature is based on
what(original design based on inflate and deflate vq)?
I am wondering if we add new feature in the future do we still need to add new 
type
of vq?
Do we need to add one command queue for the common purpose(including
different type of requests except the in/deflate ones)?
Thanks
Adam
> The second feature can be used to accelerate live migration of VMs. Here
> are some details:
> 
> Live migration needs to transfer the VM's memory from the source machine
> to the destination round by round. For the 1st round, all the VM's memory
> is transferred. From the 2nd round, only the pieces of memory that were
> written by the guest (after the 1st round) are transferred. One method
> that is popularly used by the hypervisor to track which part of memory is
> written is to write-protect all the guest memory.
> 
> The second feature  enables the optimization of the 1st round memory
> transfer - the hypervisor can skip the transfer of guest free pages in the
> 1st round. It is not concerned that the memory pages are used after they
> are given to the hypervisor as a hint of the free pages, because they will
> be tracked by the hypervisor and transferred in the next round if they are
> used and written.
> 
> Change Log:
> v12->v13:
> 1) mm: use a callback function to handle the the free page blocks from the
> report function. This avoids exposing the zone internal to a kernel module.
> 2) virtio-balloon: send balloon pages or a free page block using a single sg
> each time. This has the benefits of simpler implementation with no new APIs.
> 3) virtio-balloon: the free_page_vq is used to report free pages only (no
> multiple usages interleaving)
> 4) virtio-balloon: Balloon pages and free page blocks are sent via input sgs,
> and the completion signal to the host is sent via an output sg.
> 
> v11->v12:
> 1) xbitmap: use the xbitmap from Matthew Wilcox to record ballooned pages.
> 2) virtio-ring: enable the driver to build up a desc chain using vring desc.
> 3) virtio-ring: Add locking to the existing START_USE() and END_USE() macro
> to lock/unlock the vq when a vq operation starts/ends.
> 4) virtio-ring: add virtqueue_kick_sync() and virtqueue_kick_async()
> 5) virtio-balloon: describe chunks of ballooned pages and free pages blocks
> directly using one or more chains of desc from the vq.
> 
> v10->v11:
> 1) virtio_balloon: use vring_desc to describe a chunk;
> 2) virtio_ring: support to add an indirect desc table to virtqueue;
> 3)  virtio_balloon: use cmdq to report guest memory statistics.
> 
> v9->v10:
> 1) mm: put report_unused_page_block() under CONFIG_VIRTIO_BALLOON;
> 2) virtio-balloon: add virtballoon_validate();
> 3) virtio-balloon: msg format change;
> 4) virtio-balloon: move miscq handling to a task on system_freezable_wq;
> 5) virtio-balloon: code cleanup.
> 
> v8->v9:
> 1) Split the two new features, VIRTIO_BALLOON_F_BALLOON_CHUNKS and
> VIRTIO_BALLOON_F_MISC_VQ, which were mixed together in the previous
> implementation;
> 2) Simpler function to get the free page block.
> 
> v7->v8:
> 1) Use only one chunk format, instead of two.
> 2) re-write the virtio-balloon implementation patch.
> 3) commit changes
> 4) patch re-org
> 
> Matthew Wilcox (1):
>   Introduce xbitmap
> 
> Wei Wang (4):
>   xbitmap: add xb_find_next_bit() and xb_zero()
>   virtio-balloon: VIRTIO_BALLOON_F_SG
>   mm: support reporting free page blocks
>   virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_VQ
> 
>  drivers/virtio/virtio_balloon.c | 302 
> +++-
>  include/linux/mm.h  |   7 +
>  include/linux/mmzone.h  |   5 +
>  include/linux/radix-tree.h  |   2 +
>  include/linux/xbitmap.h |  53 +++
>  include/uapi/linux/virtio_balloon.h |   2 +
>  lib/radix-tree.c| 167 +++-
>  mm/page_alloc.c | 109 +
>  8 files changed, 609 insertions(+), 38 deletions(-)
>  create mode 100644 include/linux/xbitmap.h
> 
> -- 
> 2.7.4
> 
> 
> -
> To unsubscribe, e-mail: virtio-dev-unsubscr...@lists.oasis-open.org
> For additional commands, e-mail: virtio-dev-h...@lists.oasis-open.org

Re: [PATCHv3] perf bpf: Fix endianness problem when loading parameters in prologue

[Thomas-Mich Richter]

On 08/15/2017 05:25 PM, Arnaldo Carvalho de Melo wrote:
> Em Tue, Aug 15, 2017 at 11:21:59AM +0200, Thomas Richter escreveu:
> 
> Ok, I'm applying this, the only missing bit was the following line,
> right at the start of the patch message body;
> 
> From: Wang Nan 
> 
> To state that the patch was wrote by Wang, the fact that you
> participated in it with some adjustment is implied by having you sign
> off the patch, ok?
> 
> - Arnaldo


Thanks Arnaldo,

will /hopefully) remember next time.

-- 
Thomas Richter, Dept 3303, IBM LTC Boeblingen Germany
--
Vorsitzende des Aufsichtsrats: Martina Koederitz 
Geschäftsführung: Dirk Wittkopp
Sitz der Gesellschaft: Böblingen / Registergericht: Amtsgericht Stuttgart, HRB 
243294

Re: [PATCHv3] perf bpf: Fix endianness problem when loading parameters in prologue

[Thomas-Mich Richter]

On 08/15/2017 05:25 PM, Arnaldo Carvalho de Melo wrote:
> Em Tue, Aug 15, 2017 at 11:21:59AM +0200, Thomas Richter escreveu:
> 
> Ok, I'm applying this, the only missing bit was the following line,
> right at the start of the patch message body;
> 
> From: Wang Nan 
> 
> To state that the patch was wrote by Wang, the fact that you
> participated in it with some adjustment is implied by having you sign
> off the patch, ok?
> 
> - Arnaldo


Thanks Arnaldo,

will /hopefully) remember next time.

-- 
Thomas Richter, Dept 3303, IBM LTC Boeblingen Germany
--
Vorsitzende des Aufsichtsrats: Martina Koederitz 
Geschäftsführung: Dirk Wittkopp
Sitz der Gesellschaft: Böblingen / Registergericht: Amtsgericht Stuttgart, HRB 
243294

Re: [PATCH v4 14/20] mtd: nand: qcom: add command elements in BAM transaction

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.


Reviewed-by: Archit Taneja 

Thanks,
Archit



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index c0c140b..d17c466 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
  #include 
  #include 
  #include 
+#include 
  
  /* NANDc reg offsets */

  #define   NAND_FLASH_CMD  0x00
@@ -196,6 +197,7 @@
  /* Returns the actual register address for NAND_FLASH_DEV_* */
  #define nandc_dev_addr(nandc, reg) ((nandc)->props->flash_dev_offset + (reg))
  
+#define QPIC_PER_CW_CMD_ELEMENTS	32

  #define QPIC_PER_CW_CMD_SGL   32
  #define QPIC_PER_CW_DATA_SGL  8
  
@@ -215,8 +217,13 @@

  /*
   * This data type corresponds to the BAM transaction which will be used for 
all
   * NAND transfers.
+ * @bam_ce - the array of BAM command elements
   * @cmd_sgl - sgl for NAND BAM command pipe
   * @data_sgl - sgl for NAND BAM consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *for current sgl. It will be used for size calculation
+ *for current sgl
   * @cmd_sgl_pos - current index in command sgl.
   * @cmd_sgl_start - start index in command sgl.
   * @tx_sgl_pos - current index in data sgl for tx.
@@ -225,8 +232,11 @@
   * @rx_sgl_start - start index in data sgl for rx.
   */
  struct bam_transaction {
+   struct bam_cmd_element *bam_ce;
struct scatterlist *cmd_sgl;
struct scatterlist *data_sgl;
+   u32 bam_ce_pos;
+   u32 bam_ce_start;
u32 cmd_sgl_pos;
u32 cmd_sgl_start;
u32 tx_sgl_pos;
@@ -456,7 +466,8 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
  
  	bam_txn_size =

sizeof(*bam_txn) + num_cw *
-   ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+   ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+   (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
  
  	bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);

@@ -466,6 +477,10 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
bam_txn = bam_txn_buf;
bam_txn_buf += sizeof(*bam_txn);
  
+	bam_txn->bam_ce = bam_txn_buf;

+   bam_txn_buf +=
+   sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
bam_txn->cmd_sgl = bam_txn_buf;
bam_txn_buf +=
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
@@ -483,6 +498,8 @@ static void clear_bam_transaction(struct 
qcom_nand_controller *nandc)
if (!nandc->props->is_bam)
return;
  
+	bam_txn->bam_ce_pos = 0;

+   bam_txn->bam_ce_start = 0;
bam_txn->cmd_sgl_pos = 0;
bam_txn->cmd_sgl_start = 0;
bam_txn->tx_sgl_pos = 0;



--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v4 14/20] mtd: nand: qcom: add command elements in BAM transaction

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.


Reviewed-by: Archit Taneja 

Thanks,
Archit



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index c0c140b..d17c466 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
  #include 
  #include 
  #include 
+#include 
  
  /* NANDc reg offsets */

  #define   NAND_FLASH_CMD  0x00
@@ -196,6 +197,7 @@
  /* Returns the actual register address for NAND_FLASH_DEV_* */
  #define nandc_dev_addr(nandc, reg) ((nandc)->props->flash_dev_offset + (reg))
  
+#define QPIC_PER_CW_CMD_ELEMENTS	32

  #define QPIC_PER_CW_CMD_SGL   32
  #define QPIC_PER_CW_DATA_SGL  8
  
@@ -215,8 +217,13 @@

  /*
   * This data type corresponds to the BAM transaction which will be used for 
all
   * NAND transfers.
+ * @bam_ce - the array of BAM command elements
   * @cmd_sgl - sgl for NAND BAM command pipe
   * @data_sgl - sgl for NAND BAM consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *for current sgl. It will be used for size calculation
+ *for current sgl
   * @cmd_sgl_pos - current index in command sgl.
   * @cmd_sgl_start - start index in command sgl.
   * @tx_sgl_pos - current index in data sgl for tx.
@@ -225,8 +232,11 @@
   * @rx_sgl_start - start index in data sgl for rx.
   */
  struct bam_transaction {
+   struct bam_cmd_element *bam_ce;
struct scatterlist *cmd_sgl;
struct scatterlist *data_sgl;
+   u32 bam_ce_pos;
+   u32 bam_ce_start;
u32 cmd_sgl_pos;
u32 cmd_sgl_start;
u32 tx_sgl_pos;
@@ -456,7 +466,8 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
  
  	bam_txn_size =

sizeof(*bam_txn) + num_cw *
-   ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+   ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+   (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
  
  	bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);

@@ -466,6 +477,10 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
bam_txn = bam_txn_buf;
bam_txn_buf += sizeof(*bam_txn);
  
+	bam_txn->bam_ce = bam_txn_buf;

+   bam_txn_buf +=
+   sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
bam_txn->cmd_sgl = bam_txn_buf;
bam_txn_buf +=
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
@@ -483,6 +498,8 @@ static void clear_bam_transaction(struct 
qcom_nand_controller *nandc)
if (!nandc->props->is_bam)
return;
  
+	bam_txn->bam_ce_pos = 0;

+   bam_txn->bam_ce_start = 0;
bam_txn->cmd_sgl_pos = 0;
bam_txn->cmd_sgl_start = 0;
bam_txn->tx_sgl_pos = 0;



--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v4 13/20] mtd: nand: qcom: support for different DEV_CMD register offsets

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

The FLASH_DEV_CMD registers starting offset is not same in
different QPIC NAND controller versions. This patch adds
the starting offset in NAND controller properties and uses
the same for calculating the actual offset of these registers.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 22 --
  1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 85fbe00..c0c140b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -193,6 +193,9 @@
  ((size) << READ_LOCATION_SIZE) |\
  ((is_last) << READ_LOCATION_LAST))
  
+/* Returns the actual register address for NAND_FLASH_DEV_* */


There aren't any registers starting with NAND_FLASH_DEV_* in the registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:

Reviewed-by: Archit Taneja 

Thanks,
Archit



+#define nandc_dev_addr(nandc, reg) ((nandc)->props->flash_dev_offset + (reg))
+
  #define QPIC_PER_CW_CMD_SGL   32
  #define QPIC_PER_CW_DATA_SGL  8
  
@@ -426,10 +429,12 @@ struct qcom_nand_host {

   * among different NAND controllers.
   * @ecc_modes - ecc mode for NAND
   * @is_bam - whether NAND controller is using BAM
+ * @flash_dev_offset - NAND_FLASH_DEV_* registers start offset
   */
  struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
+   u32 flash_dev_offset;
  };
  
  /* Frees the BAM transaction memory */

@@ -844,6 +849,9 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, 
int first,
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
flow_control = true;
  
+	if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)

+   first = nandc_dev_addr(nandc, first);
+
size = num_regs * sizeof(u32);
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
@@ -881,11 +889,11 @@ static int write_reg_dma(struct qcom_nand_controller 
*nandc, int first,
if (first == NAND_EXEC_CMD)
flags |= NAND_BAM_NWD;
  
-	if (first == NAND_DEV_CMD1_RESTORE)

-   first = NAND_DEV_CMD1;
+   if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
+   first = nandc_dev_addr(nandc, NAND_DEV_CMD1);
  
-	if (first == NAND_DEV_CMD_VLD_RESTORE)

-   first = NAND_DEV_CMD_VLD;
+   if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
+   first = nandc_dev_addr(nandc, NAND_DEV_CMD_VLD);
  
  	size = num_regs * sizeof(u32);
  
@@ -2492,7 +2500,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  
  	/* kill onenand */

nandc_write(nandc, SFLASHC_BURST_CFG, 0);
-   nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
+   nandc_write(nandc, nandc_dev_addr(nandc, NAND_DEV_CMD_VLD),
+   NAND_DEV_CMD_VLD_VAL);
  
  	/* enable ADM or BAM DMA */

if (nandc->props->is_bam) {
@@ -2503,7 +2512,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller 
*nandc)
}
  
  	/* save the original values of these registers */

-   nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
+   nandc->cmd1 = nandc_read(nandc, nandc_dev_addr(nandc, NAND_DEV_CMD1));
nandc->vld = NAND_DEV_CMD_VLD_VAL;
  
  	return 0;

@@ -2752,6 +2761,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
  static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+   .flash_dev_offset = 0x0,
  };
  
  /*




--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v4 13/20] mtd: nand: qcom: support for different DEV_CMD register offsets

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

The FLASH_DEV_CMD registers starting offset is not same in
different QPIC NAND controller versions. This patch adds
the starting offset in NAND controller properties and uses
the same for calculating the actual offset of these registers.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 22 --
  1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 85fbe00..c0c140b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -193,6 +193,9 @@
  ((size) << READ_LOCATION_SIZE) |\
  ((is_last) << READ_LOCATION_LAST))
  
+/* Returns the actual register address for NAND_FLASH_DEV_* */


There aren't any registers starting with NAND_FLASH_DEV_* in the registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:

Reviewed-by: Archit Taneja 

Thanks,
Archit



+#define nandc_dev_addr(nandc, reg) ((nandc)->props->flash_dev_offset + (reg))
+
  #define QPIC_PER_CW_CMD_SGL   32
  #define QPIC_PER_CW_DATA_SGL  8
  
@@ -426,10 +429,12 @@ struct qcom_nand_host {

   * among different NAND controllers.
   * @ecc_modes - ecc mode for NAND
   * @is_bam - whether NAND controller is using BAM
+ * @flash_dev_offset - NAND_FLASH_DEV_* registers start offset
   */
  struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
+   u32 flash_dev_offset;
  };
  
  /* Frees the BAM transaction memory */

@@ -844,6 +849,9 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, 
int first,
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
flow_control = true;
  
+	if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)

+   first = nandc_dev_addr(nandc, first);
+
size = num_regs * sizeof(u32);
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
@@ -881,11 +889,11 @@ static int write_reg_dma(struct qcom_nand_controller 
*nandc, int first,
if (first == NAND_EXEC_CMD)
flags |= NAND_BAM_NWD;
  
-	if (first == NAND_DEV_CMD1_RESTORE)

-   first = NAND_DEV_CMD1;
+   if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
+   first = nandc_dev_addr(nandc, NAND_DEV_CMD1);
  
-	if (first == NAND_DEV_CMD_VLD_RESTORE)

-   first = NAND_DEV_CMD_VLD;
+   if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
+   first = nandc_dev_addr(nandc, NAND_DEV_CMD_VLD);
  
  	size = num_regs * sizeof(u32);
  
@@ -2492,7 +2500,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  
  	/* kill onenand */

nandc_write(nandc, SFLASHC_BURST_CFG, 0);
-   nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
+   nandc_write(nandc, nandc_dev_addr(nandc, NAND_DEV_CMD_VLD),
+   NAND_DEV_CMD_VLD_VAL);
  
  	/* enable ADM or BAM DMA */

if (nandc->props->is_bam) {
@@ -2503,7 +2512,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller 
*nandc)
}
  
  	/* save the original values of these registers */

-   nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
+   nandc->cmd1 = nandc_read(nandc, nandc_dev_addr(nandc, NAND_DEV_CMD1));
nandc->vld = NAND_DEV_CMD_VLD_VAL;
  
  	return 0;

@@ -2752,6 +2761,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
  static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+   .flash_dev_offset = 0x0,
  };
  
  /*




--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

linux-next: Tree for Aug 16

[Stephen Rothwell]

Hi all,

There will be no linux-next releases this coming Friday or Monday.

Changes since 20170815:

The pci tree gained a conflict against the net tree.

The net-next tree still had its build failure for which I reverted
a commit.

The akpm-current tree gained a build failure due to an interaction with
the drm-intel tree for which I applied a merge fix patch.

Non-merge commits (relative to Linus' tree): 6210
 6210 files changed, 241398 insertions(+), 119623 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig (with
CONFIG_BUILD_DOCSRC=n) for x86_64, a multi_v7_defconfig for arm and a
native build of tools/perf. After the final fixups (if any), I do an
x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And
finally, a simple boot test of the powerpc pseries_le_defconfig kernel
in qemu.

Below is a summary of the state of the merge.

I am currently merging 268 trees (counting Linus' and 41 trees of bug
fix patches pending for the current merge release).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (40c6d1b9e2fc Merge tag 'linux-kselftest-4.13-rc6-fixes' 
of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest)
Merging fixes/master (b4b8cbf679c4 Cavium CNN55XX: fix broken default Kconfig 
entry)
Merging kbuild-current/fixes (4e433fc4d1a9 fixdep: trivial: typo fix and 
correction)
Merging arc-current/for-curr (a8ec3ee861b6 arc: Mask individual IRQ lines 
during core INTC init)
Merging arm-current/fixes (1abd35023763 ARM: align .data section)
Merging m68k-current/for-linus (204a2be30a7a m68k: Remove ptrace_signal_deliver)
Merging metag-fixes/fixes (b884a190afce metag/usercopy: Add missing fixups)
Merging powerpc-fixes/fixes (96ea91e7b6ee powerpc/watchdog: add locking around 
init/exit functions)
Merging sparc/master (9157259d16a8 mm: add pmd_t initializer __pmd() to work 
around a GCC bug.)
Merging fscrypt-current/for-stable (42d97eb0ade3 fscrypt: fix renaming and 
linking special files)
Merging net/master (0a6f04184d3d Merge tag 
'wireless-drivers-for-davem-2017-08-15' of 
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers)
Merging ipsec/master (4ff0308f06da esp: Fix error handling on layer 2 xmit.)
Merging netfilter/master (9beceb54fa2c netfilter: x_tables: Fix use-after-free 
in ipt_do_table.)
Merging ipvs/master (f7fb77fc1235 netfilter: nft_compat: check extension hook 
mask only if set)
Merging wireless-drivers/master (e9bf53ab1ee3 brcmfmac: feature check for 
multi-scheduled scan fails on bcm4343x devices)
Merging mac80211/master (d7f13f745036 cfg80211: Validate frequencies nested in 
NL80211_ATTR_SCAN_FREQUENCIES)
Merging sound-current/for-linus (a8e800fe0f68 ALSA: usb-audio: Apply sample 
rate quirk to Sennheiser headset)
Merging pci-current/for-linus (8466489ef5ba xhci: Reset Renesas uPD72020x USB 
controller for 32-bit DMA issue)
Merging driver-core.current/driver-core-linus (ef954844c7ac Linux 4.13-rc5)
Merging tty.current/tty-linus (ef954844c7ac Linux 4.13-rc5)
Merging usb.current/usb-linus (ef954844c7ac Linux 4.13-rc5)
Merging usb-gadget-fixes/fixes (b7d44c36a6f6 usb: renesas_usbhs: gadget: fix 
unused-but-set-variable warning)
Merging usb-serial-fixes/usb-linus (fd1b8668af59 USB: serial: option: add 
D-Link DWM-222 device ID)
Merging usb-chipidea-fixes/ci-for-usb-stable (cbb22ebcfb99 usb: chipidea: core: 
check before accessing ci_role in ci_role_show)
Merging phy/fixes (5771a8c08880 Linux v4.13-rc1)
Merging staging.current/staging-linus (ef954844c7ac Linux 4.13-rc5)
Merging char-misc.current/char-misc-linus (ef954844c7ac Linux 4.13-rc5)
Merging input-current/for-linus (76988690402d Input: elan_i2c - Add antoher 
Lenovo ACPI ID for upcoming Lenovo NB)
Me

linux-next: Tree for Aug 16

[Stephen Rothwell]

Hi all,

There will be no linux-next releases this coming Friday or Monday.

Changes since 20170815:

The pci tree gained a conflict against the net tree.

The net-next tree still had its build failure for which I reverted
a commit.

The akpm-current tree gained a build failure due to an interaction with
the drm-intel tree for which I applied a merge fix patch.

Non-merge commits (relative to Linus' tree): 6210
 6210 files changed, 241398 insertions(+), 119623 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig (with
CONFIG_BUILD_DOCSRC=n) for x86_64, a multi_v7_defconfig for arm and a
native build of tools/perf. After the final fixups (if any), I do an
x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And
finally, a simple boot test of the powerpc pseries_le_defconfig kernel
in qemu.

Below is a summary of the state of the merge.

I am currently merging 268 trees (counting Linus' and 41 trees of bug
fix patches pending for the current merge release).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (40c6d1b9e2fc Merge tag 'linux-kselftest-4.13-rc6-fixes' 
of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest)
Merging fixes/master (b4b8cbf679c4 Cavium CNN55XX: fix broken default Kconfig 
entry)
Merging kbuild-current/fixes (4e433fc4d1a9 fixdep: trivial: typo fix and 
correction)
Merging arc-current/for-curr (a8ec3ee861b6 arc: Mask individual IRQ lines 
during core INTC init)
Merging arm-current/fixes (1abd35023763 ARM: align .data section)
Merging m68k-current/for-linus (204a2be30a7a m68k: Remove ptrace_signal_deliver)
Merging metag-fixes/fixes (b884a190afce metag/usercopy: Add missing fixups)
Merging powerpc-fixes/fixes (96ea91e7b6ee powerpc/watchdog: add locking around 
init/exit functions)
Merging sparc/master (9157259d16a8 mm: add pmd_t initializer __pmd() to work 
around a GCC bug.)
Merging fscrypt-current/for-stable (42d97eb0ade3 fscrypt: fix renaming and 
linking special files)
Merging net/master (0a6f04184d3d Merge tag 
'wireless-drivers-for-davem-2017-08-15' of 
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers)
Merging ipsec/master (4ff0308f06da esp: Fix error handling on layer 2 xmit.)
Merging netfilter/master (9beceb54fa2c netfilter: x_tables: Fix use-after-free 
in ipt_do_table.)
Merging ipvs/master (f7fb77fc1235 netfilter: nft_compat: check extension hook 
mask only if set)
Merging wireless-drivers/master (e9bf53ab1ee3 brcmfmac: feature check for 
multi-scheduled scan fails on bcm4343x devices)
Merging mac80211/master (d7f13f745036 cfg80211: Validate frequencies nested in 
NL80211_ATTR_SCAN_FREQUENCIES)
Merging sound-current/for-linus (a8e800fe0f68 ALSA: usb-audio: Apply sample 
rate quirk to Sennheiser headset)
Merging pci-current/for-linus (8466489ef5ba xhci: Reset Renesas uPD72020x USB 
controller for 32-bit DMA issue)
Merging driver-core.current/driver-core-linus (ef954844c7ac Linux 4.13-rc5)
Merging tty.current/tty-linus (ef954844c7ac Linux 4.13-rc5)
Merging usb.current/usb-linus (ef954844c7ac Linux 4.13-rc5)
Merging usb-gadget-fixes/fixes (b7d44c36a6f6 usb: renesas_usbhs: gadget: fix 
unused-but-set-variable warning)
Merging usb-serial-fixes/usb-linus (fd1b8668af59 USB: serial: option: add 
D-Link DWM-222 device ID)
Merging usb-chipidea-fixes/ci-for-usb-stable (cbb22ebcfb99 usb: chipidea: core: 
check before accessing ci_role in ci_role_show)
Merging phy/fixes (5771a8c08880 Linux v4.13-rc1)
Merging staging.current/staging-linus (ef954844c7ac Linux 4.13-rc5)
Merging char-misc.current/char-misc-linus (ef954844c7ac Linux 4.13-rc5)
Merging input-current/for-linus (76988690402d Input: elan_i2c - Add antoher 
Lenovo ACPI ID for upcoming Lenovo NB)
Me

[PATCH] Input: i8042: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/input/serio/i8042-x86ia64io.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/serio/i8042-x86ia64io.h 
b/drivers/input/serio/i8042-x86ia64io.h
index f932a83..ae81e57 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -927,7 +927,7 @@ static int i8042_pnp_aux_probe(struct pnp_dev *dev, const 
struct pnp_device_id *
return 0;
 }
 
-static struct pnp_device_id pnp_kbd_devids[] = {
+static const struct pnp_device_id pnp_kbd_devids[] = {
{ .id = "PNP0300", .driver_data = 0 },
{ .id = "PNP0301", .driver_data = 0 },
{ .id = "PNP0302", .driver_data = 0 },
@@ -957,7 +957,7 @@ static struct pnp_driver i8042_pnp_kbd_driver = {
},
 };
 
-static struct pnp_device_id pnp_aux_devids[] = {
+static const struct pnp_device_id pnp_aux_devids[] = {
{ .id = "AUI0200", .driver_data = 0 },
{ .id = "FJC6000", .driver_data = 0 },
{ .id = "FJC6001", .driver_data = 0 },
-- 
2.7.4

[PATCH] Input: i8042: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/input/serio/i8042-x86ia64io.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/serio/i8042-x86ia64io.h 
b/drivers/input/serio/i8042-x86ia64io.h
index f932a83..ae81e57 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -927,7 +927,7 @@ static int i8042_pnp_aux_probe(struct pnp_dev *dev, const 
struct pnp_device_id *
return 0;
 }
 
-static struct pnp_device_id pnp_kbd_devids[] = {
+static const struct pnp_device_id pnp_kbd_devids[] = {
{ .id = "PNP0300", .driver_data = 0 },
{ .id = "PNP0301", .driver_data = 0 },
{ .id = "PNP0302", .driver_data = 0 },
@@ -957,7 +957,7 @@ static struct pnp_driver i8042_pnp_kbd_driver = {
},
 };
 
-static struct pnp_device_id pnp_aux_devids[] = {
+static const struct pnp_device_id pnp_aux_devids[] = {
{ .id = "AUI0200", .driver_data = 0 },
{ .id = "FJC6000", .driver_data = 0 },
{ .id = "FJC6001", .driver_data = 0 },
-- 
2.7.4

Re: [PATCH v4 12/20] mtd: nand: qcom: QPIC data descriptors handling

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

1. Add the data descriptor preparation function which will be used
only by BAM DMA for forming the data SGL’s
2. Add clear BAM transaction and call it before every new request
3. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.


Reviewed-by: Archit Taneja 

Thanks,
Archit



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 76 +++
  1 file changed, 76 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index ae873d3..85fbe00 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -470,6 +470,27 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
return bam_txn;
  }
  
+/* Clears the BAM transaction indexes */

+static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   if (!nandc->props->is_bam)
+   return;
+
+   bam_txn->cmd_sgl_pos = 0;
+   bam_txn->cmd_sgl_start = 0;
+   bam_txn->tx_sgl_pos = 0;
+   bam_txn->tx_sgl_start = 0;
+   bam_txn->rx_sgl_pos = 0;
+   bam_txn->rx_sgl_start = 0;
+
+   sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_CMD_SGL);
+   sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_DATA_SGL);
+}
+
  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
  {
return container_of(chip, struct qcom_nand_host, chip);
@@ -701,6 +722,41 @@ static int prepare_bam_async_desc(struct 
qcom_nand_controller *nandc,
return 0;
  }
  
+/*

+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool 
read,
+ const void *vaddr,
+ int size, unsigned int flags)
+{
+   int ret;
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   if (read) {
+   sg_set_buf(_txn->data_sgl[bam_txn->rx_sgl_pos],
+  vaddr, size);
+   bam_txn->rx_sgl_pos++;
+   } else {
+   sg_set_buf(_txn->data_sgl[bam_txn->tx_sgl_pos],
+  vaddr, size);
+   bam_txn->tx_sgl_pos++;
+
+   /*
+* BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+* is not set, form the DMA descriptor
+*/
+   if (!(flags & NAND_BAM_NO_EOT)) {
+   ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+DMA_PREP_INTERRUPT);
+   if (ret)
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
  static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
 int reg_off, const void *vaddr, int size,
 bool flow_control)
@@ -848,6 +904,9 @@ static int write_reg_dma(struct qcom_nand_controller 
*nandc, int first,
  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 const u8 *vaddr, int size, unsigned int flags)
  {
+   if (nandc->props->is_bam)
+   return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
  }
  
@@ -862,6 +921,9 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,

  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  const u8 *vaddr, int size, unsigned int flags)
  {
+   if (nandc->props->is_bam)
+   return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
  }
  
@@ -1149,6 +1211,10 @@ static void pre_command(struct qcom_nand_host *host, int command)

host->last_command = command;
  
  	clear_read_regs(nandc);

+
+   if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
+   command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
+   clear_bam_transaction(nandc);
  }
  
  /*

@@ -1553,6 +1619,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, 
struct nand_chip *chip,
data_buf = buf;
oob_buf = oob_required ? chip->oob_poi : NULL;
  
+	clear_bam_transaction(nandc);

ret = read_page_ecc(host, data_buf, oob_buf);
if (ret) {
dev_err(nandc->dev, "failure to read page\n");
@@ -1578,6 +1645,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_buf = chip->oob_poi;
  
  	host->use_ecc = false;

+
+   

Re: [PATCH v4 12/20] mtd: nand: qcom: QPIC data descriptors handling

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

1. Add the data descriptor preparation function which will be used
only by BAM DMA for forming the data SGL’s
2. Add clear BAM transaction and call it before every new request
3. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.


Reviewed-by: Archit Taneja 

Thanks,
Archit



Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 76 +++
  1 file changed, 76 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index ae873d3..85fbe00 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -470,6 +470,27 @@ static void free_bam_transaction(struct 
qcom_nand_controller *nandc)
return bam_txn;
  }
  
+/* Clears the BAM transaction indexes */

+static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   if (!nandc->props->is_bam)
+   return;
+
+   bam_txn->cmd_sgl_pos = 0;
+   bam_txn->cmd_sgl_start = 0;
+   bam_txn->tx_sgl_pos = 0;
+   bam_txn->tx_sgl_start = 0;
+   bam_txn->rx_sgl_pos = 0;
+   bam_txn->rx_sgl_start = 0;
+
+   sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_CMD_SGL);
+   sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_DATA_SGL);
+}
+
  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
  {
return container_of(chip, struct qcom_nand_host, chip);
@@ -701,6 +722,41 @@ static int prepare_bam_async_desc(struct 
qcom_nand_controller *nandc,
return 0;
  }
  
+/*

+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool 
read,
+ const void *vaddr,
+ int size, unsigned int flags)
+{
+   int ret;
+   struct bam_transaction *bam_txn = nandc->bam_txn;
+
+   if (read) {
+   sg_set_buf(_txn->data_sgl[bam_txn->rx_sgl_pos],
+  vaddr, size);
+   bam_txn->rx_sgl_pos++;
+   } else {
+   sg_set_buf(_txn->data_sgl[bam_txn->tx_sgl_pos],
+  vaddr, size);
+   bam_txn->tx_sgl_pos++;
+
+   /*
+* BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+* is not set, form the DMA descriptor
+*/
+   if (!(flags & NAND_BAM_NO_EOT)) {
+   ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+DMA_PREP_INTERRUPT);
+   if (ret)
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
  static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
 int reg_off, const void *vaddr, int size,
 bool flow_control)
@@ -848,6 +904,9 @@ static int write_reg_dma(struct qcom_nand_controller 
*nandc, int first,
  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 const u8 *vaddr, int size, unsigned int flags)
  {
+   if (nandc->props->is_bam)
+   return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
  }
  
@@ -862,6 +921,9 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,

  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  const u8 *vaddr, int size, unsigned int flags)
  {
+   if (nandc->props->is_bam)
+   return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
  }
  
@@ -1149,6 +1211,10 @@ static void pre_command(struct qcom_nand_host *host, int command)

host->last_command = command;
  
  	clear_read_regs(nandc);

+
+   if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
+   command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
+   clear_bam_transaction(nandc);
  }
  
  /*

@@ -1553,6 +1619,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, 
struct nand_chip *chip,
data_buf = buf;
oob_buf = oob_required ? chip->oob_poi : NULL;
  
+	clear_bam_transaction(nandc);

ret = read_page_ecc(host, data_buf, oob_buf);
if (ret) {
dev_err(nandc->dev, "failure to read page\n");
@@ -1578,6 +1645,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_buf = chip->oob_poi;
  
  	host->use_ecc = false;

+
+   clear_bam_transaction(nandc);
update_rw_regs(host, 

[PATCH] sg: protect against races between mmap() and SG_SET_RESERVED_SIZE

[Todd Poynor]

Take f_mutex around mmap() processing to protect against races with
the SG_SET_RESERVED_SIZE ioctl.  Ensure the reserve buffer length
remains consistent during the mapping operation, and set the
"mmap called" flag to prevent further changes to the reserved buffer
size as an atomic operation with the mapping.

Signed-off-by: Todd Poynor 
---
 drivers/scsi/sg.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index 3a44b4bc872b..a20718e9f1f4 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1233,6 +1233,7 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
unsigned long req_sz, len, sa;
Sg_scatter_hold *rsv_schp;
int k, length;
+int ret = 0;
 
if ((!filp) || (!vma) || (!(sfp = (Sg_fd *) filp->private_data)))
return -ENXIO;
@@ -1243,8 +1244,11 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
if (vma->vm_pgoff)
return -EINVAL; /* want no offset */
rsv_schp = >reserve;
-   if (req_sz > rsv_schp->bufflen)
-   return -ENOMEM; /* cannot map more than reserved buffer */
+   mutex_lock(>f_mutex);
+   if (req_sz > rsv_schp->bufflen) {
+   ret = -ENOMEM;  /* cannot map more than reserved buffer */
+   goto out;
+   }
 
sa = vma->vm_start;
length = 1 << (PAGE_SHIFT + rsv_schp->page_order);
@@ -1258,7 +1262,9 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
vma->vm_private_data = sfp;
vma->vm_ops = _mmap_vm_ops;
-   return 0;
+out:
+   mutex_unlock(>f_mutex);
+   return ret;
 }
 
 static void
-- 
2.14.1.480.gb18f417b89-goog

[PATCH] sg: protect against races between mmap() and SG_SET_RESERVED_SIZE

[Todd Poynor]

Take f_mutex around mmap() processing to protect against races with
the SG_SET_RESERVED_SIZE ioctl.  Ensure the reserve buffer length
remains consistent during the mapping operation, and set the
"mmap called" flag to prevent further changes to the reserved buffer
size as an atomic operation with the mapping.

Signed-off-by: Todd Poynor 
---
 drivers/scsi/sg.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index 3a44b4bc872b..a20718e9f1f4 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1233,6 +1233,7 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
unsigned long req_sz, len, sa;
Sg_scatter_hold *rsv_schp;
int k, length;
+int ret = 0;
 
if ((!filp) || (!vma) || (!(sfp = (Sg_fd *) filp->private_data)))
return -ENXIO;
@@ -1243,8 +1244,11 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
if (vma->vm_pgoff)
return -EINVAL; /* want no offset */
rsv_schp = >reserve;
-   if (req_sz > rsv_schp->bufflen)
-   return -ENOMEM; /* cannot map more than reserved buffer */
+   mutex_lock(>f_mutex);
+   if (req_sz > rsv_schp->bufflen) {
+   ret = -ENOMEM;  /* cannot map more than reserved buffer */
+   goto out;
+   }
 
sa = vma->vm_start;
length = 1 << (PAGE_SHIFT + rsv_schp->page_order);
@@ -1258,7 +1262,9 @@ sg_mmap(struct file *filp, struct vm_area_struct *vma)
vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
vma->vm_private_data = sfp;
vma->vm_ops = _mmap_vm_ops;
-   return 0;
+out:
+   mutex_unlock(>f_mutex);
+   return ret;
 }
 
 static void
-- 
2.14.1.480.gb18f417b89-goog

Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Boqun Feng]

On Wed, Aug 16, 2017 at 01:37:46PM +0900, Byungchul Park wrote:
> On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > On Wed, Aug 16, 2017 at 09:16:37AM +0900, Byungchul Park wrote:
> > > On Tue, Aug 15, 2017 at 10:20:20AM +0200, Ingo Molnar wrote:
> > > > 
> > > > So with the latest fixes there's a new lockdep warning on one of my 
> > > > testboxes:
> > > > 
> > > > [   11.322487] EXT4-fs (sda2): mounted filesystem with ordered data 
> > > > mode. Opts: (null)
> > > > 
> > > > [   11.495661] ==
> > > > [   11.502093] WARNING: possible circular locking dependency detected
> > > > [   11.508507] 4.13.0-rc5-00497-g73135c58-dirty #1 Not tainted
> > > > [   11.514313] --
> > > > [   11.520725] umount/533 is trying to acquire lock:
> > > > [   11.525657]  ((complete)>done){+.+.}, at: [] 
> > > > flush_work+0x213/0x2f0
> > > > [   11.534411] 
> > > >but task is already holding lock:
> > > > [   11.540661]  (lock#3){+.+.}, at: [] 
> > > > lru_add_drain_all_cpuslocked+0x3d/0x190
> > > > [   11.549613] 
> > > >which lock already depends on the new lock.
> > > > 
> > > > The full splat is below. The kernel config is nothing fancy - distro 
> > > > derived, 
> > > > pretty close to defconfig, with lockdep enabled.
> > > 
> > > I see...
> > > 
> > > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be 
> > > released
> > > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > > Task   C : acquired of lock#3 -> wait for completion of barr->done
> > 
> > >From the stack trace below, this barr->done is for flush_work() in
> > lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> > 
> > > Worker D : wait for wfc.work to be released -> will complete barr->done
> > 
> > and this barr->done is for work "wfc.work".
> 
> I think it can be the same instance. wait_for_completion() in flush_work()
> e.g. at task C in my example, waits for completion which we expect to be
> done by a worker e.g. worker D in my example.
> 
> I think the problem is caused by a write-acquisition of wfc.work in
> process_one_work(). The acquisition of wfc.work should be reenterable,
> that is, read-acquisition, shouldn't it?
> 

The only thing is that wfc.work is not a real and please see code in
flush_work(). And if a task C do a flush_work() for "wfc.work" with
lock#3 held, it needs to "acquire" wfc.work before it
wait_for_completion(), which is already a deadlock case:

lock#3 -> wfc.work -> cpu_hotplug_lock -+
  ^ |
  | |
  +-+

, without crossrelease enabled. So the task C didn't flush work wfc.work
in the previous case, which implies barr->done in Task C and Worker D
are not the same instance.

Make sense?

Regards,
Boqun

> I might be wrong... Please fix me if so.
> 
> Thank you,
> Byungchul
> 
> > So those two barr->done could not be the same instance, IIUC. Therefore
> > the deadlock case is not possible.
> > 
> > The problem here is all barr->done instances are initialized at
> > insert_wq_barrier() and they belongs to the same lock class, to fix
> > this, we need to differ barr->done with different lock classes based on
> > the corresponding works.
> > 
> > How about the this(only compilation test):
> > 
> > ->8
> > diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> > index e86733a8b344..d14067942088 100644
> > --- a/kernel/workqueue.c
> > +++ b/kernel/workqueue.c
> > @@ -2431,6 +2431,27 @@ struct wq_barrier {
> > struct task_struct  *task;  /* purely informational */
> >  };
> >  
> > +#ifdef CONFIG_LOCKDEP_COMPLETE
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> > \
> > +  "(complete)" #barr,  
> > \
> > +  (target)->lockdep_map.key, 1);   
> > \
> > +   __init_completion(>done); 
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#else
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  

Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Boqun Feng]

On Wed, Aug 16, 2017 at 01:37:46PM +0900, Byungchul Park wrote:
> On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > On Wed, Aug 16, 2017 at 09:16:37AM +0900, Byungchul Park wrote:
> > > On Tue, Aug 15, 2017 at 10:20:20AM +0200, Ingo Molnar wrote:
> > > > 
> > > > So with the latest fixes there's a new lockdep warning on one of my 
> > > > testboxes:
> > > > 
> > > > [   11.322487] EXT4-fs (sda2): mounted filesystem with ordered data 
> > > > mode. Opts: (null)
> > > > 
> > > > [   11.495661] ==
> > > > [   11.502093] WARNING: possible circular locking dependency detected
> > > > [   11.508507] 4.13.0-rc5-00497-g73135c58-dirty #1 Not tainted
> > > > [   11.514313] --
> > > > [   11.520725] umount/533 is trying to acquire lock:
> > > > [   11.525657]  ((complete)>done){+.+.}, at: [] 
> > > > flush_work+0x213/0x2f0
> > > > [   11.534411] 
> > > >but task is already holding lock:
> > > > [   11.540661]  (lock#3){+.+.}, at: [] 
> > > > lru_add_drain_all_cpuslocked+0x3d/0x190
> > > > [   11.549613] 
> > > >which lock already depends on the new lock.
> > > > 
> > > > The full splat is below. The kernel config is nothing fancy - distro 
> > > > derived, 
> > > > pretty close to defconfig, with lockdep enabled.
> > > 
> > > I see...
> > > 
> > > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be 
> > > released
> > > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > > Task   C : acquired of lock#3 -> wait for completion of barr->done
> > 
> > >From the stack trace below, this barr->done is for flush_work() in
> > lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> > 
> > > Worker D : wait for wfc.work to be released -> will complete barr->done
> > 
> > and this barr->done is for work "wfc.work".
> 
> I think it can be the same instance. wait_for_completion() in flush_work()
> e.g. at task C in my example, waits for completion which we expect to be
> done by a worker e.g. worker D in my example.
> 
> I think the problem is caused by a write-acquisition of wfc.work in
> process_one_work(). The acquisition of wfc.work should be reenterable,
> that is, read-acquisition, shouldn't it?
> 

The only thing is that wfc.work is not a real and please see code in
flush_work(). And if a task C do a flush_work() for "wfc.work" with
lock#3 held, it needs to "acquire" wfc.work before it
wait_for_completion(), which is already a deadlock case:

lock#3 -> wfc.work -> cpu_hotplug_lock -+
  ^ |
  | |
  +-+

, without crossrelease enabled. So the task C didn't flush work wfc.work
in the previous case, which implies barr->done in Task C and Worker D
are not the same instance.

Make sense?

Regards,
Boqun

> I might be wrong... Please fix me if so.
> 
> Thank you,
> Byungchul
> 
> > So those two barr->done could not be the same instance, IIUC. Therefore
> > the deadlock case is not possible.
> > 
> > The problem here is all barr->done instances are initialized at
> > insert_wq_barrier() and they belongs to the same lock class, to fix
> > this, we need to differ barr->done with different lock classes based on
> > the corresponding works.
> > 
> > How about the this(only compilation test):
> > 
> > ->8
> > diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> > index e86733a8b344..d14067942088 100644
> > --- a/kernel/workqueue.c
> > +++ b/kernel/workqueue.c
> > @@ -2431,6 +2431,27 @@ struct wq_barrier {
> > struct task_struct  *task;  /* purely informational */
> >  };
> >  
> > +#ifdef CONFIG_LOCKDEP_COMPLETE
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> > \
> > +   lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> > \
> > +  "(complete)" #barr,  
> > \
> > +  (target)->lockdep_map.key, 1);   
> > \
> > +   __init_completion(>done); 
> > \
> > +   barr->task = current;   
> > \
> > +} while (0)
> > +#else
> > +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target)   
> > \
> > +do {   
> > \
> > +   INIT_WORK_ONSTACK(&(barr)->work, func); 
> > \
> > +   __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  

[PATCH 1/2] cpufreq: dt-platdev: Automatically create cpufreq device with OPP v2

[Viresh Kumar]

The initial idea of creating the cpufreq-dt-platdev.c file was to keep a
list of platforms that use the "operating-points" (V1) bindings and
create cpufreq device for them only, as we weren't sure which platforms
would want the device to get created automatically as some had their own
cpufreq drivers as well, or wanted to initialize cpufreq after doing
some stuff from platform code.

But that wasn't the case with platforms using "operating-points-v2"
property. We wanted the device to get created automatically without the
need of adding them to the whitelist. Though, we will still have some
exceptions where we don't want to create the device automatically.

Rename the earlier platform list as *whitelist* and create a new
*blacklist* as well.

The cpufreq-dt device will get created if:
- The platform is there in the whitelist OR
- The platform has "operating-points-v2" property in CPU0's DT node and
  isn't part of the blacklist .

Reported-by: Geert Uytterhoeven 
Signed-off-by: Viresh Kumar 
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 45 
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index bcee384b3251..061b468512a2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -9,11 +9,16 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include "cpufreq-dt.h"
 
-static const struct of_device_id machines[] __initconst = {
+/*
+ * Machines for which the cpufreq device is *always* created, mostly used for
+ * platforms using "operating-points" (V1) property.
+ */
+static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun4i-a10", },
{ .compatible = "allwinner,sun5i-a10s", },
{ .compatible = "allwinner,sun5i-a13", },
@@ -101,21 +106,51 @@ static const struct of_device_id machines[] __initconst = 
{
{ }
 };
 
+/*
+ * Machines for which the cpufreq device is *not* created, mostly used for
+ * platforms using "operating-points-v2" property.
+ */
+static const struct of_device_id blacklist[] __initconst = {
+   { }
+};
+
+static bool __init cpu0_node_has_opp_v2_prop(void)
+{
+   struct device_node *np = of_cpu_device_node_get(0);
+   bool ret = false;
+
+   if (of_get_property(np, "operating-points-v2", NULL))
+   ret = true;
+
+   of_node_put(np);
+   return ret;
+}
+
 static int __init cpufreq_dt_platdev_init(void)
 {
struct device_node *np = of_find_node_by_path("/");
const struct of_device_id *match;
+   const void *data = NULL;
 
if (!np)
return -ENODEV;
 
-   match = of_match_node(machines, np);
+   match = of_match_node(whitelist, np);
+   if (match) {
+   data = match->data;
+   goto create_pdev;
+   }
+
+   if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
+   goto create_pdev;
+
of_node_put(np);
-   if (!match)
-   return -ENODEV;
+   return -ENODEV;
 
+create_pdev:
+   of_node_put(np);
return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
-  -1, match->data,
+  -1, data,
   sizeof(struct cpufreq_dt_platform_data)));
 }
 device_initcall(cpufreq_dt_platdev_init);
-- 
2.7.4

[PATCH 2/2] cpufreq: dt-platdev: Drop few entries from whitelist

[Viresh Kumar]

Drop few ARM (32 and 64 bit) platforms from the whitelist which always
use "operating-points-v2" property from their DT. They should continue
to work after this patch.

Tested on Hikey platform (only the "hisilicon,hi6220" entry).

Signed-off-by: Viresh Kumar 
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 061b468512a2..45f2ec3b7f7a 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -27,7 +27,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun6i-a31s", },
{ .compatible = "allwinner,sun7i-a20", },
{ .compatible = "allwinner,sun8i-a23", },
-   { .compatible = "allwinner,sun8i-a33", },
{ .compatible = "allwinner,sun8i-a83t", },
{ .compatible = "allwinner,sun8i-h3", },
 
@@ -37,7 +36,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "arm,integrator-cp", },
 
{ .compatible = "hisilicon,hi3660", },
-   { .compatible = "hisilicon,hi6220", },
 
{ .compatible = "fsl,imx27", },
{ .compatible = "fsl,imx51", },
@@ -51,11 +49,8 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "samsung,exynos3250", },
{ .compatible = "samsung,exynos4210", },
{ .compatible = "samsung,exynos4212", },
-   { .compatible = "samsung,exynos4412", },
{ .compatible = "samsung,exynos5250", },
 #ifndef CONFIG_BL_SWITCHER
-   { .compatible = "samsung,exynos5420", },
-   { .compatible = "samsung,exynos5433", },
{ .compatible = "samsung,exynos5800", },
 #endif
 
@@ -87,11 +82,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "rockchip,rk3368", },
{ .compatible = "rockchip,rk3399", },
 
-   { .compatible = "socionext,uniphier-pro5", },
-   { .compatible = "socionext,uniphier-pxs2", },
{ .compatible = "socionext,uniphier-ld6b", },
-   { .compatible = "socionext,uniphier-ld11", },
-   { .compatible = "socionext,uniphier-ld20", },
 
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap3", },
@@ -101,8 +92,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "xlnx,zynq-7000", },
{ .compatible = "xlnx,zynqmp", },
 
-   { .compatible = "zte,zx296718", },
-
{ }
 };
 
-- 
2.7.4

[PATCH 1/2] cpufreq: dt-platdev: Automatically create cpufreq device with OPP v2

[Viresh Kumar]

The initial idea of creating the cpufreq-dt-platdev.c file was to keep a
list of platforms that use the "operating-points" (V1) bindings and
create cpufreq device for them only, as we weren't sure which platforms
would want the device to get created automatically as some had their own
cpufreq drivers as well, or wanted to initialize cpufreq after doing
some stuff from platform code.

But that wasn't the case with platforms using "operating-points-v2"
property. We wanted the device to get created automatically without the
need of adding them to the whitelist. Though, we will still have some
exceptions where we don't want to create the device automatically.

Rename the earlier platform list as *whitelist* and create a new
*blacklist* as well.

The cpufreq-dt device will get created if:
- The platform is there in the whitelist OR
- The platform has "operating-points-v2" property in CPU0's DT node and
  isn't part of the blacklist .

Reported-by: Geert Uytterhoeven 
Signed-off-by: Viresh Kumar 
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 45 
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index bcee384b3251..061b468512a2 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -9,11 +9,16 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include "cpufreq-dt.h"
 
-static const struct of_device_id machines[] __initconst = {
+/*
+ * Machines for which the cpufreq device is *always* created, mostly used for
+ * platforms using "operating-points" (V1) property.
+ */
+static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun4i-a10", },
{ .compatible = "allwinner,sun5i-a10s", },
{ .compatible = "allwinner,sun5i-a13", },
@@ -101,21 +106,51 @@ static const struct of_device_id machines[] __initconst = 
{
{ }
 };
 
+/*
+ * Machines for which the cpufreq device is *not* created, mostly used for
+ * platforms using "operating-points-v2" property.
+ */
+static const struct of_device_id blacklist[] __initconst = {
+   { }
+};
+
+static bool __init cpu0_node_has_opp_v2_prop(void)
+{
+   struct device_node *np = of_cpu_device_node_get(0);
+   bool ret = false;
+
+   if (of_get_property(np, "operating-points-v2", NULL))
+   ret = true;
+
+   of_node_put(np);
+   return ret;
+}
+
 static int __init cpufreq_dt_platdev_init(void)
 {
struct device_node *np = of_find_node_by_path("/");
const struct of_device_id *match;
+   const void *data = NULL;
 
if (!np)
return -ENODEV;
 
-   match = of_match_node(machines, np);
+   match = of_match_node(whitelist, np);
+   if (match) {
+   data = match->data;
+   goto create_pdev;
+   }
+
+   if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
+   goto create_pdev;
+
of_node_put(np);
-   if (!match)
-   return -ENODEV;
+   return -ENODEV;
 
+create_pdev:
+   of_node_put(np);
return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
-  -1, match->data,
+  -1, data,
   sizeof(struct cpufreq_dt_platform_data)));
 }
 device_initcall(cpufreq_dt_platdev_init);
-- 
2.7.4

[PATCH 2/2] cpufreq: dt-platdev: Drop few entries from whitelist

[Viresh Kumar]

Drop few ARM (32 and 64 bit) platforms from the whitelist which always
use "operating-points-v2" property from their DT. They should continue
to work after this patch.

Tested on Hikey platform (only the "hisilicon,hi6220" entry).

Signed-off-by: Viresh Kumar 
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 061b468512a2..45f2ec3b7f7a 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -27,7 +27,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun6i-a31s", },
{ .compatible = "allwinner,sun7i-a20", },
{ .compatible = "allwinner,sun8i-a23", },
-   { .compatible = "allwinner,sun8i-a33", },
{ .compatible = "allwinner,sun8i-a83t", },
{ .compatible = "allwinner,sun8i-h3", },
 
@@ -37,7 +36,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "arm,integrator-cp", },
 
{ .compatible = "hisilicon,hi3660", },
-   { .compatible = "hisilicon,hi6220", },
 
{ .compatible = "fsl,imx27", },
{ .compatible = "fsl,imx51", },
@@ -51,11 +49,8 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "samsung,exynos3250", },
{ .compatible = "samsung,exynos4210", },
{ .compatible = "samsung,exynos4212", },
-   { .compatible = "samsung,exynos4412", },
{ .compatible = "samsung,exynos5250", },
 #ifndef CONFIG_BL_SWITCHER
-   { .compatible = "samsung,exynos5420", },
-   { .compatible = "samsung,exynos5433", },
{ .compatible = "samsung,exynos5800", },
 #endif
 
@@ -87,11 +82,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "rockchip,rk3368", },
{ .compatible = "rockchip,rk3399", },
 
-   { .compatible = "socionext,uniphier-pro5", },
-   { .compatible = "socionext,uniphier-pxs2", },
{ .compatible = "socionext,uniphier-ld6b", },
-   { .compatible = "socionext,uniphier-ld11", },
-   { .compatible = "socionext,uniphier-ld20", },
 
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap3", },
@@ -101,8 +92,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "xlnx,zynq-7000", },
{ .compatible = "xlnx,zynqmp", },
 
-   { .compatible = "zte,zx296718", },
-
{ }
 };
 
-- 
2.7.4

Re: [PATCH] scsi: cxlflash: Fix an error handling path in 'cxlflash_disk_attach()'

[Andrew Donnellan]

On 16/08/17 06:18, Christophe JAILLET wrote:

'rc' is known to be 0 at this point.
If 'create_context()' fails, returns -ENOMEM instead of 0 which means
success.

Signed-off-by: Christophe JAILLET 


ENOMEM seems right here.

Reviewed-by: Andrew Donnellan 


---
  drivers/scsi/cxlflash/superpipe.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/scsi/cxlflash/superpipe.c 
b/drivers/scsi/cxlflash/superpipe.c
index ad0f9968ccfb..08da593cb2f6 100644
--- a/drivers/scsi/cxlflash/superpipe.c
+++ b/drivers/scsi/cxlflash/superpipe.c
@@ -1390,6 +1390,7 @@ static int cxlflash_disk_attach(struct scsi_device *sdev,
if (unlikely(!ctxi)) {
dev_err(dev, "%s: Failed to create context ctxid=%d\n",
__func__, ctxid);
+   rc = -ENOMEM;
goto err;
}
  



--
Andrew Donnellan  OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com  IBM Australia Limited

Re: [PATCH] scsi: cxlflash: Fix an error handling path in 'cxlflash_disk_attach()'

[Andrew Donnellan]

On 16/08/17 06:18, Christophe JAILLET wrote:

'rc' is known to be 0 at this point.
If 'create_context()' fails, returns -ENOMEM instead of 0 which means
success.

Signed-off-by: Christophe JAILLET 


ENOMEM seems right here.

Reviewed-by: Andrew Donnellan 


---
  drivers/scsi/cxlflash/superpipe.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/scsi/cxlflash/superpipe.c 
b/drivers/scsi/cxlflash/superpipe.c
index ad0f9968ccfb..08da593cb2f6 100644
--- a/drivers/scsi/cxlflash/superpipe.c
+++ b/drivers/scsi/cxlflash/superpipe.c
@@ -1390,6 +1390,7 @@ static int cxlflash_disk_attach(struct scsi_device *sdev,
if (unlikely(!ctxi)) {
dev_err(dev, "%s: Failed to create context ctxid=%d\n",
__func__, ctxid);
+   rc = -ENOMEM;
goto err;
}
  



--
Andrew Donnellan  OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com  IBM Australia Limited

[PATCH] sata: ahci-da850: Fix some error handling paths in 'ahci_da850_probe()'

[Christophe JAILLET]

'rc' is known to be 0 at this point.
If 'platform_get_resource()' or 'devm_ioremap()' fail, return -ENOMEM
instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/ata/ahci_da850.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
index 1a50cd3b4233..eb46cad4d514 100644
--- a/drivers/ata/ahci_da850.c
+++ b/drivers/ata/ahci_da850.c
@@ -216,12 +216,16 @@ static int ahci_da850_probe(struct platform_device *pdev)
return rc;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-   if (!res)
+   if (!res) {
+   rc = -ENOMEM;
goto disable_resources;
+   }
 
pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
-   if (!pwrdn_reg)
+   if (!pwrdn_reg) {
+   rc = -ENOMEM;
goto disable_resources;
+   }
 
da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
 
-- 
2.11.0

[PATCH] sata: ahci-da850: Fix some error handling paths in 'ahci_da850_probe()'

[Christophe JAILLET]

'rc' is known to be 0 at this point.
If 'platform_get_resource()' or 'devm_ioremap()' fail, return -ENOMEM
instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/ata/ahci_da850.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
index 1a50cd3b4233..eb46cad4d514 100644
--- a/drivers/ata/ahci_da850.c
+++ b/drivers/ata/ahci_da850.c
@@ -216,12 +216,16 @@ static int ahci_da850_probe(struct platform_device *pdev)
return rc;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-   if (!res)
+   if (!res) {
+   rc = -ENOMEM;
goto disable_resources;
+   }
 
pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
-   if (!pwrdn_reg)
+   if (!pwrdn_reg) {
+   rc = -ENOMEM;
goto disable_resources;
+   }
 
da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
 
-- 
2.11.0

[PATCH] [media] radio: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/media/radio/radio-cadet.c| 2 +-
 drivers/media/radio/radio-gemtek.c   | 2 +-
 drivers/media/radio/radio-sf16fmr2.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/media/radio/radio-cadet.c 
b/drivers/media/radio/radio-cadet.c
index cbaf850..6888b7d 100644
--- a/drivers/media/radio/radio-cadet.c
+++ b/drivers/media/radio/radio-cadet.c
@@ -528,7 +528,7 @@ static const struct v4l2_ctrl_ops cadet_ctrl_ops = {
 
 #ifdef CONFIG_PNP
 
-static struct pnp_device_id cadet_pnp_devices[] = {
+static const struct pnp_device_id cadet_pnp_devices[] = {
/* ADS Cadet AM/FM Radio Card */
{.id = "MSM0c24", .driver_data = 0},
{.id = ""}
diff --git a/drivers/media/radio/radio-gemtek.c 
b/drivers/media/radio/radio-gemtek.c
index ca051ccb..ddc12b1 100644
--- a/drivers/media/radio/radio-gemtek.c
+++ b/drivers/media/radio/radio-gemtek.c
@@ -281,7 +281,7 @@ static const struct radio_isa_ops gemtek_ops = {
 static const int gemtek_ioports[] = { 0x20c, 0x30c, 0x24c, 0x34c, 0x248, 0x28c 
};
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id gemtek_pnp_devices[] = {
+static const struct pnp_device_id gemtek_pnp_devices[] = {
/* AOpen FX-3D/Pro Radio */
{.id = "ADS7183", .driver_data = 0},
{.id = ""}
diff --git a/drivers/media/radio/radio-sf16fmr2.c 
b/drivers/media/radio/radio-sf16fmr2.c
index dc81d42..de79d55 100644
--- a/drivers/media/radio/radio-sf16fmr2.c
+++ b/drivers/media/radio/radio-sf16fmr2.c
@@ -197,7 +197,7 @@ static int fmr2_tea_ext_init(struct snd_tea575x *tea)
return 0;
 }
 
-static struct pnp_device_id fmr2_pnp_ids[] = {
+static const struct pnp_device_id fmr2_pnp_ids[] = {
{ .id = "MFRad13" }, /* tuner subdevice of SF16-FMD2 */
{ .id = "" }
 };
-- 
2.7.4

[PATCH] [media] radio: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/media/radio/radio-cadet.c| 2 +-
 drivers/media/radio/radio-gemtek.c   | 2 +-
 drivers/media/radio/radio-sf16fmr2.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/media/radio/radio-cadet.c 
b/drivers/media/radio/radio-cadet.c
index cbaf850..6888b7d 100644
--- a/drivers/media/radio/radio-cadet.c
+++ b/drivers/media/radio/radio-cadet.c
@@ -528,7 +528,7 @@ static const struct v4l2_ctrl_ops cadet_ctrl_ops = {
 
 #ifdef CONFIG_PNP
 
-static struct pnp_device_id cadet_pnp_devices[] = {
+static const struct pnp_device_id cadet_pnp_devices[] = {
/* ADS Cadet AM/FM Radio Card */
{.id = "MSM0c24", .driver_data = 0},
{.id = ""}
diff --git a/drivers/media/radio/radio-gemtek.c 
b/drivers/media/radio/radio-gemtek.c
index ca051ccb..ddc12b1 100644
--- a/drivers/media/radio/radio-gemtek.c
+++ b/drivers/media/radio/radio-gemtek.c
@@ -281,7 +281,7 @@ static const struct radio_isa_ops gemtek_ops = {
 static const int gemtek_ioports[] = { 0x20c, 0x30c, 0x24c, 0x34c, 0x248, 0x28c 
};
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id gemtek_pnp_devices[] = {
+static const struct pnp_device_id gemtek_pnp_devices[] = {
/* AOpen FX-3D/Pro Radio */
{.id = "ADS7183", .driver_data = 0},
{.id = ""}
diff --git a/drivers/media/radio/radio-sf16fmr2.c 
b/drivers/media/radio/radio-sf16fmr2.c
index dc81d42..de79d55 100644
--- a/drivers/media/radio/radio-sf16fmr2.c
+++ b/drivers/media/radio/radio-sf16fmr2.c
@@ -197,7 +197,7 @@ static int fmr2_tea_ext_init(struct snd_tea575x *tea)
return 0;
 }
 
-static struct pnp_device_id fmr2_pnp_ids[] = {
+static const struct pnp_device_id fmr2_pnp_ids[] = {
{ .id = "MFRad13" }, /* tuner subdevice of SF16-FMD2 */
{ .id = "" }
 };
-- 
2.7.4

[PATCH v2 4/4] staging: pi433: Remove camel case variable names

[Rishabh Hardas]

Remove Camel casing by renaming variables.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.c | 4 ++--
 drivers/staging/pi433/pi433_if.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.c b/drivers/staging/pi433/pi433_if.c
index ed737f4..11c042b 100644
--- a/drivers/staging/pi433/pi433_if.c
+++ b/drivers/staging/pi433/pi433_if.c
@@ -192,7 +192,7 @@ struct pi433_instance {
SET_CHECKED(rf69_set_modulation (dev->spi, rx_cfg->modulation));
SET_CHECKED(rf69_set_antenna_impedance   (dev->spi, 
rx_cfg->antenna_impedance));
SET_CHECKED(rf69_set_rssi_threshold  (dev->spi, 
rx_cfg->rssi_threshold));
-   SET_CHECKED(rf69_set_ook_threshold_dec   (dev->spi, 
rx_cfg->thresholdDecrement));
+   SET_CHECKED(rf69_set_ook_threshold_dec   (dev->spi, 
rx_cfg->threshold_decrement));
SET_CHECKED(rf69_set_bandwidth   (dev->spi, 
rx_cfg->bw_mantisse, rx_cfg->bw_exponent));
SET_CHECKED(rf69_set_bandwidth_during_afc(dev->spi, 
rx_cfg->bw_mantisse, rx_cfg->bw_exponent));
SET_CHECKED(rf69_set_dagc(dev->spi, rx_cfg->dagc));
@@ -254,7 +254,7 @@ struct pi433_instance {
SET_CHECKED(rf69_set_modulation (dev->spi, tx_cfg->modulation));
SET_CHECKED(rf69_set_deviation  (dev->spi, tx_cfg->dev_frequency));
SET_CHECKED(rf69_set_pa_ramp(dev->spi, tx_cfg->pa_ramp));
-   SET_CHECKED(rf69_set_modulation_shaping(dev->spi, tx_cfg->modShaping));
+   SET_CHECKED(rf69_set_modulation_shaping(dev->spi, tx_cfg->mod_shaping));
SET_CHECKED(rf69_set_tx_start_condition(dev->spi, 
tx_cfg->tx_start_condition));

/* packet format enable */
diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 2929de0..7f57e7d 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -62,7 +62,7 @@ struct pi433_tx_cfg {
__u16   bit_rate;
__u32   dev_frequency;
enum modulation modulation;
-   enum mod_shapingmodShaping;
+   enum mod_shapingmod_shaping;

enum pa_ramppa_ramp;

@@ -114,8 +114,8 @@ struct pi433_rx_cfg {

__u8rssi_threshold;

-   enum threshold_decrementthresholdDecrement;
-   enum antenna_impedance  antenna_impedance;
+   enum threshold_decrementthreshold_decrement;
+   enum antenna_impedance  antenna_impedance;
enum lna_gain   lna_gain;
enum mantisse   bw_mantisse;/* normal: 0x50 */
__u8bw_exponent;/* during AFC: 0x8b */
--
1.9.1

[PATCH v2 4/4] staging: pi433: Remove camel case variable names

[Rishabh Hardas]

Remove Camel casing by renaming variables.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.c | 4 ++--
 drivers/staging/pi433/pi433_if.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.c b/drivers/staging/pi433/pi433_if.c
index ed737f4..11c042b 100644
--- a/drivers/staging/pi433/pi433_if.c
+++ b/drivers/staging/pi433/pi433_if.c
@@ -192,7 +192,7 @@ struct pi433_instance {
SET_CHECKED(rf69_set_modulation (dev->spi, rx_cfg->modulation));
SET_CHECKED(rf69_set_antenna_impedance   (dev->spi, 
rx_cfg->antenna_impedance));
SET_CHECKED(rf69_set_rssi_threshold  (dev->spi, 
rx_cfg->rssi_threshold));
-   SET_CHECKED(rf69_set_ook_threshold_dec   (dev->spi, 
rx_cfg->thresholdDecrement));
+   SET_CHECKED(rf69_set_ook_threshold_dec   (dev->spi, 
rx_cfg->threshold_decrement));
SET_CHECKED(rf69_set_bandwidth   (dev->spi, 
rx_cfg->bw_mantisse, rx_cfg->bw_exponent));
SET_CHECKED(rf69_set_bandwidth_during_afc(dev->spi, 
rx_cfg->bw_mantisse, rx_cfg->bw_exponent));
SET_CHECKED(rf69_set_dagc(dev->spi, rx_cfg->dagc));
@@ -254,7 +254,7 @@ struct pi433_instance {
SET_CHECKED(rf69_set_modulation (dev->spi, tx_cfg->modulation));
SET_CHECKED(rf69_set_deviation  (dev->spi, tx_cfg->dev_frequency));
SET_CHECKED(rf69_set_pa_ramp(dev->spi, tx_cfg->pa_ramp));
-   SET_CHECKED(rf69_set_modulation_shaping(dev->spi, tx_cfg->modShaping));
+   SET_CHECKED(rf69_set_modulation_shaping(dev->spi, tx_cfg->mod_shaping));
SET_CHECKED(rf69_set_tx_start_condition(dev->spi, 
tx_cfg->tx_start_condition));

/* packet format enable */
diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 2929de0..7f57e7d 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -62,7 +62,7 @@ struct pi433_tx_cfg {
__u16   bit_rate;
__u32   dev_frequency;
enum modulation modulation;
-   enum mod_shapingmodShaping;
+   enum mod_shapingmod_shaping;

enum pa_ramppa_ramp;

@@ -114,8 +114,8 @@ struct pi433_rx_cfg {

__u8rssi_threshold;

-   enum threshold_decrementthresholdDecrement;
-   enum antenna_impedance  antenna_impedance;
+   enum threshold_decrementthreshold_decrement;
+   enum antenna_impedance  antenna_impedance;
enum lna_gain   lna_gain;
enum mantisse   bw_mantisse;/* normal: 0x50 */
__u8bw_exponent;/* during AFC: 0x8b */
--
1.9.1

[PATCH v2 3/4] staging: pi433: Renaming Enums

[Rishabh Hardas]

Remove camel casing by renaming enums.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h  | 36 
 drivers/staging/pi433/rf69.c  | 26 +-
 drivers/staging/pi433/rf69.h  | 26 +-
 drivers/staging/pi433/rf69_enum.h | 16 
 4 files changed, 50 insertions(+), 54 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 84032f3..2929de0 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -62,21 +62,20 @@ struct pi433_tx_cfg {
__u16   bit_rate;
__u32   dev_frequency;
enum modulation modulation;
-   enum modShaping modShaping;
+   enum mod_shapingmodShaping;

-   enum paRamp pa_ramp;
+   enum pa_ramppa_ramp;

-   enum txStartCondition   tx_start_condition;
+   enum tx_start_condition tx_start_condition;

__u16   repetitions;

-
/* packet format */
-   enum optionOnOffenable_preamble;
-   enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;
-   enum optionOnOffenable_address_byte;
-   enum optionOnOffenable_crc;
+   enum option_on_off  enable_preamble;
+   enum option_on_off  enable_sync;
+   enum option_on_off  enable_length_byte;
+   enum option_on_off  enable_address_byte;
+   enum option_on_off  enable_crc;

__u16   preamble_length;
__u8sync_length;
@@ -86,7 +85,6 @@ struct pi433_tx_cfg {
__u8address_byte;
 };

-
 /**
  * struct pi433_rx_config - describes the configuration of the radio module for
  * sending
@@ -115,25 +113,24 @@ struct pi433_rx_cfg {
enum modulation modulation;

__u8rssi_threshold;
-   enum thresholdDecrement thresholdDecrement;
-   enum antennaImpedance   antenna_impedance;
-   enum lnaGainlna_gain;
+
+   enum threshold_decrementthresholdDecrement;
+   enum antenna_impedance  antenna_impedance;
+   enum lna_gain   lna_gain;
enum mantisse   bw_mantisse;/* normal: 0x50 */
__u8bw_exponent;/* during AFC: 0x8b */
enum dagc   dagc;

-
-
/* packet format */
-   enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;   /* should be used in
+   enum option_on_off  enable_sync;
+   enum option_on_off  enable_length_byte;   /* should be used in
   * combination with
   * sync, only
   */
-   enum addressFiltering   enable_address_filtering; /* operational
+   enum address_filtering  enable_address_filtering; /* operational
   * with sync, only
   */
-   enum optionOnOffenable_crc;   /* only operational,
+   enum option_on_off  enable_crc;   /* only operational,
   *if sync on and fixed
   * length or length
   * byte is used
@@ -148,7 +145,6 @@ struct pi433_rx_cfg {
__u8broadcast_address;
 };

-
 #define PI433_IOC_MAGIC'r'

 #define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
diff --git a/drivers/staging/pi433/rf69.c b/drivers/staging/pi433/rf69.c
index f83523e..b7b8c7c 100644
--- a/drivers/staging/pi433/rf69.c
+++ b/drivers/staging/pi433/rf69.c
@@ -109,7 +109,7 @@ enum modulation rf69_get_modulation(struct spi_device *spi)
}
 }

-int rf69_set_modulation_shaping(struct spi_device *spi, enum modShaping 
modShaping)
+int rf69_set_modulation_shaping(struct spi_device *spi, enum mod_shaping 
modShaping)
 {
#ifdef DEBUG
dev_dbg(>dev, "set: mod shaping");
@@ -264,7 +264,7 @@ int rf69_set_frequency(struct spi_device *spi, u32 
frequency)
return 0;
 }

-int rf69_set_amplifier_0(struct spi_device *spi, enum optionOnOff optionOnOff)
+int rf69_set_amplifier_0(struct spi_device *spi, enum option_on_off 
optionOnOff)
 {
#ifdef DEBUG
dev_dbg(>dev, "set: amp #0");
@@ -277,7 +277,7 @@ int rf69_set_amplifier_0(struct spi_device *spi, enum 
optionOnOff optionOnOff)
}
 }

-int rf69_set_amplifier_1(struct spi_device *spi, enum optionOnOff optionOnOff)
+int 

[PATCH v2 3/4] staging: pi433: Renaming Enums

[Rishabh Hardas]

Remove camel casing by renaming enums.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h  | 36 
 drivers/staging/pi433/rf69.c  | 26 +-
 drivers/staging/pi433/rf69.h  | 26 +-
 drivers/staging/pi433/rf69_enum.h | 16 
 4 files changed, 50 insertions(+), 54 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 84032f3..2929de0 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -62,21 +62,20 @@ struct pi433_tx_cfg {
__u16   bit_rate;
__u32   dev_frequency;
enum modulation modulation;
-   enum modShaping modShaping;
+   enum mod_shapingmodShaping;

-   enum paRamp pa_ramp;
+   enum pa_ramppa_ramp;

-   enum txStartCondition   tx_start_condition;
+   enum tx_start_condition tx_start_condition;

__u16   repetitions;

-
/* packet format */
-   enum optionOnOffenable_preamble;
-   enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;
-   enum optionOnOffenable_address_byte;
-   enum optionOnOffenable_crc;
+   enum option_on_off  enable_preamble;
+   enum option_on_off  enable_sync;
+   enum option_on_off  enable_length_byte;
+   enum option_on_off  enable_address_byte;
+   enum option_on_off  enable_crc;

__u16   preamble_length;
__u8sync_length;
@@ -86,7 +85,6 @@ struct pi433_tx_cfg {
__u8address_byte;
 };

-
 /**
  * struct pi433_rx_config - describes the configuration of the radio module for
  * sending
@@ -115,25 +113,24 @@ struct pi433_rx_cfg {
enum modulation modulation;

__u8rssi_threshold;
-   enum thresholdDecrement thresholdDecrement;
-   enum antennaImpedance   antenna_impedance;
-   enum lnaGainlna_gain;
+
+   enum threshold_decrementthresholdDecrement;
+   enum antenna_impedance  antenna_impedance;
+   enum lna_gain   lna_gain;
enum mantisse   bw_mantisse;/* normal: 0x50 */
__u8bw_exponent;/* during AFC: 0x8b */
enum dagc   dagc;

-
-
/* packet format */
-   enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;   /* should be used in
+   enum option_on_off  enable_sync;
+   enum option_on_off  enable_length_byte;   /* should be used in
   * combination with
   * sync, only
   */
-   enum addressFiltering   enable_address_filtering; /* operational
+   enum address_filtering  enable_address_filtering; /* operational
   * with sync, only
   */
-   enum optionOnOffenable_crc;   /* only operational,
+   enum option_on_off  enable_crc;   /* only operational,
   *if sync on and fixed
   * length or length
   * byte is used
@@ -148,7 +145,6 @@ struct pi433_rx_cfg {
__u8broadcast_address;
 };

-
 #define PI433_IOC_MAGIC'r'

 #define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
diff --git a/drivers/staging/pi433/rf69.c b/drivers/staging/pi433/rf69.c
index f83523e..b7b8c7c 100644
--- a/drivers/staging/pi433/rf69.c
+++ b/drivers/staging/pi433/rf69.c
@@ -109,7 +109,7 @@ enum modulation rf69_get_modulation(struct spi_device *spi)
}
 }

-int rf69_set_modulation_shaping(struct spi_device *spi, enum modShaping 
modShaping)
+int rf69_set_modulation_shaping(struct spi_device *spi, enum mod_shaping 
modShaping)
 {
#ifdef DEBUG
dev_dbg(>dev, "set: mod shaping");
@@ -264,7 +264,7 @@ int rf69_set_frequency(struct spi_device *spi, u32 
frequency)
return 0;
 }

-int rf69_set_amplifier_0(struct spi_device *spi, enum optionOnOff optionOnOff)
+int rf69_set_amplifier_0(struct spi_device *spi, enum option_on_off 
optionOnOff)
 {
#ifdef DEBUG
dev_dbg(>dev, "set: amp #0");
@@ -277,7 +277,7 @@ int rf69_set_amplifier_0(struct spi_device *spi, enum 
optionOnOff optionOnOff)
}
 }

-int rf69_set_amplifier_1(struct spi_device *spi, enum optionOnOff optionOnOff)
+int rf69_set_amplifier_1(struct spi_device 

[PATCH v2 2/4] staging: pi433: Change Comments

[Rishabh Hardas]

Shorten long comments and format them in kernel style comments.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 91e4a01..84032f3 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -126,9 +126,18 @@ struct pi433_rx_cfg {

/* packet format */
enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;   /* should be used in 
combination with sync, only */
-   enum addressFiltering   enable_address_filtering; /* operational with 
sync, only */
-   enum optionOnOffenable_crc;   /* only operational, 
if sync on and fixed length or length byte is used */
+   enum optionOnOffenable_length_byte;   /* should be used in
+  * combination with
+  * sync, only
+  */
+   enum addressFiltering   enable_address_filtering; /* operational
+  * with sync, only
+  */
+   enum optionOnOffenable_crc;   /* only operational,
+  *if sync on and fixed
+  * length or length
+  * byte is used
+  */

__u8sync_length;
__u8fixed_message_length;
--
1.9.1

[PATCH v2 2/4] staging: pi433: Change Comments

[Rishabh Hardas]

Shorten long comments and format them in kernel style comments.

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index 91e4a01..84032f3 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -126,9 +126,18 @@ struct pi433_rx_cfg {

/* packet format */
enum optionOnOffenable_sync;
-   enum optionOnOffenable_length_byte;   /* should be used in 
combination with sync, only */
-   enum addressFiltering   enable_address_filtering; /* operational with 
sync, only */
-   enum optionOnOffenable_crc;   /* only operational, 
if sync on and fixed length or length byte is used */
+   enum optionOnOffenable_length_byte;   /* should be used in
+  * combination with
+  * sync, only
+  */
+   enum addressFiltering   enable_address_filtering; /* operational
+  * with sync, only
+  */
+   enum optionOnOffenable_crc;   /* only operational,
+  *if sync on and fixed
+  * length or length
+  * byte is used
+  */

__u8sync_length;
__u8fixed_message_length;
--
1.9.1

[PATCH v2 1/4] staging: pi433: Style fix - Correct long lines

[Rishabh Hardas]

Correct lines above 80 characters in pi433_if.h

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h | 28 +++-
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index e6ed3cd..91e4a01 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -33,14 +33,13 @@
 #include "rf69_enum.h"

 /*---*/
-
-
 /*---*/

 /* IOCTL structs and commands */

 /**
- * struct pi433_tx_config - describes the configuration of the radio module 
for sending
+ * struct pi433_tx_config - describes the configuration of the radio module for
+ * sending
  * @frequency:
  * @bit_rate:
  * @modulation:
@@ -57,9 +56,8 @@
  *
  * NOTE: struct layout is the same in 64bit and 32bit userspace.
  */
-#define PI433_TX_CFG_IOCTL_NR  0
-struct pi433_tx_cfg
-{
+#define PI433_TX_CFG_IOCTL_NR  0
+struct pi433_tx_cfg {
__u32   frequency;
__u16   bit_rate;
__u32   dev_frequency;
@@ -90,7 +88,8 @@ struct pi433_tx_cfg


 /**
- * struct pi433_rx_config - describes the configuration of the radio module 
for sending
+ * struct pi433_rx_config - describes the configuration of the radio module for
+ * sending
  * @frequency:
  * @bit_rate:
  * @modulation:
@@ -107,7 +106,7 @@ struct pi433_tx_cfg
  *
  * NOTE: struct layout is the same in 64bit and 32bit userspace.
  */
-#define PI433_RX_CFG_IOCTL_NR  1
+#define PI433_RX_CFG_IOCTL_NR  1
 struct pi433_rx_cfg {
__u32   frequency;
__u16   bit_rate;
@@ -143,10 +142,13 @@ struct pi433_rx_cfg {

 #define PI433_IOC_MAGIC'r'

-#define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_tx_cfg)])
-#define PI433_IOC_WR_TX_CFG_IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_tx_cfg)])
-
-#define PI433_IOC_RD_RX_CFG_IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_rx_cfg)])
-#define PI433_IOC_WR_RX_CFG_IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_rx_cfg)])
+#define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_tx_cfg)])
+#define PI433_IOC_WR_TX_CFG_IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_tx_cfg)])
+#define PI433_IOC_RD_RX_CFG_IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_rx_cfg)])
+#define PI433_IOC_WR_RX_CFG_IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_rx_cfg)])

 #endif /* PI433_H */
--
1.9.1

[PATCH v2 0/4] staging: pi433: Rename camel case and other style issues

[Rishabh Hardas]

Hi,

This series pf patches solves some of the coding style
issues. I have corrected long lines, changed comment style,
renamed enums and variables that were in camel case.

Tried to get zero erros and warnings on the pi433_if.h file.

Regards,
Rishabh Hardas

Rishabh Hardas (4):
  staging: pi433: Style fix - Correct long lines
  staging: pi433: Change Comments
  staging: pi433: Renaming Enums
  staging: pi433: Remove camel case variable names

 drivers/staging/pi433/pi433_if.c  |  4 +--
 drivers/staging/pi433/pi433_if.h  | 73 +--
 drivers/staging/pi433/rf69.c  | 26 +++---
 drivers/staging/pi433/rf69.h  | 26 +++---
 drivers/staging/pi433/rf69_enum.h | 16 -
 5 files changed, 76 insertions(+), 69 deletions(-)

--
1.9.1

[PATCH v2 1/4] staging: pi433: Style fix - Correct long lines

[Rishabh Hardas]

Correct lines above 80 characters in pi433_if.h

Signed-off-by: Rishabh Hardas 
---
 drivers/staging/pi433/pi433_if.h | 28 +++-
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/staging/pi433/pi433_if.h b/drivers/staging/pi433/pi433_if.h
index e6ed3cd..91e4a01 100644
--- a/drivers/staging/pi433/pi433_if.h
+++ b/drivers/staging/pi433/pi433_if.h
@@ -33,14 +33,13 @@
 #include "rf69_enum.h"

 /*---*/
-
-
 /*---*/

 /* IOCTL structs and commands */

 /**
- * struct pi433_tx_config - describes the configuration of the radio module 
for sending
+ * struct pi433_tx_config - describes the configuration of the radio module for
+ * sending
  * @frequency:
  * @bit_rate:
  * @modulation:
@@ -57,9 +56,8 @@
  *
  * NOTE: struct layout is the same in 64bit and 32bit userspace.
  */
-#define PI433_TX_CFG_IOCTL_NR  0
-struct pi433_tx_cfg
-{
+#define PI433_TX_CFG_IOCTL_NR  0
+struct pi433_tx_cfg {
__u32   frequency;
__u16   bit_rate;
__u32   dev_frequency;
@@ -90,7 +88,8 @@ struct pi433_tx_cfg


 /**
- * struct pi433_rx_config - describes the configuration of the radio module 
for sending
+ * struct pi433_rx_config - describes the configuration of the radio module for
+ * sending
  * @frequency:
  * @bit_rate:
  * @modulation:
@@ -107,7 +106,7 @@ struct pi433_tx_cfg
  *
  * NOTE: struct layout is the same in 64bit and 32bit userspace.
  */
-#define PI433_RX_CFG_IOCTL_NR  1
+#define PI433_RX_CFG_IOCTL_NR  1
 struct pi433_rx_cfg {
__u32   frequency;
__u16   bit_rate;
@@ -143,10 +142,13 @@ struct pi433_rx_cfg {

 #define PI433_IOC_MAGIC'r'

-#define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_tx_cfg)])
-#define PI433_IOC_WR_TX_CFG_IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_tx_cfg)])
-
-#define PI433_IOC_RD_RX_CFG_IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_rx_cfg)])
-#define PI433_IOC_WR_RX_CFG_IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, 
char[sizeof(struct pi433_rx_cfg)])
+#define PI433_IOC_RD_TX_CFG_IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_tx_cfg)])
+#define PI433_IOC_WR_TX_CFG_IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_tx_cfg)])
+#define PI433_IOC_RD_RX_CFG_IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_rx_cfg)])
+#define PI433_IOC_WR_RX_CFG_IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR,\
+char[sizeof(struct pi433_rx_cfg)])

 #endif /* PI433_H */
--
1.9.1

[PATCH v2 0/4] staging: pi433: Rename camel case and other style issues

[Rishabh Hardas]

Hi,

This series pf patches solves some of the coding style
issues. I have corrected long lines, changed comment style,
renamed enums and variables that were in camel case.

Tried to get zero erros and warnings on the pi433_if.h file.

Regards,
Rishabh Hardas

Rishabh Hardas (4):
  staging: pi433: Style fix - Correct long lines
  staging: pi433: Change Comments
  staging: pi433: Renaming Enums
  staging: pi433: Remove camel case variable names

 drivers/staging/pi433/pi433_if.c  |  4 +--
 drivers/staging/pi433/pi433_if.h  | 73 +--
 drivers/staging/pi433/rf69.c  | 26 +++---
 drivers/staging/pi433/rf69.h  | 26 +++---
 drivers/staging/pi433/rf69_enum.h | 16 -
 5 files changed, 76 insertions(+), 69 deletions(-)

--
1.9.1

Re: [PATCH 2/3] libnvdimm, pfn, dax: show supported dax/pfn region alignments in sysfs

[Oliver]

On Wed, Aug 16, 2017 at 1:47 AM, Dan Williams  wrote:
> On Mon, Aug 14, 2017 at 11:46 PM, Oliver  wrote:
>> On Tue, Aug 15, 2017 at 4:02 PM, kbuild test robot  wrote:
> [..]
>>>114  static const unsigned long *nd_pfn_supported_alignments(void)
>>>115  {
>>>116  /*
>>>117   * This needs to be a local variable because the *_SIZE 
>>> macros
>>>118   * aren't always constants.
>>>119   */
>>
>> I probably should have been clearer, "local" here really means
>> "non-static". Otherwise the array could have been made a global.
>>
>
> Whoops, my fault. How about this:
>
> @@ -127,8 +127,11 @@ static const unsigned long
> *nd_pfn_supported_alignments(void)
>  #endif
> 0,
> };
> +   static unsigned long data[ARRAY_SIZE(supported_alignments)];
>
> -   return supported_alignments;
> +   memcpy(data, supported_alignments, sizeof(data));
> +
> +   return data;
>  }

That should do the trick, but you'll need to fix up the source array
declaration too.

Re: [PATCH 2/3] libnvdimm, pfn, dax: show supported dax/pfn region alignments in sysfs

[Oliver]

On Wed, Aug 16, 2017 at 1:47 AM, Dan Williams  wrote:
> On Mon, Aug 14, 2017 at 11:46 PM, Oliver  wrote:
>> On Tue, Aug 15, 2017 at 4:02 PM, kbuild test robot  wrote:
> [..]
>>>114  static const unsigned long *nd_pfn_supported_alignments(void)
>>>115  {
>>>116  /*
>>>117   * This needs to be a local variable because the *_SIZE 
>>> macros
>>>118   * aren't always constants.
>>>119   */
>>
>> I probably should have been clearer, "local" here really means
>> "non-static". Otherwise the array could have been made a global.
>>
>
> Whoops, my fault. How about this:
>
> @@ -127,8 +127,11 @@ static const unsigned long
> *nd_pfn_supported_alignments(void)
>  #endif
> 0,
> };
> +   static unsigned long data[ARRAY_SIZE(supported_alignments)];
>
> -   return supported_alignments;
> +   memcpy(data, supported_alignments, sizeof(data));
> +
> +   return data;
>  }

That should do the trick, but you'll need to fix up the source array
declaration too.

[rcu:rcu/dev 14/15] kernel/time/tick-sched.c:820: undefined reference to `__divdi3'

[kbuild test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git 
rcu/dev
head:   551164572a4a41968abd020ec24499085cc2adf7
commit: 33103e7b1f89ef432dfe3337d2a6932cdf5c1312 [14/15] EXP: Trace tick return 
from tick_nohz_stop_sched_tick
config: mips-nlm_xlr_defconfig (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 33103e7b1f89ef432dfe3337d2a6932cdf5c1312
# save the attached .config to linux build tree
make.cross ARCH=mips 

All errors (new ones prefixed by >>):

   kernel/time/tick-sched.o: In function `tick_nohz_stop_sched_tick':
>> kernel/time/tick-sched.c:820: undefined reference to `__divdi3'

vim +820 kernel/time/tick-sched.c

   758  
   759  /* Calculate the next expiry time */
   760  if (delta < (KTIME_MAX - basemono))
   761  expires = basemono + delta;
   762  else
   763  expires = KTIME_MAX;
   764  
   765  expires = min_t(u64, expires, next_tick);
   766  tick = expires;
   767  
   768  /* Skip reprogram of event if its not changed */
   769  if (ts->tick_stopped && (expires == ts->next_tick)) {
   770  /* Sanity check: make sure clockevent is actually 
programmed */
   771  if (tick == KTIME_MAX || ts->next_tick == 
hrtimer_get_expires(>sched_timer))
   772  goto out;
   773  
   774  WARN_ON_ONCE(1);
   775  printk_once("basemono: %llu ts->next_tick: %llu 
dev->next_event: %llu timer->active: %d timer->expires: %llu\n",
   776  basemono, ts->next_tick, dev->next_event,
   777  hrtimer_active(>sched_timer), 
hrtimer_get_expires(>sched_timer));
   778  }
   779  
   780  /*
   781   * nohz_stop_sched_tick can be called several times before
   782   * the nohz_restart_sched_tick is called. This happens when
   783   * interrupts arrive which do not cause a reschedule. In the
   784   * first call we save the current tick time, so we can restart
   785   * the scheduler tick in nohz_restart_sched_tick.
   786   */
   787  if (!ts->tick_stopped) {
   788  calc_load_nohz_start();
   789  cpu_load_update_nohz_start();
   790  
   791  ts->last_tick = hrtimer_get_expires(>sched_timer);
   792  ts->tick_stopped = 1;
   793  trace_tick_stop(1, TICK_DEP_MASK_NONE);
   794  }
   795  
   796  ts->next_tick = tick;
   797  
   798  /*
   799   * If the expiration time == KTIME_MAX, then we simply stop
   800   * the tick timer.
   801   */
   802  if (unlikely(expires == KTIME_MAX)) {
   803  if (ts->nohz_mode == NOHZ_MODE_HIGHRES)
   804  hrtimer_cancel(>sched_timer);
   805  goto out;
   806  }
   807  
   808  hrtimer_set_expires(>sched_timer, tick);
   809  
   810  if (ts->nohz_mode == NOHZ_MODE_HIGHRES)
   811  hrtimer_start_expires(>sched_timer, 
HRTIMER_MODE_ABS_PINNED);
   812  else
   813  tick_program_event(tick, 1);
   814  out:
   815  /*
   816   * Update the estimated sleep length until the next timer
   817   * (not only the tick).
   818   */
   819  ts->sleep_length = ktime_sub(dev->next_event, now);
 > 820  trace_printk("tick_nohz_stop_sched_tick: %lld\n", (tick - 
 > ktime_get()) / 1000);
   821  return tick;
   822  }
   823  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[rcu:rcu/dev 14/15] kernel/time/tick-sched.c:820: undefined reference to `__divdi3'

[kbuild test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git 
rcu/dev
head:   551164572a4a41968abd020ec24499085cc2adf7
commit: 33103e7b1f89ef432dfe3337d2a6932cdf5c1312 [14/15] EXP: Trace tick return 
from tick_nohz_stop_sched_tick
config: mips-nlm_xlr_defconfig (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 33103e7b1f89ef432dfe3337d2a6932cdf5c1312
# save the attached .config to linux build tree
make.cross ARCH=mips 

All errors (new ones prefixed by >>):

   kernel/time/tick-sched.o: In function `tick_nohz_stop_sched_tick':
>> kernel/time/tick-sched.c:820: undefined reference to `__divdi3'

vim +820 kernel/time/tick-sched.c

   758  
   759  /* Calculate the next expiry time */
   760  if (delta < (KTIME_MAX - basemono))
   761  expires = basemono + delta;
   762  else
   763  expires = KTIME_MAX;
   764  
   765  expires = min_t(u64, expires, next_tick);
   766  tick = expires;
   767  
   768  /* Skip reprogram of event if its not changed */
   769  if (ts->tick_stopped && (expires == ts->next_tick)) {
   770  /* Sanity check: make sure clockevent is actually 
programmed */
   771  if (tick == KTIME_MAX || ts->next_tick == 
hrtimer_get_expires(>sched_timer))
   772  goto out;
   773  
   774  WARN_ON_ONCE(1);
   775  printk_once("basemono: %llu ts->next_tick: %llu 
dev->next_event: %llu timer->active: %d timer->expires: %llu\n",
   776  basemono, ts->next_tick, dev->next_event,
   777  hrtimer_active(>sched_timer), 
hrtimer_get_expires(>sched_timer));
   778  }
   779  
   780  /*
   781   * nohz_stop_sched_tick can be called several times before
   782   * the nohz_restart_sched_tick is called. This happens when
   783   * interrupts arrive which do not cause a reschedule. In the
   784   * first call we save the current tick time, so we can restart
   785   * the scheduler tick in nohz_restart_sched_tick.
   786   */
   787  if (!ts->tick_stopped) {
   788  calc_load_nohz_start();
   789  cpu_load_update_nohz_start();
   790  
   791  ts->last_tick = hrtimer_get_expires(>sched_timer);
   792  ts->tick_stopped = 1;
   793  trace_tick_stop(1, TICK_DEP_MASK_NONE);
   794  }
   795  
   796  ts->next_tick = tick;
   797  
   798  /*
   799   * If the expiration time == KTIME_MAX, then we simply stop
   800   * the tick timer.
   801   */
   802  if (unlikely(expires == KTIME_MAX)) {
   803  if (ts->nohz_mode == NOHZ_MODE_HIGHRES)
   804  hrtimer_cancel(>sched_timer);
   805  goto out;
   806  }
   807  
   808  hrtimer_set_expires(>sched_timer, tick);
   809  
   810  if (ts->nohz_mode == NOHZ_MODE_HIGHRES)
   811  hrtimer_start_expires(>sched_timer, 
HRTIMER_MODE_ABS_PINNED);
   812  else
   813  tick_program_event(tick, 1);
   814  out:
   815  /*
   816   * Update the estimated sleep length until the next timer
   817   * (not only the tick).
   818   */
   819  ts->sleep_length = ktime_sub(dev->next_event, now);
 > 820  trace_printk("tick_nohz_stop_sched_tick: %lld\n", (tick - 
 > ktime_get()) / 1000);
   821  return tick;
   822  }
   823  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[PATCH] crypto: cavium/nitrox - Fix an error handling path in 'nitrox_probe()'

[Christophe JAILLET]

'err' is known to be 0 at this point.
If 'kzalloc()' fails, returns -ENOMEM instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c 
b/drivers/crypto/cavium/nitrox/nitrox_main.c
index 9ccefb9b7232..fee7cb2ce747 100644
--- a/drivers/crypto/cavium/nitrox/nitrox_main.c
+++ b/drivers/crypto/cavium/nitrox/nitrox_main.c
@@ -513,8 +513,10 @@ static int nitrox_probe(struct pci_dev *pdev,
pci_set_master(pdev);
 
ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
-   if (!ndev)
+   if (!ndev) {
+   err = -ENOMEM;
goto ndev_fail;
+   }
 
pci_set_drvdata(pdev, ndev);
ndev->pdev = pdev;
-- 
2.11.0

[PATCH] crypto: cavium/nitrox - Fix an error handling path in 'nitrox_probe()'

[Christophe JAILLET]

'err' is known to be 0 at this point.
If 'kzalloc()' fails, returns -ENOMEM instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c 
b/drivers/crypto/cavium/nitrox/nitrox_main.c
index 9ccefb9b7232..fee7cb2ce747 100644
--- a/drivers/crypto/cavium/nitrox/nitrox_main.c
+++ b/drivers/crypto/cavium/nitrox/nitrox_main.c
@@ -513,8 +513,10 @@ static int nitrox_probe(struct pci_dev *pdev,
pci_set_master(pdev);
 
ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
-   if (!ndev)
+   if (!ndev) {
+   err = -ENOMEM;
goto ndev_fail;
+   }
 
pci_set_drvdata(pdev, ndev);
ndev->pdev = pdev;
-- 
2.11.0

[PATCH] bpf: Update sysctl documentation to list all supported architectures

[Michael Ellerman]

The sysctl documentation states that the JIT is only available on
x86_64, which is no longer correct.

Update the list to include all architectures that enable HAVE_CBPF_JIT
or HAVE_EBPF_JIT under some configuration.

Signed-off-by: Michael Ellerman 
---
 Documentation/sysctl/net.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt
index 14db18c970b1..f68356024d09 100644
--- a/Documentation/sysctl/net.txt
+++ b/Documentation/sysctl/net.txt
@@ -36,8 +36,9 @@ bpf_jit_enable
 --
 
 This enables Berkeley Packet Filter Just in Time compiler.
-Currently supported on x86_64 architecture, bpf_jit provides a framework
-to speed packet filtering, the one used by tcpdump/libpcap for example.
+Currently supported on arm, arm64, mips, powerpc, s390, sparc and x86_64
+architectures, bpf_jit provides a framework to speed packet filtering, the one
+used by tcpdump/libpcap for example.
 Values :
0 - disable the JIT (default value)
1 - enable the JIT
-- 
2.7.4

[PATCH] bpf: Update sysctl documentation to list all supported architectures

[Michael Ellerman]

The sysctl documentation states that the JIT is only available on
x86_64, which is no longer correct.

Update the list to include all architectures that enable HAVE_CBPF_JIT
or HAVE_EBPF_JIT under some configuration.

Signed-off-by: Michael Ellerman 
---
 Documentation/sysctl/net.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt
index 14db18c970b1..f68356024d09 100644
--- a/Documentation/sysctl/net.txt
+++ b/Documentation/sysctl/net.txt
@@ -36,8 +36,9 @@ bpf_jit_enable
 --
 
 This enables Berkeley Packet Filter Just in Time compiler.
-Currently supported on x86_64 architecture, bpf_jit provides a framework
-to speed packet filtering, the one used by tcpdump/libpcap for example.
+Currently supported on arm, arm64, mips, powerpc, s390, sparc and x86_64
+architectures, bpf_jit provides a framework to speed packet filtering, the one
+used by tcpdump/libpcap for example.
 Values :
0 - disable the JIT (default value)
1 - enable the JIT
-- 
2.7.4

RE: [PATCH v2 19/22] fpga: intel: afu: add header sub feature support

[Wu, Hao]

>  On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao  wrote:
> 
> Hi Hao,
> 
> > The header register set is always present for the Port/AFU, it is mainly
> > for capability, control and status of the ports that AFU connected to.
> 
> So just to be clear, the reset function is acting on the Port, not the
> AFU, right?

Hi Alan

AFU will be reset as well. Once port reset is issued, a compliant HW
AFU will reset all its state and stop sending requests, and HW will set
port reset ack bit when all outstanding requests initiated have been
drained.

Will add some notes here.

> 
> >
> > This patch implements header sub feature support.
> 
> Please add a brief reminder here what the 'header' is.  It's defined
> in patch 7 as being part of the feature list, but hardly mentioned
> when I grep intel-fpga.txt.

Sure, will adds some notes here.

Actually the header sub feature means the registers belong to the
feature device (e.g port and FME), not any sub features (e.g PR, 
Power management).

> 
> > Below user interfaces
> > are created by this patch.
> >
> > Sysfs interface:
> > * /sys/class/fpga///id
> >   Read-only. Port ID.
> >
> > Ioctl interface:
> > * FPGA_PORT_RESET
> >   Reset the FPGA AFU Port.
> >
> > Signed-off-by: Tim Whisonant 
> > Signed-off-by: Enno Luebbers 
> > Signed-off-by: Shiva Rao 
> > Signed-off-by: Christopher Rauer 
> > Signed-off-by: Xiao Guangrong 
> > Signed-off-by: Wu Hao 
> > ---
> > v2: add sysfs documentation.
> > ---
> >  .../ABI/testing/sysfs-platform-intel-fpga-afu  |  7 
> >  drivers/fpga/intel-afu-main.c  | 44 
> > +-
> >  include/uapi/linux/intel-fpga.h| 14 +++
> >  3 files changed, 64 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga-
> afu
> >
> > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> > new file mode 100644
> > index 000..8ad22c9
> > --- /dev/null
> > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> > @@ -0,0 +1,7 @@
> > +What:  /sys/bus/platform/devices/intel-fpga-port.0/id
> > +Date:  June 2017
> > +KernelVersion:  4.12
> > +Contact:   Wu Hao 
> > +Description:   Read-only. It returns id of this port. One Intel FPGA device
> > +   may have more than one port. Userspace could use this id to
> > +   distinguish different ports under same FPGA device.
> > diff --git a/drivers/fpga/intel-afu-main.c b/drivers/fpga/intel-afu-main.c
> > index 96d0367..2a17cde 100644
> > --- a/drivers/fpga/intel-afu-main.c
> > +++ b/drivers/fpga/intel-afu-main.c
> > @@ -18,25 +18,66 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >
> >  #include "intel-feature-dev.h"
> >
> > +static ssize_t
> > +id_show(struct device *dev, struct device_attribute *attr, char *buf)
> > +{
> > +   int id = fpga_port_id(to_platform_device(dev));
> > +
> > +   return scnprintf(buf, PAGE_SIZE, "%d\n", id);
> > +}
> > +static DEVICE_ATTR_RO(id);
> > +
> > +static const struct attribute *port_hdr_attrs[] = {
> > +   _attr_id.attr,
> > +   NULL,
> > +};
> > +
> >  static int port_hdr_init(struct platform_device *pdev, struct feature 
> > *feature)
> >  {
> > dev_dbg(>dev, "PORT HDR Init.\n");
> >
> > -   return 0;
> > +   fpga_port_reset(pdev);
> 
> So the port will be reset here, which happens during fme_probe().
> IIUC the PR region is empty then, there is just the static region,
> right?

port_hdr_init is invoked during afu_probe() function. The fpga_port_reset
only resets the AFU's state and not empty the PR region. User doesn't need
to program it again after port reset.

The purpose of this reset in port_hdr_init function, is to make sure that we 
could have a clean start whenever the port driver module is loaded. And
similar as the one added in afu release.

> 
> > +
> > +   return sysfs_create_files(>dev.kobj, port_hdr_attrs);
> 
> Greg wrote an article that there could be a race condition caused by
> creating sysfs files this late [1] and I see sysfs_create_files() used
> very sparingly in the kernel.  I'm thinking that fpga-bridge should
> provide a place to create sysfs files earlier by adding an
> attribute_group to fpga_bridge_ops (same for fpga-mgr and fpga-region)
> and then fpga_bridge_register could do bridge->dev.groups =
> br_ops->groups.  I'll put a patch for that out soon.
> 

Hm... I understand there could be a race condition if creates sysfs files late.
Actually the reasons I prefer to have each sub feature to create its own sysfs
files are, 1) if any sub feature is not present, then related init function 
won't 
be invoked and related sysfs files won't be created at all. Then end user could
know which sub 

RE: [PATCH v2 19/22] fpga: intel: afu: add header sub feature support

[Wu, Hao]

>  On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao  wrote:
> 
> Hi Hao,
> 
> > The header register set is always present for the Port/AFU, it is mainly
> > for capability, control and status of the ports that AFU connected to.
> 
> So just to be clear, the reset function is acting on the Port, not the
> AFU, right?

Hi Alan

AFU will be reset as well. Once port reset is issued, a compliant HW
AFU will reset all its state and stop sending requests, and HW will set
port reset ack bit when all outstanding requests initiated have been
drained.

Will add some notes here.

> 
> >
> > This patch implements header sub feature support.
> 
> Please add a brief reminder here what the 'header' is.  It's defined
> in patch 7 as being part of the feature list, but hardly mentioned
> when I grep intel-fpga.txt.

Sure, will adds some notes here.

Actually the header sub feature means the registers belong to the
feature device (e.g port and FME), not any sub features (e.g PR, 
Power management).

> 
> > Below user interfaces
> > are created by this patch.
> >
> > Sysfs interface:
> > * /sys/class/fpga///id
> >   Read-only. Port ID.
> >
> > Ioctl interface:
> > * FPGA_PORT_RESET
> >   Reset the FPGA AFU Port.
> >
> > Signed-off-by: Tim Whisonant 
> > Signed-off-by: Enno Luebbers 
> > Signed-off-by: Shiva Rao 
> > Signed-off-by: Christopher Rauer 
> > Signed-off-by: Xiao Guangrong 
> > Signed-off-by: Wu Hao 
> > ---
> > v2: add sysfs documentation.
> > ---
> >  .../ABI/testing/sysfs-platform-intel-fpga-afu  |  7 
> >  drivers/fpga/intel-afu-main.c  | 44 
> > +-
> >  include/uapi/linux/intel-fpga.h| 14 +++
> >  3 files changed, 64 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga-
> afu
> >
> > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> > new file mode 100644
> > index 000..8ad22c9
> > --- /dev/null
> > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
> > @@ -0,0 +1,7 @@
> > +What:  /sys/bus/platform/devices/intel-fpga-port.0/id
> > +Date:  June 2017
> > +KernelVersion:  4.12
> > +Contact:   Wu Hao 
> > +Description:   Read-only. It returns id of this port. One Intel FPGA device
> > +   may have more than one port. Userspace could use this id to
> > +   distinguish different ports under same FPGA device.
> > diff --git a/drivers/fpga/intel-afu-main.c b/drivers/fpga/intel-afu-main.c
> > index 96d0367..2a17cde 100644
> > --- a/drivers/fpga/intel-afu-main.c
> > +++ b/drivers/fpga/intel-afu-main.c
> > @@ -18,25 +18,66 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >
> >  #include "intel-feature-dev.h"
> >
> > +static ssize_t
> > +id_show(struct device *dev, struct device_attribute *attr, char *buf)
> > +{
> > +   int id = fpga_port_id(to_platform_device(dev));
> > +
> > +   return scnprintf(buf, PAGE_SIZE, "%d\n", id);
> > +}
> > +static DEVICE_ATTR_RO(id);
> > +
> > +static const struct attribute *port_hdr_attrs[] = {
> > +   _attr_id.attr,
> > +   NULL,
> > +};
> > +
> >  static int port_hdr_init(struct platform_device *pdev, struct feature 
> > *feature)
> >  {
> > dev_dbg(>dev, "PORT HDR Init.\n");
> >
> > -   return 0;
> > +   fpga_port_reset(pdev);
> 
> So the port will be reset here, which happens during fme_probe().
> IIUC the PR region is empty then, there is just the static region,
> right?

port_hdr_init is invoked during afu_probe() function. The fpga_port_reset
only resets the AFU's state and not empty the PR region. User doesn't need
to program it again after port reset.

The purpose of this reset in port_hdr_init function, is to make sure that we 
could have a clean start whenever the port driver module is loaded. And
similar as the one added in afu release.

> 
> > +
> > +   return sysfs_create_files(>dev.kobj, port_hdr_attrs);
> 
> Greg wrote an article that there could be a race condition caused by
> creating sysfs files this late [1] and I see sysfs_create_files() used
> very sparingly in the kernel.  I'm thinking that fpga-bridge should
> provide a place to create sysfs files earlier by adding an
> attribute_group to fpga_bridge_ops (same for fpga-mgr and fpga-region)
> and then fpga_bridge_register could do bridge->dev.groups =
> br_ops->groups.  I'll put a patch for that out soon.
> 

Hm... I understand there could be a race condition if creates sysfs files late.
Actually the reasons I prefer to have each sub feature to create its own sysfs
files are, 1) if any sub feature is not present, then related init function 
won't 
be invoked and related sysfs files won't be created at all. Then end user could
know which sub features are present by checking these sysfs nodes easily. 
2) Another point of view is about extension of each sub feature, for example,
Some new registers introduced when sub feature's 

RE: [PATCH 0/5] cramfs refresh for embedded usage

[Nicolas Pitre]

On Tue, 15 Aug 2017, Chris Brandt wrote:

> On Tuesday, August 15, 2017 1, Nicolas Pitre wrote:
> > I was able to reproduce. The following patch on top should partially fix
> > it.  I'm trying to figure out how to split a vma and link it properly in
> > the case the vma cannot be mapped entirely. In the mean time shared libs
> > won't be XIP.
> > 
> > 
> > diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c
> > index 5aedbd224e..4c7f01fcd2 100644
> > --- a/fs/cramfs/inode.c
> > +++ b/fs/cramfs/inode.c
> 
> 
> Yes, now I can boot with my rootfs being a XIP cramfs.
> 
> However, like you said, libc is not XIP.

I think I have it working now. Probably learned more about the memory 
management internals than I ever wanted to know. Please try the patch 
below on top of all the previous ones. If it works for you as well then 
I'll rebase and repost the whole thing.

diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c
index 4c7f01fcd2..0b651f985c 100644
--- a/fs/cramfs/inode.c
+++ b/fs/cramfs/inode.c
@@ -321,6 +321,86 @@ static u32 cramfs_get_block_range(struct inode *inode, u32 
pgoff, u32 *pages)
return blockaddr << 2;
 }
 
+/*
+ * It is possible for cramfs_physmem_mmap() to partially populate the mapping
+ * causing page faults in the unmapped area. When that happens, we need to
+ * split the vma so that the unmapped area gets its own vma that can be backed
+ * with actual memory pages and loaded normally. This is necessary because
+ * remap_pfn_range() overwrites vma->vm_pgoff with the pfn and filemap_fault()
+ * no longer works with it. Furthermore this makes /proc/x/maps right.
+ * Q: is there a way to do split vma at mmap() time?
+ */
+static const struct vm_operations_struct cramfs_vmasplit_ops;
+static int cramfs_vmasplit_fault(struct vm_fault *vmf)
+{
+   struct mm_struct *mm = vmf->vma->vm_mm;
+   struct vm_area_struct *vma, *new_vma;
+   unsigned long split_val, split_addr;
+   unsigned int split_pgoff, split_page;
+   int ret;
+
+   /* Retrieve the vma split address and validate it */
+   vma = vmf->vma;
+   split_val = (unsigned long)vma->vm_private_data;
+   split_pgoff = split_val & 0x;
+   split_page = split_val >> 16;
+   split_addr = vma->vm_start + split_page * PAGE_SIZE;
+   pr_debug("fault: addr=%#lx vma=%#lx-%#lx split=%#lx\n",
+vmf->address, vma->vm_start, vma->vm_end, split_addr);
+   if (!split_val || split_addr >= vma->vm_end || vmf->address < 
split_addr)
+   return VM_FAULT_SIGSEGV;
+
+   /* We have some vma surgery to do and need the write lock. */
+   up_read(>mmap_sem);
+   if (down_write_killable(>mmap_sem))
+   return VM_FAULT_RETRY;
+
+   /* Make sure the vma didn't change between the locks */
+   vma = find_vma(mm, vmf->address);
+   if (vma->vm_ops != _vmasplit_ops) {
+   /*
+* Someone else raced with us and could have handled the fault.
+* Let it go back to user space and fault again if necessary.
+*/
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_NOPAGE;
+   }
+
+   /* Split the vma between the directly mapped area and the rest */
+   ret = split_vma(mm, vma, split_addr, 0);
+   if (ret) {
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_OOM;
+   }
+
+   /* The direct vma should no longer ever fault */
+   vma->vm_ops = NULL;
+
+   /* Retrieve the new vma covering the unmapped area */
+   new_vma = find_vma(mm, split_addr);
+   BUG_ON(new_vma == vma);
+   if (!new_vma) {
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_SIGSEGV;
+   }
+
+   /*
+* Readjust the new vma with the actual file based pgoff and
+* process the fault normally on it.
+*/
+   new_vma->vm_pgoff = split_pgoff;
+   new_vma->vm_ops = _file_vm_ops;
+   vmf->vma = new_vma;
+   vmf->pgoff = split_pgoff;
+   vmf->pgoff += (vmf->address - new_vma->vm_start) >> PAGE_SHIFT;
+   downgrade_write(>mmap_sem);
+   return filemap_fault(vmf);
+}
+
+static const struct vm_operations_struct cramfs_vmasplit_ops = {
+   .fault  = cramfs_vmasplit_fault,
+};
+
 static int cramfs_physmem_mmap(struct file *file, struct vm_area_struct *vma)
 {
struct inode *inode = file_inode(file);
@@ -337,6 +417,7 @@ static int cramfs_physmem_mmap(struct file *file, struct 
vm_area_struct *vma)
if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE))
return -EINVAL;
 
+   /* Could COW work here? */
fail_reason = "vma is writable";
if (vma->vm_flags & VM_WRITE)
goto fail;
@@ -364,7 +445,7 @@ static int cramfs_physmem_mmap(struct file *file, struct 
vm_area_struct *vma)
unsigned int partial = offset_in_page(inode->i_size);
if (partial) {
char 

RE: [PATCH 0/5] cramfs refresh for embedded usage

[Nicolas Pitre]

On Tue, 15 Aug 2017, Chris Brandt wrote:

> On Tuesday, August 15, 2017 1, Nicolas Pitre wrote:
> > I was able to reproduce. The following patch on top should partially fix
> > it.  I'm trying to figure out how to split a vma and link it properly in
> > the case the vma cannot be mapped entirely. In the mean time shared libs
> > won't be XIP.
> > 
> > 
> > diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c
> > index 5aedbd224e..4c7f01fcd2 100644
> > --- a/fs/cramfs/inode.c
> > +++ b/fs/cramfs/inode.c
> 
> 
> Yes, now I can boot with my rootfs being a XIP cramfs.
> 
> However, like you said, libc is not XIP.

I think I have it working now. Probably learned more about the memory 
management internals than I ever wanted to know. Please try the patch 
below on top of all the previous ones. If it works for you as well then 
I'll rebase and repost the whole thing.

diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c
index 4c7f01fcd2..0b651f985c 100644
--- a/fs/cramfs/inode.c
+++ b/fs/cramfs/inode.c
@@ -321,6 +321,86 @@ static u32 cramfs_get_block_range(struct inode *inode, u32 
pgoff, u32 *pages)
return blockaddr << 2;
 }
 
+/*
+ * It is possible for cramfs_physmem_mmap() to partially populate the mapping
+ * causing page faults in the unmapped area. When that happens, we need to
+ * split the vma so that the unmapped area gets its own vma that can be backed
+ * with actual memory pages and loaded normally. This is necessary because
+ * remap_pfn_range() overwrites vma->vm_pgoff with the pfn and filemap_fault()
+ * no longer works with it. Furthermore this makes /proc/x/maps right.
+ * Q: is there a way to do split vma at mmap() time?
+ */
+static const struct vm_operations_struct cramfs_vmasplit_ops;
+static int cramfs_vmasplit_fault(struct vm_fault *vmf)
+{
+   struct mm_struct *mm = vmf->vma->vm_mm;
+   struct vm_area_struct *vma, *new_vma;
+   unsigned long split_val, split_addr;
+   unsigned int split_pgoff, split_page;
+   int ret;
+
+   /* Retrieve the vma split address and validate it */
+   vma = vmf->vma;
+   split_val = (unsigned long)vma->vm_private_data;
+   split_pgoff = split_val & 0x;
+   split_page = split_val >> 16;
+   split_addr = vma->vm_start + split_page * PAGE_SIZE;
+   pr_debug("fault: addr=%#lx vma=%#lx-%#lx split=%#lx\n",
+vmf->address, vma->vm_start, vma->vm_end, split_addr);
+   if (!split_val || split_addr >= vma->vm_end || vmf->address < 
split_addr)
+   return VM_FAULT_SIGSEGV;
+
+   /* We have some vma surgery to do and need the write lock. */
+   up_read(>mmap_sem);
+   if (down_write_killable(>mmap_sem))
+   return VM_FAULT_RETRY;
+
+   /* Make sure the vma didn't change between the locks */
+   vma = find_vma(mm, vmf->address);
+   if (vma->vm_ops != _vmasplit_ops) {
+   /*
+* Someone else raced with us and could have handled the fault.
+* Let it go back to user space and fault again if necessary.
+*/
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_NOPAGE;
+   }
+
+   /* Split the vma between the directly mapped area and the rest */
+   ret = split_vma(mm, vma, split_addr, 0);
+   if (ret) {
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_OOM;
+   }
+
+   /* The direct vma should no longer ever fault */
+   vma->vm_ops = NULL;
+
+   /* Retrieve the new vma covering the unmapped area */
+   new_vma = find_vma(mm, split_addr);
+   BUG_ON(new_vma == vma);
+   if (!new_vma) {
+   downgrade_write(>mmap_sem);
+   return VM_FAULT_SIGSEGV;
+   }
+
+   /*
+* Readjust the new vma with the actual file based pgoff and
+* process the fault normally on it.
+*/
+   new_vma->vm_pgoff = split_pgoff;
+   new_vma->vm_ops = _file_vm_ops;
+   vmf->vma = new_vma;
+   vmf->pgoff = split_pgoff;
+   vmf->pgoff += (vmf->address - new_vma->vm_start) >> PAGE_SHIFT;
+   downgrade_write(>mmap_sem);
+   return filemap_fault(vmf);
+}
+
+static const struct vm_operations_struct cramfs_vmasplit_ops = {
+   .fault  = cramfs_vmasplit_fault,
+};
+
 static int cramfs_physmem_mmap(struct file *file, struct vm_area_struct *vma)
 {
struct inode *inode = file_inode(file);
@@ -337,6 +417,7 @@ static int cramfs_physmem_mmap(struct file *file, struct 
vm_area_struct *vma)
if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE))
return -EINVAL;
 
+   /* Could COW work here? */
fail_reason = "vma is writable";
if (vma->vm_flags & VM_WRITE)
goto fail;
@@ -364,7 +445,7 @@ static int cramfs_physmem_mmap(struct file *file, struct 
vm_area_struct *vma)
unsigned int partial = offset_in_page(inode->i_size);
if (partial) {
char 

Re: Possible race in c4.ko

[Carsten Paeth]

Hello Anton,

Thanks for reviewing the code.

This would be right, if the c4 could rise an interrupt at this moment ...

After a reset with c4_reset(), the card will not generate an interrupt,
until firmware has been loaded and the SEND_INIT message has been sent.
c4_load_firmware() -> c4_send_init() sets the card number in the card.

Therefor it's not an issue.

best regards,

calle

Tue, Aug 15, 2017 at 04:22:16PM +0300, Anton Volkov schrieb:
> Hello.
> 
> While searching for races in the Linux kernel I've come across
> "drivers/isdn/hardware/avm/c4.ko" module. Here is a question that I came up
> with while analyzing results. Lines are given using the info from Linux
> v4.12.
> 
> Consider the following case:
> 
> Thread 1:  Thread 2:
> c4_probe
> ->c4_add_card
> request_irq()
>c4_interrupt
>->c4_handle_interrupt
>  ->c4_handle_rx
> card->cardnr = ... cidx = f(card->cardnr)
> (c4.c: line 1227)  (c4.c: line 526)
>if (cidx >= card->nlogcontr) cidx = 0;
>ctrl = >ctrlinfo[cidx].capi_ctrl
> 
> card->cardnr is 0 until it is initialized in c4_add_card(). If at the moment
> of read access in c4_handle_rx() it is still 0, cidx may then be assigned an
> undesirable value and wrong controller may handle messages. Is this case
> feasible from your point of view?
> 
> Thank you for your time.
> 
> -- Anton Volkov
> Linux Verification Center, ISPRAS
> web: http://linuxtesting.org
> e-mail: avol...@ispras.ru

Re: Possible race in c4.ko

[Carsten Paeth]

Hello Anton,

Thanks for reviewing the code.

This would be right, if the c4 could rise an interrupt at this moment ...

After a reset with c4_reset(), the card will not generate an interrupt,
until firmware has been loaded and the SEND_INIT message has been sent.
c4_load_firmware() -> c4_send_init() sets the card number in the card.

Therefor it's not an issue.

best regards,

calle

Tue, Aug 15, 2017 at 04:22:16PM +0300, Anton Volkov schrieb:
> Hello.
> 
> While searching for races in the Linux kernel I've come across
> "drivers/isdn/hardware/avm/c4.ko" module. Here is a question that I came up
> with while analyzing results. Lines are given using the info from Linux
> v4.12.
> 
> Consider the following case:
> 
> Thread 1:  Thread 2:
> c4_probe
> ->c4_add_card
> request_irq()
>c4_interrupt
>->c4_handle_interrupt
>  ->c4_handle_rx
> card->cardnr = ... cidx = f(card->cardnr)
> (c4.c: line 1227)  (c4.c: line 526)
>if (cidx >= card->nlogcontr) cidx = 0;
>ctrl = >ctrlinfo[cidx].capi_ctrl
> 
> card->cardnr is 0 until it is initialized in c4_add_card(). If at the moment
> of read access in c4_handle_rx() it is still 0, cidx may then be assigned an
> undesirable value and wrong controller may handle messages. Is this case
> feasible from your point of view?
> 
> Thank you for your time.
> 
> -- Anton Volkov
> Linux Verification Center, ISPRAS
> web: http://linuxtesting.org
> e-mail: avol...@ispras.ru

Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Byungchul Park]

On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > I see...
> > 
> > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be released
> > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > Task   C : acquired of lock#3 -> wait for completion of barr->done
> 
> >From the stack trace below, this barr->done is for flush_work() in
> lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> 
> > Worker D : wait for wfc.work to be released -> will complete barr->done
> 
> and this barr->done is for work "wfc.work".
> 
> So those two barr->done could not be the same instance, IIUC. Therefore
> the deadlock case is not possible.
> 
> The problem here is all barr->done instances are initialized at
> insert_wq_barrier() and they belongs to the same lock class, to fix

I'm not sure this caused the lockdep warning but, if they belongs to the
same class even though they couldn't be the same instance as you said, I
also think that is another problem and should be fixed.

> this, we need to differ barr->done with different lock classes based on
> the corresponding works.
> 
> How about the this(only compilation test):
> 
> ->8
> diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> index e86733a8b344..d14067942088 100644
> --- a/kernel/workqueue.c
> +++ b/kernel/workqueue.c
> @@ -2431,6 +2431,27 @@ struct wq_barrier {
>   struct task_struct  *task;  /* purely informational */
>  };
>  
> +#ifdef CONFIG_LOCKDEP_COMPLETE
> +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target) 
> \
> +do { 
> \
> + INIT_WORK_ONSTACK(&(barr)->work, func); 
> \
> + __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> \
> + lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> \
> +"(complete)" #barr,  
> \
> +(target)->lockdep_map.key, 1);   
> \
> + __init_completion(>done); 
> \
> + barr->task = current;   
> \
> +} while (0)
> +#else
> +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target) 
> \
> +do { 
> \
> + INIT_WORK_ONSTACK(&(barr)->work, func); 
> \
> + __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> \
> + init_completion(>done);   
> \
> + barr->task = current;   
> \
> +} while (0)
> +#endif
> +
>  static void wq_barrier_func(struct work_struct *work)
>  {
>   struct wq_barrier *barr = container_of(work, struct wq_barrier, work);
> @@ -2474,10 +2495,7 @@ static void insert_wq_barrier(struct pool_workqueue 
> *pwq,
>* checks and call back into the fixup functions where we
>* might deadlock.
>*/
> - INIT_WORK_ONSTACK(>work, wq_barrier_func);
> - __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(>work));
> - init_completion(>done);
> - barr->task = current;
> + INIT_WQ_BARRIER_ONSTACK(barr, wq_barrier_func, target);
>  
>   /*
>* If @target is currently being executed, schedule the

Re: [PATCH v8 00/14] lockdep: Implement crossrelease feature

[Byungchul Park]

On Wed, Aug 16, 2017 at 12:05:31PM +0800, Boqun Feng wrote:
> > I see...
> > 
> > Worker A : acquired of wfc.work -> wait for cpu_hotplug_lock to be released
> > Task   B : acquired of cpu_hotplug_lock -> wait for lock#3 to be released
> > Task   C : acquired of lock#3 -> wait for completion of barr->done
> 
> >From the stack trace below, this barr->done is for flush_work() in
> lru_add_drain_all_cpuslocked(), i.e. for work "per_cpu(lru_add_drain_work)"
> 
> > Worker D : wait for wfc.work to be released -> will complete barr->done
> 
> and this barr->done is for work "wfc.work".
> 
> So those two barr->done could not be the same instance, IIUC. Therefore
> the deadlock case is not possible.
> 
> The problem here is all barr->done instances are initialized at
> insert_wq_barrier() and they belongs to the same lock class, to fix

I'm not sure this caused the lockdep warning but, if they belongs to the
same class even though they couldn't be the same instance as you said, I
also think that is another problem and should be fixed.

> this, we need to differ barr->done with different lock classes based on
> the corresponding works.
> 
> How about the this(only compilation test):
> 
> ->8
> diff --git a/kernel/workqueue.c b/kernel/workqueue.c
> index e86733a8b344..d14067942088 100644
> --- a/kernel/workqueue.c
> +++ b/kernel/workqueue.c
> @@ -2431,6 +2431,27 @@ struct wq_barrier {
>   struct task_struct  *task;  /* purely informational */
>  };
>  
> +#ifdef CONFIG_LOCKDEP_COMPLETE
> +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target) 
> \
> +do { 
> \
> + INIT_WORK_ONSTACK(&(barr)->work, func); 
> \
> + __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> \
> + lockdep_init_map_crosslock((struct lockdep_map *)&(barr)->done.map, 
> \
> +"(complete)" #barr,  
> \
> +(target)->lockdep_map.key, 1);   
> \
> + __init_completion(>done); 
> \
> + barr->task = current;   
> \
> +} while (0)
> +#else
> +# define INIT_WQ_BARRIER_ONSTACK(barr, func, target) 
> \
> +do { 
> \
> + INIT_WORK_ONSTACK(&(barr)->work, func); 
> \
> + __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&(barr)->work));  
> \
> + init_completion(>done);   
> \
> + barr->task = current;   
> \
> +} while (0)
> +#endif
> +
>  static void wq_barrier_func(struct work_struct *work)
>  {
>   struct wq_barrier *barr = container_of(work, struct wq_barrier, work);
> @@ -2474,10 +2495,7 @@ static void insert_wq_barrier(struct pool_workqueue 
> *pwq,
>* checks and call back into the fixup functions where we
>* might deadlock.
>*/
> - INIT_WORK_ONSTACK(>work, wq_barrier_func);
> - __set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(>work));
> - init_completion(>done);
> - barr->task = current;
> + INIT_WQ_BARRIER_ONSTACK(barr, wq_barrier_func, target);
>  
>   /*
>* If @target is currently being executed, schedule the

[PATCH] EDAC, altera: Fix an error handling path in 'altr_edac_device_probe()'

[Christophe JAILLET]

'res' is known to be 0 at this point.
If 'devm_ioremap()' fails, returns -ENOMEM instead of 0 which means
success.

Signed-off-by: Christophe JAILLET 
---
 drivers/edac/altera_edac.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index fa2e5db56d24..346c4987b284 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -747,8 +747,10 @@ static int altr_edac_device_probe(struct platform_device 
*pdev)
drvdata->edac_dev_name = ecc_name;
 
drvdata->base = devm_ioremap(>dev, r->start, resource_size(r));
-   if (!drvdata->base)
+   if (!drvdata->base) {
+   res = -ENOMEM;
goto fail1;
+   }
 
/* Get driver specific data for this EDAC device */
drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
-- 
2.11.0

[PATCH] EDAC, altera: Fix an error handling path in 'altr_edac_device_probe()'

[Christophe JAILLET]

'res' is known to be 0 at this point.
If 'devm_ioremap()' fails, returns -ENOMEM instead of 0 which means
success.

Signed-off-by: Christophe JAILLET 
---
 drivers/edac/altera_edac.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index fa2e5db56d24..346c4987b284 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -747,8 +747,10 @@ static int altr_edac_device_probe(struct platform_device 
*pdev)
drvdata->edac_dev_name = ecc_name;
 
drvdata->base = devm_ioremap(>dev, r->start, resource_size(r));
-   if (!drvdata->base)
+   if (!drvdata->base) {
+   res = -ENOMEM;
goto fail1;
+   }
 
/* Get driver specific data for this EDAC device */
drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
-- 
2.11.0

[PATCH] scsi: aha1542: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/scsi/aha1542.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/aha1542.c b/drivers/scsi/aha1542.c
index a23cc9a..1242179 100644
--- a/drivers/scsi/aha1542.c
+++ b/drivers/scsi/aha1542.c
@@ -986,7 +986,7 @@ static struct isa_driver aha1542_isa_driver = {
 static int isa_registered;
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id aha1542_pnp_ids[] = {
+static const struct pnp_device_id aha1542_pnp_ids[] = {
{ .id = "ADP1542" },
{ .id = "" }
 };
-- 
2.7.4

[PATCH] scsi: ncr5380: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/scsi/g_NCR5380.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/g_NCR5380.c b/drivers/scsi/g_NCR5380.c
index c34fc91..1968d81 100644
--- a/drivers/scsi/g_NCR5380.c
+++ b/drivers/scsi/g_NCR5380.c
@@ -703,7 +703,7 @@ static struct isa_driver generic_NCR5380_isa_driver = {
 };
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id generic_NCR5380_pnp_ids[] = {
+static const struct pnp_device_id generic_NCR5380_pnp_ids[] = {
{ .id = "DTC436e", .driver_data = BOARD_DTC3181E },
{ .id = "" }
 };
-- 
2.7.4

[PATCH] scsi: aha1542: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/scsi/aha1542.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/aha1542.c b/drivers/scsi/aha1542.c
index a23cc9a..1242179 100644
--- a/drivers/scsi/aha1542.c
+++ b/drivers/scsi/aha1542.c
@@ -986,7 +986,7 @@ static struct isa_driver aha1542_isa_driver = {
 static int isa_registered;
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id aha1542_pnp_ids[] = {
+static const struct pnp_device_id aha1542_pnp_ids[] = {
{ .id = "ADP1542" },
{ .id = "" }
 };
-- 
2.7.4

[PATCH] scsi: ncr5380: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/scsi/g_NCR5380.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/g_NCR5380.c b/drivers/scsi/g_NCR5380.c
index c34fc91..1968d81 100644
--- a/drivers/scsi/g_NCR5380.c
+++ b/drivers/scsi/g_NCR5380.c
@@ -703,7 +703,7 @@ static struct isa_driver generic_NCR5380_isa_driver = {
 };
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id generic_NCR5380_pnp_ids[] = {
+static const struct pnp_device_id generic_NCR5380_pnp_ids[] = {
{ .id = "DTC436e", .driver_data = BOARD_DTC3181E },
{ .id = "" }
 };
-- 
2.7.4

Re: [PATCH v7 9/9] sparc64: Add support for ADI (Application Data Integrity)

[David Miller]

From: Khalid Aziz 
Date: Wed,  9 Aug 2017 15:26:02 -0600

> +void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma,
> +   unsigned long addr, pte_t pte)
> +{
 ...
> + tag = tag_start(addr, tag_desc);
> + paddr = pte_val(pte) & _PAGE_PADDR_4V;
> + for (tmp = paddr; tmp < (paddr+PAGE_SIZE); tmp += adi_blksize()) {
> + version1 = (*tag) >> 4;
> + version2 = (*tag) & 0x0f;
> + *tag++ = 0;
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (version1), "r" (tmp),
> +   "i" (ASI_MCD_REAL));
> + tmp += adi_blksize();
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (version2), "r" (tmp),
> +   "i" (ASI_MCD_REAL));
> + }
> + asm volatile("membar #Sync\n\t");

You do a membar here.

> + for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
> + asm volatile("ldxa [%1] %2, %0\n\t"
> + : "=r" (adi_tag)
> + :  "r" (i), "i" (ASI_MCD_REAL));
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (adi_tag), "r" (pto),
> +   "i" (ASI_MCD_REAL));

But not here.

Is this OK?  I suspect you need to add a membar this this second piece
of MCD tag storing code.

Re: [PATCH v7 9/9] sparc64: Add support for ADI (Application Data Integrity)

[David Miller]

From: Khalid Aziz 
Date: Wed,  9 Aug 2017 15:26:02 -0600

> +void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma,
> +   unsigned long addr, pte_t pte)
> +{
 ...
> + tag = tag_start(addr, tag_desc);
> + paddr = pte_val(pte) & _PAGE_PADDR_4V;
> + for (tmp = paddr; tmp < (paddr+PAGE_SIZE); tmp += adi_blksize()) {
> + version1 = (*tag) >> 4;
> + version2 = (*tag) & 0x0f;
> + *tag++ = 0;
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (version1), "r" (tmp),
> +   "i" (ASI_MCD_REAL));
> + tmp += adi_blksize();
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (version2), "r" (tmp),
> +   "i" (ASI_MCD_REAL));
> + }
> + asm volatile("membar #Sync\n\t");

You do a membar here.

> + for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
> + asm volatile("ldxa [%1] %2, %0\n\t"
> + : "=r" (adi_tag)
> + :  "r" (i), "i" (ASI_MCD_REAL));
> + asm volatile("stxa %0, [%1] %2\n\t"
> + :
> + : "r" (adi_tag), "r" (pto),
> +   "i" (ASI_MCD_REAL));

But not here.

Is this OK?  I suspect you need to add a membar this this second piece
of MCD tag storing code.

[PATCH] EDAC, thunderx: Fix an error handling path in 'thunderx_lmc_probe()'

[Christophe JAILLET]

'ret' is known to be 0 at this point.
If 'ioremap()' fails, returns -ENOMEM instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/edac/thunderx_edac.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c
index c8e8b9fd4772..00b89f057695 100644
--- a/drivers/edac/thunderx_edac.c
+++ b/drivers/edac/thunderx_edac.c
@@ -779,6 +779,7 @@ static int thunderx_lmc_probe(struct pci_dev *pdev,
 
if (!l2c_ioaddr) {
dev_err(>dev, "Cannot map L2C_CTL\n");
+   ret = -ENOMEM;
goto err_free;
}
 
-- 
2.11.0

[PATCH] EDAC, thunderx: Fix an error handling path in 'thunderx_lmc_probe()'

[Christophe JAILLET]

'ret' is known to be 0 at this point.
If 'ioremap()' fails, returns -ENOMEM instead of 0 which means success.

Signed-off-by: Christophe JAILLET 
---
 drivers/edac/thunderx_edac.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c
index c8e8b9fd4772..00b89f057695 100644
--- a/drivers/edac/thunderx_edac.c
+++ b/drivers/edac/thunderx_edac.c
@@ -779,6 +779,7 @@ static int thunderx_lmc_probe(struct pci_dev *pdev,
 
if (!l2c_ioaddr) {
dev_err(>dev, "Cannot map L2C_CTL\n");
+   ret = -ENOMEM;
goto err_free;
}
 
-- 
2.11.0

[PATCH] watchdog: sc1200: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/watchdog/sc1200wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c
index b34d3d5..8e4e2fc 100644
--- a/drivers/watchdog/sc1200wdt.c
+++ b/drivers/watchdog/sc1200wdt.c
@@ -342,7 +342,7 @@ static int __init sc1200wdt_probe(void)
 
 #if defined CONFIG_PNP
 
-static struct pnp_device_id scl200wdt_pnp_devices[] = {
+static const struct pnp_device_id scl200wdt_pnp_devices[] = {
/* National Semiconductor PC87307/PC97307 watchdog component */
{.id = "NSC0800", .driver_data = 0},
{.id = ""},
-- 
2.7.4

[PATCH] watchdog: sc1200: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/watchdog/sc1200wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c
index b34d3d5..8e4e2fc 100644
--- a/drivers/watchdog/sc1200wdt.c
+++ b/drivers/watchdog/sc1200wdt.c
@@ -342,7 +342,7 @@ static int __init sc1200wdt_probe(void)
 
 #if defined CONFIG_PNP
 
-static struct pnp_device_id scl200wdt_pnp_devices[] = {
+static const struct pnp_device_id scl200wdt_pnp_devices[] = {
/* National Semiconductor PC87307/PC97307 watchdog component */
{.id = "NSC0800", .driver_data = 0},
{.id = ""},
-- 
2.7.4

[PATCH] net: 3c509: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/net/ethernet/3com/3c509.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/3com/3c509.c 
b/drivers/net/ethernet/3com/3c509.c
index f66c971..077d01d 100644
--- a/drivers/net/ethernet/3com/3c509.c
+++ b/drivers/net/ethernet/3com/3c509.c
@@ -392,7 +392,7 @@ static struct isa_driver el3_isa_driver = {
 static int isa_registered;
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id el3_pnp_ids[] = {
+static const struct pnp_device_id el3_pnp_ids[] = {
{ .id = "TCM5090" }, /* 3Com Etherlink III (TP) */
{ .id = "TCM5091" }, /* 3Com Etherlink III */
{ .id = "TCM5094" }, /* 3Com Etherlink III (combo) */
-- 
2.7.4

[PATCH] net: 3c509: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/net/ethernet/3com/3c509.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/3com/3c509.c 
b/drivers/net/ethernet/3com/3c509.c
index f66c971..077d01d 100644
--- a/drivers/net/ethernet/3com/3c509.c
+++ b/drivers/net/ethernet/3com/3c509.c
@@ -392,7 +392,7 @@ static struct isa_driver el3_isa_driver = {
 static int isa_registered;
 
 #ifdef CONFIG_PNP
-static struct pnp_device_id el3_pnp_ids[] = {
+static const struct pnp_device_id el3_pnp_ids[] = {
{ .id = "TCM5090" }, /* 3Com Etherlink III (TP) */
{ .id = "TCM5091" }, /* 3Com Etherlink III */
{ .id = "TCM5094" }, /* 3Com Etherlink III (combo) */
-- 
2.7.4

Re: [PATCH] ASoC: Medfield: Delete an error message for a failed memory allocation in snd_mfld_mc_probe()

[Vinod Koul]

On Fri, Aug 11, 2017 at 11:33:56AM +0200, SF Markus Elfring wrote:
> From: Markus Elfring 
> Date: Fri, 11 Aug 2017 11:25:41 +0200
> 
> Omit an extra message for a memory allocation failure in this function.
> 
> This issue was detected by using the Coccinelle software.

Acked-By: Vinod Koul 

> 
> Link: 
> http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
> Signed-off-by: Markus Elfring 
> ---
>  sound/soc/intel/boards/mfld_machine.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/sound/soc/intel/boards/mfld_machine.c 
> b/sound/soc/intel/boards/mfld_machine.c
> index 4e08885f37aa..6f44acfb4aae 100644
> --- a/sound/soc/intel/boards/mfld_machine.c
> +++ b/sound/soc/intel/boards/mfld_machine.c
> @@ -376,10 +376,8 @@ static int snd_mfld_mc_probe(struct platform_device 
> *pdev)
>   /* audio interrupt base of SRAM location where
>* interrupts are stored by System FW */
>   mc_drv_ctx = devm_kzalloc(>dev, sizeof(*mc_drv_ctx), GFP_ATOMIC);
> - if (!mc_drv_ctx) {
> - pr_err("allocation failed\n");
> + if (!mc_drv_ctx)
>   return -ENOMEM;
> - }
>  
>   irq_mem = platform_get_resource_byname(
>   pdev, IORESOURCE_MEM, "IRQ_BASE");
> -- 
> 2.14.0
> 

-- 
~Vinod

Re: [PATCH] ASoC: Medfield: Delete an error message for a failed memory allocation in snd_mfld_mc_probe()

[Vinod Koul]

On Fri, Aug 11, 2017 at 11:33:56AM +0200, SF Markus Elfring wrote:
> From: Markus Elfring 
> Date: Fri, 11 Aug 2017 11:25:41 +0200
> 
> Omit an extra message for a memory allocation failure in this function.
> 
> This issue was detected by using the Coccinelle software.

Acked-By: Vinod Koul 

> 
> Link: 
> http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
> Signed-off-by: Markus Elfring 
> ---
>  sound/soc/intel/boards/mfld_machine.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/sound/soc/intel/boards/mfld_machine.c 
> b/sound/soc/intel/boards/mfld_machine.c
> index 4e08885f37aa..6f44acfb4aae 100644
> --- a/sound/soc/intel/boards/mfld_machine.c
> +++ b/sound/soc/intel/boards/mfld_machine.c
> @@ -376,10 +376,8 @@ static int snd_mfld_mc_probe(struct platform_device 
> *pdev)
>   /* audio interrupt base of SRAM location where
>* interrupts are stored by System FW */
>   mc_drv_ctx = devm_kzalloc(>dev, sizeof(*mc_drv_ctx), GFP_ATOMIC);
> - if (!mc_drv_ctx) {
> - pr_err("allocation failed\n");
> + if (!mc_drv_ctx)
>   return -ENOMEM;
> - }
>  
>   irq_mem = platform_get_resource_byname(
>   pdev, IORESOURCE_MEM, "IRQ_BASE");
> -- 
> 2.14.0
> 

-- 
~Vinod

[PATCH] PNP: ide: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/ide/ide-pnp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ide/ide-pnp.c b/drivers/ide/ide-pnp.c
index f5f2b62..859ddab 100644
--- a/drivers/ide/ide-pnp.c
+++ b/drivers/ide/ide-pnp.c
@@ -22,7 +22,7 @@
 #define DRV_NAME "ide-pnp"
 
 /* Add your devices here :)) */
-static struct pnp_device_id idepnp_devices[] = {
+static const struct pnp_device_id idepnp_devices[] = {
/* Generic ESDI/IDE/ATA compatible hard disk controller */
{.id = "PNP0600", .driver_data = 0},
{.id = ""}
-- 
2.7.4

[PATCH] PNP: ide: constify pnp_device_id

[Arvind Yadav]

pnp_device_id are not supposed to change at runtime. All functions
working with pnp_device_id provided by  work with
const pnp_device_id. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav 
---
 drivers/ide/ide-pnp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ide/ide-pnp.c b/drivers/ide/ide-pnp.c
index f5f2b62..859ddab 100644
--- a/drivers/ide/ide-pnp.c
+++ b/drivers/ide/ide-pnp.c
@@ -22,7 +22,7 @@
 #define DRV_NAME "ide-pnp"
 
 /* Add your devices here :)) */
-static struct pnp_device_id idepnp_devices[] = {
+static const struct pnp_device_id idepnp_devices[] = {
/* Generic ESDI/IDE/ATA compatible hard disk controller */
{.id = "PNP0600", .driver_data = 0},
{.id = ""}
-- 
2.7.4

Re: [PATCH v7 2/9] mm, swap: Add infrastructure for saving page metadata on swap

[David Miller]

From: Khalid Aziz 
Date: Wed,  9 Aug 2017 15:25:55 -0600

> @@ -1399,6 +1399,12 @@ static bool try_to_unmap_one(struct page *page, struct 
> vm_area_struct *vma,
>   (flags & TTU_MIGRATION)) {
>   swp_entry_t entry;
>   pte_t swp_pte;
> +
> + if (arch_unmap_one(mm, vma, address, pteval) < 0) {
> + set_pte_at(mm, address, pvmw.pte, pteval);
> + ret = false;
> + page_vma_mapped_walk_done();
> + break;
>   /*
>* Store the pfn of the page in a special migration
>* pte. do_swap_page() will wait until the migration
> @@ -1410,6 +1416,7 @@ static bool try_to_unmap_one(struct page *page, struct 
> vm_area_struct *vma,
>   if (pte_soft_dirty(pteval))
>   swp_pte = pte_swp_mksoft_dirty(swp_pte);
>   set_pte_at(mm, address, pvmw.pte, swp_pte);
> + }

This basic block doesn't look right.  I think the new closing brace is
intended to be right after the new break; statement.  If not at the
very least the indentation of the existing code in there needs to be
adjusted.

[PATCH v2 0/5] K2G: Add QSPI support

[Vignesh R]

This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
The patches enhance the existing cadence-quadspi driver to support
loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.


Changes in v2:
* Drop DT patches. Will be sent as separate series as requested by
 maintainer.
* Split binding docs into separate patches.
* Address comments by Rob Herring.

Vignesh R (5):
  mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
circuit
  mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support

 .../devicetree/bindings/mtd/cadence-quadspi.txt|  7 +++-
 drivers/mtd/spi-nor/cadence-quadspi.c  | 46 --
 2 files changed, 49 insertions(+), 4 deletions(-)

-- 
2.14.1

Re: [PATCH v7 2/9] mm, swap: Add infrastructure for saving page metadata on swap

[David Miller]

From: Khalid Aziz 
Date: Wed,  9 Aug 2017 15:25:55 -0600

> @@ -1399,6 +1399,12 @@ static bool try_to_unmap_one(struct page *page, struct 
> vm_area_struct *vma,
>   (flags & TTU_MIGRATION)) {
>   swp_entry_t entry;
>   pte_t swp_pte;
> +
> + if (arch_unmap_one(mm, vma, address, pteval) < 0) {
> + set_pte_at(mm, address, pvmw.pte, pteval);
> + ret = false;
> + page_vma_mapped_walk_done();
> + break;
>   /*
>* Store the pfn of the page in a special migration
>* pte. do_swap_page() will wait until the migration
> @@ -1410,6 +1416,7 @@ static bool try_to_unmap_one(struct page *page, struct 
> vm_area_struct *vma,
>   if (pte_soft_dirty(pteval))
>   swp_pte = pte_swp_mksoft_dirty(swp_pte);
>   set_pte_at(mm, address, pvmw.pte, swp_pte);
> + }

This basic block doesn't look right.  I think the new closing brace is
intended to be right after the new break; statement.  If not at the
very least the indentation of the existing code in there needs to be
adjusted.

[PATCH v2 0/5] K2G: Add QSPI support

[Vignesh R]

This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
The patches enhance the existing cadence-quadspi driver to support
loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.


Changes in v2:
* Drop DT patches. Will be sent as separate series as requested by
 maintainer.
* Split binding docs into separate patches.
* Address comments by Rob Herring.

Vignesh R (5):
  mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
circuit
  mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support

 .../devicetree/bindings/mtd/cadence-quadspi.txt|  7 +++-
 drivers/mtd/spi-nor/cadence-quadspi.c  | 46 --
 2 files changed, 49 insertions(+), 4 deletions(-)

-- 
2.14.1

[PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R 
---
v2:
Split binding doc to separate patch
Use data pointer to indicate write delay.

 drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..bb0cb02a6938 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -38,6 +38,9 @@
 #define CQSPI_NAME "cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT   16
 
+/* Quirks */
+#define CQSPI_NEEDS_WR_DELAY   BIT(0)
+
 struct cqspi_st;
 
 struct cqspi_flash_pdata {
@@ -76,6 +79,7 @@ struct cqspi_st {
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
+   u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor 
*nor,
reinit_completion(>transfer_complete);
writel(CQSPI_REG_INDIRECTWR_START_MASK,
   reg_base + CQSPI_REG_INDIRECTWR);
+   /*
+* As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+* Controller programming sequence, couple of cycles of
+* QSPI_REF_CLK delay is required for the above bit to
+* be internally synchronized by the QSPI module. Provide 5
+* cycles of delay.
+*/
+   if (cqspi->wr_delay)
+   ndelay(cqspi->wr_delay);
 
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
@@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
struct cqspi_st *cqspi;
struct resource *res;
struct resource *res_ahb;
+   u32 data;
int ret;
int irq;
 
@@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
}
 
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+   data  = (u32)of_device_get_match_data(>dev);
+   if (data & CQSPI_NEEDS_WR_DELAY)
+   cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+  cqspi->master_ref_clk_hz);
 
ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
   pdev->name, cqspi);
@@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 #endif
 
 static const struct of_device_id cqspi_dt_ids[] = {
-   {.compatible = "cdns,qspi-nor",},
+   {
+   .compatible = "cdns,qspi-nor",
+   .data = (void *)0,
+   },
+   {
+   .compatible = "ti,k2g-qspi",
+   .data = (void *)CQSPI_NEEDS_WR_DELAY,
+   },
{ /* end of table */ }
 };
 
-- 
2.14.1

[PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R 
---
v2:
Split binding doc to separate patch
Use data pointer to indicate write delay.

 drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..bb0cb02a6938 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -38,6 +38,9 @@
 #define CQSPI_NAME "cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT   16
 
+/* Quirks */
+#define CQSPI_NEEDS_WR_DELAY   BIT(0)
+
 struct cqspi_st;
 
 struct cqspi_flash_pdata {
@@ -76,6 +79,7 @@ struct cqspi_st {
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
+   u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor 
*nor,
reinit_completion(>transfer_complete);
writel(CQSPI_REG_INDIRECTWR_START_MASK,
   reg_base + CQSPI_REG_INDIRECTWR);
+   /*
+* As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+* Controller programming sequence, couple of cycles of
+* QSPI_REF_CLK delay is required for the above bit to
+* be internally synchronized by the QSPI module. Provide 5
+* cycles of delay.
+*/
+   if (cqspi->wr_delay)
+   ndelay(cqspi->wr_delay);
 
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
@@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
struct cqspi_st *cqspi;
struct resource *res;
struct resource *res_ahb;
+   u32 data;
int ret;
int irq;
 
@@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
}
 
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+   data  = (u32)of_device_get_match_data(>dev);
+   if (data & CQSPI_NEEDS_WR_DELAY)
+   cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+  cqspi->master_ref_clk_hz);
 
ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
   pdev->name, cqspi);
@@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 #endif
 
 static const struct of_device_id cqspi_dt_ids[] = {
-   {.compatible = "cdns,qspi-nor",},
+   {
+   .compatible = "cdns,qspi-nor",
+   .data = (void *)0,
+   },
+   {
+   .compatible = "ti,k2g-qspi",
+   .data = (void *)CQSPI_NEEDS_WR_DELAY,
+   },
{ /* end of table */ }
 };
 
-- 
2.14.1

[PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible

[Vignesh R]

Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.

Signed-off-by: Vignesh R 
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..7dbe3bd9ac56 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
 * Cadence Quad SPI controller
 
 Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+   Generic default - "cdns,qspi-nor".
+   For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
 - reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
-- 
2.14.1

[PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit

[Vignesh R]

Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit
for boards which do have QSPI return clock provided. Update binding
documentation for the same.

Signed-off-by: Vignesh R 
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index 7dbe3bd9ac56..bb2075df9b38 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -16,6 +16,9 @@ Required properties:
 
 Optional properties:
 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
 
 Optional subnodes:
 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-- 
2.14.1

[PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit

[Vignesh R]

Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit
for boards which do have QSPI return clock provided. Update binding
documentation for the same.

Signed-off-by: Vignesh R 
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index 7dbe3bd9ac56..bb2075df9b38 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -16,6 +16,9 @@ Required properties:
 
 Optional properties:
 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
 
 Optional subnodes:
 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-- 
2.14.1

[PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible

[Vignesh R]

Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.

Signed-off-by: Vignesh R 
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..7dbe3bd9ac56 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
 * Cadence Quad SPI controller
 
 Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+   Generic default - "cdns,qspi-nor".
+   For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
 - reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
-- 
2.14.1

[PATCH][RFC v2] PM / Hibernate: Disable wathdog when creating snapshot

[Chen Yu]

There is a problem that when counting the pages for creating
the hibernation snapshot will take significant amount of
time, especially on system with large memory. Since the counting
job is performed with irq disabled, this might lead to NMI lockup.
The following warning were found on a system with 1.5TB DRAM:

[ 1124.758184] Freezing user space processes ... (elapsed 0.002 seconds) done.
[ 1124.768721] OOM killer disabled.
[ 1124.847009] PM: Preallocating image memory...
[ 1139.392042] NMI watchdog: Watchdog detected hard LOCKUP on cpu 27
[ 1139.392076] CPU: 27 PID: 3128 Comm: systemd-sleep Not tainted 
4.13.0-0.rc2.git0.1.fc27.x86_64 #1
[ 1139.392077] task: 9f01971ac000 task.stack: b1a3f325c000
[ 1139.392083] RIP: 0010:memory_bm_find_bit+0xf4/0x100
[ 1139.392084] RSP: 0018:b1a3f325fc20 EFLAGS: 0006
[ 1139.392084] RAX:  RBX: 13b83000 RCX: 9fbe89caf000
[ 1139.392085] RDX: b1a3f325fc30 RSI: 3200 RDI: 9fbeae80
[ 1139.392085] RBP: b1a3f325fc40 R08: 13b8 R09: 9fbe89c54878
[ 1139.392085] R10: b1a3f325fc2c R11: 13b83200 R12: 0400
[ 1139.392086] R13: fd552e0c R14: 9fc1bffd31e0 R15: 0202
[ 1139.392086] FS:  7f3189704180() GS:9fbec8ec() 
knlGS:
[ 1139.392087] CS:  0010 DS:  ES:  CR0: 80050033
[ 1139.392087] CR2: 0085da0f7398 CR3: 01771cf9a000 CR4: 007406e0
[ 1139.392088] DR0:  DR1:  DR2: 
[ 1139.392088] DR3:  DR6: fffe0ff0 DR7: 0400
[ 1139.392088] PKRU: 5554
[ 1139.392089] Call Trace:
[ 1139.392092]  ? memory_bm_set_bit+0x29/0x60
[ 1139.392094]  swsusp_set_page_free+0x2b/0x30
[ 1139.392098]  mark_free_pages+0x147/0x1c0
[ 1139.392099]  count_data_pages+0x41/0xa0
[ 1139.392101]  hibernate_preallocate_memory+0x80/0x450
[ 1139.392102]  hibernation_snapshot+0x58/0x410
[ 1139.392103]  hibernate+0x17c/0x310
[ 1139.392104]  state_store+0xdf/0xf0
[ 1139.392107]  kobj_attr_store+0xf/0x20
[ 1139.392111]  sysfs_kf_write+0x37/0x40
[ 1139.392113]  kernfs_fop_write+0x11c/0x1a0
[ 1139.392117]  __vfs_write+0x37/0x170
[ 1139.392121]  ? handle_mm_fault+0xd8/0x230
[ 1139.392122]  vfs_write+0xb1/0x1a0
[ 1139.392123]  SyS_write+0x55/0xc0
[ 1139.392126]  entry_SYSCALL_64_fastpath+0x1a/0xa5

So avoid the NMI lockup by disabling the watchdog temporarily.

Reported-by: Jan Filipcewicz 
Cc: Andrew Morton 
Cc: Michal Hocko 
Cc: Mel Gorman 
Cc: Vlastimil Babka 
Cc: "Rafael J. Wysocki" 
Cc: Len Brown 
Cc: Dan Williams 
Cc: linux...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Chen Yu 
---
 v2: Change the 'feed' action by touch_nmi_watchdog()
 to 'disable' the watchdog by lockup_detector_suspend().
---
 mm/page_alloc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 6d00f74..adff934 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -66,6 +66,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -2537,10 +2538,15 @@ void mark_free_pages(struct zone *zone)
unsigned long flags;
unsigned int order, t;
struct page *page;
+   bool wd_suspended;
 
if (zone_is_empty(zone))
return;
 
+   wd_suspended = lockup_detector_suspend() ? false : true;
+   if (!wd_suspended)
+   pr_warn_once("Failed to disable lockup detector during 
hibernation.\n");
+
spin_lock_irqsave(>lock, flags);
 
max_zone_pfn = zone_end_pfn(zone);
@@ -2566,6 +2572,9 @@ void mark_free_pages(struct zone *zone)
}
}
spin_unlock_irqrestore(>lock, flags);
+
+   if (wd_suspended)
+   lockup_detector_resume();
 }
 #endif /* CONFIG_PM */
 
-- 
2.7.4

[PATCH v2 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support

[Vignesh R]

Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.

Signed-off-by: Vignesh R 
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index c11ced529ddd..4fd6fb9c83b3 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)
return -ENXIO;
}
 
+   pm_runtime_enable(>dev);
+   ret = pm_runtime_get_sync(>dev);
+   if (ret < 0) {
+   pm_runtime_put_noidle(>dev);
+   return ret;
+   }
+
ret = clk_prepare_enable(cqspi->clk);
if (ret) {
dev_err(dev, "Cannot enable QSPI clock.\n");
@@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)
 
clk_disable_unprepare(cqspi->clk);
 
+   pm_runtime_put_sync(>dev);
+   pm_runtime_disable(>dev);
+
return 0;
 }
 
-- 
2.14.1

[PATCH][RFC v2] PM / Hibernate: Disable wathdog when creating snapshot

[Chen Yu]

There is a problem that when counting the pages for creating
the hibernation snapshot will take significant amount of
time, especially on system with large memory. Since the counting
job is performed with irq disabled, this might lead to NMI lockup.
The following warning were found on a system with 1.5TB DRAM:

[ 1124.758184] Freezing user space processes ... (elapsed 0.002 seconds) done.
[ 1124.768721] OOM killer disabled.
[ 1124.847009] PM: Preallocating image memory...
[ 1139.392042] NMI watchdog: Watchdog detected hard LOCKUP on cpu 27
[ 1139.392076] CPU: 27 PID: 3128 Comm: systemd-sleep Not tainted 
4.13.0-0.rc2.git0.1.fc27.x86_64 #1
[ 1139.392077] task: 9f01971ac000 task.stack: b1a3f325c000
[ 1139.392083] RIP: 0010:memory_bm_find_bit+0xf4/0x100
[ 1139.392084] RSP: 0018:b1a3f325fc20 EFLAGS: 0006
[ 1139.392084] RAX:  RBX: 13b83000 RCX: 9fbe89caf000
[ 1139.392085] RDX: b1a3f325fc30 RSI: 3200 RDI: 9fbeae80
[ 1139.392085] RBP: b1a3f325fc40 R08: 13b8 R09: 9fbe89c54878
[ 1139.392085] R10: b1a3f325fc2c R11: 13b83200 R12: 0400
[ 1139.392086] R13: fd552e0c R14: 9fc1bffd31e0 R15: 0202
[ 1139.392086] FS:  7f3189704180() GS:9fbec8ec() 
knlGS:
[ 1139.392087] CS:  0010 DS:  ES:  CR0: 80050033
[ 1139.392087] CR2: 0085da0f7398 CR3: 01771cf9a000 CR4: 007406e0
[ 1139.392088] DR0:  DR1:  DR2: 
[ 1139.392088] DR3:  DR6: fffe0ff0 DR7: 0400
[ 1139.392088] PKRU: 5554
[ 1139.392089] Call Trace:
[ 1139.392092]  ? memory_bm_set_bit+0x29/0x60
[ 1139.392094]  swsusp_set_page_free+0x2b/0x30
[ 1139.392098]  mark_free_pages+0x147/0x1c0
[ 1139.392099]  count_data_pages+0x41/0xa0
[ 1139.392101]  hibernate_preallocate_memory+0x80/0x450
[ 1139.392102]  hibernation_snapshot+0x58/0x410
[ 1139.392103]  hibernate+0x17c/0x310
[ 1139.392104]  state_store+0xdf/0xf0
[ 1139.392107]  kobj_attr_store+0xf/0x20
[ 1139.392111]  sysfs_kf_write+0x37/0x40
[ 1139.392113]  kernfs_fop_write+0x11c/0x1a0
[ 1139.392117]  __vfs_write+0x37/0x170
[ 1139.392121]  ? handle_mm_fault+0xd8/0x230
[ 1139.392122]  vfs_write+0xb1/0x1a0
[ 1139.392123]  SyS_write+0x55/0xc0
[ 1139.392126]  entry_SYSCALL_64_fastpath+0x1a/0xa5

So avoid the NMI lockup by disabling the watchdog temporarily.

Reported-by: Jan Filipcewicz 
Cc: Andrew Morton 
Cc: Michal Hocko 
Cc: Mel Gorman 
Cc: Vlastimil Babka 
Cc: "Rafael J. Wysocki" 
Cc: Len Brown 
Cc: Dan Williams 
Cc: linux...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Chen Yu 
---
 v2: Change the 'feed' action by touch_nmi_watchdog()
 to 'disable' the watchdog by lockup_detector_suspend().
---
 mm/page_alloc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 6d00f74..adff934 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -66,6 +66,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -2537,10 +2538,15 @@ void mark_free_pages(struct zone *zone)
unsigned long flags;
unsigned int order, t;
struct page *page;
+   bool wd_suspended;
 
if (zone_is_empty(zone))
return;
 
+   wd_suspended = lockup_detector_suspend() ? false : true;
+   if (!wd_suspended)
+   pr_warn_once("Failed to disable lockup detector during 
hibernation.\n");
+
spin_lock_irqsave(>lock, flags);
 
max_zone_pfn = zone_end_pfn(zone);
@@ -2566,6 +2572,9 @@ void mark_free_pages(struct zone *zone)
}
}
spin_unlock_irqrestore(>lock, flags);
+
+   if (wd_suspended)
+   lockup_detector_resume();
 }
 #endif /* CONFIG_PM */
 
-- 
2.7.4

[PATCH v2 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support

[Vignesh R]

Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.

Signed-off-by: Vignesh R 
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index c11ced529ddd..4fd6fb9c83b3 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)
return -ENXIO;
}
 
+   pm_runtime_enable(>dev);
+   ret = pm_runtime_get_sync(>dev);
+   if (ret < 0) {
+   pm_runtime_put_noidle(>dev);
+   return ret;
+   }
+
ret = clk_prepare_enable(cqspi->clk);
if (ret) {
dev_err(dev, "Cannot enable QSPI clock.\n");
@@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)
 
clk_disable_unprepare(cqspi->clk);
 
+   pm_runtime_put_sync(>dev);
+   pm_runtime_disable(>dev);
+
return 0;
 }
 
-- 
2.14.1

Re: [PATCH][RFC] PM / Hibernate: Feed NMI wathdog when creating snapshot

[Chen Yu]

On Tue, Aug 15, 2017 at 02:41:19PM +0200, Michal Hocko wrote:
> On Tue 15-08-17 01:19:16, Chen Yu wrote:
> [...]
> > @@ -2561,8 +2562,10 @@ void mark_free_pages(struct zone *zone)
> > unsigned long i;
> >  
> > pfn = page_to_pfn(page);
> > -   for (i = 0; i < (1UL << order); i++)
> > +   for (i = 0; i < (1UL << order); i++) {
> > swsusp_set_page_free(pfn_to_page(pfn + i));
> > +   touch_nmi_watchdog();
> > +   }
> 
> this is rather excessive. Why don't you simply call touch_nmi_watchdog
> once per every 1000 pages? Or once per free_list entry?
> 
> Moreover why don't you need to touch_nmi_watchdog in the loop over all
> pfns in the zone (right above this loop)?
> --
After re-checking the code, I think we can simply disable the watchdog
temporarily, thus to avoid feeding the watchdog in the loop.
I'm sending another version based on this.
Thanks,
Yu
> Michal Hocko
> SUSE Labs

Re: [PATCH][RFC] PM / Hibernate: Feed NMI wathdog when creating snapshot

[Chen Yu]

On Tue, Aug 15, 2017 at 02:41:19PM +0200, Michal Hocko wrote:
> On Tue 15-08-17 01:19:16, Chen Yu wrote:
> [...]
> > @@ -2561,8 +2562,10 @@ void mark_free_pages(struct zone *zone)
> > unsigned long i;
> >  
> > pfn = page_to_pfn(page);
> > -   for (i = 0; i < (1UL << order); i++)
> > +   for (i = 0; i < (1UL << order); i++) {
> > swsusp_set_page_free(pfn_to_page(pfn + i));
> > +   touch_nmi_watchdog();
> > +   }
> 
> this is rather excessive. Why don't you simply call touch_nmi_watchdog
> once per every 1000 pages? Or once per free_list entry?
> 
> Moreover why don't you need to touch_nmi_watchdog in the loop over all
> pfns in the zone (right above this loop)?
> --
After re-checking the code, I think we can simply disable the watchdog
temporarily, thus to avoid feeding the watchdog in the loop.
I'm sending another version based on this.
Thanks,
Yu
> Michal Hocko
> SUSE Labs

[PATCH v2 4/5] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit

[Vignesh R]

Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.

Based on DT parameter cdns,rclk-en enable adapted loop-back circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.

Signed-off-by: Vignesh R 
---

v2:
Split doc update to separate patch

 drivers/mtd/spi-nor/cadence-quadspi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index bb0cb02a6938..c11ced529ddd 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -78,6 +78,7 @@ struct cqspi_st {
boolis_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+   boolrclk_en;
u32 trigger_address;
u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -788,7 +789,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st 
*cqspi)
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
-  const unsigned int bypass,
+  const bool bypass,
   const unsigned int delay)
 {
void __iomem *reg_base = cqspi->iobase;
@@ -852,7 +853,8 @@ static void cqspi_configure(struct spi_nor *nor)
cqspi->sclk = sclk;
cqspi_config_baudrate_div(cqspi);
cqspi_delay(nor);
-   cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+   cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+  f_pdata->read_delay);
}
 
if (switch_cs || switch_ck)
@@ -1049,6 +1051,8 @@ static int cqspi_of_get_pdata(struct platform_device 
*pdev)
return -ENXIO;
}
 
+   cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
return 0;
 }
 
-- 
2.14.1

[PATCH v2 4/5] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit

[Vignesh R]

Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.

Based on DT parameter cdns,rclk-en enable adapted loop-back circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.

Signed-off-by: Vignesh R 
---

v2:
Split doc update to separate patch

 drivers/mtd/spi-nor/cadence-quadspi.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index bb0cb02a6938..c11ced529ddd 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -78,6 +78,7 @@ struct cqspi_st {
boolis_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+   boolrclk_en;
u32 trigger_address;
u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -788,7 +789,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st 
*cqspi)
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
-  const unsigned int bypass,
+  const bool bypass,
   const unsigned int delay)
 {
void __iomem *reg_base = cqspi->iobase;
@@ -852,7 +853,8 @@ static void cqspi_configure(struct spi_nor *nor)
cqspi->sclk = sclk;
cqspi_config_baudrate_div(cqspi);
cqspi_delay(nor);
-   cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+   cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+  f_pdata->read_delay);
}
 
if (switch_cs || switch_ck)
@@ -1049,6 +1051,8 @@ static int cqspi_of_get_pdata(struct platform_device 
*pdev)
return -ENXIO;
}
 
+   cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
return 0;
 }
 
-- 
2.14.1

Re: [PATCH v2] zsmalloc: zs_page_migrate: schedule free_work if zspage is ZS_EMPTY

[Minchan Kim]

On Wed, Aug 16, 2017 at 10:49:14AM +0800, Hui Zhu wrote:
> Hi Minchan,
> 
> 2017-08-16 10:13 GMT+08:00 Minchan Kim :
> > Hi Hui,
> >
> > On Mon, Aug 14, 2017 at 05:56:30PM +0800, Hui Zhu wrote:
> >> After commit e2846124f9a2 ("zsmalloc: zs_page_migrate: skip unnecessary
> >
> > This patch is not merged yet so the hash is invalid.
> > That means we may fold this patch to [1] in current mmotm.
> >
> > [1] 
> > zsmalloc-zs_page_migrate-skip-unnecessary-loops-but-not-return-ebusy-if-zspage-is-not-inuse-fix.patch
> >
> >> loops but not return -EBUSY if zspage is not inuse") zs_page_migrate
> >> can handle the ZS_EMPTY zspage.
> >>
> >> But I got some false in zs_page_isolate:
> >>   if (get_zspage_inuse(zspage) == 0) {
> >>   spin_unlock(>lock);
> >>   return false;
> >>   }
> >
> > I also realized we should make zs_page_isolate succeed on empty zspage
> > because we allow the empty zspage migration from now on.
> > Could you send a patch for that as well?
> 
> OK.  I will make a patch for that later.

Please send the patch so I want to fold it to [1] before Andrew is going
to send [1] to Linus.

Thanks.

Re: [PATCH v2] zsmalloc: zs_page_migrate: schedule free_work if zspage is ZS_EMPTY

[Minchan Kim]

On Wed, Aug 16, 2017 at 10:49:14AM +0800, Hui Zhu wrote:
> Hi Minchan,
> 
> 2017-08-16 10:13 GMT+08:00 Minchan Kim :
> > Hi Hui,
> >
> > On Mon, Aug 14, 2017 at 05:56:30PM +0800, Hui Zhu wrote:
> >> After commit e2846124f9a2 ("zsmalloc: zs_page_migrate: skip unnecessary
> >
> > This patch is not merged yet so the hash is invalid.
> > That means we may fold this patch to [1] in current mmotm.
> >
> > [1] 
> > zsmalloc-zs_page_migrate-skip-unnecessary-loops-but-not-return-ebusy-if-zspage-is-not-inuse-fix.patch
> >
> >> loops but not return -EBUSY if zspage is not inuse") zs_page_migrate
> >> can handle the ZS_EMPTY zspage.
> >>
> >> But I got some false in zs_page_isolate:
> >>   if (get_zspage_inuse(zspage) == 0) {
> >>   spin_unlock(>lock);
> >>   return false;
> >>   }
> >
> > I also realized we should make zs_page_isolate succeed on empty zspage
> > because we allow the empty zspage migration from now on.
> > Could you send a patch for that as well?
> 
> OK.  I will make a patch for that later.

Please send the patch so I want to fold it to [1] before Andrew is going
to send [1] to Linus.

Thanks.

Re: [PATCH v4 11/20] mtd: nand: qcom: enable BAM or ADM mode

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
be enabled before starting any BAM transfers.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 17 ++---
  1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 3d9fd7f..ae873d3 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -163,6 +163,9 @@
  #define NAND_DEV_CMD_VLD_VAL  (READ_START_VLD | WRITE_START_VLD | \
 ERASE_START_VLD | SEQ_READ_START_VLD)
  
+/* NAND_CTRL bits */

+#defineBAM_MODE_EN BIT(0)
+
  /*
   * the NAND controller performs reads/writes with ECC in 516 byte chunks.
   * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -1035,7 +1038,8 @@ static int read_id(struct qcom_nand_host *host, int 
column)
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
nandc_set_reg(nandc, NAND_ADDR0, column);
nandc_set_reg(nandc, NAND_ADDR1, 0);
-   nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+ nandc->props->is_bam ? 0 : DM_EN);


I'm not sure why the above register was configured in read_id in the first 
place. Would
it be required later if we want the controller to support multiple NAND chips? 
If not,
then we could consider dropping this. Anyway, that can be posted as a separate 
patch
later.

Reviewed-by: Archit Taneja 

Thanks,
Archit


nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
  
  	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);

@@ -2408,12 +2412,19 @@ static void qcom_nandc_unalloc(struct 
qcom_nand_controller *nandc)
  /* one time setup of a few nand controller registers */
  static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  {
+   u32 nand_ctrl;
+
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
  
-	/* enable ADM DMA */

-   nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   /* enable ADM or BAM DMA */
+   if (nandc->props->is_bam) {
+   nand_ctrl = nandc_read(nandc, NAND_CTRL);
+   nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+   } else {
+   nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   }
  
  	/* save the original values of these registers */

nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);



--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v4 11/20] mtd: nand: qcom: enable BAM or ADM mode

[Archit Taneja]

On 08/11/2017 05:09 PM, Abhishek Sahu wrote:

1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
be enabled before starting any BAM transfers.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 17 ++---
  1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 3d9fd7f..ae873d3 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -163,6 +163,9 @@
  #define NAND_DEV_CMD_VLD_VAL  (READ_START_VLD | WRITE_START_VLD | \
 ERASE_START_VLD | SEQ_READ_START_VLD)
  
+/* NAND_CTRL bits */

+#defineBAM_MODE_EN BIT(0)
+
  /*
   * the NAND controller performs reads/writes with ECC in 516 byte chunks.
   * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -1035,7 +1038,8 @@ static int read_id(struct qcom_nand_host *host, int 
column)
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
nandc_set_reg(nandc, NAND_ADDR0, column);
nandc_set_reg(nandc, NAND_ADDR1, 0);
-   nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+ nandc->props->is_bam ? 0 : DM_EN);


I'm not sure why the above register was configured in read_id in the first 
place. Would
it be required later if we want the controller to support multiple NAND chips? 
If not,
then we could consider dropping this. Anyway, that can be posted as a separate 
patch
later.

Reviewed-by: Archit Taneja 

Thanks,
Archit


nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
  
  	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);

@@ -2408,12 +2412,19 @@ static void qcom_nandc_unalloc(struct 
qcom_nand_controller *nandc)
  /* one time setup of a few nand controller registers */
  static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  {
+   u32 nand_ctrl;
+
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
  
-	/* enable ADM DMA */

-   nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   /* enable ADM or BAM DMA */
+   if (nandc->props->is_bam) {
+   nand_ctrl = nandc_read(nandc, NAND_CTRL);
+   nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+   } else {
+   nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+   }
  
  	/* save the original values of these registers */

nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);



--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH] sg: recheck MMAP_IO request length with lock held

[Todd Poynor]

Commit 1bc0eb044615 ("scsi: sg: protect accesses to 'reserved' page
array") adds needed concurrency protection for the "reserve" buffer.
Some checks that are initially made outside the lock are replicated once
the lock is taken to ensure the checks and resulting decisions are made
using consistent state.

The check that a request with flag SG_FLAG_MMAP_IO set fits in the
reserve buffer also needs to be performed again under the lock to
ensure the reserve buffer length compared against matches the value in
effect when the request is linked to the reserve buffer.  An -ENOMEM
should be returned in this case, instead of switching over to an
indirect buffer as for non-MMAP_IO requests.

Signed-off-by: Todd Poynor 
---
 drivers/scsi/sg.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index d7ff71e0c85c..3a44b4bc872b 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1735,9 +1735,12 @@ sg_start_req(Sg_request *srp, unsigned char *cmd)
!sfp->res_in_use) {
sfp->res_in_use = 1;
sg_link_reserve(sfp, srp, dxfer_len);
-   } else if ((hp->flags & SG_FLAG_MMAP_IO) && sfp->res_in_use) {
+   } else if (hp->flags & SG_FLAG_MMAP_IO) {
+   res = -EBUSY; /* sfp->res_in_use == 1 */
+   if (dxfer_len > rsv_schp->bufflen)
+   res = -ENOMEM;
mutex_unlock(>f_mutex);
-   return -EBUSY;
+   return res;
} else {
res = sg_build_indirect(req_schp, sfp, dxfer_len);
if (res) {
-- 
2.14.1.480.gb18f417b89-goog

[PATCH] sg: recheck MMAP_IO request length with lock held

[Todd Poynor]

Commit 1bc0eb044615 ("scsi: sg: protect accesses to 'reserved' page
array") adds needed concurrency protection for the "reserve" buffer.
Some checks that are initially made outside the lock are replicated once
the lock is taken to ensure the checks and resulting decisions are made
using consistent state.

The check that a request with flag SG_FLAG_MMAP_IO set fits in the
reserve buffer also needs to be performed again under the lock to
ensure the reserve buffer length compared against matches the value in
effect when the request is linked to the reserve buffer.  An -ENOMEM
should be returned in this case, instead of switching over to an
indirect buffer as for non-MMAP_IO requests.

Signed-off-by: Todd Poynor 
---
 drivers/scsi/sg.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index d7ff71e0c85c..3a44b4bc872b 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1735,9 +1735,12 @@ sg_start_req(Sg_request *srp, unsigned char *cmd)
!sfp->res_in_use) {
sfp->res_in_use = 1;
sg_link_reserve(sfp, srp, dxfer_len);
-   } else if ((hp->flags & SG_FLAG_MMAP_IO) && sfp->res_in_use) {
+   } else if (hp->flags & SG_FLAG_MMAP_IO) {
+   res = -EBUSY; /* sfp->res_in_use == 1 */
+   if (dxfer_len > rsv_schp->bufflen)
+   res = -ENOMEM;
mutex_unlock(>f_mutex);
-   return -EBUSY;
+   return res;
} else {
res = sg_build_indirect(req_schp, sfp, dxfer_len);
if (res) {
-- 
2.14.1.480.gb18f417b89-goog

Re: [PATCH v1 2/6] fs: use on-stack-bio if backing device has BDI_CAP_SYNC capability

[Minchan Kim]

Hi Jens,

On Mon, Aug 14, 2017 at 10:17:09AM -0600, Jens Axboe wrote:
> On 08/14/2017 09:38 AM, Jens Axboe wrote:
> > On 08/14/2017 09:31 AM, Minchan Kim wrote:
> >>> Secondly, generally you don't have slow devices and fast devices
> >>> intermingled when running workloads. That's the rare case.
> >>
> >> Not true. zRam is really popular swap for embedded devices where
> >> one of low cost product has a really poor slow nand compared to
> >> lz4/lzo [de]comression.
> > 
> > I guess that's true for some cases. But as I said earlier, the recycling
> > really doesn't care about this at all. They can happily coexist, and not
> > step on each others toes.
> 
> Dusted it off, result is here against -rc5:
> 
> http://git.kernel.dk/cgit/linux-block/log/?h=cpu-alloc-cache
> 
> I'd like to split the amount of units we cache and the amount of units
> we free, right now they are both CPU_ALLOC_CACHE_SIZE. This means that
> once we hit that count, we free all of the, and then store the one we
> were asked to free. That always keeps 1 local, but maybe it'd make more
> sense to cache just free CPU_ALLOC_CACHE_SIZE/2 (or something like that)
> so that we retain more than 1 per cpu in case and app preempts when
> sleeping for IO and the new task on that CPU then issues IO as well.
> Probably minor.
> 
> Ran a quick test on nullb0 with 32 sync readers. The test was O_DIRECT
> on the block device, so I disabled the __blkdev_direct_IO_simple()
> bypass. With the above branch, we get ~18.0M IOPS, and without we get
> ~14M IOPS. Both ran with iostats disabled, to avoid any interference
> from that.

Looks promising.
If recycling bio works well enough, I think we don't need to introduce
new split in the path for on-stack bio.
I will test your version on zram-swap!

Thanks.

Re: [PATCH v1 2/6] fs: use on-stack-bio if backing device has BDI_CAP_SYNC capability

[Minchan Kim]

Hi Jens,

On Mon, Aug 14, 2017 at 10:17:09AM -0600, Jens Axboe wrote:
> On 08/14/2017 09:38 AM, Jens Axboe wrote:
> > On 08/14/2017 09:31 AM, Minchan Kim wrote:
> >>> Secondly, generally you don't have slow devices and fast devices
> >>> intermingled when running workloads. That's the rare case.
> >>
> >> Not true. zRam is really popular swap for embedded devices where
> >> one of low cost product has a really poor slow nand compared to
> >> lz4/lzo [de]comression.
> > 
> > I guess that's true for some cases. But as I said earlier, the recycling
> > really doesn't care about this at all. They can happily coexist, and not
> > step on each others toes.
> 
> Dusted it off, result is here against -rc5:
> 
> http://git.kernel.dk/cgit/linux-block/log/?h=cpu-alloc-cache
> 
> I'd like to split the amount of units we cache and the amount of units
> we free, right now they are both CPU_ALLOC_CACHE_SIZE. This means that
> once we hit that count, we free all of the, and then store the one we
> were asked to free. That always keeps 1 local, but maybe it'd make more
> sense to cache just free CPU_ALLOC_CACHE_SIZE/2 (or something like that)
> so that we retain more than 1 per cpu in case and app preempts when
> sleeping for IO and the new task on that CPU then issues IO as well.
> Probably minor.
> 
> Ran a quick test on nullb0 with 32 sync readers. The test was O_DIRECT
> on the block device, so I disabled the __blkdev_direct_IO_simple()
> bypass. With the above branch, we get ~18.0M IOPS, and without we get
> ~14M IOPS. Both ran with iostats disabled, to avoid any interference
> from that.

Looks promising.
If recycling bio works well enough, I think we don't need to introduce
new split in the path for on-stack bio.
I will test your version on zram-swap!

Thanks.