Re: [PATCHv2] x86/boot/KASLR: skip the specified crashkernel reserved region
On Fri, Mar 22, 2019 at 4:34 PM Baoquan He wrote:
>
> On 03/22/19 at 03:52pm, Baoquan He wrote:
> > On 03/22/19 at 03:43pm, Pingfan Liu wrote:
> > > > > +/* parse crashkernel=x@y option */
> > > > > +static void mem_avoid_crashkernel_simple(char *option)
> > > >
> > > > Chao ever mentioned this, I want to ask again, why does it has to be
> > > > xxx_simple()?
> > > >
> > > Seems that I had replied Chao's question in another email. The naming
> > > follows the function parse_crashkernel_simple(), as the notes above
> >
> >
> > Sorry, I don't get. typo?
>
> OK, I misunderstood it. We do have parse_crashkernel_simple() to handle
> crashkernel=size[@offset] case, to differente with other complicated
> cases, like crashkernel=size,[high|low],
>
> Then I am fine with this naming. Soryy about the noise.
>
> By the way, do you think if we should take care of this case:
> crashkernel=:[,:,...][@offset]
>
> It can also specify @offset. Not sure if it's too complicated, you may
> have a investigation.
>
OK, I will try it.
> These two cases have dependency on your crashkernel=X bug fix patch.
No, crashkernel=x@y should have no dependcy on crashkernel=X, the
later one relies on memblock searching.
> The current code only allow crashkernel= to reserve under 896MB. I
> noticed Boris has agreed on the solution. Maybe you can repost a new
> version based on the discussion.
I will sync with Dave to see whether he will post the new version.
Thank you for kindly review.
Regards,
Pingfan
>
> http://lkml.kernel.org/r/1548047768-7656-1-git-send-email-kernelf...@gmail.com
> [PATCHv7] x86/kdump: bugfix, make the behavior of crashkernel=X consistent
> with kaslr
>
> Thanks
> Baoquan
>
> >
> > > the definition
> > > /*
> > > * That function parses "simple" (old) crashkernel command lines like
> > > *
> > > * crashkernel=size[@offset]
> >
> > Hmm, should only crashkernel=size@offset be cared? crashkernel=size will
> > auto finding a place to reserve, and that is after KASLR.
> >
> > > *
> > > * It returns 0 on success and -EINVAL on failure.
> > > */
> > > static int __init parse_crashkernel_simple(char *cmdline,
> > >
> > > Do you have alternative suggestion?
> > >
> > > > Except of these, patch looks good to me. It's a nice catch, and only
> > > > need a simple fix based on the current code.
> > > >
> > > Thank you for the kindly review.
> > >
> > > Regards,
> > > Pingfan
> > >
> > > > Thanks
> > > > Baoquan
> > > >
> > > > > +{
> > > > > + unsigned long long crash_size, crash_base;
> > > > > + char *cur = option;
> > > > > +
> > > > > + crash_size = memparse(option, );
> > > > > + if (option == cur)
> > > > > + return;
> > > > > +
> > > > > + if (*cur == '@') {
> > > > > + option = cur + 1;
> > > > > + crash_base = memparse(option, );
> > > > > + if (option == cur)
> > > > > + return;
> > > > > + mem_avoid[MEM_AVOID_CRASHKERNEL].start = crash_base;
> > > > > + mem_avoid[MEM_AVOID_CRASHKERNEL].size = crash_size;
> > > > > + }
> > > > > +}
> > > > >
> > > > > static void handle_mem_options(void)
> > > > > {
> > > > > @@ -250,7 +270,7 @@ static void handle_mem_options(void)
> > > > > u64 mem_size;
> > > > >
> > > > > if (!strstr(args, "memmap=") && !strstr(args, "mem=") &&
> > > > > - !strstr(args, "hugepages"))
> > > > > + !strstr(args, "hugepages") && !strstr(args,
> > > > > "crashkernel="))
> > > > > return;
> > > > >
> > > > > tmp_cmdline = malloc(len + 1);
> > > > > @@ -286,6 +306,8 @@ static void handle_mem_options(void)
> > > > > goto out;
> > > > >
> > > > > mem_limit = mem_size;
> > > > > + } else if (strstr(param, "crashkernel")) {
> > > > > + mem_avoid_crashkernel_simple(val);
> > > > > }
> > > > > }
> > > > >
> > > > > @@ -414,7 +436,7 @@ static void mem_avoid_init(unsigned long input,
> > > > > unsigned long input_size,
> > > > >
> > > > > /* We don't need to set a mapping for setup_data. */
> > > > >
> > > > > - /* Mark the memmap regions we need to avoid */
> > > > > + /* Mark the regions we need to avoid */
> > > > > handle_mem_options();
> > > > >
> > > > > #ifdef CONFIG_X86_VERBOSE_BOOTUP
> > > > > --
> > > > > 2.7.4
> > > > >
Re: [PATCH] dma:xgene-dma:move spin_lock_bh to spin_lock in tasklet
On 20-03-19, 00:45, Jeff Xie wrote: > It is unnecessary to call spin_lock_bh in a tasklet. 1. Please use the right subsystem name, dmaengine: xxx (you cna find that by git log on that subsystem) 2. Space after each :, like dmaengine: xgene-dma: move... 3. Please explain a bit more about the change on why it is unnecessary :) Nevertheless, I have fixed 1 & 2 above and applied it -- ~Vinod
[PATCH V2 4/8] mtip32xx: use blk_mq_queue_tag_inflight_iter
blk_mq_tagset_busy_iter is not safe that it could get stale request in tags->rqs[]. Use blk_mq_queue_tag_inflight_iter here. Signed-off-by: Jianchao Wang --- drivers/block/mtip32xx/mtip32xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/block/mtip32xx/mtip32xx.c b/drivers/block/mtip32xx/mtip32xx.c index 83302ec..103e691 100644 --- a/drivers/block/mtip32xx/mtip32xx.c +++ b/drivers/block/mtip32xx/mtip32xx.c @@ -2771,12 +2771,12 @@ static int mtip_service_thread(void *data) blk_mq_quiesce_queue(dd->queue); - blk_mq_tagset_busy_iter(>tags, mtip_queue_cmd, dd); + blk_mq_queue_tag_inflight_iter(dd->queue, mtip_queue_cmd, dd); set_bit(MTIP_PF_ISSUE_CMDS_BIT, >port->flags); if (mtip_device_reset(dd)) - blk_mq_tagset_busy_iter(>tags, + blk_mq_queue_tag_inflight_iter(dd->queue, mtip_abort_cmd, dd); clear_bit(MTIP_PF_TO_ACTIVE_BIT, >port->flags); @@ -3903,7 +3903,7 @@ static int mtip_block_remove(struct driver_data *dd) blk_freeze_queue_start(dd->queue); blk_mq_quiesce_queue(dd->queue); - blk_mq_tagset_busy_iter(>tags, mtip_no_dev_cleanup, dd); + blk_mq_queue_tag_inflight_iter(dd->queue, mtip_no_dev_cleanup, dd); blk_mq_unquiesce_queue(dd->queue); /* -- 2.7.4
[PATCH V2 0/8]: blk-mq: use static_rqs to iterate busy tags
Hi Jens As we know, there is a risk of accesing stale requests when iterate in-flight requests with tags->rqs[] and this has been talked in following thread, [1] https://marc.info/?l=linux-scsi=154511693912752=2 [2] https://marc.info/?l=linux-block=154526189023236=2 A typical sence could be blk_mq_get_request blk_mq_queue_tag_busy_iter -> blk_mq_get_tag -> bt_for_each -> bt_iter -> rq = taags->rqs[] -> rq->q -> blk_mq_rq_ctx_init -> data->hctx->tags->rqs[rq->tag] = rq; The root cause is that there is a window between set bit on tag sbitmap and set tags->rqs[]. This patch would fix this issue by iterating requests with tags->static_rqs[] instead of tags->rqs[] which would be changed dynamically. Moreover, we will try to get a non-zero q_usage_counter before access hctxs and tags and thus could avoid the race with updating nr_hw_queues, switching io scheduler and even queue clean up which are all under a frozen and drained queue. The 1st patch get rid of the useless of synchronize_rcu in __blk_mq_update_nr_hw_queues The 2nd patch modify the blk_mq_queue_tag_busy_iter to use tags->static_rqs[] instead of tags->rqs[] to iterate the busy tags. The 3rd ~ 7th patch change the blk_mq_tagset_busy_iter to blk_mq_queue_tag_busy_iter which is safer The 8th patch get rid of the blk_mq_tagset_busy_iter. Change log V1 -> V2: - Add wrapper to hide the 'infligh' parameter to user based on Sagi's suggestion. - Other misc changes on comment. Jianchao Wang (8) blk-mq: get rid of the synchronize_rcu in blk-mq: use static_rqs instead of rqs to iterate tags blk-mq: use blk_mq_queue_tag_inflight_iter in debugfs mtip32xx: use blk_mq_queue_tag_inflight_iter nbd: use blk_mq_queue_tag_inflight_iter skd: use blk_mq_queue_tag_inflight_iter nvme: use blk_mq_queue_tag_inflight_iter blk-mq: remove blk_mq_tagset_busy_iter diff stat block/blk-mq-debugfs.c| 2 +- block/blk-mq-tag.c| 193 ++ block/blk-mq-tag.h| 4 +- block/blk-mq.c| 31 ++ drivers/block/mtip32xx/mtip32xx.c | 6 +- drivers/block/nbd.c | 2 +- drivers/block/skd_main.c | 4 +- drivers/nvme/host/core.c | 12 +++ drivers/nvme/host/fc.c| 10 +- drivers/nvme/host/nvme.h | 2 + drivers/nvme/host/pci.c | 5 +- drivers/nvme/host/rdma.c | 4 +- drivers/nvme/host/tcp.c | 5 +- drivers/nvme/target/loop.c| 4 +- include/linux/blk-mq.h| 7 +- 15 files changed, 119 insertions(+), 172 deletions(-) Thanks Jianchao
[PATCH V2 7/8] nvme: use blk_mq_queue_tag_inflight_iter
blk_mq_tagset_inflight_iter is not safe that it could get stale request
in tags->rqs[]. Use blk_mq_queue_tag_inflight_iter here. A new helper
interface nvme_iterate_inflight_rqs is introduced to iterate
all of the ns under a ctrl.
Signed-off-by: Jianchao Wang
---
drivers/nvme/host/core.c | 12
drivers/nvme/host/fc.c | 10 +-
drivers/nvme/host/nvme.h | 2 ++
drivers/nvme/host/pci.c| 5 +++--
drivers/nvme/host/rdma.c | 4 ++--
drivers/nvme/host/tcp.c| 5 +++--
drivers/nvme/target/loop.c | 4 ++--
7 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 4706019..d6c53fe 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -3874,6 +3874,18 @@ void nvme_start_queues(struct nvme_ctrl *ctrl)
}
EXPORT_SYMBOL_GPL(nvme_start_queues);
+void nvme_iterate_inflight_rqs(struct nvme_ctrl *ctrl,
+ busy_iter_fn *fn, void *data)
+{
+ struct nvme_ns *ns;
+
+ down_read(>namespaces_rwsem);
+ list_for_each_entry(ns, >namespaces, list)
+ blk_mq_queue_tag_inflight_iter(ns->queue, fn, data);
+ up_read(>namespaces_rwsem);
+}
+EXPORT_SYMBOL_GPL(nvme_iterate_inflight_rqs);
+
int __init nvme_core_init(void)
{
int result = -ENOMEM;
diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c
index f3b9d91..667da72 100644
--- a/drivers/nvme/host/fc.c
+++ b/drivers/nvme/host/fc.c
@@ -2367,7 +2367,7 @@ nvme_fc_complete_rq(struct request *rq)
/*
* This routine is used by the transport when it needs to find active
* io on a queue that is to be terminated. The transport uses
- * blk_mq_tagset_busy_itr() to find the busy requests, which then invoke
+ * blk_mq_queue_tag_inflight_iter() to find the busy requests, which then
invoke
* this routine to kill them on a 1 by 1 basis.
*
* As FC allocates FC exchange for each io, the transport must contact
@@ -2740,7 +2740,7 @@ nvme_fc_delete_association(struct nvme_fc_ctrl *ctrl)
* If io queues are present, stop them and terminate all outstanding
* ios on them. As FC allocates FC exchange for each io, the
* transport must contact the LLDD to terminate the exchange,
-* thus releasing the FC exchange. We use blk_mq_tagset_busy_itr()
+* thus releasing the FC exchange. We use blk_mq_queue_tag_inflight_iter
* to tell us what io's are busy and invoke a transport routine
* to kill them with the LLDD. After terminating the exchange
* the LLDD will call the transport's normal io done path, but it
@@ -2750,7 +2750,7 @@ nvme_fc_delete_association(struct nvme_fc_ctrl *ctrl)
*/
if (ctrl->ctrl.queue_count > 1) {
nvme_stop_queues(>ctrl);
- blk_mq_tagset_busy_iter(>tag_set,
+ nvme_iterate_inflight_rqs(>ctrl,
nvme_fc_terminate_exchange, >ctrl);
}
@@ -2768,11 +2768,11 @@ nvme_fc_delete_association(struct nvme_fc_ctrl *ctrl)
/*
* clean up the admin queue. Same thing as above.
-* use blk_mq_tagset_busy_itr() and the transport routine to
+* use blk_mq_queue_tag_inflight_iter() and the transport routine to
* terminate the exchanges.
*/
blk_mq_quiesce_queue(ctrl->ctrl.admin_q);
- blk_mq_tagset_busy_iter(>admin_tag_set,
+ blk_mq_queue_tag_inflight_iter(ctrl->ctrl.admin_q,
nvme_fc_terminate_exchange, >ctrl);
/* kill the aens as they are a separate path */
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 527d645..4c6bc803 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -445,6 +445,8 @@ void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);
+void nvme_iterate_inflight_rqs(struct nvme_ctrl *ctrl,
+ busy_iter_fn *fn, void *data);
#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index a90cf5d..96faa36 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2430,8 +2430,9 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool
shutdown)
nvme_suspend_queue(>queues[0]);
nvme_pci_disable(dev);
- blk_mq_tagset_busy_iter(>tagset, nvme_cancel_request, >ctrl);
- blk_mq_tagset_busy_iter(>admin_tagset, nvme_cancel_request,
>ctrl);
+ nvme_iterate_inflight_rqs(>ctrl, nvme_cancel_request, >ctrl);
+ blk_mq_queue_tag_inflight_iter(dev->ctrl.admin_q,
+ nvme_cancel_request, >ctrl);
/*
* The driver will not be starting up queues again if shutting down so
diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c
index 11a5eca..5660200 100644
[PATCH V2 2/8] blk-mq: use static_rqs instead of rqs to iterate tags
tags->rqs[] will not been cleaned when free driver tag to avoid
an extra store on a shared area in the per io path. But there
is a window between get driver tag and write tags->rqs[], so we
may see stale rq in tags->rqs[] which may have been freed, as
following case,
blk_mq_get_request blk_mq_queue_tag_busy_iter
-> blk_mq_get_tag
-> bt_for_each
-> bt_iter
-> rq = taags->rqs[]
-> rq->q
-> blk_mq_rq_ctx_init
-> data->hctx->tags->rqs[rq->tag] = rq;
In additiion, tags->rqs[] only contains the requests that get
driver tag. It is not accurate for io-scheduler case when account
busy tags in part_in_flight.
To fix both of them, the blk_mq_queue_tag_busy_iter is changed
in this patch to use tags->static_rqs[] instead of tags->rqs[].
We have to identify whether there is a io scheduler attached to
decide to use hctx->tags or hctx->sched_tags. And we will try to
get a non-zero q_usage_counter before that, then could avoid race
with update nr_hw_queues, switch io-scheduler and even queue cleanup.
Add 'inflight' parameter to determine to iterate in-flight
requests or just busy tags and add a new helper interface
blk_mq_queue_tag_inflight_iter to iterate all of the in-flight
tags and export this interface for drivers.
Signed-off-by: Jianchao Wang
---
block/blk-mq-tag.c | 96 --
block/blk-mq-tag.h | 4 +--
block/blk-mq.c | 27 +-
include/linux/blk-mq.h | 5 +--
4 files changed, 83 insertions(+), 49 deletions(-)
diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c
index 5f28002..bf7b235 100644
--- a/block/blk-mq-tag.c
+++ b/block/blk-mq-tag.c
@@ -216,26 +216,38 @@ struct bt_iter_data {
busy_iter_fn *fn;
void *data;
bool reserved;
+ bool inflight;
};
static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data)
{
struct bt_iter_data *iter_data = data;
struct blk_mq_hw_ctx *hctx = iter_data->hctx;
- struct blk_mq_tags *tags = hctx->tags;
bool reserved = iter_data->reserved;
+ struct blk_mq_tags *tags;
struct request *rq;
+ tags = hctx->sched_tags ? hctx->sched_tags : hctx->tags;
+
if (!reserved)
bitnr += tags->nr_reserved_tags;
- rq = tags->rqs[bitnr];
+ /*
+* Because tags->rqs[] will not been cleaned when free driver tag
+* and there is a window between get driver tag and write tags->rqs[],
+* so we may see stale rq in tags->rqs[] which may have been freed.
+* Using static_rqs[] is safer.
+*/
+ rq = tags->static_rqs[bitnr];
/*
-* We can hit rq == NULL here, because the tagging functions
-* test and set the bit before assigning ->rqs[].
+* There is a small window between get tag and blk_mq_rq_ctx_init,
+* so rq->q and rq->mq_hctx maybe different.
*/
- if (rq && rq->q == hctx->queue)
- return iter_data->fn(hctx, rq, iter_data->data, reserved);
+ if (rq && rq->q == hctx->queue &&
+ rq->mq_hctx == hctx &&
+ (!iter_data->inflight ||
+blk_mq_rq_state(rq) == MQ_RQ_IN_FLIGHT))
+ return iter_data->fn(rq, iter_data->data, reserved);
return true;
}
@@ -246,7 +258,7 @@ static bool bt_iter(struct sbitmap *bitmap, unsigned int
bitnr, void *data)
* or the bitmap_tags member of struct blk_mq_tags.
* @fn:Pointer to the function that will be called for each
request
* associated with @hctx that has been assigned a driver tag.
- * @fn will be called as follows: @fn(@hctx, rq, @data, @reserved)
+ * @fn will be called as follows: @fn(rq, @data, @reserved)
* where rq is a pointer to a request. Return true to continue
* iterating tags, false to stop.
* @data: Will be passed as third argument to @fn.
@@ -254,13 +266,14 @@ static bool bt_iter(struct sbitmap *bitmap, unsigned int
bitnr, void *data)
* bitmap_tags member of struct blk_mq_tags.
*/
static void bt_for_each(struct blk_mq_hw_ctx *hctx, struct sbitmap_queue *bt,
- busy_iter_fn *fn, void *data, bool reserved)
+ busy_iter_fn *fn, void *data, bool reserved, bool
inflight)
{
struct bt_iter_data iter_data = {
.hctx = hctx,
.fn = fn,
.data = data,
.reserved = reserved,
+ .inflight = inflight,
};
sbitmap_for_each_set(>sb, bt_iter, _data);
@@ -362,36 +375,33 @@ void blk_mq_tagset_busy_iter(struct blk_mq_tag_set
*tagset,
EXPORT_SYMBOL(blk_mq_tagset_busy_iter);
/**
- * blk_mq_queue_tag_busy_iter - iterate over all requests with a driver tag
+ * __blk_mq_queue_tag_busy_iter - iterate over all
[PATCH V2 5/8] nbd: use blk_mq_queue_tag_inflight_iter
blk_mq_tagset_busy_iter is not safe that it could get stale request
in tags->rqs[]. Use blk_mq_queue_tag_inflight_iter here.
Signed-off-by: Jianchao Wang
---
drivers/block/nbd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
index 90ba9f4..c48984b 100644
--- a/drivers/block/nbd.c
+++ b/drivers/block/nbd.c
@@ -747,7 +747,7 @@ static bool nbd_clear_req(struct request *req, void *data,
bool reserved)
static void nbd_clear_que(struct nbd_device *nbd)
{
blk_mq_quiesce_queue(nbd->disk->queue);
- blk_mq_tagset_busy_iter(>tag_set, nbd_clear_req, NULL);
+ blk_mq_queue_tag_inflight_iter(nbd->disk->queue, nbd_clear_req, NULL);
blk_mq_unquiesce_queue(nbd->disk->queue);
dev_dbg(disk_to_dev(nbd->disk), "queue cleared\n");
}
--
2.7.4
[PATCH V2 6/8] skd: use blk_mq_queue_tag_inflight_iter
blk_mq_tagset_busy_iter is not safe that it could get stale request
in tags->rqs[]. Use blk_mq_queue_tag_inflight_iter here.
Signed-off-by: Jianchao Wang
---
drivers/block/skd_main.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/block/skd_main.c b/drivers/block/skd_main.c
index 7d3ad6c..0213b19 100644
--- a/drivers/block/skd_main.c
+++ b/drivers/block/skd_main.c
@@ -395,7 +395,7 @@ static int skd_in_flight(struct skd_device *skdev)
{
int count = 0;
- blk_mq_tagset_busy_iter(>tag_set, skd_inc_in_flight, );
+ blk_mq_queue_tag_inflight_iter(skdev->queue, skd_inc_in_flight, );
return count;
}
@@ -1916,7 +1916,7 @@ static bool skd_recover_request(struct request *req, void
*data, bool reserved)
static void skd_recover_requests(struct skd_device *skdev)
{
- blk_mq_tagset_busy_iter(>tag_set, skd_recover_request, skdev);
+ blk_mq_queue_tag_inflight_iter(skdev->queue, skd_recover_request,
skdev);
}
static void skd_isr_msg_from_dev(struct skd_device *skdev)
--
2.7.4
[PATCH V2 8/8] blk-mq: remove blk_mq_tagset_busy_iter
As nobody uses blk_mq_tagset_busy_iter, remove it.
Signed-off-by: Jianchao Wang
---
block/blk-mq-tag.c | 95 --
include/linux/blk-mq.h | 2 --
2 files changed, 97 deletions(-)
diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c
index bf7b235..a6a28dd 100644
--- a/block/blk-mq-tag.c
+++ b/block/blk-mq-tag.c
@@ -279,101 +279,6 @@ static void bt_for_each(struct blk_mq_hw_ctx *hctx,
struct sbitmap_queue *bt,
sbitmap_for_each_set(>sb, bt_iter, _data);
}
-struct bt_tags_iter_data {
- struct blk_mq_tags *tags;
- busy_tag_iter_fn *fn;
- void *data;
- bool reserved;
-};
-
-static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void
*data)
-{
- struct bt_tags_iter_data *iter_data = data;
- struct blk_mq_tags *tags = iter_data->tags;
- bool reserved = iter_data->reserved;
- struct request *rq;
-
- if (!reserved)
- bitnr += tags->nr_reserved_tags;
-
- /*
-* We can hit rq == NULL here, because the tagging functions
-* test and set the bit before assining ->rqs[].
-*/
- rq = tags->rqs[bitnr];
- if (rq && blk_mq_request_started(rq))
- return iter_data->fn(rq, iter_data->data, reserved);
-
- return true;
-}
-
-/**
- * bt_tags_for_each - iterate over the requests in a tag map
- * @tags: Tag map to iterate over.
- * @bt:sbitmap to examine. This is either the breserved_tags
member
- * or the bitmap_tags member of struct blk_mq_tags.
- * @fn:Pointer to the function that will be called for each
started
- * request. @fn will be called as follows: @fn(rq, @data,
- * @reserved) where rq is a pointer to a request. Return true
- * to continue iterating tags, false to stop.
- * @data: Will be passed as second argument to @fn.
- * @reserved: Indicates whether @bt is the breserved_tags member or the
- * bitmap_tags member of struct blk_mq_tags.
- */
-static void bt_tags_for_each(struct blk_mq_tags *tags, struct sbitmap_queue
*bt,
-busy_tag_iter_fn *fn, void *data, bool reserved)
-{
- struct bt_tags_iter_data iter_data = {
- .tags = tags,
- .fn = fn,
- .data = data,
- .reserved = reserved,
- };
-
- if (tags->rqs)
- sbitmap_for_each_set(>sb, bt_tags_iter, _data);
-}
-
-/**
- * blk_mq_all_tag_busy_iter - iterate over all started requests in a tag map
- * @tags: Tag map to iterate over.
- * @fn:Pointer to the function that will be called for each
started
- * request. @fn will be called as follows: @fn(rq, @priv,
- * reserved) where rq is a pointer to a request. 'reserved'
- * indicates whether or not @rq is a reserved request. Return
- * true to continue iterating tags, false to stop.
- * @priv: Will be passed as second argument to @fn.
- */
-static void blk_mq_all_tag_busy_iter(struct blk_mq_tags *tags,
- busy_tag_iter_fn *fn, void *priv)
-{
- if (tags->nr_reserved_tags)
- bt_tags_for_each(tags, >breserved_tags, fn, priv, true);
- bt_tags_for_each(tags, >bitmap_tags, fn, priv, false);
-}
-
-/**
- * blk_mq_tagset_busy_iter - iterate over all started requests in a tag set
- * @tagset:Tag set to iterate over.
- * @fn:Pointer to the function that will be called for each
started
- * request. @fn will be called as follows: @fn(rq, @priv,
- * reserved) where rq is a pointer to a request. 'reserved'
- * indicates whether or not @rq is a reserved request. Return
- * true to continue iterating tags, false to stop.
- * @priv: Will be passed as second argument to @fn.
- */
-void blk_mq_tagset_busy_iter(struct blk_mq_tag_set *tagset,
- busy_tag_iter_fn *fn, void *priv)
-{
- int i;
-
- for (i = 0; i < tagset->nr_hw_queues; i++) {
- if (tagset->tags && tagset->tags[i])
- blk_mq_all_tag_busy_iter(tagset->tags[i], fn, priv);
- }
-}
-EXPORT_SYMBOL(blk_mq_tagset_busy_iter);
-
/**
* __blk_mq_queue_tag_busy_iter - iterate over all busy or inflight tags
* @q: Request queue to examine.
diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h
index dff9bb6..3ba8001 100644
--- a/include/linux/blk-mq.h
+++ b/include/linux/blk-mq.h
@@ -318,8 +318,6 @@ void blk_mq_unquiesce_queue(struct request_queue *q);
void blk_mq_delay_run_hw_queue(struct blk_mq_hw_ctx *hctx, unsigned long
msecs);
bool blk_mq_run_hw_queue(struct blk_mq_hw_ctx *hctx, bool async);
void blk_mq_run_hw_queues(struct request_queue *q, bool async);
-void blk_mq_tagset_busy_iter(struct blk_mq_tag_set *tagset,
- busy_tag_iter_fn *fn, void *priv);
void
[PATCH V2 1/8] blk-mq: get rid of the synchronize_rcu in __blk_mq_update_nr_hw_queues
In commit 530ca2c (blk-mq: Allow blocking queue tag iter callbacks), we try to get a non-zero q_usage_counter to avoid access hctxs that being modified. So the synchronize_rcu is useless and should be removed. Reviewed-by: Ming Lei Signed-off-by: Jianchao Wang --- block/blk-mq-tag.c | 4 +--- block/blk-mq.c | 4 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index a4931fc..5f28002 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -384,9 +384,7 @@ void blk_mq_queue_tag_busy_iter(struct request_queue *q, busy_iter_fn *fn, /* * __blk_mq_update_nr_hw_queues() updates nr_hw_queues and queue_hw_ctx * while the queue is frozen. So we can use q_usage_counter to avoid -* racing with it. __blk_mq_update_nr_hw_queues() uses -* synchronize_rcu() to ensure this function left the critical section -* below. +* racing with it. */ if (!percpu_ref_tryget(>q_usage_counter)) return; diff --git a/block/blk-mq.c b/block/blk-mq.c index a9c1816..2102d91 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -3211,10 +3211,6 @@ static void __blk_mq_update_nr_hw_queues(struct blk_mq_tag_set *set, list_for_each_entry(q, >tag_list, tag_set_list) blk_mq_freeze_queue(q); /* -* Sync with blk_mq_queue_tag_busy_iter. -*/ - synchronize_rcu(); - /* * Switch IO scheduler to 'none', cleaning up the data associated * with the previous scheduler. We will switch back once we are done * updating the new sw to hw queue mappings. -- 2.7.4
[PATCH V2 3/8] blk-mq: use blk_mq_queue_tag_inflight_iter in debugfs
blk_mq_tagset_busy_iter is not safe that it could get stale request
in tags->rqs[]. Use blk_mq_queue_tag_inflight_iter here.
Signed-off-by: Jianchao Wang
---
block/blk-mq-debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/blk-mq-debugfs.c b/block/blk-mq-debugfs.c
index ec1d18c..b7f2538 100644
--- a/block/blk-mq-debugfs.c
+++ b/block/blk-mq-debugfs.c
@@ -438,7 +438,7 @@ static int hctx_busy_show(void *data, struct seq_file *m)
struct blk_mq_hw_ctx *hctx = data;
struct show_busy_params params = { .m = m, .hctx = hctx };
- blk_mq_tagset_busy_iter(hctx->queue->tag_set, hctx_show_busy_rq,
+ blk_mq_queue_tag_inflight_iter(hctx->queue, hctx_show_busy_rq,
);
return 0;
--
2.7.4
Re: [PATCH v2] RISC-V: Always compile mm/init.c with cmodel=medany
Hi Anup,
Sorry for being late to the party. I think one more thing should
move together with setup_vm():
On Mon, Mar 25, 2019 at 03:37:38AM +, Anup Patel wrote:
> The Linux RISC-V 32bit kernel is broken after we moved setup_vm() from
> kernel/setup.c to mm/init.c because Linux RISC-V 32bit kernel by default
> uses cmodel=medlow which results in a non-position-independent setup_vm().
>
> This patch fixes Linux RISC-V 32bit kernel booting by:
> 1. Forcing cmodel=medany for mm/init.c
> 2. Moving remaing MM-related stuff va_pa_offset, pfn_base and
>empty_zero_page from kernel/setup.c to mm/init.c
>
> Fixes: 6f1e9e946f0b ("RISC-V: Move setup_vm() to mm/init.c")
> Suggested-by: Christoph Hellwig
> Suggested-by: Mike Rapoport
> Signed-off-by: Anup Patel
> ---
> v2: Removed CFLAGS_setup.o from kernel/Makefile and replaced SoBs
> ---
> arch/riscv/kernel/Makefile | 2 --
> arch/riscv/kernel/setup.c | 8
> arch/riscv/mm/Makefile | 2 ++
> arch/riscv/mm/init.c | 9 +
> 4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index f13f7f276639..8b9780b6bd7f 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
earlier in this file, there are four lines about ftrace,
5 ifdef CONFIG_FTRACE
6 CFLAGS_REMOVE_ftrace.o = -pg
7 CFLAGS_REMOVE_setup.o = -pg
8 endif
removing "-pg" flag from setup.o was necessary for ftrace to work, since
setup_vm() cannot process the trampoline of ftrace properly.
As setup_vm() is being moved to mm/init.c, you may either mark it with a
"notrace" attribute with its declaration, or adding corresponding CFLAGS_REMOVE*
to mm/Makefile.
> @@ -29,8 +29,6 @@ obj-y += vdso.o
> obj-y+= cacheinfo.o
> obj-y+= vdso/
>
> -CFLAGS_setup.o := -mcmodel=medany
> -
> obj-$(CONFIG_FPU)+= fpu.o
> obj-$(CONFIG_SMP)+= smpboot.o
> obj-$(CONFIG_SMP)+= smp.o
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index ecb654f6a79e..540a331d1376 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -48,14 +48,6 @@ struct screen_info screen_info = {
> };
> #endif
>
> -unsigned long va_pa_offset;
> -EXPORT_SYMBOL(va_pa_offset);
> -unsigned long pfn_base;
> -EXPORT_SYMBOL(pfn_base);
> -
> -unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
> __page_aligned_bss;
> -EXPORT_SYMBOL(empty_zero_page);
> -
> /* The lucky hart to first increment this variable will boot the other cores
> */
> atomic_t hart_lottery;
> unsigned long boot_cpu_hartid;
> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> index eb22ab49b3e0..7307609d405b 100644
> --- a/arch/riscv/mm/Makefile
> +++ b/arch/riscv/mm/Makefile
> @@ -3,3 +3,5 @@ obj-y += fault.o
> obj-y += extable.o
> obj-y += ioremap.o
> obj-y += cacheflush.o
> +
> +CFLAGS_init.o := -mcmodel=medany
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index b379a75ac6a6..7a7c454378cb 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -25,6 +25,10 @@
> #include
> #include
>
> +unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
> + __page_aligned_bss;
> +EXPORT_SYMBOL(empty_zero_page);
> +
> static void __init zone_sizes_init(void)
> {
> unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
> @@ -143,6 +147,11 @@ void __init setup_bootmem(void)
> }
> }
>
> +unsigned long va_pa_offset;
> +EXPORT_SYMBOL(va_pa_offset);
> +unsigned long pfn_base;
> +EXPORT_SYMBOL(pfn_base);
> +
> pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
> pgd_t trampoline_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE);
>
> --
> 2.17.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Alan
Re: Virtio-scsi multiqueue irq affinity
On Sat, Mar 23, 2019 at 06:15:59PM +0100, Thomas Gleixner wrote:
> Peter,
Hi, Thomas,
>
> On Mon, 18 Mar 2019, Peter Xu wrote:
> > I noticed that starting from commit 0d9f0a52c8b9 ("virtio_scsi: use
> > virtio IRQ affinity", 2017-02-27) the virtio scsi driver is using a
> > new way (via irq_create_affinity_masks()) to automatically initialize
> > IRQ affinities for the multi-queues, which is different comparing to
> > all the other virtio devices (like virtio-net, which still uses
> > virtqueue_set_affinity(), which is actually, irq_set_affinity_hint()).
> >
> > Firstly, it will definitely broke some of the userspace programs with
> > that when the scripts wanted to do the bindings explicitly like before
> > and they could simply fail with -EIO now every time when echoing to
> > /proc/irq/N/smp_affinity of any of the multi-queues (see
> > write_irq_affinity()).
>
> Did it break anything? I did not see a report so far. Assumptions about
> potential breakage are not really useful.
It broke some automation scripts e.g. where they tried to bind CPUs to
IRQs before staring IO but these scripts failed early during setup
when trying to echo into the affinity procfs file. Actually I started
to look into this because of such script breakage reported by QEs.
Iinitially it was thought as a kernel bug but later we noticed that
it's a change in policy.
>
> > Is there any specific reason to do it with the new way? Since AFAIU
> > we should still allow the system admins to decide what to do for such
> > configurations, .e.g., what if we only want to provision half of the
> > CPU resources to handle IRQs for a specific virtio-scsi controller?
> > We won't be able to achieve that with current policy. Or, could this
> > be a question for the IRQ system (irq_create_affinity_masks()) in
> > general? Any special considerations behind the big picture?
>
> That has nothing to do with the irq subsystem. That merily provides the
> mechanisms.
>
> The reason behind this is that multi-queue devices set up queues per cpu or
> if not enough queues are available queues per cpu groups. So it does not
> make sense to move the interrupt away from the CPU or the CPU group.
>
> Aside of that in the CPU hotunplug case, interrupts used to be moved to the
> online CPUs which resulted in problems for e.g. hibernation because on
> large systems moving all interrupts to the boot CPU does not work due to
> vector space exhaustion. Also CPU hotunplug is used for power management
> purposes and there it does not make sense either to have the per cpu queues
> of the offlined CPUs moved to the still online CPUs which then end up with
> several queues.
>
> The new way to deal with this is to strictly bind per CPU (per CPU group)
> queues. If the CPU or the last CPU in the group goes offline the following
> happens:
>
> 1) The queue is disabled, i.e. no new requests can be queued
>
> 2) Wait for the outstanding requests to complete
>
> 3) Shut down the interrupt
>
> This avoids having multiple queues moved to the still online CPUs and also
> prevents vector space exhaustion because the shut down interrupt does not
> have to be migrated.
>
> When the CPU (or the first in the group) comes online again:
>
> 1) Reenable the interrupt
>
> 2) Reenable the queue
>
> Hope that helps.
Thanks for explaining everything! It helps a lot, and yes it makes
perfect sense to me.
If no one reported any issue I think either the scripts are not
checking the return code so they might fail silently but it might not
matter much (e.g., if the only thing that a script wants to do is to
spread the CPUs upon the IRQs then the script can simply cancel the
setup procedure of this, and even failing of those echos won't affect
much too), or they're just simpled fixed up later on. Now the only
thing I am unsure about is whether there could be scenarios that we
may not want to use the default policy to spread the cores.
One thing I can think of is the real-time scenario where "isolcpus="
is provided, then logically we should not allow any isolated CPUs to
be bound to any of the multi-queue IRQs. Though Ming Lei and I had a
discussion offlist before and Ming explained to me that as long as the
isolated CPUs do not generate any IO then there will be no IRQ on
those isolated (real-time) CPUs at all. Can we guarantee that? Now
I'm thinking whether the ideal way should be that, when multi-queue is
used with "isolcpus=" then we only spread the queues upon housekeeping
CPUs somehow? Because AFAIU general real-time applications should not
use block IOs at all (and if not those hardware multi-queues running
upon isolated CPUs would probably be a pure waste too because they
could be always idle on the isolated cores where the real-time
application runs).
CCing Ming too.
Thanks,
--
Peter Xu
[PATCH] ARM: dts: imx6qdl: Specify IMX6QDL_CLK_IPG as "ipg" clock for SDMA
Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6QDL_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA functionality(this at least
breaks RAVE SP serdev driver on RDU2). Fix the code to specify
IMX6QDL_CLK_IPG as "ipg" clock for SDMA, to the problem.
Fixes: 25aaa75df1e6 ("dmaengine: imx-sdma: add clock ratio 1:1 check")
Signed-off-by: Andrey Smirnov
Cc: Angus Ainslie (Purism)
Cc: Chris Healy
Cc: Lucas Stach
Cc: Fabio Estevam
Cc: Shawn Guo
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
This probably has been fixed already, so please ignore this patch if
that is the case.
Thanks,
Andrey Smirnov
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9f9aa6e7ed0e..354feba077b2 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -949,7 +949,7 @@
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = < IMX6QDL_CLK_SDMA>,
+ clocks = < IMX6QDL_CLK_IPG>,
< IMX6QDL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
--
2.20.1
Re: [PATCH v2] dmaengine: pl330: introduce debugfs interface
On 17-03-19, 19:03, Katsuhiro Suzuki wrote: > This patch adds debugfs interface to show the relationship between > DMA threads (hardware resource for transferring data) and DMA > channel ID of DMA slave. > > Typically, PL330 has many slaves than number of DMA threads. > So sometimes PL330 cannot allocate DMA threads for all slaves even > if a user specify DMA channel ID in devicetree. This interface will > be useful for checking that DMA threads are allocated or not. > > Below is an output sample: > > $ sudo cat /sys/kernel/debug/ff1f.dmac > PL330 physical channels: > THREAD: CHANNEL: > - > 0 8 > 1 9 > 2 11 > 3 12 > 4 14 > 5 15 > 6 10 > 7 -- > Applied, thanks -- ~Vinod
Re: KASAN: use-after-free Read in path_lookupat
On Sun, Mar 24, 2019 at 06:23:24PM -0700, Linus Torvalds wrote:
> Al, comments? At the very least, if we don't make
> simple_symlink_inode_operations() do that, we should have a *big*
> comment that if it's not part of the inode data, it needs to be
> RCU-delayed.
simple_symlink_inode_operations is red herring here - what matters
is ->i_link being set; those have ->get_link == simple_get_link,
but note that it is *not* called:
res = inode->i_link;
if (!res) {
const char * (*get)(struct dentry *, struct inode *,
struct delayed_call *);
get = inode->i_op->get_link;
if (nd->flags & LOOKUP_RCU) {
res = get(NULL, inode, >done);
if (res == ERR_PTR(-ECHILD)) {
if (unlikely(unlazy_walk(nd)))
return ERR_PTR(-ECHILD);
res = get(dentry, inode, >done);
}
} else {
res = get(dentry, inode, >done);
}
if (IS_ERR_OR_NULL(res))
return res;
}
for traversal and similar for readlink(2). And we certainly don't want
to allocate copies in those cases - it would fuck RCU traversals for
all fast symlinks (i.e. for the majority of symlinks out there).
Actual situation:
* shmem, erofs: OK, kfree() from the thing ->destroy_inode() is calling via
call_rcu().
* befs, ext2, ext4, freevxfs, jfs, orangefs, ufs: OK, coallocated with inode
* debugfs: broken
* jffs2: broken, freeing of f->target should be moved to jffs2_i_callback().
* ubifs: broken, ought to move kfree(ui->data); from ubifs_destroy_inode() to
ubifs_i_callback()
* ceph: broken, needs to move kfree(ci->symlink) from ceph_destroy_inode()
to ceph_i_callback().
* bpf: broken
So we have 5 broken cases, all with the same kind of fix: move freeing
into the RCU-delayed part of ->destroy_inode(); for debugfs and bpf
that requires adding ->alloc_inode()/->destroy_inode(), rather than
relying upon the defaults from fs/inode.c
> Or maybe we could add a final inode callback function for "rcu_free"
> that is called as the RCU-delayed freeing of the inode itself happens?
> And then people could hook into that for freeing the inode->i_link
> data.
You mean, split ->destroy_inode() into immediate and RCU-delayed parts?
There are filesystems where both parts are non-empty - we can't just
switch all ->destroy_inode() work to call_rcu().
> So many choices.. But the current situation seems unnecessarily
> complex for the filesystem, and isn't really documented.
>
> Our documentation currently says for get_link(): "If the body won't go
> away until the inode is gone, nothing else is needed", which is wrong
> (or at least very misleading, since the last "inode is gone" callback
> we have is that evict() function).
s/inode is gone/struct inode is freed/, but it's obviously not clear
enough.
Re: [PATCH 2/3] dmaengine: omap-dma: make omap_dma_filter_fn private
On 08-03-19, 16:32, Peter Ujfalusi wrote: > > > On 07/03/2019 17.16, Arnd Bergmann wrote: > > With the audio driver no longer referring to this function, it > > can be made private to the dmaengine driver itself, and the > > header file removed. Applied, thanks -- ~Vinod
Re: [PATCH 3/3] dmaengine: edma: make edma_filter_fn private
On 07-03-19, 16:16, Arnd Bergmann wrote: > With the audio driver no longer referring to this function, it > can be made private to the dmaengine driver itself, and the > header file removed. Applied, thanks -- ~Vinod
RE: [PATCH v3 2/5] dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle.
>From: Enric Balletbo i Serra > >The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU >general register files to know the DRAM type, so add a phandle to the >syscon that manages these registers. > >Signed-off-by: Enric Balletbo i Serra >Reviewed-by: Chanwoo Choi >Acked-by: Rob Herring >Signed-off-by: Gael PORTAY >--- > >Changes in v3: >- [PATCH v2 2/5] Add Signed-off-by: Gael PORTAY . > >Changes in v2: None > >Changes in v1: >- [RFC 2/10] Add reviewed and acked tags from Chanwoo Choi and Rob Herring > > Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: MyungJoo Ham
Re: [PATCH v3 1/2] dmaengine: tegra210-adma: use devm_clk_*() helpers
On 13-03-19, 17:02, Sameer Pujar wrote: > adma driver is using pm_clk_*() interface for managing clock resources. > With this it is observed that clocks remain ON always. This happens on > Tegra devices which use BPMP co-processor to manage clock resources, > where clocks are enabled during prepare phase. This is necessary because > clocks to BPMP are always blocking. When pm_clk_*() interface is used on > such Tegra devices, clock prepare count is not balanced till remove call > happens for the driver and hence clocks are seen ON always. Thus this > patch replaces pm_clk_*() with devm_clk_*() framework. Both applied, thanks -- ~Vinod
RE: [PATCH v3 1/5] devfreq: rockchip-dfi: Move GRF definitions to a common place.
>From: Enric Balletbo i Serra > >Some rk3399 GRF (Generic Register Files) definitions can be used for >different drivers. Move these definitions to a common include so we >don't need to duplicate these definitions. > >Signed-off-by: Enric Balletbo i Serra >Acked-by: Chanwoo Choi >Signed-off-by: Gael PORTAY >--- > >Changes in v3: >- [PATCH v2 1/5] Add Signed-off-by: Gael PORTAY . > >Changes in v2: >- [PATCH 1/8] Really add Acked-by: Chanwoo Choi . > >Changes in v1: >- [RFC 1/10] Add Acked-by: Chanwoo Choi >- [RFC 1/10] s/Generic/General/ (Robin Murphy) >- [RFC 4/10] Removed from the series. I did not found a use case where not >holding the mutex causes the issue. >- [RFC 7/10] Removed from the series. I did not found a use case where this >matters. > > drivers/devfreq/event/rockchip-dfi.c | 23 +++ > include/soc/rockchip/rk3399_grf.h| 21 + > 2 files changed, 28 insertions(+), 16 deletions(-) > create mode 100644 include/soc/rockchip/rk3399_grf.h > Acked-by: MyungJoo Ham
RE: Re: [PATCH] PM / devfreq: exynos-bus: Suspend all devices on system shutdown
>Hi Chanwoo,
>
>On 2019-03-21 10:19, Chanwoo Choi wrote:
>> On 19. 3. 21. 오후 6:01, Marek Szyprowski wrote:
>>> Force all Exynos buses to safe operation points before doing the system
>>> reboot operation. There are board on which some aggressive power saving
>>> operation points are behind the capabilities of the bootloader to properly
>>> reset the hardware and boot the board. This way one can avoid board crash
>>> early after reboot.
>>>
>>> This fixes reboot issue on OdroidU3 board both with eMMC and SD boot.
>>>
>>> Reported-by: Markus Reichl
>>> Signed-off-by: Marek Szyprowski
>>> ---
>>> This is an alternative to https://patchwork.kernel.org/patch/10781433/
>>> limited only to Exynos-bus driver.
>>> ---
>>> drivers/devfreq/exynos-bus.c | 8
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c
>>> index c25658b26598..486cc5b422f1 100644
>>> --- a/drivers/devfreq/exynos-bus.c
>>> +++ b/drivers/devfreq/exynos-bus.c
>>> @@ -514,6 +514,13 @@ static int exynos_bus_probe(struct platform_device
>>> *pdev)
>>> return ret;
>>> }
>>>
>>> +static void exynos_bus_shutdown(struct platform_device *pdev)
>>> +{
>>> + struct exynos_bus *bus = dev_get_drvdata(>dev);
>>> +
>>> + devfreq_suspend_device(bus->devfreq);
>>> +}
>>> +
>>> #ifdef CONFIG_PM_SLEEP
>>> static int exynos_bus_resume(struct device *dev)
>>> {
>>> @@ -556,6 +563,7 @@ MODULE_DEVICE_TABLE(of, exynos_bus_of_match);
>>>
>>> static struct platform_driver exynos_bus_platdrv = {
>>> .probe = exynos_bus_probe,
>>> + .shutdown = exynos_bus_shutdown,
>>> .driver = {
>>> .name = "exynos-bus",
>>> .pm = _bus_pm,
>>>
>> Actually, I already agreed the previous patch.
>> Also, it looks good to me.
>
>Yes, I know, but MyungJoo had some objections, that's why I prepared
>alternative version.
>
>> Acked-by: Chanwoo Choi
>>
This has become looking good now :)
Acked-by: MyungJoo Ham
Cheers,
MyungJoo
Re: [PATCH v2 4/9] dt-bindings: power: Add rpm power domain bindings for qcs404
On 3/24/2019 11:20 PM, Sibi Sankar wrote: From: Bjorn Andersson Add RPM Power domain bindings for the qcs404 family of SoC [sibis: Add supported rpmpd states for qcs404] Signed-off-by: Sibi Sankar SoB ordering seems wrong. Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/power/qcom,rpmpd.txt | 1 + include/dt-bindings/power/qcom-rpmpd.h| 22 +++ 2 files changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt index 980e5413d18f..172ccf940c5c 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt @@ -6,6 +6,7 @@ which then translates it into a corresponding voltage on a rail Required Properties: - compatible: Should be one of the following * qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC + * qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC - #power-domain-cells: number of cells in Power domain specifier must be 1. diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 87d9c6611682..450378662944 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -36,4 +36,26 @@ #define MSM8996_VDDSSCX 5 #define MSM8996_VDDSSCX_VFC 6 +/* QCS404 Power Domains */ +#define QCS404_VDDMX 0 +#define QCS404_VDDMX_AO1 +#define QCS404_VDDMX_VFL 2 +#define QCS404_LPICX 3 +#define QCS404_LPICX_VFL 4 +#define QCS404_LPIMX 5 +#define QCS404_LPIMX_VFL 6 + +/* RPM SMD Power Domain performance levels */ so unlike in the sdm845 case where we map these levels to (contiguous) corners before passing it over to rpm, we seem to pass these as-is to rpm, right? Does this work if the user passes some value which does not really map to a level defined here? For instance if value passed is 17 for instance do we fall back to 16? +#define RPM_SMD_LEVEL_RETENTION 16 +#define RPM_SMD_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_LEVEL_MIN_SVS 48 +#define RPM_SMD_LEVEL_LOW_SVS 64 +#define RPM_SMD_LEVEL_SVS 128 +#define RPM_SMD_LEVEL_SVS_PLUS192 +#define RPM_SMD_LEVEL_NOM 256 +#define RPM_SMD_LEVEL_NOM_PLUS320 +#define RPM_SMD_LEVEL_TURBO 384 +#define RPM_SMD_LEVEL_TURBO_NO_CPR416 +#define RPM_SMD_LEVEL_BINNING 512 + #endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 2/5] RISC-V: Make setup_vm() independent of GCC code model
On Sat, Mar 23, 2019 at 9:15 PM Mike Rapoport wrote:
>
> On Thu, Mar 21, 2019 at 09:47:47AM +, Anup Patel wrote:
> > The setup_vm() must access kernel symbols in a position independent way
> > because it will be called from head.S with MMU off.
> >
> > If we compile kernel with cmodel=medany then PC-relative addressing will
> > be used in setup_vm() to access kernel symbols so it works perfectly fine.
> >
> > Although, if we compile kernel with cmodel=medlow then either absolute
> > addressing or PC-relative addressing (based on whichever requires fewer
> > instructions) is used to access kernel symbols in setup_vm(). This can
> > break setup_vm() whenever any absolute addressing is used to access
> > kernel symbols.
> >
> > With the movement of setup_vm() from kernel/setup.c to mm/init.c, the
> > setup_vm() is now broken for cmodel=medlow but it works perfectly fine
> > for cmodel=medany.
> >
> > This patch fixes setup_vm() and makes it independent of GCC code model
> > by accessing kernel symbols relative to kernel load address instead of
> > assuming PC-relative addressing.
> >
> > Fixes: 6f1e9e946f0b ("RISC-V: Move setup_vm() to mm/init.c")
> > Signed-off-by: Anup Patel
> > ---
> > arch/riscv/kernel/head.S | 1 +
> > arch/riscv/mm/init.c | 73 ++--
> > 2 files changed, 49 insertions(+), 25 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index fe884cd69abd..7966262b4f9d 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -62,6 +62,7 @@ clear_bss_done:
> >
> > /* Initialize page tables and relocate to virtual addresses */
> > la sp, init_thread_union + THREAD_SIZE
> > + la a0, _start
> > call setup_vm
> > call relocate
> >
> > diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> > index b379a75ac6a6..e38f8195e45b 100644
> > --- a/arch/riscv/mm/init.c
> > +++ b/arch/riscv/mm/init.c
> > @@ -172,55 +172,78 @@ void __set_fixmap(enum fixed_addresses idx,
> > phys_addr_t phys, pgprot_t prot)
> > }
> > }
> >
> > -asmlinkage void __init setup_vm(void)
> > +static inline void *__load_addr(void *ptr, uintptr_t load_pa)
> > {
> > extern char _start;
> > + uintptr_t va = (uintptr_t)ptr;
> > + uintptr_t sz = (uintptr_t)(&_end) - (uintptr_t)(&_start);
> > +
> > + if (va >= PAGE_OFFSET && va <= (PAGE_OFFSET + sz))
> > + return (void *)(load_pa + (va - PAGE_OFFSET));
> > + return (void *)va;
> > +}
> > +
> > +#define __load_va(ptr, load_pa) __load_addr(ptr, load_pa)
> > +#define __load_pa(ptr, load_pa) ((uintptr_t)__load_addr(ptr, load_pa))
> > +
> > +asmlinkage void __init setup_vm(uintptr_t load_pa)
> > +{
> > uintptr_t i;
> > - uintptr_t pa = (uintptr_t) &_start;
> > +#ifndef __PAGETABLE_PMD_FOLDED
> > + pmd_t *pmdp;
> > +#endif
> > + pgd_t *pgdp;
> > + phys_addr_t map_pa;
> > + pgprot_t tableprot = __pgprot(_PAGE_TABLE);
> > pgprot_t prot = __pgprot(pgprot_val(PAGE_KERNEL) | _PAGE_EXEC);
> >
> > - va_pa_offset = PAGE_OFFSET - pa;
> > - pfn_base = PFN_DOWN(pa);
> > + va_pa_offset = PAGE_OFFSET - load_pa;
> > + pfn_base = PFN_DOWN(load_pa);
> >
> > /* Sanity check alignment and size */
> > BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0);
> > - BUG_ON((pa % (PAGE_SIZE * PTRS_PER_PTE)) != 0);
> > + BUG_ON((load_pa % (PAGE_SIZE * PTRS_PER_PTE)) != 0);
> >
> > #ifndef __PAGETABLE_PMD_FOLDED
> > - trampoline_pg_dir[(PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD] =
> > - pfn_pgd(PFN_DOWN((uintptr_t)trampoline_pmd),
> > - __pgprot(_PAGE_TABLE));
> > - trampoline_pmd[0] = pfn_pmd(PFN_DOWN(pa), prot);
> > + pgdp = __load_va(trampoline_pg_dir, load_pa);
> > + map_pa = __load_pa(trampoline_pmd, load_pa);
> > + pgdp[(PAGE_OFFSET >> PGDIR_SHIFT) % PTRS_PER_PGD] =
>
> Can we use pgd_index(PAGE_OFFSET) here as index to PGD?
>
> > + pfn_pgd(PFN_DOWN(map_pa), tableprot);
>
> It seems that __load_pa result is always used with PFN_DOWN(), it's worth
> adding __load_pfn(). Then the last two statements become
>
> map_pfn = __load_pfn(trampoline_pmd, load_pa);
> pgdp[pgd_index(PAGE_OFFSET)] = pfn_pgd(map_pfn, tableprot);
>
> This applies to most of the mappings below as well.
Thanks for the comments.
I am going to drop this patch because we have other patch which uses
"CFLAGS_init.o := -cmodel=medany" in mm/Makefile
Regards,
Anup
Re: [PATCH v2 4/5] RISC-V: Remove redundant trampoline page table
On Fri, Mar 22, 2019 at 7:03 PM Christoph Hellwig wrote: > > > > > - /* Compute satp for kernel page tables, but don't load it yet */ > > + /* Compute satp for kernel page directory, but don't load it yet */ > > > > /* > > - * Load trampoline page directory, which will cause us to trap to > > + * Load kernel page directory, which will cause us to trap to > >* stvec if VA != PA, or simply fall through if VA == PA > >*/ > > If we want to nitpick comments I think this should take about the > page table root or something like that. Okay, I will update comments. > > Otherwise the idea looks good, but I really think we should do this > before all the changes to the setup_vm code. Sure, I will move it before setup_vm code so that setup_vm code is further simplified. Regards, Anup
[PATCH 2/2] dmaengine: milbeaut: Add Milbeaut AXI DMA controller
Add Milbeaut AXI DMA controller. This DMA controller has
only capable of memory to memory transfer.
Signed-off-by: Kazuhiro Kasai
---
drivers/dma/Kconfig | 8 +
drivers/dma/Makefile | 1 +
drivers/dma/xdmac-milbeaut.c | 353 +++
3 files changed, 362 insertions(+)
create mode 100644 drivers/dma/xdmac-milbeaut.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 0b1dfb5..733fe5f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -612,6 +612,14 @@ config UNIPHIER_MDMAC
UniPhier platform. This DMA controller is used as the external
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
+config XDMAC_MILBEAUT
+ tristate "Milbeaut AXI DMA support"
+ depends on ARCH_MILBEAUT || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for Milbeaut AXI DMA controller driver. The DMA controller
+ has only memory to memory capability.
+
config XGENE_DMA
tristate "APM X-Gene DMA support"
depends on ARCH_XGENE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6126e1c..4aab810 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
+obj-$(CONFIG_XDMAC_MILBEAUT) += xdmac-milbeaut.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
diff --git a/drivers/dma/xdmac-milbeaut.c b/drivers/dma/xdmac-milbeaut.c
new file mode 100644
index 000..7035c61
--- /dev/null
+++ b/drivers/dma/xdmac-milbeaut.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Socionext Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dmaengine.h"
+
+/* global register */
+#define M10V_XDACS 0x00
+
+/* channel local register */
+#define M10V_XDTBC 0x10
+#define M10V_XDSSA 0x14
+#define M10V_XDDSA 0x18
+#define M10V_XDSAC 0x1C
+#define M10V_XDDAC 0x20
+#define M10V_XDDCC 0x24
+#define M10V_XDDES 0x28
+#define M10V_XDDPC 0x2C
+#define M10V_XDDSD 0x30
+
+#define M10V_XDACS_XE BIT(28)
+
+#define M10V_XDSAC_SBS GENMASK(17, 16)
+#define M10V_XDSAC_SBL GENMASK(11, 8)
+
+#define M10V_XDDAC_DBS GENMASK(17, 16)
+#define M10V_XDDAC_DBL GENMASK(11, 8)
+
+#define M10V_XDDES_CE BIT(28)
+#define M10V_XDDES_SE BIT(24)
+#define M10V_XDDES_SA BIT(15)
+#define M10V_XDDES_TF GENMASK(23, 20)
+#define M10V_XDDES_EI BIT(1)
+#define M10V_XDDES_TI BIT(0)
+
+#define M10V_XDDSD_IS_MASK GENMASK(3, 0)
+#define M10V_XDDSD_IS_NORMAL 0x8
+
+#define M10V_XDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
+BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
+BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
+BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
+
+#define M10V_XDMAC_CHAN_BASE(base, i) ((base) + (i) * 0x30)
+
+#define to_m10v_dma_chan(c)container_of((c), struct m10v_dma_chan, chan)
+
+struct m10v_dma_desc {
+ struct dma_async_tx_descriptor txd;
+ size_t len;
+ dma_addr_t src;
+ dma_addr_t dst;
+};
+
+struct m10v_dma_chan {
+ struct dma_chan chan;
+ struct m10v_dma_device *mdmac;
+ void __iomem *regs;
+ int irq;
+ struct m10v_dma_desc mdesc;
+ spinlock_t lock;
+};
+
+struct m10v_dma_device {
+ struct dma_device dmac;
+ void __iomem *regs;
+ unsigned int channels;
+ struct m10v_dma_chan mchan[0];
+};
+
+static void m10v_xdmac_enable_dma(struct m10v_dma_device *mdmac)
+{
+ unsigned int val;
+
+ val = readl(mdmac->regs + M10V_XDACS);
+ val &= ~M10V_XDACS_XE;
+ val |= FIELD_PREP(M10V_XDACS_XE, 1);
+ writel(val, mdmac->regs + M10V_XDACS);
+}
+
+static void m10v_xdmac_disable_dma(struct m10v_dma_device *mdmac)
+{
+ unsigned int val;
+
+ val = readl(mdmac->regs + M10V_XDACS);
+ val &= ~M10V_XDACS_XE;
+ val |= FIELD_PREP(M10V_XDACS_XE, 0);
+ writel(val, mdmac->regs + M10V_XDACS);
+}
+
+static void m10v_xdmac_config_chan(struct m10v_dma_chan *mchan)
+{
+ u32 val;
+
+ val = mchan->mdesc.len - 1;
+ writel(val, mchan->regs + M10V_XDTBC);
+
+ val = mchan->mdesc.src;
+ writel(val, mchan->regs + M10V_XDSSA);
+
+ val = mchan->mdesc.dst;
+ writel(val, mchan->regs + M10V_XDDSA);
+
+ val = readl(mchan->regs + M10V_XDSAC);
+ val &= ~(M10V_XDSAC_SBS | M10V_XDSAC_SBL);
+ val |= FIELD_PREP(M10V_XDSAC_SBS, 0x3) |
+ FIELD_PREP(M10V_XDSAC_SBL, 0xf);
+ writel(val, mchan->regs + M10V_XDSAC);
+
+ val = readl(mchan->regs + M10V_XDDAC);
+ val &= ~(M10V_XDDAC_DBS | M10V_XDDAC_DBL);
+ val |= FIELD_PREP(M10V_XDDAC_DBS, 0x3) |
+ FIELD_PREP(M10V_XDDAC_DBL, 0xf);
+
[PATCH 1/2] dt-bindings: dmaengine: Add Milbeaut AXI DMA controller bindings
Add Milbeaut AXI DMA controller bindings. This DMA controller has
only capable of memory to memory transfer.
Signed-off-by: Kazuhiro Kasai
---
.../devicetree/bindings/dma/xdmac-milbeaut.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
diff --git a/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
b/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
new file mode 100644
index 000..3a77fb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
@@ -0,0 +1,24 @@
+* Milbeaut AXI DMA Controller
+
+Milbeaut AXI DMA controller has only memory to memory transfer capability.
+
+* DMA controller
+
+Required property:
+- compatible: Should be "socionext,milbeaut-m10v-xdmac"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+- #dma-cells: Should be 1.
+- dma-channels:Number of DMA channels supported by the controller.
+
+Example:
+ xdmac0: dma-controller@1c25 {
+ compatible = "socionext,milbeaut-m10v-xdmac";
+ reg = <0x1c25 0x1000>;
+ interrupts = <0 17 0x4>,
+<0 18 0x4>,
+<0 19 0x4>,
+<0 20 0x4>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ };
--
1.9.1
[PATCH 0/2] Add support for AXI DMA controller on Milbeaut series
The following series adds AXI DMA controller support on Milbeaut series. This controller has only capable of memory to memory transfer. Kazuhiro Kasai (2): dt-bindings: dmaengine: Add Milbeaut AXI DMA controller bindings dmaengine: milbeaut: Add Milbeaut AXI DMA controller .../devicetree/bindings/dma/xdmac-milbeaut.txt | 24 ++ drivers/dma/Kconfig| 8 + drivers/dma/Makefile | 1 + drivers/dma/xdmac-milbeaut.c | 353 + 4 files changed, 386 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt create mode 100644 drivers/dma/xdmac-milbeaut.c -- 1.9.1
Re: [PATCH v2 3/9] soc: qcom: rpmpd: Modify corner defining macros
On 3/24/2019 11:20 PM, Sibi Sankar wrote:
From: Bjorn Andersson
QCS404 uses individual resource type magic for each power-domain, so
adjust the macros slightly to make them reusable for this.
[sibi: Extend rpmpd corner pair to a generic rpmpd pair]
This needs to be right above your SoB I think.
Signed-off-by: Bjorn Andersson
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 39 +--
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 71fdfafad2ea..17cd59d1ac3b 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -17,8 +17,8 @@
#define domain_to_rpmpd(domain) container_of(domain, struct rpmpd, pd)
/* Resource types */
-#define RPMPD_SMPA 0x61706d73
-#define RPMPD_LDOA 0x616f646c
+#define RPMPD_SMPA 0x61706d73 /* smpa */
+#define RPMPD_LDOA 0x616f646c /* ldoa */
/* Operation Keys */
#define KEY_CORNER0x6e726f63 /* corn */
@@ -27,46 +27,41 @@
#define MAX_RPMPD_STATE 6
-#define DEFINE_RPMPD_CORNER_SMPA(_platform, _name, _active, r_id) \
+#define DEFINE_RPMPD_PAIR(_platform, _name, _active, r_type, r_key,\
+ r_id) \
static struct rpmpd _platform##_##_active; \
static struct rpmpd _platform##_##_name = { \
.pd = { .name = #_name, }, \
.peer = &_platform##_##_active, \
- .res_type = RPMPD_SMPA, \
+ .res_type = RPMPD_##r_type, \
.res_id = r_id, \
- .key = KEY_CORNER, \
+ .key = KEY_##r_key, \
}; \
static struct rpmpd _platform##_##_active = { \
.pd = { .name = #_active, },\
.peer = &_platform##_##_name, \
.active_only = true,\
- .res_type = RPMPD_SMPA, \
+ .res_type = RPMPD_##r_type, \
.res_id = r_id, \
- .key = KEY_CORNER, \
+ .key = KEY_##r_key, \
}
-#define DEFINE_RPMPD_CORNER_LDOA(_platform, _name, r_id) \
+#define DEFINE_RPMPD_CORNER(_platform, _name, r_type, r_id)\
static struct rpmpd _platform##_##_name = { \
.pd = { .name = #_name, }, \
- .res_type = RPMPD_LDOA, \
+ .res_type = RPMPD_##r_type, \
.res_id = r_id, \
.key = KEY_CORNER, \
}
-#define DEFINE_RPMPD_VFC(_platform, _name, r_id, r_type) \
+#define DEFINE_RPMPD_VFC(_platform, _name, r_type, r_id) \
static struct rpmpd _platform##_##_name = { \
.pd = { .name = #_name, }, \
- .res_type = r_type, \
+ .res_type = RPMPD_##r_type, \
.res_id = r_id, \
.key = KEY_FLOOR_CORNER,\
}
-#define DEFINE_RPMPD_VFC_SMPA(_platform, _name, r_id) \
- DEFINE_RPMPD_VFC(_platform, _name, r_id, RPMPD_SMPA)
-
-#define DEFINE_RPMPD_VFC_LDOA(_platform, _name, r_id) \
- DEFINE_RPMPD_VFC(_platform, _name, r_id, RPMPD_LDOA)
-
struct rpmpd_req {
__le32 key;
__le32 nbytes;
@@ -96,12 +91,12 @@ struct rpmpd_desc {
static DEFINE_MUTEX(rpmpd_lock);
/* msm8996 RPM Power domains */
-DEFINE_RPMPD_CORNER_SMPA(msm8996, vddcx, vddcx_ao, 1);
-DEFINE_RPMPD_CORNER_SMPA(msm8996, vddmx, vddmx_ao, 2);
-DEFINE_RPMPD_CORNER_LDOA(msm8996, vddsscx, 26);
+DEFINE_RPMPD_PAIR(msm8996, vddcx, vddcx_ao, SMPA, CORNER, 1);
+DEFINE_RPMPD_PAIR(msm8996, vddmx, vddmx_ao, SMPA, CORNER, 2);
+DEFINE_RPMPD_CORNER(msm8996, vddsscx, LDOA, 26);
-DEFINE_RPMPD_VFC_SMPA(msm8996, vddcx_vfc, 1);
-DEFINE_RPMPD_VFC_LDOA(msm8996, vddsscx_vfc, 26);
+DEFINE_RPMPD_VFC(msm8996, vddcx_vfc, SMPA, 1);
+DEFINE_RPMPD_VFC(msm8996, vddsscx_vfc, LDOA, 26);
static struct rpmpd *msm8996_rpmpds[] = {
[MSM8996_VDDCX] = _vddcx,
--
QUALCOMM INDIA, on behalf of
Re: [PATCH] nds32: remove unused generic-y += cmpxchg-local.h
Hi Yamada, Masahiro Yamada 於 2019年3月22日 週五 下午11:22寫道： > > NDS32 is the only architecture that creates , > which is not included anyone. > > Signed-off-by: Masahiro Yamada > --- > > arch/nds32/include/asm/Kbuild | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/nds32/include/asm/Kbuild b/arch/nds32/include/asm/Kbuild > index 7ef8695..c131e0e 100644 > --- a/arch/nds32/include/asm/Kbuild > +++ b/arch/nds32/include/asm/Kbuild > @@ -5,7 +5,6 @@ generic-y += bug.h > generic-y += bugs.h > generic-y += checksum.h > generic-y += cmpxchg.h > -generic-y += cmpxchg-local.h > generic-y += compat.h > generic-y += device.h > generic-y += div64.h Thank you. Acked-by: Greentime Hu
Re: [PATCH v2 2/9] soc: qcom: rpmpd: Add support to set rpmpd state to max
On 3/24/2019 11:20 PM, Sibi Sankar wrote:
Add support to set rpmpd state to max across SoCs.
Changelog could be better, 'rpmpd max state varies across SoCs
and SoC families, add support in the driver to make it SoC/SoC
family specific'
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 235d01870dd8..71fdfafad2ea 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -83,12 +83,14 @@ struct rpmpd {
const int res_type;
const int res_id;
struct qcom_smd_rpm *rpm;
+ unsigned int max_state;
__le32 key;
};
struct rpmpd_desc {
struct rpmpd **rpmpds;
size_t num_pds;
+ unsigned int max_state;
};
static DEFINE_MUTEX(rpmpd_lock);
@@ -114,6 +116,7 @@ static struct rpmpd *msm8996_rpmpds[] = {
static const struct rpmpd_desc msm8996_desc = {
.rpmpds = msm8996_rpmpds,
.num_pds = ARRAY_SIZE(msm8996_rpmpds),
+ .max_state = MAX_RPMPD_STATE,
Maybe this needs to be renamed to avoid confusion, MAX_8996_RPMPD_STATE?
};
static const struct of_device_id rpmpd_match_table[] = {
@@ -225,8 +228,8 @@ static int rpmpd_set_performance(struct generic_pm_domain
*domain,
int ret = 0;
struct rpmpd *pd = domain_to_rpmpd(domain);
- if (state > MAX_RPMPD_STATE)
- state = MAX_RPMPD_STATE;
+ if (state > pd->max_state)
+ state = pd->max_state;
mutex_lock(_lock);
@@ -287,6 +290,7 @@ static int rpmpd_probe(struct platform_device *pdev)
}
rpmpds[i]->rpm = rpm;
+ rpmpds[i]->max_state = desc->max_state;
rpmpds[i]->pd.power_off = rpmpd_power_off;
rpmpds[i]->pd.power_on = rpmpd_power_on;
rpmpds[i]->pd.set_performance_state = rpmpd_set_performance;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 1/9] soc: qcom: rpmpd: fixup rpmpd set performance state
On 3/24/2019 11:19 PM, Sibi Sankar wrote:
Fixup rpmpd state to max if the required state is greater than all the
supported states.
This should also say why, 'so the clients which just want to vote on whatever
is the max state supported can do so by passing an INT_MAX'?
Fixes: 075d3db8d10d ("Add support for the .set_performace_state() and
.opp_to_performance_state()")
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 005326050c23..235d01870dd8 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -226,7 +226,7 @@ static int rpmpd_set_performance(struct generic_pm_domain
*domain,
struct rpmpd *pd = domain_to_rpmpd(domain);
if (state > MAX_RPMPD_STATE)
- goto out;
+ state = MAX_RPMPD_STATE;
mutex_lock(_lock);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
RE: [RFC PATCH 2/3] arch/x86/acrn: Use HYPERVISOR_CALLBACK_VECTOR for Acrn upcall vector
>-Original Message-
>From: Thomas Gleixner [mailto:t...@linutronix.de]
>Sent: Friday, March 22, 2019 11:45 PM
>To: Zhao, Yakui
>Cc: linux-kernel@vger.kernel.org; x...@kernel.org; Chen, Jason CJ
>
>Subject: Re: [RFC PATCH 2/3] arch/x86/acrn: Use
>HYPERVISOR_CALLBACK_VECTOR for Acrn upcall vector
>
>On Thu, 7 Mar 2019, Zhao Yakui wrote:
>
>> WHen it works in hypervisor guest mode, Linux kernel uses the
>> HYPERVISOR_CALLBACK_VECTOR for hypervisor upcall vector. And it is
>> already used for Xen and HyperV. After Acrn hypervisor is detected, it
>> will also use this defined vector as notify vector to kernel.
>> And two APIs are added so that the other module can add/remove the
>> hypervisor callback irq handler.
>
>Which other module?
>
This work is divided into two steps. The first is to add the support of
acrn-guest under arch/x86.
The second is to add one driver that allows the acrn-guest to communicate with
the acrn-hypervisor.
As the second part has the dependency on the first part, we hope that the
acrn-guest is added firstly and the
required API is also added.
>> Signed-off-by: Jason Chen CJ
>> Signed-off-by: Zhao Yakui
>
>Same SOB issue.
Sure. It will be updated.
>
>> +#if IS_ENABLED(CONFIG_ACRN)
>> +apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
>> +acrn_hv_callback_vector acrn_hv_vector_handler #endif
>> +
>> idtentry debug do_debug
> has_error_code=0paranoid=1 shift_ist=DEBUG_STACK
>> idtentry int3 do_int3 has_error_code=0
>> idtentry stack_segment do_stack_segment
> has_error_code=1
>> diff --git a/arch/x86/include/asm/acrnhyper.h
>> b/arch/x86/include/asm/acrnhyper.h
>> new file mode 100644
>> index 000..2562a82
>> --- /dev/null
>> +++ b/arch/x86/include/asm/acrnhyper.h
>> @@ -0,0 +1,16 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_ACRNHYPER_H
>> +#define _ASM_X86_ACRNHYPER_H
>> +
>> +#include
>> +#include
>> +
>> +#ifdef CONFIG_ACRN
>> +/* ACRN Hypervisor callback */
>> +void acrn_hv_callback_vector(void);
>
>What declares acrn_hv_vector_handler() ?
Acrn_hv_callback_vector is defined in arch/x86/entry/entry_64.S, which will be
used as
the parameter of alloc_intr_gate
Acrn_hv_vector_handler is the real ISR handler, which is defined in acrn.c.
>
>> #include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>
>First of all the include order is always:
>
> #include
> #include
>
> #include
>
>Aside of that including 'linux/irq.h' should include everything you need. No
>need for gazillion of includes.
OK. The include order will be updated in next version.
>
>> static bool acrn_x2apic_available(void) @@ -26,6 +33,37 @@ static
>> bool acrn_x2apic_available(void)
>> return false;
>> }
>>
>> +
>
>Stray newline
>
Sure. The extra newline will be removed.
>> +static void (*acrn_intr_handler)(void);
>> +/*
>
>Which should have been above this comment. Glueing stuff together makes it
>unreadable.
>
>> + * Handler for ACRN_HV_CALLBACK.
>
>Err? This handles the HYPERVISOR_CALLBACK_VECTOR
>
I will remove the confusing comment.
In fact this acrn_intr_handle is similar to the vmbus_handler in
arch/x86/kernel/cpu/mshyperv.c
>> + */
>> +__visible void __irq_entry acrn_hv_vector_handler(struct pt_regs
>> +*regs) {
>> +struct pt_regs *old_regs = set_irq_regs(regs);
>> +
>> +entering_ack_irq();
>> +inc_irq_stat(irq_hv_callback_count);
>> +
>> +if (acrn_intr_handler)
>> +acrn_intr_handler();
>> +
>> +exiting_irq();
>> +set_irq_regs(old_regs);
>> +}
>> +
>> +void acrn_setup_intr_irq(void (*handler)(void)) {
>> +acrn_intr_handler = handler;
>> +}
>> +EXPORT_SYMBOL(acrn_setup_intr_irq);
>> +
>> +void acrn_remove_intr_irq(void)
>> +{
>> +acrn_intr_handler = NULL;
>> +}
>> +EXPORT_SYMBOL(acrn_remove_intr_irq);
>
>Where is the code which uses these exports? We are not adding exports just
>because or for consumption by out of tree modules.
Understand it.
Is it reasonable that the above two functions are added in the driver patch set?
>
>Thanks,
>
> tglx
[patch v14 4/4] irqchip/qeic: remove PPCisms for QEIC
QEIC was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms, so remove PPCisms. Signed-off-by: Zhao Qiang --- arch/powerpc/platforms/83xx/km83xx.c |1 - arch/powerpc/platforms/83xx/misc.c|1 - arch/powerpc/platforms/83xx/mpc832x_mds.c |1 - arch/powerpc/platforms/83xx/mpc832x_rdb.c |1 - arch/powerpc/platforms/83xx/mpc836x_mds.c |1 - arch/powerpc/platforms/83xx/mpc836x_rdk.c |1 - arch/powerpc/platforms/85xx/corenet_generic.c |1 - arch/powerpc/platforms/85xx/mpc85xx_mds.c |1 - arch/powerpc/platforms/85xx/mpc85xx_rdb.c |1 - arch/powerpc/platforms/85xx/twr_p102x.c |1 - drivers/irqchip/irq-qeic.c| 188 +++-- include/soc/fsl/qe/qe_ic.h| 132 - 12 files changed, 80 insertions(+), 250 deletions(-) delete mode 100644 include/soc/fsl/qe/qe_ic.h diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c index d8642a4..b1cef0a 100644 --- a/arch/powerpc/platforms/83xx/km83xx.c +++ b/arch/powerpc/platforms/83xx/km83xx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index 4150b56..b033a10 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index 74c154e..f86371b 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -37,7 +37,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c index 4389865..da91395 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index fd44dd0..9b8bc8b 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -45,7 +45,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c index 93f024f..82fa344 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c +++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index e44bb44..ac2478d 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 6892bc1..809266d 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include #include "smp.h" diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index 000d385..f806b6b 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 6be9b33..4f620f2 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c index a6ccbfb..723c52e 100644 --- a/drivers/irqchip/irq-qeic.c +++ b/drivers/irqchip/irq-qeic.c @@ -18,8 +18,11 @@ #include #include #include +#include #include #include +#include +#include #include #include #include @@ -27,9 +30,8 @@ #include #include #include -#include +#include #include -#include #define NR_QE_IC_INTS 64 @@ -87,6 +89,43 @@ #define SIGNAL_HIGH2 #define SIGNAL_LOW 0 +#define NUM_OF_QE_IC_GROUPS6 + +/* Flags when we init the QE IC */ +#define QE_IC_SPREADMODE_GRP_W BIT(0) +#define QE_IC_SPREADMODE_GRP_X BIT(1) +#define QE_IC_SPREADMODE_GRP_Y BIT(2) +#define QE_IC_SPREADMODE_GRP_Z BIT(3) +#define QE_IC_SPREADMODE_GRP_RISCA BIT(4) +#define QE_IC_SPREADMODE_GRP_RISCB BIT(5) +
[patch v14 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
MAINTAINERS|6 +
drivers/irqchip/Makefile |1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 141
drivers/soc/fsl/qe/Makefile|2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 --
5 files changed, 123 insertions(+), 130 deletions(-)
rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (81%)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e5a5d2..540a82d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6255,6 +6255,12 @@ F: drivers/soc/fsl/qe/
F: include/soc/fsl/*qe*.h
F: include/soc/fsl/*ucc*.h
+FREESCALE QEIC DRIVERS
+M: Qiang Zhao
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: drivers/irqchip/irq-qeic.c
+
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
M: Li Yang
L: net...@vger.kernel.org
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 85972ae..726c0ba 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -97,3 +97,4 @@ obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
similarity index 81%
rename from drivers/soc/fsl/qe/qe_ic.c
rename to drivers/irqchip/irq-qeic.c
index ec2ca86..aba7135 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -1,7 +1,7 @@
/*
- * arch/powerpc/sysdev/qe_lib/qe_ic.c
+ * drivers/irqchip/irq-qeic.c
*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Li Yang
* Based on code from Shlomi Gridish
@@ -30,145 +30,234 @@
#include
#include
-#include "qe_ic.h"
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC0x10
+#define QEIC_CIPYCC0x14
+#define QEIC_CIPWCC0x18
+#define QEIC_CIPZCC0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA0x30
+#define QEIC_CIPRTB0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0 29
+#define CIPCC_SHIFT_PRI1 26
+#define CIPCC_SHIFT_PRI2 23
+#define CIPCC_SHIFT_PRI3 20
+#define CIPCC_SHIFT_PRI4 13
+#define CIPCC_SHIFT_PRI5 10
+#define CIPCC_SHIFT_PRI6 7
+#define CIPCC_SHIFT_PRI7 4
+
+/* CICR priority modes */
+#define CICR_GWCC BIT(18)
+#define CICR_GXCC BIT(17)
+#define CICR_GYCC BIT(16)
+#define CICR_GZCC BIT(19)
+#define CICR_GRTA BIT(21)
+#define CICR_GRTB BIT(22)
+#define CICR_HPIT_SHIFT8
+#define CICR_HPIT_MASK 0x0300
+#define CICR_HP_SHIFT 24
+#define CICR_HP_MASK 0x3f00
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT 20
+#define CICNR_ZCC1T_SHIFT 28
+#define CICNR_YCC1T_SHIFT 12
+#define CICNR_XCC1T_SHIFT 4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT 20
+#define CRICR_RTB1T_SHIFT 28
+
+/* Signal indicator */
+#define SIGNAL_MASK3
+#define SIGNAL_HIGH2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+ /* Control registers offset */
+ u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* location of this source at the QIMR register. */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+* for grouped interrupts sources - the interrupt
+* code as appears at the group priority register
+*/
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
static DEFINE_RAW_SPINLOCK(qe_ic_lock);
static struct qe_ic_info qe_ic_info[] = {
[1] = {
- .mask = 0x8000,
+ .mask = BIT(15),
.mask_reg = QEIC_CIMR,
.pri_code = 0,
[patch v14 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang
---
arch/powerpc/platforms/83xx/misc.c| 15 ---
arch/powerpc/platforms/85xx/corenet_generic.c |9 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16
arch/powerpc/platforms/85xx/twr_p102x.c | 14 --
drivers/irqchip/irq-qeic.c| 13 +
6 files changed, 13 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index 2b6589f..4150b56 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -94,24 +94,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 785e964..e44bb44 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -42,8 +42,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -51,13 +49,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 80939a4..6892bc1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -283,20 +283,6 @@ static void __init mpc85xx_mds_qeic_init(void)
of_node_put(np);
return;
}
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1006950..000d385 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -48,10 +48,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -66,18 +62,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c
b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f625..6be9b33 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -35,26 +35,12 @@ static void __init twr_p1025_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct
[PATCH 0/4] This patchset is to remove PPCisms for QEIC
QE is an IP block included in SoC of fsl PowerPC series and layerscape series,
its interrupt contoller was put under drivers/soc/fsl/qe, now move to
driver/irqchip.
And QEIC is supported more than just powerpc boards, so remove PPCisms.
changelog:
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
- remove include/soc/fsl/qe/qe_ic.h
Changes for v9:
- rebase
- fix the compile issue when apply the second patch, in fact, there was
no compile issue
when apply all the patches of this patchset
Changes for v10:
- simplify codes, remove duplicated codes
Changes for v11:
- rebase
Changes for v12:
Changes for v13:
- rewrite single-bit constants to BIT(x) to make the code more readable
Changes for v14:
- rebase
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
irqchip/qeic: merge qeic init code from platforms to a common
function
irqchip/qeic: merge qeic_of_init into qe_ic_init
irqchip/qeic: remove PPCisms for QEIC
MAINTAINERS|6 +
arch/powerpc/platforms/83xx/km83xx.c |1 -
arch/powerpc/platforms/83xx/misc.c | 16 -
arch/powerpc/platforms/83xx/mpc832x_mds.c |1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c |1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c |1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c |1 -
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
drivers/irqchip/Makefile |1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423 ++-
drivers/soc/fsl/qe/Makefile|2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 -
include/soc/fsl/qe/qe_ic.h | 139 ---
16 files changed, 231 insertions(+), 521 deletions(-)
rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h
[patch v14 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
drivers/irqchip/irq-qeic.c | 110
include/soc/fsl/qe/qe_ic.h |7 ---
2 files changed, 30 insertions(+), 87 deletions(-)
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 673afb4..a6ccbfb 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -407,27 +407,30 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static int __init qe_ic_init(struct device_node *node,
+struct device_node *parent)
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ int ret = 0;
ret = of_address_to_resource(node, 0, );
- if (ret)
- return;
+ if (ret) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
- if (qe_ic == NULL)
- return;
+ if (qe_ic == NULL) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
_ic_host_ops, qe_ic);
if (qe_ic->irqhost == NULL) {
- kfree(qe_ic);
- return;
+ ret = -ENOMEM;
+ goto err_free_qe_ic;
}
qe_ic->regs = ioremap(res.start, resource_size());
@@ -438,42 +441,30 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
if (qe_ic->virq_low == NO_IRQ) {
- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
- kfree(qe_ic);
- return;
- }
-
- /* default priority scheme is grouped. If spread mode is*/
- /* required, configure cicr accordingly.*/
- if (flags & QE_IC_SPREADMODE_GRP_W)
- temp |= CICR_GWCC;
- if (flags & QE_IC_SPREADMODE_GRP_X)
- temp |= CICR_GXCC;
- if (flags & QE_IC_SPREADMODE_GRP_Y)
- temp |= CICR_GYCC;
- if (flags & QE_IC_SPREADMODE_GRP_Z)
- temp |= CICR_GZCC;
- if (flags & QE_IC_SPREADMODE_GRP_RISCA)
- temp |= CICR_GRTA;
- if (flags & QE_IC_SPREADMODE_GRP_RISCB)
- temp |= CICR_GRTB;
-
- /* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL) {
- temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
- high_active = 1;
+ pr_err("Failed to map QE_IC low IRQ\n");
+ ret = -ENOMEM;
+ goto err_domain_remove;
}
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-
irq_set_handler_data(qe_ic->virq_low, qe_ic);
- irq_set_chained_handler(qe_ic->virq_low, low_handler);
+ irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
if (qe_ic->virq_high != NO_IRQ &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
- irq_set_chained_handler(qe_ic->virq_high, high_handler);
+ irq_set_chained_handler(qe_ic->virq_high,
+ qe_ic_cascade_high_mpic);
}
+ of_node_put(node);
+ return 0;
+
+err_domain_remove:
+ irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+ kfree(qe_ic);
+err_put_node:
+ of_node_put(node);
+ return ret;
}
void qe_ic_set_highest_priority(unsigned int virq, int high)
@@ -570,45 +561,4 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned
int priority, int high)
return 0;
}
-static struct bus_type qe_ic_subsys = {
- .name = "qe_ic",
- .dev_name = "qe_ic",
-};
-
-static struct device device_qe_ic = {
- .id = 0,
- .bus = _ic_subsys,
-};
-
-static int __init init_qe_ic_sysfs(void)
-{
- int rc;
-
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
-
- rc = subsys_system_register(_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
- return -ENODEV;
- }
- rc = device_register(_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
-
-static int __init qeic_of_init(struct device_node *node,
-
Re: [PATCH v4 4/6] x86/mm/KASLR: Fix the wrong calculation of memory region initial size
On 03/24/19 at 09:58pm, Thomas Gleixner wrote:
> On Thu, 14 Mar 2019, Baoquan He wrote:
> > In memory region KASLR, __PHYSICAL_MASK_SHIFT is taken to calculate
> > the initial size of the direct mapping region. This is correct in
> > the old code where __PHYSICAL_MASK_SHIFT was equal to MAX_PHYSMEM_BITS,
> > 46 bits, and only 4-level mode was supported.
> >
> > Later, in commit:
> > b83ce5ee91471d ("x86/mm/64: Make __PHYSICAL_MASK_SHIFT always 52"),
> > __PHYSICAL_MASK_SHIFT was changed to be always 52 bits, no matter it's
> > 5-level or 4-level. This is wrong for 4-level paging. Then when we
> > adapt physical memory region size based on available memory, it
> > will overflow if the amount of system RAM and the padding is bigger
> > than 64 TB.
>
> I have no idea what that sentence means and what will overflow. Neither I
> have the time to stare at the code to figure it out. Changelogs need to be
> self explanatory. Providing a simple example with numbers or an
> illustration would be helpful.
>
> > In fact, here MAX_PHYSMEM_BITS should be used instead. Fix it by
> > replacing __PHYSICAL_MASK_SHIFT with MAX_PHYSMEM_BITS.
> >
> > Signed-off-by: Baoquan He
> > Acked-by: Kirill A. Shutemov
> > Reviewed-by: Thomas Garnier
> > Acked-by: Kees Cook
>
> So this is an actual bug fix, which is in the middle of this series. Bug
> fixes go first and need to be independent of the rest of the series.
>
> They also need a Fixes: tag.
>
> > diff --git a/arch/x86/mm/kaslr.c b/arch/x86/mm/kaslr.c
> > index d7ea6b252594..ebf6d1d92385 100644
> > --- a/arch/x86/mm/kaslr.c
> > +++ b/arch/x86/mm/kaslr.c
> > @@ -131,7 +131,7 @@ void __init kernel_randomize_memory(void)
> > if (!kaslr_memory_enabled())
> > return;
> >
> > - kaslr_regions[0].size_tb = 1 << (__PHYSICAL_MASK_SHIFT - TB_SHIFT);
> > + kaslr_regions[0].size_tb = 1 << (MAX_PHYSMEM_BITS - TB_SHIFT);
> > kaslr_regions[1].size_tb = VMALLOC_SIZE_TB;
>
> That said, I surely can understand why this change needs to be done, but
> the changelog needs to explain the issue so someone with less experience or
> someone looking at this in a year from now doesn't have to bang his head
> against the wall.
OK, let me add example into log and make log more understandable.
Thanks.
I will take out patch 4, 5, 6 of this series and send them out
separately. Then send patch 1, 2 ,3 as a clean up patch series.
[PATCH v2] RISC-V: Always compile mm/init.c with cmodel=medany
The Linux RISC-V 32bit kernel is broken after we moved setup_vm() from
kernel/setup.c to mm/init.c because Linux RISC-V 32bit kernel by default
uses cmodel=medlow which results in a non-position-independent setup_vm().
This patch fixes Linux RISC-V 32bit kernel booting by:
1. Forcing cmodel=medany for mm/init.c
2. Moving remaing MM-related stuff va_pa_offset, pfn_base and
empty_zero_page from kernel/setup.c to mm/init.c
Fixes: 6f1e9e946f0b ("RISC-V: Move setup_vm() to mm/init.c")
Suggested-by: Christoph Hellwig
Suggested-by: Mike Rapoport
Signed-off-by: Anup Patel
---
v2: Removed CFLAGS_setup.o from kernel/Makefile and replaced SoBs
---
arch/riscv/kernel/Makefile | 2 --
arch/riscv/kernel/setup.c | 8
arch/riscv/mm/Makefile | 2 ++
arch/riscv/mm/init.c | 9 +
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index f13f7f276639..8b9780b6bd7f 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -29,8 +29,6 @@ obj-y += vdso.o
obj-y += cacheinfo.o
obj-y += vdso/
-CFLAGS_setup.o := -mcmodel=medany
-
obj-$(CONFIG_FPU) += fpu.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index ecb654f6a79e..540a331d1376 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -48,14 +48,6 @@ struct screen_info screen_info = {
};
#endif
-unsigned long va_pa_offset;
-EXPORT_SYMBOL(va_pa_offset);
-unsigned long pfn_base;
-EXPORT_SYMBOL(pfn_base);
-
-unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
__page_aligned_bss;
-EXPORT_SYMBOL(empty_zero_page);
-
/* The lucky hart to first increment this variable will boot the other cores */
atomic_t hart_lottery;
unsigned long boot_cpu_hartid;
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index eb22ab49b3e0..7307609d405b 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -3,3 +3,5 @@ obj-y += fault.o
obj-y += extable.o
obj-y += ioremap.o
obj-y += cacheflush.o
+
+CFLAGS_init.o := -mcmodel=medany
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index b379a75ac6a6..7a7c454378cb 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -25,6 +25,10 @@
#include
#include
+unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
+ __page_aligned_bss;
+EXPORT_SYMBOL(empty_zero_page);
+
static void __init zone_sizes_init(void)
{
unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
@@ -143,6 +147,11 @@ void __init setup_bootmem(void)
}
}
+unsigned long va_pa_offset;
+EXPORT_SYMBOL(va_pa_offset);
+unsigned long pfn_base;
+EXPORT_SYMBOL(pfn_base);
+
pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
pgd_t trampoline_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE);
--
2.17.1
RE: [RFC PATCH 1/3] arch/x86: add ACRN hypervisor guest
Hi, Tglx
Thanks for your nice review.
>-Original Message-
>From: Thomas Gleixner [mailto:t...@linutronix.de]
>Sent: Friday, March 22, 2019 11:20 PM
>To: Zhao, Yakui
>Cc: linux-kernel@vger.kernel.org; x...@kernel.org; Chen, Jason CJ
>
>Subject: Re: [RFC PATCH 1/3] arch/x86: add ACRN hypervisor guest
>
>Zhao,
>
>On Thu, 7 Mar 2019, Zhao Yakui wrote:
>
>> ACRN is one open-source hypervisour, which is maintained by Linux
>> foundation. This is to add the para-virtualization support so that it
>> allows to enable the Linux guest on acrn-hypervisor.
>>
>> This adds x86_hyper_acrn into supported hypervisors array, which
>> enables ACRN services guest running on ACRN hypervisor. It is
>
>What is a ACRN services guest?
It should be "ACRN guest".
>
>> restricted to X86_64.
>>
>> Signed-off-by: Jason Chen CJ
>> Signed-off-by: Zhao Yakui
>
>This SOB chain is wrong. If Jason wrote the patch, then there should be a
>'From: Jason ..' line at the top of the change log. If you both wrote it then
>Jason's SOB wants to be preceeded by a 'Co-developed-by: Jason'
>line. See Documentation/process/
Sure. It will be updated to "Co-developed-by: Jason" in next version.
>
>> +config ACRN
>> +bool "Enable services on ACRN hypervisor"
>> +depends on X86_64 && PARAVIRT
>> +help
>> + This option allows to run Linux as guest in ACRN hypervisor.
>> + It is needed if you want to run ACRN services linux on top of
>> + ACRN hypervisor.
>
>This help text does not make any sense to me.
"Enable Services on ACRN hypervisor" is a little confusing.
In next version it will be changed to "ACRN_GUEST". How about the below:
config ACRN_GUEST
bool "ACRN Guest Support"
depends on X86_64 && PARAVIRT
help
This option allows to run Linux as guest in ACRN hypervisor. Enabling
this will allow the
kernel to boot in a paravirtualized environment under the ACRN
hypervisor
>
>> +const struct hypervisor_x86 x86_hyper_acrn = {
>> +.name = "ACRN",
>> +.detect = acrn_detect,
>> +.type = X86_HYPER_ACRN,
>> +.init.init_platform = acrn_init_platform,
>> +.init.x2apic_available = acrn_x2apic_available, };
>> +EXPORT_SYMBOL(x86_hyper_acrn);
>
>Whay is this exported? The only user of this is hypervisor.c and that is built
>in.
>Please remove.
You are right.
It will be removed and the x86_hyper_acrn will also be added into "__initconst"
section.
>
>Thanks,
>
> tglx
[PATCH 06/17] fpga: dfl: pci: enable SRIOV support.
This patch enables the standard sriov support. It allows user to
enable SRIOV (and VFs), then user could pass through accelerators
(VFs) into virtual machine or use VFs directly in host.
Signed-off-by: Zhang Yi Z
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-pci.c | 40
drivers/fpga/dfl.c | 41 +
drivers/fpga/dfl.h | 1 +
3 files changed, 82 insertions(+)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index 66b5720..2fa571b 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -223,8 +223,46 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct
pci_device_id *pcidevid)
return ret;
}
+static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
+{
+ struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
+ struct dfl_fpga_cdev *cdev = drvdata->cdev;
+ int ret = 0;
+
+ mutex_lock(>lock);
+
+ if (!num_vfs) {
+ /*
+* disable SRIOV and then put released ports back to default
+* PF access mode.
+*/
+ pci_disable_sriov(pcidev);
+
+ __dfl_fpga_cdev_config_port_vf(cdev, false);
+
+ } else if (cdev->released_port_num == num_vfs) {
+ /*
+* only enable SRIOV if cdev has matched released ports, put
+* released ports into VF access mode firstly.
+*/
+ __dfl_fpga_cdev_config_port_vf(cdev, true);
+
+ ret = pci_enable_sriov(pcidev, num_vfs);
+ if (ret)
+ __dfl_fpga_cdev_config_port_vf(cdev, false);
+ } else {
+ ret = -EINVAL;
+ }
+
+ mutex_unlock(>lock);
+ return ret;
+}
+
static void cci_pci_remove(struct pci_dev *pcidev)
{
+ if (dev_is_pf(>dev))
+ cci_pci_sriov_configure(pcidev, 0);
+
cci_remove_feature_devs(pcidev);
pci_disable_pcie_error_reporting(pcidev);
}
@@ -234,6 +272,7 @@ static struct pci_driver cci_pci_driver = {
.id_table = cci_pcie_id_tbl,
.probe = cci_pci_probe,
.remove = cci_pci_remove,
+ .sriov_configure = cci_pci_sriov_configure,
};
module_pci_driver(cci_pci_driver);
@@ -241,3 +280,4 @@ module_pci_driver(cci_pci_driver);
MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index a6b6d38..c5aa287 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -1098,6 +1098,47 @@ int dfl_fpga_cdev_config_port(struct dfl_fpga_cdev *cdev,
}
EXPORT_SYMBOL_GPL(dfl_fpga_cdev_config_port);
+static void config_port_vf(struct device *fme_dev, int port_id, bool is_vf)
+{
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(fme_dev, FME_FEATURE_ID_HEADER);
+
+ v = readq(base + FME_HDR_PORT_OFST(port_id));
+
+ v &= ~FME_PORT_OFST_ACC_CTRL;
+ v |= FIELD_PREP(FME_PORT_OFST_ACC_CTRL,
+ is_vf ? FME_PORT_OFST_ACC_VF : FME_PORT_OFST_ACC_PF);
+
+ writeq(v, base + FME_HDR_PORT_OFST(port_id));
+}
+
+/**
+ * __dfl_fpga_cdev_config_port_vf - configure port to VF access mode
+ *
+ * @cdev: parent container device.
+ * @if_vf: true for VF access mode, and false for PF access mode
+ *
+ * Return: 0 on success, negative error code otherwise.
+ *
+ * This function is needed in sriov configuration routine. It could be used to
+ * configures the released ports access mode to VF or PF.
+ * The caller needs to hold lock for protection.
+ */
+void __dfl_fpga_cdev_config_port_vf(struct dfl_fpga_cdev *cdev, bool is_vf)
+{
+ struct dfl_feature_platform_data *pdata;
+
+ list_for_each_entry(pdata, >port_dev_list, node) {
+ if (device_is_registered(>dev->dev))
+ continue;
+
+ config_port_vf(cdev->fme_dev, pdata->id, is_vf);
+ }
+}
+EXPORT_SYMBOL_GPL(__dfl_fpga_cdev_config_port_vf);
+
static int __init dfl_fpga_init(void)
{
int ret;
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 63f39ab..1350e8e 100644
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -421,5 +421,6 @@ dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void
*data,
int dfl_fpga_cdev_config_port(struct dfl_fpga_cdev *cdev,
u32 port_id, bool release);
+void __dfl_fpga_cdev_config_port_vf(struct dfl_fpga_cdev *cdev, bool is_vf);
#endif /* __FPGA_DFL_H */
--
2.7.4
[PATCH 03/17] fpga: dfl: fme: support 512bit data width PR
In early partial reconfiguration private feature, it only
supports 32bit data width when writing data to hardware for
PR. 512bit data width PR support is an important optimization
for some specific solutions (e.g. XEON with FPGA integrated),
it allows driver to use AVX512 instruction to improve the
performance of partial reconfiguration. e.g. programming one
100MB bitstream image via this 512bit data width PR hardware
only takes ~300ms, but 32bit revision requires ~3s per test
result.
Please note now this optimization is only done on revision 2
of this PR private feature which is only used in integrated
solution that AVX512 is always supported.
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-fme-main.c | 3 ++
drivers/fpga/dfl-fme-mgr.c | 75 +
drivers/fpga/dfl-fme-pr.c | 45 ---
drivers/fpga/dfl-fme.h | 2 ++
drivers/fpga/dfl.h | 5 +++
5 files changed, 99 insertions(+), 31 deletions(-)
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 086ad24..076d74f 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -21,6 +21,8 @@
#include "dfl.h"
#include "dfl-fme.h"
+#define DRV_VERSION"0.8"
+
static ssize_t ports_num_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -277,3 +279,4 @@ MODULE_DESCRIPTION("FPGA Management Engine driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dfl-fme");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
index b3f7eee..027d457 100644
--- a/drivers/fpga/dfl-fme-mgr.c
+++ b/drivers/fpga/dfl-fme-mgr.c
@@ -22,14 +22,18 @@
#include
#include
+#include "dfl.h"
#include "dfl-fme-pr.h"
+#define DRV_VERSION"0.8"
+
/* FME Partial Reconfiguration Sub Feature Register Set */
#define FME_PR_DFH 0x0
#define FME_PR_CTRL0x8
#define FME_PR_STS 0x10
#define FME_PR_DATA0x18
#define FME_PR_ERR 0x20
+#define FME_PR_512_DATA0x40 /* Data Register for 512bit
datawidth PR */
#define FME_PR_INTFC_ID_L 0xA8
#define FME_PR_INTFC_ID_H 0xB0
@@ -67,8 +71,31 @@
#define PR_WAIT_TIMEOUT 800
#define PR_HOST_STATUS_IDLE0
+#if defined(CONFIG_X86) && defined(CONFIG_AS_AVX512)
+
+#include
+
+static inline void copy512(void *src, void __iomem *dst)
+{
+ kernel_fpu_begin();
+
+ asm volatile("vmovdqu64 (%0), %%zmm0;"
+"vmovntdq %%zmm0, (%1);"
+:
+: "r"(src), "r"(dst));
+
+ kernel_fpu_end();
+}
+#else
+static inline void copy512(void *src, void __iomem *dst)
+{
+ WARN_ON_ONCE(1);
+}
+#endif
+
struct fme_mgr_priv {
void __iomem *ioaddr;
+ unsigned int pr_datawidth;
u64 pr_error;
};
@@ -169,7 +196,7 @@ static int fme_mgr_write(struct fpga_manager *mgr,
struct fme_mgr_priv *priv = mgr->priv;
void __iomem *fme_pr = priv->ioaddr;
u64 pr_ctrl, pr_status, pr_data;
- int delay = 0, pr_credit, i = 0;
+ int ret = 0, delay = 0, pr_credit;
dev_dbg(dev, "start request\n");
@@ -181,9 +208,9 @@ static int fme_mgr_write(struct fpga_manager *mgr,
/*
* driver can push data to PR hardware using PR_DATA register once HW
-* has enough pr_credit (> 1), pr_credit reduces one for every 32bit
-* pr data write to PR_DATA register. If pr_credit <= 1, driver needs
-* to wait for enough pr_credit from hardware by polling.
+* has enough pr_credit (> 1), pr_credit reduces one for every pr data
+* width write to PR_DATA register. If pr_credit <= 1, driver needs to
+* wait for enough pr_credit from hardware by polling.
*/
pr_status = readq(fme_pr + FME_PR_STS);
pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
@@ -192,7 +219,8 @@ static int fme_mgr_write(struct fpga_manager *mgr,
while (pr_credit <= 1) {
if (delay++ > PR_WAIT_TIMEOUT) {
dev_err(dev, "PR_CREDIT timeout\n");
- return -ETIMEDOUT;
+ ret = -ETIMEDOUT;
+ goto done;
}
udelay(1);
@@ -200,21 +228,32 @@ static int fme_mgr_write(struct fpga_manager *mgr,
pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
}
- if (count < 4) {
+ if (count < priv->pr_datawidth) {
dev_err(dev, "Invalid PR bitstream size\n");
return -EINVAL;
}
- pr_data = 0;
- pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
-
[PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support.
In order to support virtualization usage via PCIe SRIOV, this patch
adds two ioctls under FPGA Management Engine (FME) to release and
assign back the port device. In order to safely turn Port from PF
into VF and enable PCIe SRIOV, it requires user to invoke this
PORT_RELEASE ioctl to release port firstly to remove userspace
interfaces, and then configure the PF/VF access register in FME.
After disable SRIOV, it requires user to invoke this PORT_ASSIGN
ioctl to attach the port back to PF.
Ioctl interfaces:
* DFL_FPGA_FME_PORT_RELEASE
Release platform device of given port, it deletes port platform
device to remove related userspace interfaces on PF, then
configures PF/VF access mode to VF.
* DFL_FPGA_FME_PORT_ASSIGN
Assign platform device of given port back to PF, it configures
PF/VF access mode to PF, then adds port platform device back to
re-enable related userspace interfaces on PF.
Signed-off-by: Zhang Yi Z
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-fme-main.c | 54 +
drivers/fpga/dfl.c| 107 +-
drivers/fpga/dfl.h| 10
include/uapi/linux/fpga-dfl.h | 32 +
4 files changed, 191 insertions(+), 12 deletions(-)
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 076d74f..8b2a337 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -16,6 +16,7 @@
#include
#include
+#include
#include
#include "dfl.h"
@@ -105,9 +106,62 @@ static void fme_hdr_uinit(struct platform_device *pdev,
sysfs_remove_files(>dev.kobj, fme_hdr_attrs);
}
+static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
+ void __user *arg)
+{
+ struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
+ struct dfl_fpga_fme_port_release release;
+ unsigned long minsz;
+
+ minsz = offsetofend(struct dfl_fpga_fme_port_release, port_id);
+
+ if (copy_from_user(, arg, minsz))
+ return -EFAULT;
+
+ if (release.argsz < minsz || release.flags)
+ return -EINVAL;
+
+ return dfl_fpga_cdev_config_port(cdev, release.port_id, true);
+}
+
+static long fme_hdr_ioctl_assign_port(struct dfl_feature_platform_data *pdata,
+ void __user *arg)
+{
+ struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
+ struct dfl_fpga_fme_port_assign assign;
+ unsigned long minsz;
+
+ minsz = offsetofend(struct dfl_fpga_fme_port_assign, port_id);
+
+ if (copy_from_user(, arg, minsz))
+ return -EFAULT;
+
+ if (assign.argsz < minsz || assign.flags)
+ return -EINVAL;
+
+ return dfl_fpga_cdev_config_port(cdev, assign.port_id, false);
+}
+
+static long fme_hdr_ioctl(struct platform_device *pdev,
+ struct dfl_feature *feature,
+ unsigned int cmd, unsigned long arg)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(>dev);
+
+ switch (cmd) {
+ case DFL_FPGA_FME_PORT_RELEASE:
+ return fme_hdr_ioctl_release_port(pdata, (void __user *)arg);
+ case DFL_FPGA_FME_PORT_ASSIGN:
+ return fme_hdr_ioctl_assign_port(pdata, (void __user *)arg);
+ }
+
+ return -ENODEV;
+}
+
static const struct dfl_feature_ops fme_hdr_ops = {
.init = fme_hdr_init,
.uinit = fme_hdr_uinit,
+ .ioctl = fme_hdr_ioctl,
};
static struct dfl_feature_driver fme_feature_drvs[] = {
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 2c09e50..a6b6d38 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -224,16 +224,20 @@ EXPORT_SYMBOL_GPL(dfl_fpga_port_ops_del);
*/
int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id)
{
- struct dfl_fpga_port_ops *port_ops = dfl_fpga_port_ops_get(pdev);
- int port_id;
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(>dev);
+ struct dfl_fpga_port_ops *port_ops;
+
+ if (pdata->id != FEATURE_DEV_ID_UNUSED)
+ return pdata->id == *(int *)pport_id;
+ port_ops = dfl_fpga_port_ops_get(pdev);
if (!port_ops || !port_ops->get_id)
return 0;
- port_id = port_ops->get_id(pdev);
+ pdata->id = port_ops->get_id(pdev);
dfl_fpga_port_ops_put(port_ops);
- return port_id == *(int *)pport_id;
+ return pdata->id == *(int *)pport_id;
}
EXPORT_SYMBOL_GPL(dfl_fpga_check_port_id);
@@ -462,6 +466,7 @@ static int build_info_commit_dev(struct
build_feature_devs_info *binfo)
pdata->dev = fdev;
pdata->num = binfo->feature_num;
pdata->dfl_cdev = binfo->cdev;
+ pdata->id = FEATURE_DEV_ID_UNUSED;
mutex_init(>lock);
/*
@@ -959,25 +964,27 @@ void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev
*cdev)
{
struct
[PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces
This patch introduces more sysfs interfaces for Accelerated
Function Unit (AFU). These interfaces allow users to read
current AFU Power State (APx), read / clear AFU Power (APx)
events which are sticky to identify transient APx state,
and manage AFU's LTR (latency tolerance reporting).
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-port | 30 +
drivers/fpga/dfl-afu-main.c | 144 ++
drivers/fpga/dfl.h| 11 ++
3 files changed, 185 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port
b/Documentation/ABI/testing/sysfs-platform-dfl-port
index 6a92dda..f0c4e92 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-port
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
@@ -14,3 +14,33 @@ Description: Read-only. User can program different PR
bitstreams to FPGA
Accelerator Function Unit (AFU) for different functions. It
returns uuid which could be used to identify which PR bitstream
is programmed in this AFU.
+
+What: /sys/bus/platform/devices/dfl-port.0/power_state
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It reports the APx (AFU Power) state, different APx
+ means different throttling level. When reading this file, it
+ returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
+
+What: /sys/bus/platform/devices/dfl-port.0/ap1_event
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-write. Read or set 1 to clear AP1 (AFU Power State 1)
+ event. It's used to indicate transient AP1 state.
+
+What: /sys/bus/platform/devices/dfl-port.0/ap2_event
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-write. Read or set 1 to clear AP2 (AFU Power State 2)
+ event. It's used to indicate transient AP2 state.
+
+What: /sys/bus/platform/devices/dfl-port.0/ltr
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-write. Read and set AFU latency tolerance reporting value.
+ Set ltr to 1 if the AFU can tolerate latency >= 40us or set it
+ to 0 if it is latency sensitive.
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 02baa6a..2ffec06 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -21,6 +21,8 @@
#include "dfl-afu.h"
+#define DRV_VERSION"0.8"
+
/**
* port_enable - enable a port
* @pdev: port platform device.
@@ -141,8 +143,149 @@ id_show(struct device *dev, struct device_attribute
*attr, char *buf)
}
static DEVICE_ATTR_RO(id);
+static ssize_t
+ltr_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ mutex_lock(>lock);
+ v = readq(base + PORT_HDR_CTRL);
+ mutex_unlock(>lock);
+
+ return scnprintf(buf, PAGE_SIZE, "%x\n",
+(u8)FIELD_GET(PORT_CTRL_LATENCY, v));
+}
+
+static ssize_t
+ltr_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ void __iomem *base;
+ u8 ltr;
+ u64 v;
+
+ if (kstrtou8(buf, 0, ) || ltr > 1)
+ return -EINVAL;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ mutex_lock(>lock);
+ v = readq(base + PORT_HDR_CTRL);
+ v &= ~PORT_CTRL_LATENCY;
+ v |= FIELD_PREP(PORT_CTRL_LATENCY, ltr);
+ writeq(v, base + PORT_HDR_CTRL);
+ mutex_unlock(>lock);
+
+ return count;
+}
+static DEVICE_ATTR_RW(ltr);
+
+static ssize_t
+ap1_event_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ mutex_lock(>lock);
+ v = readq(base + PORT_HDR_STS);
+ mutex_unlock(>lock);
+
+ return scnprintf(buf, PAGE_SIZE, "%x\n",
+(u8)FIELD_GET(PORT_STS_AP1_EVT, v));
+}
+
+static ssize_t
+ap1_event_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ void __iomem *base;
+ u8 ap1_event;
+
+ if (kstrtou8(buf, 0, _event) || ap1_event != 1)
+ return -EINVAL;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+
[PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces
This patch adds 3 read-only sysfs interfaces for FPGA Management Engine
(FME) block for capabilities including cache_size, fabric_version and
socket_id.
Signed-off-by: Luwei Kang
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-fme | 23
drivers/fpga/dfl-fme-main.c | 48
2 files changed, 71 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme
b/Documentation/ABI/testing/sysfs-platform-dfl-fme
index 8fa4feb..b8327e9 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
@@ -21,3 +21,26 @@ Contact: Wu Hao
Description: Read-only. It returns Bitstream (static FPGA region) meta
data, which includes the synthesis date, seed and other
information of this static FPGA region.
+
+What: /sys/bus/platform/devices/dfl-fme.0/cache_size
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns cache size of this FPGA device.
+
+What: /sys/bus/platform/devices/dfl-fme.0/fabric_version
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns fabric version of this FPGA device.
+ Userspace applications need this information to select
+ best data channels per different fabric design.
+
+What: /sys/bus/platform/devices/dfl-fme.0/socket_id
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns socket_id to indicate which socket
+ this FPGA belongs to, only valid for integrated solution.
+ User only needs this information, in case standard numa node
+ can't provide correct information.
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 38c6342..8339ee8 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -75,10 +75,58 @@ static ssize_t bitstream_metadata_show(struct device *dev,
}
static DEVICE_ATTR_RO(bitstream_metadata);
+static ssize_t cache_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
+
+ v = readq(base + FME_HDR_CAP);
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+(unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
+}
+static DEVICE_ATTR_RO(cache_size);
+
+static ssize_t fabric_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
+
+ v = readq(base + FME_HDR_CAP);
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+(unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
+}
+static DEVICE_ATTR_RO(fabric_version);
+
+static ssize_t socket_id_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
+
+ v = readq(base + FME_HDR_CAP);
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n",
+(unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
+}
+static DEVICE_ATTR_RO(socket_id);
+
static const struct attribute *fme_hdr_attrs[] = {
_attr_ports_num.attr,
_attr_bitstream_id.attr,
_attr_bitstream_metadata.attr,
+ _attr_cache_size.attr,
+ _attr_fabric_version.attr,
+ _attr_socket_id.attr,
NULL,
};
--
2.7.4
[PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support
STP (SignalTap) is one of the private features under the port for
debugging. This patch adds private feature driver support for it
to allow userspace applications to mmap related mmio region and
provide STP service.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-afu-main.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 754729e..14970a4 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -518,6 +518,36 @@ static const struct dfl_feature_ops port_afu_ops = {
.uinit = port_afu_uinit,
};
+static int port_stp_init(struct platform_device *pdev,
+struct dfl_feature *feature)
+{
+ struct resource *res = >resource[feature->resource_index];
+
+ dev_dbg(>dev, "PORT STP Init.\n");
+
+ return afu_mmio_region_add(dev_get_platdata(>dev),
+ DFL_PORT_REGION_INDEX_STP,
+ resource_size(res), res->start,
+ DFL_PORT_REGION_MMAP | DFL_PORT_REGION_READ |
+ DFL_PORT_REGION_WRITE);
+}
+
+static void port_stp_uinit(struct platform_device *pdev,
+ struct dfl_feature *feature)
+{
+ dev_dbg(>dev, "PORT STP UInit.\n");
+}
+
+static const struct dfl_feature_id port_stp_id_table[] = {
+ {.id = PORT_FEATURE_ID_STP,},
+ {0,}
+};
+
+static const struct dfl_feature_ops port_stp_ops = {
+ .init = port_stp_init,
+ .uinit = port_stp_uinit,
+};
+
static struct dfl_feature_driver port_feature_drvs[] = {
{
.id_table = port_hdr_id_table,
@@ -532,6 +562,10 @@ static struct dfl_feature_driver port_feature_drvs[] = {
.ops = _err_ops,
},
{
+ .id_table = port_stp_id_table,
+ .ops = _stp_ops,
+ },
+ {
.ops = NULL,
}
};
--
2.7.4
[PATCH 16/17] fpga: dfl: fme: add global error reporting support
This patch adds support for global error reporting for FPGA Management Engine (FME), it introduces sysfs interfaces to report different error detected by the hardware, and allow user to clear errors or inject error for testing purpose. Signed-off-by: Luwei Kang Signed-off-by: Ananda Ravuri Signed-off-by: Xu Yilun Signed-off-by: Wu Hao --- Documentation/ABI/testing/sysfs-platform-dfl-fme | 58 drivers/fpga/Makefile| 2 +- drivers/fpga/dfl-fme-error.c | 390 +++ drivers/fpga/dfl-fme-main.c | 4 + drivers/fpga/dfl-fme.h | 2 + drivers/fpga/dfl.h | 2 + 6 files changed, 457 insertions(+), 1 deletion(-) create mode 100644 drivers/fpga/dfl-fme-error.c diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme index 4b6448f..38f9cdd 100644 --- a/Documentation/ABI/testing/sysfs-platform-dfl-fme +++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme @@ -156,3 +156,61 @@ KernelVersion: 5.2 Contact: Wu Hao Description: Read-only. Read this file to get power limit for fpga, it is only valid for integrated solution. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/fme-errors/errors +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. Read this file to get errors detected by hardware. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/fme-errors/first_error +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. Read this file to get the first error detected by + hardware. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/fme-errors/next_error +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. Read this file to get the second error detected by + hardware. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/fme-errors/clear +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Write-only. Write error code to this file to clear errors. If + the input error code doesn't match, it returns -EBUSY. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie0_errors +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. It returns errors detected on pcie0 link. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie1_errors +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. It returns errors detected on pcie1 link. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/nonfatal_errors +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. It returns non-fatal errors detected. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/catfatal_errors +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-only. It returns catastrophic and fatal errors detected. + +What: /sys/bus/platform/devices/dfl-fme.0/errors/inject_error +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Write this file to inject errors for testing + purpose. Read this file to check errors injected. diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index f1f0af7..1a9fa3d 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o -dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o +dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o diff --git a/drivers/fpga/dfl-fme-error.c b/drivers/fpga/dfl-fme-error.c new file mode 100644 index 000..f2bd5f8 --- /dev/null +++ b/drivers/fpga/dfl-fme-error.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Management Engine Error Management + * + * Copyright 2019 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Mitchel, Henry + */ + +#include + +#include "dfl.h" +#include "dfl-fme.h" + +#define FME_ERROR_MASK 0x8 +#define FME_ERROR 0x10 +#define MBP_ERROR BIT_ULL(6) +#define PCIE0_ERROR_MASK 0x18 +#define PCIE0_ERROR0x20 +#define PCIE1_ERROR_MASK 0x28 +#define PCIE1_ERROR0x30 +#define FME_FIRST_ERROR0x38 +#define FME_NEXT_ERROR 0x40 +#define RAS_NONFAT_ERROR_MASK 0x48 +#define RAS_NONFAT_ERROR
[PATCH 11/17] fpga: dfl: afu: add error reporting support.
Error reporting is one important private feature, it reports error
detected on port and accelerated function unit (AFU). It introduces
several sysfs interfaces to allow userspace to check and clear
errors detected by hardware.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-port | 29 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-afu-error.c | 225 ++
drivers/fpga/dfl-afu-main.c | 4 +
drivers/fpga/dfl-afu.h| 4 +
5 files changed, 263 insertions(+)
create mode 100644 drivers/fpga/dfl-afu-error.c
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port
b/Documentation/ABI/testing/sysfs-platform-dfl-port
index f611e47..e6140aa 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-port
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
@@ -79,3 +79,32 @@ KernelVersion: 5.2
Contact: Wu Hao
Description: Read-only. Read this file to get the status of issued command
to userclck_freqcntrcmd.
+
+What: /sys/bus/platform/devices/dfl-port.0/errors/errors
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get errors detected on port and
+ Accelerated Function Unit (AFU).
+
+What: /sys/bus/platform/devices/dfl-port.0/errors/first_error
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the first error detected by
+ hardware.
+
+What: /sys/bus/platform/devices/dfl-port.0/errors/first_malformed_req
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the first malformed request
+ captured by hardware.
+
+What: /sys/bus/platform/devices/dfl-port.0/errors/clear
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Write-only. Write error code to this file to clear errors. If
+ the input error code doesn't match, it returns -EBUSY error
+ code.
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index c0dd4c8..f1f0af7 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_FPGA_DFL_AFU)+= dfl-afu.o
dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
+dfl-afu-objs += dfl-afu-error.o
# Drivers for FPGAs which implement DFL
obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
diff --git a/drivers/fpga/dfl-afu-error.c b/drivers/fpga/dfl-afu-error.c
new file mode 100644
index 000..b66bd4a
--- /dev/null
+++ b/drivers/fpga/dfl-afu-error.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for FPGA Accelerated Function Unit (AFU) Error Reporting
+ *
+ * Copyright 2019 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Wu Hao
+ * Xiao Guangrong
+ * Joseph Grecco
+ * Enno Luebbers
+ * Tim Whisonant
+ * Ananda Ravuri
+ * Mitchel Henry
+ */
+
+#include
+
+#include "dfl-afu.h"
+
+#define PORT_ERROR_MASK0x8
+#define PORT_ERROR 0x10
+#define PORT_FIRST_ERROR 0x18
+#define PORT_MALFORMED_REQ00x20
+#define PORT_MALFORMED_REQ10x28
+
+#define ERROR_MASK GENMASK_ULL(63, 0)
+
+/* mask or unmask port errors by the error mask register. */
+static void __port_err_mask(struct device *dev, bool mask)
+{
+ void __iomem *base;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
+
+ writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK);
+}
+
+/* clear port errors. */
+static int __port_err_clear(struct device *dev, u64 err)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ void __iomem *base_err, *base_hdr;
+ int ret;
+ u64 v;
+
+ base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
+ base_hdr = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ /*
+* clear Port Errors
+*
+* - Check for AP6 State
+* - Halt Port by keeping Port in reset
+* - Set PORT Error mask to all 1 to mask errors
+* - Clear all errors
+* - Set Port mask to all 0 to enable errors
+* - All errors start capturing new errors
+* - Enable Port by pulling the port out of reset
+*/
+
+ /* if device is still in AP6 power state, can not clear any error. */
+ v = readq(base_hdr + PORT_HDR_STS);
+ if (FIELD_GET(PORT_STS_PWR_STATE, v) == PORT_STS_PWR_STATE_AP6) {
+ dev_err(dev, "Could not clear errors, device in AP6 state.\n");
+ return -EBUSY;
+ }
+
+ /* Halt Port by keeping Port in reset */
+ ret = __port_disable(pdev);
+ if (ret)
+ return
[PATCH 15/17] fpga: dfl: fme: add power management support
This patch adds support for power management private feature under
FPGA Management Engine (FME), sysfs interfaces are introduced for
different power management functions, users could use these sysfs
interface to get current number of consumed power, throttling
thresholds, threshold status and other information, and configure
different value for throttling thresholds too.
Signed-off-by: Luwei Kang
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-fme | 56 +
drivers/fpga/dfl-fme-main.c | 257 +++
2 files changed, 313 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme
b/Documentation/ABI/testing/sysfs-platform-dfl-fme
index d3aeb88..4b6448f 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
@@ -100,3 +100,59 @@ Description: Read-only. Read this file to get the
policy of temperature
threshold1. It only supports two value (policy):
0 - AP2 state (90% throttling)
1 - AP1 state (50% throttling)
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/consumed
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns current power consumed by FPGA.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/threshold1
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-Write. Read/Write this file to get/set current power
+ threshold1 in Watts.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/threshold2
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-Write. Read/Write this file to get/set current power
+ threshold2 in Watts.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/threshold1_status
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns 1 if power consumption reaches the
+ threshold1, otherwise 0.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/threshold2_status
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns 1 if power consumption reaches the
+ threshold2, otherwise 0.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/ltr
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get current Latency Tolerance
+ Reporting (ltr) value, it's only valid for integrated
+ solution as it blocks CPU on low power state.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/xeon_limit
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get power limit for xeon, it
+ is only valid for integrated solution.
+
+What: /sys/bus/platform/devices/dfl-fme.0/power_mgmt/fpga_limit
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get power limit for fpga, it
+ is only valid for integrated solution.
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 449a17d..dafa6580 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -415,6 +415,259 @@ static const struct dfl_feature_ops fme_thermal_mgmt_ops
= {
.uinit = fme_thermal_mgmt_uinit,
};
+#define FME_PWR_STATUS 0x8
+#define FME_LATENCY_TOLERANCE BIT_ULL(18)
+#define PWR_CONSUMED GENMASK_ULL(17, 0)
+
+#define FME_PWR_THRESHOLD 0x10
+#define PWR_THRESHOLD1 GENMASK_ULL(6, 0) /* in Watts */
+#define PWR_THRESHOLD2 GENMASK_ULL(14, 8) /* in Watts */
+#define PWR_THRESHOLD_MAX 0x7f
+#define PWR_THRESHOLD1_STATUS BIT_ULL(16)
+#define PWR_THRESHOLD2_STATUS BIT_ULL(17)
+
+#define FME_PWR_XEON_LIMIT 0x18
+#define XEON_PWR_LIMIT GENMASK_ULL(14, 0)
+#define XEON_PWR_ENBIT_ULL(15)
+#define FME_PWR_FPGA_LIMIT 0x20
+#define FPGA_PWR_LIMIT GENMASK_ULL(14, 0)
+#define FPGA_PWR_ENBIT_ULL(15)
+
+#define POWER_ATTR(_name, _mode, _show, _store)\
+struct device_attribute power_attr_##_name = \
+ __ATTR(_name, _mode, _show, _store)
+
+#define POWER_ATTR_RO(_name, _show)\
+ POWER_ATTR(_name, 0444, _show, NULL)
+
+#define POWER_ATTR_RW(_name, _show, _store)\
+ POWER_ATTR(_name, 0644, _show, _store)
+
+static ssize_t pwr_consumed_show(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+ void __iomem *base;
+ u64 v;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_POWER_MGMT);
+
+ v = readq(base +
[PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function.
As these two functions are used by other private features. e.g.
in error reporting private feature, it requires to check port status
and reset port for error clearing.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-afu-main.c | 25 ++---
drivers/fpga/dfl-afu.h | 3 +++
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 2916876..e727d9b 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -24,14 +24,16 @@
#define DRV_VERSION"0.8"
/**
- * port_enable - enable a port
+ * __port_enable - enable a port
* @pdev: port platform device.
*
* Enable Port by clear the port soft reset bit, which is set by default.
* The AFU is unable to respond to any MMIO access while in reset.
- * port_enable function should only be used after port_disable function.
+ * __port_enable function should only be used after __port_disable function.
+ *
+ * The caller needs to hold lock for protection.
*/
-static void port_enable(struct platform_device *pdev)
+void __port_enable(struct platform_device *pdev)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(>dev);
void __iomem *base;
@@ -54,13 +56,14 @@ static void port_enable(struct platform_device *pdev)
#define RST_POLL_TIMEOUT 1000 /* us */
/**
- * port_disable - disable a port
+ * __port_disable - disable a port
* @pdev: port platform device.
*
- * Disable Port by setting the port soft reset bit, it puts the port into
- * reset.
+ * Disable Port by setting the port soft reset bit, it puts the port into
reset.
+ *
+ * The caller needs to hold lock for protection.
*/
-static int port_disable(struct platform_device *pdev)
+int __port_disable(struct platform_device *pdev)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(>dev);
void __iomem *base;
@@ -106,9 +109,9 @@ static int __port_reset(struct platform_device *pdev)
{
int ret;
- ret = port_disable(pdev);
+ ret = __port_disable(pdev);
if (!ret)
- port_enable(pdev);
+ __port_enable(pdev);
return ret;
}
@@ -810,9 +813,9 @@ static int port_enable_set(struct platform_device *pdev,
bool enable)
mutex_lock(>lock);
if (enable)
- port_enable(pdev);
+ __port_enable(pdev);
else
- ret = port_disable(pdev);
+ ret = __port_disable(pdev);
mutex_unlock(>lock);
return ret;
diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h
index 0c7630a..35e60c5 100644
--- a/drivers/fpga/dfl-afu.h
+++ b/drivers/fpga/dfl-afu.h
@@ -79,6 +79,9 @@ struct dfl_afu {
struct dfl_feature_platform_data *pdata;
};
+void __port_enable(struct platform_device *pdev);
+int __port_disable(struct platform_device *pdev);
+
void afu_mmio_region_init(struct dfl_feature_platform_data *pdata);
int afu_mmio_region_add(struct dfl_feature_platform_data *pdata,
u32 region_index, u64 region_size, u64 phys, u32 flags);
--
2.7.4
[PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces.
This patch adds virtualization support description for DFL based FPGA devices (based on PCIe SRIOV), and introductions to new interfaces added by new dfl private features. Signed-off-by: Xu Yilun Signed-off-by: Wu Hao --- Documentation/fpga/dfl.txt | 115 + 1 file changed, 115 insertions(+) diff --git a/Documentation/fpga/dfl.txt b/Documentation/fpga/dfl.txt index 6df4621..360c1d9 100644 --- a/Documentation/fpga/dfl.txt +++ b/Documentation/fpga/dfl.txt @@ -84,6 +84,8 @@ The following functions are exposed through ioctls: Get driver API version (DFL_FPGA_GET_API_VERSION) Check for extensions (DFL_FPGA_CHECK_EXTENSION) Program bitstream (DFL_FPGA_FME_PORT_PR) + Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN) + Release port from PF (DFL_FPGA_FME_PORT_RELEASE) More functions are exposed through sysfs (/sys/class/fpga_region/regionX/dfl-fme.n/): @@ -99,6 +101,24 @@ More functions are exposed through sysfs one FPGA device may have more than one port, this sysfs interface indicates how many ports the FPGA device has. + Power management (power_mgmt/) + power management sysfs interfaces allow user to read power management + information (power consumption, power limits, throttling thresholds, + thresholds status, etc) and configure power thresholds for different + throttling levels. + + Thermal management (thermal_mgmt/) + thermal management sysfs interfaces allow user to read temperature, + thresholds, thresholds status and other thermal related information. + + Global error reporting management (errors/) + error reporting sysfs interfaces allow user to read errors detected by the + hardware, and clear the logged errors. + + Performance counters (perf/) + performance counters sysfs interfaces allow user to use different counters + to get performance data. + FIU - PORT == @@ -139,6 +159,10 @@ More functions are exposed through sysfs: Read Accelerator GUID (afu_id) afu_id indicates which PR bitstream is programmed to this AFU. + Error reporting (errors/) + error reporting sysfs interfaces allow user to read port/afu errors + detected by the hardware, and clear the logged errors. + DFL Framework Overview == @@ -212,6 +236,97 @@ the compat_id exposed by the target FPGA region. This check is usually done by userspace before calling the reconfiguration IOCTL. +FPGA virtualization - PCIe SRIOV + +This section describes the virtualization support on DFL based FPGA device to +enable accessing an accelerator from applications running in a virtual machine +(VM). This section only describes the PCIe based FPGA device with SRIOV support. + +Features supported by the particular FPGA device are exposed through Device +Feature Lists, as illustrated below: + + +---+ +-+ + | PF | | VF | + +---+ +-+ + ^^ ^ ^ + || | | ++-||-|--|---+ +| || | | | +| +-+ +---+ +---+ +---+ | +| | FME | | Port0 | | Port1 | | Port2 | | +| +-+ +---+ +---+ +---+ | +| ^ ^ ^ | +| | | | | +| +---+ +--+ +---+ | +| | AFU | | AFU | | AFU | | +| +---+ +--+ +---+ | +| | +|DFL based FPGA PCIe Device | ++---+ + +FME is always accessed through the physical function (PF). + +Ports (and related AFUs) are accessed via PF by default, but could be exposed +through virtual function (VF) devices via PCIe SRIOV. Each VF only contains +1 Port and 1 AFU for isolation. Users could assign individual VFs (accelerators) +created via PCIe SRIOV interface, to virtual machines. + +The driver organization in virtualization case is illustrated below: + + +---++--++--+ | + | FME || FME || FME | | + | FPGA || FPGA || FPGA | | + |Manager||Bridge||Region| | + +---++--++--+ | + +---+ ++ | ++ + | FME | | AFU | | | AFU | + | Module| | Module | | | Module | + +---+ ++ | ++ ++---+ | +---+ +| FPGA Container Device | | | FPGA Container Device | +| (FPGA Base Region) | | | (FPGA Base Region) | +
[PATCH 17/17] fpga: dfl: fme: add performance reporting support
This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Actually it supports 4 categories performance counters, 'clock', 'cache', 'iommu' and 'fabric', user could read the performance counter via exposed sysfs interfaces. Please refer to sysfs doc for more details. Signed-off-by: Luwei Kang Signed-off-by: Xu Yilun Signed-off-by: Wu Hao --- Documentation/ABI/testing/sysfs-platform-dfl-fme | 86 ++ drivers/fpga/Makefile| 1 + drivers/fpga/dfl-fme-main.c | 4 + drivers/fpga/dfl-fme-perf.c | 950 +++ drivers/fpga/dfl-fme.h | 2 + drivers/fpga/dfl.c | 1 + drivers/fpga/dfl.h | 2 + 7 files changed, 1046 insertions(+) create mode 100644 drivers/fpga/dfl-fme-perf.c diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme index 38f9cdd..12f9449 100644 --- a/Documentation/ABI/testing/sysfs-platform-dfl-fme +++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme @@ -214,3 +214,89 @@ KernelVersion: 5.2 Contact: Wu Hao Description: Read-Write. Write this file to inject errors for testing purpose. Read this file to check errors injected. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/clock +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read for Accelerator Function Unit (AFU) clock + counter. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/cache/freeze +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Read and Write this file to freeze or unfreeze + the 'cache' category performance counters. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/cache/ +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read 'cache' category performance counters: + read_hit, read_miss, write_hit, write_miss, hold_request, + data_write_port_contention, tag_write_port_contention, + tx_req_stall, rx_req_stall and rx_eviction. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/iommu/freeze +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Read and Write this file to freeze or unfreeze + the 'iommu' category performance counters. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/iommu/ +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read 'iommu' category 'sip' sub category + performance counters: iotlb_4k_hit, iotlb_2m_hit, + iotlb_1g_hit, slpwc_l3_hit, slpwc_l4_hit, rcc_hit, + rcc_miss, iotlb_4k_miss, iotlb_2m_miss, iotlb_1g_miss, + slpwc_l3_miss and slpwc_l4_miss. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/iommu/afu0/ +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read 'iommu' category 'afuX' sub category + performance counters: read_transaction, write_transaction, + devtlb_read_hit, devtlb_write_hit, devtlb_4k_fill, + devtlb_2m_fill and devtlb_1g_fill. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/fabric/freeze +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Read and Write this file to freeze or unfreeze + the 'fabric' category performance counters. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/fabric/ +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read 'fabric' category performance counters: + pcie0_read, pcie0_write, pcie1_read, pcie1_write, + upi_read, upi_write and mmio_read. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/fabric/enable +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Read and write this file to enable device + level fabric counters sysfs interfaces in the same folder. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/fabric/port0/ +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Only. Read 'fabric' category "portX" sub category + performance counters: pcie0_read, pcie0_write, pcie1_read, + pcie1_write, upi_read, upi_write and mmio_read. + +What: /sys/bus/platform/devices/dfl-fme.0/perf/fabric/port0/enable +Date: March 2019 +KernelVersion: 5.2 +Contact: Wu Hao +Description: Read-Write. Read and write this file to enable port level + fabric counters sysfs interfaces in the same folder. diff --git
[PATCH 14/17] fpga: dfl: fme: add thermal management support
This patch adds support to thermal management private feature for DFL
FPGA Management Engine (FME). As thermal throttling is handled by
hardware automatically per pre-defined thresholds, this private
feature driver only provides read-only sysfs interfaces for user
to read temperature, thresholds, threshold policy and other info.
Signed-off-by: Luwei Kang
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-fme | 56 +++
drivers/fpga/dfl-fme-main.c | 202 +++
2 files changed, 258 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme
b/Documentation/ABI/testing/sysfs-platform-dfl-fme
index b8327e9..d3aeb88 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
@@ -44,3 +44,59 @@ Description: Read-only. It returns socket_id to indicate
which socket
this FPGA belongs to, only valid for integrated solution.
User only needs this information, in case standard numa node
can't provide correct information.
+
+What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/temperature
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns temperature (in Celsius) of this FPGA
+ device.
+
+What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the temperature threshold1
+ (in Celsius).
+
+What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold2
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the temperature threshold2
+ (in Celsius).
+
+What: /sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/trip_threshold
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns trip threshold (in Celsius), once FPGA
+ temperature reaches trip threshold, it triggers a fatal event
+ to board management controller (BMC) to shutdown FPGA.
+
+What:
/sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1_status
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns 1 if temperature reaches threshold1,
+ otherwise 0. Once temperature reaches threshold1, hardware
+ will automatically enter throttling state (AP1 - 50%
+ or AP2 - 90% throttling, see 'threshold1_policy').
+
+What:
/sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold2_status
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. It returns 1 if temperature reaches threshold2,
+ otherwise 0. Once temperature reaches threshold2, hardware
+ will automatically enter the deepest throttling state (AP6
+ - 100% throttling).
+
+What:
/sys/bus/platform/devices/dfl-fme.0/thermal_mgmt/threshold1_policy
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the policy of temperature
+ threshold1. It only supports two value (policy):
+ 0 - AP2 state (90% throttling)
+ 1 - AP1 state (50% throttling)
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 8339ee8..449a17d 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include "dfl.h"
#include "dfl-fme.h"
@@ -217,6 +218,203 @@ static const struct dfl_feature_ops fme_hdr_ops = {
.ioctl = fme_hdr_ioctl,
};
+#define FME_THERM_THRESHOLD0x8
+#define TEMP_THRESHOLD1GENMASK_ULL(6, 0)
+#define TEMP_THRESHOLD1_EN BIT_ULL(7)
+#define TEMP_THRESHOLD2GENMASK_ULL(14, 8)
+#define TEMP_THRESHOLD2_EN BIT_ULL(15)
+#define TRIP_THRESHOLD GENMASK_ULL(30, 24)
+#define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
+#define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
+/* threshold1 policy: 0 - AP2 (90% throttle) / 1 - AP1 (50% throttle) */
+#define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
+
+#define FME_THERM_RDSENSOR_FMT10x10
+#define FPGA_TEMPERATURE GENMASK_ULL(6, 0)
+
+#define FME_THERM_CAP 0x20
+#define TEMP_THRESHOLD_DISABLE BIT_ULL(0)
+
+#define THERMAL_ATTR(_name, _mode, _show, _store) \
+struct device_attribute thermal_attr_##_name = \
+ __ATTR(_name, _mode, _show, _store)
+
+#define THERMAL_ATTR_RO(_name, _show) \
+ THERMAL_ATTR(_name, 0444, _show, NULL)
+
+static ssize_t
[PATCH 08/17] fpga: dfl: afu: add userclock sysfs interfaces.
This patch introduces userclock sysfs interfaces for AFU, user
could use these interfaces for clock setting to AFU.
Please note that, this is only working for port header feature
with revision 0, for later revisions, userclock setting is moved
to a separated private feature, so one revision sysfs interface
is exposed to userspace application for this purpose too.
Signed-off-by: Ananda Ravuri
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
Documentation/ABI/testing/sysfs-platform-dfl-port | 35 +++
drivers/fpga/dfl-afu-main.c | 114 +-
drivers/fpga/dfl.h| 4 +
3 files changed, 152 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port
b/Documentation/ABI/testing/sysfs-platform-dfl-port
index f0c4e92..f611e47 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-port
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
@@ -44,3 +44,38 @@ Contact: Wu Hao
Description: Read-write. Read and set AFU latency tolerance reporting value.
Set ltr to 1 if the AFU can tolerate latency >= 40us or set it
to 0 if it is latency sensitive.
+
+What: /sys/bus/platform/devices/dfl-port.0/revision
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the revision of port header
+ feature.
+
+What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcmd
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Write-only. User writes command to this interface to set
+ userclock to AFU.
+
+What: /sys/bus/platform/devices/dfl-port.0/userclk_freqsts
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the status of issued command
+ to userclck_freqcmd.
+
+What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcntrcmd
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Write-only. User writes command to this interface to set
+ userclock counter.
+
+What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcntrsts
+Date: March 2019
+KernelVersion: 5.2
+Contact: Wu Hao
+Description: Read-only. Read this file to get the status of issued command
+ to userclck_freqcntrcmd.
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 2ffec06..82fd80a 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -144,6 +144,17 @@ id_show(struct device *dev, struct device_attribute *attr,
char *buf)
static DEVICE_ATTR_RO(id);
static ssize_t
+revision_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ void __iomem *base;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ return scnprintf(buf, PAGE_SIZE, "%x\n", dfl_feature_revision(base));
+}
+static DEVICE_ATTR_RO(revision);
+
+static ssize_t
ltr_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
@@ -282,6 +293,7 @@ static DEVICE_ATTR_RO(power_state);
static const struct attribute *port_hdr_attrs[] = {
_attr_id.attr,
+ _attr_revision.attr,
_attr_ltr.attr,
_attr_ap1_event.attr,
_attr_ap2_event.attr,
@@ -289,14 +301,113 @@ static const struct attribute *port_hdr_attrs[] = {
NULL,
};
+static ssize_t
+userclk_freqcmd_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ u64 userclk_freq_cmd;
+ void __iomem *base;
+
+ if (kstrtou64(buf, 0, _freq_cmd))
+ return -EINVAL;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ mutex_lock(>lock);
+ writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0);
+ mutex_unlock(>lock);
+
+ return count;
+}
+static DEVICE_ATTR_WO(userclk_freqcmd);
+
+static ssize_t
+userclk_freqcntrcmd_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+ u64 userclk_freqcntr_cmd;
+ void __iomem *base;
+
+ if (kstrtou64(buf, 0, _freqcntr_cmd))
+ return -EINVAL;
+
+ base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
+
+ mutex_lock(>lock);
+ writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1);
+ mutex_unlock(>lock);
+
+ return count;
+}
+static DEVICE_ATTR_WO(userclk_freqcntrcmd);
+
+static ssize_t
+userclk_freqsts_show(struct device *dev, struct device_attribute *attr,
+char
[PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.
FME_PR_INTFC_ID is used as compat_id for fpga manager and region, but high 64 bits and low 64 bits of the compat_id are swapped by mistake. This patch fixes this problem by fixing register address. Signed-off-by: Wu Hao --- drivers/fpga/dfl-fme-mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index 76f3770..b3f7eee 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -30,8 +30,8 @@ #define FME_PR_STS 0x10 #define FME_PR_DATA0x18 #define FME_PR_ERR 0x20 -#define FME_PR_INTFC_ID_H 0xA8 -#define FME_PR_INTFC_ID_L 0xB0 +#define FME_PR_INTFC_ID_L 0xA8 +#define FME_PR_INTFC_ID_H 0xB0 /* FME PR Control Register Bitfield */ #define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */ -- 2.7.4
[PATCH 00/17] add new features for FPGA DFL drivers
This patchset adds more features support for FPGA Device Feature List (DFL) drivers, including PR enhancement, virtualization support based on PCIe SRIOV, private features to Port, private features to FME, and enhancement to DFL framework. Please refer to details in below list. Patch 1: A bug fixing to current dfl-fme-mgr driver. Patch 2-3: add 512bit data width PR support. Patch 4-6: add virtualization support based on PCIe SRIOV. Patch 7-8: add new AFU state and userclock related sysfs to dfl-afu. Patch 9-10: enhancement to DFL framework in order to support id_table. Patch 11: add error reporting private feature support to dfl-afu. Patch 12: add STP (SignalTap) private feature support to dfl-afu. Patch 13: add capability sysfs interfaces to dfl-fme. Patch 14: add thermal management private feature support to dfl-fme. Patch 15: add power management private feature support to dfl-fme. Patch 16: add global error reporitng private feature support to dfl-fme. Patch 17: add performance reporting support to dfl-fme. Wu Hao (17): fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address. fpga: dfl: fme: align PR buffer size per PR datawidth fpga: dfl: fme: support 512bit data width PR Documentation: fpga: dfl: add descriptions for virtualization and new interfaces. fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support. fpga: dfl: pci: enable SRIOV support. fpga: dfl: afu: add AFU state related sysfs interfaces fpga: dfl: afu: add userclock sysfs interfaces. fpga: dfl: add id_table for dfl private feature driver fpga: dfl: afu: export __port_enable/disable function. fpga: dfl: afu: add error reporting support. fpga: dfl: afu: add STP (SignalTap) support fpga: dfl: fme: add capability sysfs interfaces fpga: dfl: fme: add thermal management support fpga: dfl: fme: add power management support fpga: dfl: fme: add global error reporting support fpga: dfl: fme: add performance reporting support Documentation/ABI/testing/sysfs-platform-dfl-fme | 279 +++ Documentation/ABI/testing/sysfs-platform-dfl-port | 94 +++ Documentation/fpga/dfl.txt| 115 +++ drivers/fpga/Makefile | 4 +- drivers/fpga/dfl-afu-error.c | 225 + drivers/fpga/dfl-afu-main.c | 335 +++- drivers/fpga/dfl-afu.h| 7 + drivers/fpga/dfl-fme-error.c | 390 + drivers/fpga/dfl-fme-main.c | 583 - drivers/fpga/dfl-fme-mgr.c| 79 +- drivers/fpga/dfl-fme-perf.c | 950 ++ drivers/fpga/dfl-fme-pr.c | 64 +- drivers/fpga/dfl-fme.h| 9 +- drivers/fpga/dfl-pci.c| 40 + drivers/fpga/dfl.c| 170 +++- drivers/fpga/dfl.h| 56 +- include/uapi/linux/fpga-dfl.h | 32 + 17 files changed, 3355 insertions(+), 77 deletions(-) create mode 100644 drivers/fpga/dfl-afu-error.c create mode 100644 drivers/fpga/dfl-fme-error.c create mode 100644 drivers/fpga/dfl-fme-perf.c -- 2.7.4
[PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver
This patch adds id_table for each dfl private feature driver,
it allows to reuse same private feature driver to match and support
multiple dfl private features.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
---
drivers/fpga/dfl-afu-main.c | 14 --
drivers/fpga/dfl-fme-main.c | 11 ---
drivers/fpga/dfl-fme-pr.c | 7 ++-
drivers/fpga/dfl-fme.h | 3 ++-
drivers/fpga/dfl.c | 21 +++--
drivers/fpga/dfl.h | 21 +++--
6 files changed, 62 insertions(+), 15 deletions(-)
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 82fd80a..2916876 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -440,6 +440,11 @@ port_hdr_ioctl(struct platform_device *pdev, struct
dfl_feature *feature,
return ret;
}
+static const struct dfl_feature_id port_hdr_id_table[] = {
+ {.id = PORT_FEATURE_ID_HEADER,},
+ {0,}
+};
+
static const struct dfl_feature_ops port_hdr_ops = {
.init = port_hdr_init,
.uinit = port_hdr_uinit,
@@ -500,6 +505,11 @@ static void port_afu_uinit(struct platform_device *pdev,
sysfs_remove_files(>dev.kobj, port_afu_attrs);
}
+static const struct dfl_feature_id port_afu_id_table[] = {
+ {.id = PORT_FEATURE_ID_AFU,},
+ {0,}
+};
+
static const struct dfl_feature_ops port_afu_ops = {
.init = port_afu_init,
.uinit = port_afu_uinit,
@@ -507,11 +517,11 @@ static const struct dfl_feature_ops port_afu_ops = {
static struct dfl_feature_driver port_feature_drvs[] = {
{
- .id = PORT_FEATURE_ID_HEADER,
+ .id_table = port_hdr_id_table,
.ops = _hdr_ops,
},
{
- .id = PORT_FEATURE_ID_AFU,
+ .id_table = port_afu_id_table,
.ops = _afu_ops,
},
{
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
index 8b2a337..38c6342 100644
--- a/drivers/fpga/dfl-fme-main.c
+++ b/drivers/fpga/dfl-fme-main.c
@@ -158,6 +158,11 @@ static long fme_hdr_ioctl(struct platform_device *pdev,
return -ENODEV;
}
+static const struct dfl_feature_id fme_hdr_id_table[] = {
+ {.id = FME_FEATURE_ID_HEADER,},
+ {0,}
+};
+
static const struct dfl_feature_ops fme_hdr_ops = {
.init = fme_hdr_init,
.uinit = fme_hdr_uinit,
@@ -166,12 +171,12 @@ static const struct dfl_feature_ops fme_hdr_ops = {
static struct dfl_feature_driver fme_feature_drvs[] = {
{
- .id = FME_FEATURE_ID_HEADER,
+ .id_table = fme_hdr_id_table,
.ops = _hdr_ops,
},
{
- .id = FME_FEATURE_ID_PR_MGMT,
- .ops = _mgmt_ops,
+ .id_table = fme_pr_mgmt_id_table,
+ .ops = _pr_mgmt_ops,
},
{
.ops = NULL,
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 8a0e46a..b054ac6 100644
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -482,7 +482,12 @@ static long fme_pr_ioctl(struct platform_device *pdev,
return ret;
}
-const struct dfl_feature_ops pr_mgmt_ops = {
+const struct dfl_feature_id fme_pr_mgmt_id_table[] = {
+ {.id = FME_FEATURE_ID_PR_MGMT,},
+ {0}
+};
+
+const struct dfl_feature_ops fme_pr_mgmt_ops = {
.init = pr_mgmt_init,
.uinit = pr_mgmt_uinit,
.ioctl = fme_pr_ioctl,
diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h
index de20755..7a021c4 100644
--- a/drivers/fpga/dfl-fme.h
+++ b/drivers/fpga/dfl-fme.h
@@ -35,6 +35,7 @@ struct dfl_fme {
struct dfl_feature_platform_data *pdata;
};
-extern const struct dfl_feature_ops pr_mgmt_ops;
+extern const struct dfl_feature_ops fme_pr_mgmt_ops;
+extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
#endif /* __DFL_FME_H */
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index c5aa287..65f91ef 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -14,6 +14,8 @@
#include "dfl.h"
+#define DRV_VERSION"0.8"
+
static DEFINE_MUTEX(dfl_id_mutex);
/*
@@ -274,6 +276,21 @@ static int dfl_feature_instance_init(struct
platform_device *pdev,
return ret;
}
+static bool dfl_feature_drv_match(struct dfl_feature *feature,
+ struct dfl_feature_driver *driver)
+{
+ const struct dfl_feature_id *ids = driver->id_table;
+
+ if (ids) {
+ while (ids->id) {
+ if (ids->id == feature->id)
+ return true;
+ ids++;
+ }
+ }
+ return false;
+}
+
/**
* dfl_fpga_dev_feature_init - init for sub features of dfl feature device
* @pdev: feature device.
@@ -294,8 +311,7 @@ int dfl_fpga_dev_feature_init(struct platform_device *pdev,
while (drv->ops) {
dfl_fpga_dev_for_each_feature(pdata, feature) {
-
[PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth
Current driver checks if input bitstream file size is aligned or not per PR data width (default 32bits). It requires one additional step for end user when they generate the bitstream file, padding extra zeros to bitstream file to align its size per PR data width, but they don't have to as hardware will drop extra padding bytes automatically. In order to simplify the user steps, this patch aligns PR buffer size per PR data width in driver, to allow user to pass unaligned size bitstream files to driver. Signed-off-by: Xu Yilun Signed-off-by: Wu Hao --- drivers/fpga/dfl-fme-pr.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c index d9ca955..c1fb1fe 100644 --- a/drivers/fpga/dfl-fme-pr.c +++ b/drivers/fpga/dfl-fme-pr.c @@ -74,6 +74,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) struct dfl_fme *fme; unsigned long minsz; void *buf = NULL; + size_t length; int ret = 0; u64 v; @@ -85,9 +86,6 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) if (port_pr.argsz < minsz || port_pr.flags) return -EINVAL; - if (!IS_ALIGNED(port_pr.buffer_size, 4)) - return -EINVAL; - /* get fme header region */ fme_hdr = dfl_get_feature_ioaddr_by_id(>dev, FME_FEATURE_ID_HEADER); @@ -103,7 +101,13 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) port_pr.buffer_size)) return -EFAULT; - buf = vmalloc(port_pr.buffer_size); + /* +* align PR buffer per PR bandwidth, as HW ignores the extra padding +* data automatically. +*/ + length = ALIGN(port_pr.buffer_size, 4); + + buf = vmalloc(length); if (!buf) return -ENOMEM; @@ -140,7 +144,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg) fpga_image_info_free(region->info); info->buf = buf; - info->count = port_pr.buffer_size; + info->count = length; info->region_id = port_pr.port_id; region->info = info; -- 2.7.4
Re: [PATCH] RISC-V: Always compile mm/init.c with cmodel=medany
On Mon, Mar 25, 2019 at 12:44 AM Gary Guo wrote: > > > > > -Original Message- > > From: linux-riscv On Behalf Of > > Anup > > Patel > > Sent: Sunday, March 24, 2019 11:08 > > To: Palmer Dabbelt ; Albert Ou > > Cc: Anup Patel ; linux-kernel@vger.kernel.org; Mike > > Rapoport ; Christoph Hellwig ; Atish > > Patra ; Paul Walmsley ; > > linux-ri...@lists.infradead.org; Christoph Hellwig > > Subject: [PATCH] RISC-V: Always compile mm/init.c with cmodel=medany > > > > diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile > > index eb22ab49b3e0..7307609d405b 100644 > > --- a/arch/riscv/mm/Makefile > > +++ b/arch/riscv/mm/Makefile > > @@ -3,3 +3,5 @@ obj-y += fault.o > > obj-y += extable.o > > obj-y += ioremap.o > > obj-y += cacheflush.o > > + > > +CFLAGS_init.o := -mcmodel=medany > > I think you should also remove CFLAGS_setup.o from kernel/Makefile, as I > think it was there solely for the correctness of setup_vm. As setup_vm is now > in mm/init.o, the old CFLAGS probably isn't needed and should be removed in > the same patch. Disclaimer: I haven't tested it. Sure, I will remove it in v2 patch. Thanks for catching. Regards, Anup
Re: [PATCH] RISC-V: Always compile mm/init.c with cmodel=medany
On Sun, Mar 24, 2019 at 8:27 PM Christoph Hellwig wrote: > > On Sun, Mar 24, 2019 at 11:08:29AM +, Anup Patel wrote: > > Signed-off-by: Christoph Hellwig > > Signed-off-by: Mike Rapoport > > Huh? I don't think this is from Mike and me. > > > +unsigned long va_pa_offset; > > +EXPORT_SYMBOL(va_pa_offset); > > +unsigned long pfn_base; > > +EXPORT_SYMBOL(pfn_base); > > Can you move va_pa_offset and pfn_base next to the swapper_pg_dir > declaration? Thats where I move them in my current nommu patchset, > as that allows to just have a single CONFIG_NOMMU in mm/init.c. > > Otherwise this looks fine to me. Sure, no problem. I will send update and send v2. Regards, Anup
Re: [PATCH] RISC-V: Always compile mm/init.c with cmodel=medany
On Sun, Mar 24, 2019 at 10:13 PM Mike Rapoport wrote: > > On Sun, Mar 24, 2019 at 03:57:08PM +0100, Christoph Hellwig wrote: > > On Sun, Mar 24, 2019 at 11:08:29AM +, Anup Patel wrote: > > > Signed-off-by: Christoph Hellwig > > > Signed-off-by: Mike Rapoport > > > > Huh? I don't think this is from Mike and me. > > Suggested-by: would me more appropriate indeed :) Sure, I will use Suggested-by: here. Regards, Anup
[PATCH 3/3] clocksource/drivers/timer-milbeaut: Cleanup common register accesses
Aggregate common register accesses into shared functions for
maintainability.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 62 +++-
1 file changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index f478061..fa9fb4e 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -26,8 +26,8 @@
#define MLB_TMR_TMCSR_CSL_DIV2 0
#define MLB_TMR_DIV_CNT2
-#define MLB_TMR_SRC_CH (1)
-#define MLB_TMR_EVT_CH (0)
+#define MLB_TMR_SRC_CH 1
+#define MLB_TMR_EVT_CH 0
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
@@ -43,6 +43,8 @@
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
#define MLB_TIMER_RATING 500
+#define MLB_TIMER_ONESHOT 0
+#define MLB_TIMER_PERIODIC 1
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
{
@@ -59,38 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int mlb_set_state_periodic(struct clock_event_device *clk)
+static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
{
- struct timer_of *to = to_timer_of(clk);
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+ val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ if (periodic)
+ val |= MLB_TMR_TMCSR_RELD;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_stop(struct timer_of *to)
+{
+ u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- writel_relaxed(to->of_clk.period, timer_of_base(to) +
- MLB_TMR_EVT_TMRLR1_OFS);
- val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
- MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
+ val &= ~MLB_TMR_TMCSR_CNTE;
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+}
+
+static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long
cnt)
+{
+ writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
+}
+
+static int mlb_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, to->of_clk.period);
+ mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
return 0;
}
static int mlb_set_state_oneshot(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
- val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_set_state_shutdown(struct clock_event_device *clk)
{
struct timer_of *to = to_timer_of(clk);
- u32 val = MLB_TMR_TMCSR_CSL_DIV2;
- writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
return 0;
}
@@ -99,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event,
{
struct timer_of *to = to_timer_of(clk);
- writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
- writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
- MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
- MLB_TMR_TMCSR_TRG, timer_of_base(to) +
- MLB_TMR_EVT_TMCSR_OFS);
+ mlb_evt_timer_stop(to);
+ mlb_evt_timer_register_count(to, event);
+ mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
return 0;
}
static int mlb_config_clock_source(struct timer_of *to)
{
- writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
- writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
- writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
- MLB_TMR_SRC_TMCSR_OFS);
+ val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
return 0;
}
--
1.9.1
[PATCH 0/3] Bugfix and cleanup the timer driver for Milbeaut M10V
This series fixes a bug and cleanup code about timer driver for Milbeaut M10V. Since it is difficult to separate, it is integrated into a series. Sugaya Taichi (3): clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Cleanup common register accesses drivers/clocksource/timer-milbeaut.c | 66 +--- 1 file changed, 47 insertions(+), 19 deletions(-) -- 1.9.1
linux-next: Tree for Mar 25
Hi all, Changes since 20190322: Non-merge commits (relative to Linus' tree): 2741 2308 files changed, 76588 insertions(+), 37798 deletions(-) I have created today's linux-next tree at git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git (patches at http://www.kernel.org/pub/linux/kernel/next/ ). If you are tracking the linux-next tree using git, you should not use "git pull" to do so as that will try to merge the new linux-next release with the old one. You should use "git fetch" and checkout or reset to the new master. You can see which trees have been included by looking in the Next/Trees file in the source. There are also quilt-import.log and merge.log files in the Next directory. Between each merge, the tree was built with a ppc64_defconfig for powerpc, an allmodconfig for x86_64, a multi_v7_defconfig for arm and a native build of tools/perf. After the final fixups (if any), I do an x86_64 modules_install followed by builds for x86_64 allnoconfig, powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And finally, a simple boot test of the powerpc pseries_le_defconfig kernel in qemu (with and without kvm enabled). Below is a summary of the state of the merge. I am currently merging 299 trees (counting Linus' and 70 trees of bug fix patches pending for the current merge release). Stats about the size of the tree over time can be seen at http://neuling.org/linux-next-size.html . Status of my local build tests will be at http://kisskb.ellerman.id.au/linux-next . If maintainers want to give advice about cross compilers/configs that work, we are always open to add more builds. Thanks to Randy Dunlap for doing many randconfig builds. And to Paul Gortmaker for triage and bug fixes. -- Cheers, Stephen Rothwell $ git checkout master $ git reset --hard stable Merging origin/master (231c807a6071 Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip) Merging fixes/master (b352face4ca9 adfs: mark expected switch fall-throughs) Merging kspp-gustavo/for-next/kspp (1f7ae812f87e x86/syscalls: Mark expected switch fall-throughs) Merging kbuild-current/fixes (688931a5ad4e kbuild: skip sub-make for in-tree build with GNU Make 4.x) Merging arc-current/for-curr (9a18b5a412ba arch: arc: Kconfig: pedantic formatting) Merging arm-current/fixes (d410a8a49e3e ARM: 8849/1: NOMMU: Fix encodings for PMSAv8's PRBAR4/PRLAR4) Merging arm64-fixes/for-next/fixes (e5a5af771861 arm64: remove obsolete selection of MULTI_IRQ_HANDLER) Merging m68k-current/for-linus (28713169d879 m68k: Add -ffreestanding to CFLAGS) Merging powerpc-fixes/fixes (92edf8df0ff2 powerpc/security: Fix spectre_v2 reporting) Merging sparc/master (7d762d69145a afs: Fix manually set volume location server list) Merging fscrypt-current/for-stable (ae64f9bd1d36 Linux 4.15-rc2) Merging net/master (526949e877f4 rxrpc: avoid clang -Wuninitialized warning) Merging bpf/master (83d163124cf1 bpf: verifier: propagate liveness on all frames) Merging ipsec/master (01ce31c57b3f vti4: removed duplicate log message.) Merging netfilter/master (5f543a54eec0 net: hns3: fix for not calculating tx bd num correctly) Merging ipvs/master (b2e3d68d1251 netfilter: nft_compat: destroy function must not have side effects) Merging wireless-drivers/master (7dfc45e6282a mt76x02: do not enable RTS/CTS by default) Merging mac80211/master (d235c48b40d3 net: dsa: mv88e6xxx: power serdes on/off for 10G interfaces on 6390X) Merging rdma-fixes/for-rc (ec4fe4bcc584 i40iw: Avoid panic when handling the inetdev event) Merging sound-current/for-linus (4fc90fb883fc ALSA: hda/ca0132 - Simplify alt firmware loading code) Merging sound-asoc-fixes/for-linus (0ff4e8c61b79 ASoC: fsl_esai: fix channel swap issue when stream starts) Merging regmap-fixes/for-linus (9e98c678c2d6 Linux 5.1-rc1) Merging regulator-fixes/for-linus (3e8a4628a4d4 Merge branch 'regulator-5.1' into regulator-linus) Merging spi-fixes/for-linus (35137ca07194 Merge branch 'spi-5.1' into spi-linus) Merging pci-current/for-linus (9e98c678c2d6 Linux 5.1-rc1) Merging driver-core.current/driver-core-linus (cd1b772d4881 driver core: remove BUS_ATTR()) Merging tty.current/tty-linus (93bcefd4c6ba serial: sh-sci: Fix setting SCSCR_TIE while transferring data) Merging usb.current/usb-linus (d92f2c59cc2c xhci: Don't let USB3 ports stuck in polling state prevent suspend) Merging usb-gadget-fixes/fixes (a53469a68eb8 usb: phy: am335x: fix race condition in _probe) Merging usb-serial-fixes/usb-linus (2908b076f519 USB: serial: mos7720: fix mos_parport refcount imbalance on error path) Merging usb-chipidea-fixes/ci-for-usb-stable (d6d768a0ec3c usb: chipidea: fix static checker warning for NULL pointer) Merging phy/fixes (9e98c678c2d6 Linux 5.1-rc1) Merging staging.current/staging-linus (6a8ca24590a2 staging: rtlwifi:
[PATCH v2 -next] ASoC: simple-card-utils: remove set but not used variable 'dai_name'
Fixes gcc '-Wunused-but-set-variable' warning:
sound/soc/generic/simple-card-utils.c: In function 'asoc_simple_parse_clk':
sound/soc/generic/simple-card-utils.c:164:18: warning:
parameter 'dai_name' set but not used [-Wunused-but-set-parameter]
It's not used since commit 0580dde59438 ("ASoC: simple-card-utils: add
asoc_simple_debug_info()"), so can be removed.
Signed-off-by: YueHaibing
Acked-by: Kuninori Morimoto
---
v2: fix patch title
---
sound/soc/generic/simple-card-utils.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/sound/soc/generic/simple-card-utils.c
b/sound/soc/generic/simple-card-utils.c
index 4ed68348f939..db1458a19985 100644
--- a/sound/soc/generic/simple-card-utils.c
+++ b/sound/soc/generic/simple-card-utils.c
@@ -173,10 +173,8 @@ int asoc_simple_parse_clk(struct device *dev,
* see
* soc-core.c :: snd_soc_init_multicodec()
*/
- if (dlc) {
+ if (dlc)
dai_of_node = dlc->of_node;
- dai_name= dlc->dai_name;
- }
/*
* Parse dai->sysclk come from "clocks = <>"
[PATCH 2/3] clocksource/drivers/timer-milbeaut: Add shutdown function
Add a shutdown operation to support shutdown timer.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/timer-milbeaut.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/timer-milbeaut.c
b/drivers/clocksource/timer-milbeaut.c
index 9fd5d08..f478061 100644
--- a/drivers/clocksource/timer-milbeaut.c
+++ b/drivers/clocksource/timer-milbeaut.c
@@ -85,6 +85,15 @@ static int mlb_set_state_oneshot(struct clock_event_device
*clk)
return 0;
}
+static int mlb_set_state_shutdown(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+ u32 val = MLB_TMR_TMCSR_CSL_DIV2;
+
+ writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
+ return 0;
+}
+
static int mlb_clkevt_next_event(unsigned long event,
struct clock_event_device *clk)
{
@@ -125,6 +134,7 @@ static int mlb_config_clock_event(struct timer_of *to)
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
.set_state_oneshot = mlb_set_state_oneshot,
.set_state_periodic = mlb_set_state_periodic,
+ .set_state_shutdown = mlb_set_state_shutdown,
.set_next_event = mlb_clkevt_next_event,
},
--
1.9.1
[PATCH 1/3] clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer
Fix mlb_set_oneshot_state() to enable one-shot timer. The function should stop and start a timer, but "start" statement was dropped. Kick the register to start one-shot timer. Signed-off-by: Sugaya Taichi --- drivers/clocksource/timer-milbeaut.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index f2019a8..9fd5d08 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -80,6 +80,8 @@ static int mlb_set_state_oneshot(struct clock_event_device *clk) u32 val = MLB_TMR_TMCSR_CSL_DIV2; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); return 0; } -- 1.9.1
Re: [PATCH -next] ASoC: simple-card-utils: remove set but not used variable ''
On 2019/3/25 10:31, Kuninori Morimoto wrote:
>
> Hi
>
>> Fixes gcc '-Wunused-but-set-variable' warning:
>>
>> sound/soc/generic/simple-card-utils.c: In function 'asoc_simple_parse_clk':
>> sound/soc/generic/simple-card-utils.c:164:18: warning:
>> parameter 'dai_name' set but not used [-Wunused-but-set-parameter]
>>
>> It's not used since commit 0580dde59438 ("ASoC: simple-card-utils: add
>> asoc_simple_debug_info()"), so can be removed.
>>
>> Signed-off-by: YueHaibing
>> ---
>
> I think dai_name parameter itself is no longer needed for this function,
> but, it will be removed if all driver switched to modern dai_link style.
> So, it is not a big deal.
>
> Acked-by: Kuninori Morimoto
Thanks, yes, this just a code cleanup.
>
> Best regards
> ---
> Kuninori Morimoto
>
> .
>
Re: Linux 5.1-rc2
On 3/24/19 2:26 PM, Linus Torvalds wrote: > Well, we're a week away from the merge window close, and here's rc2. > Things look fairly normal, but honestly, rc2 is usually too early to > tell. People haven't necessarily had time to notice problems yet. > Which is just another way of saying "please test harder". > > Nothing particularly stands out. Yes, we had some fixes for the new > io_ring code for issues that were discussed when merging it. Other > than that, worth noting is that the bulk of the patches are for > tooling, not the core kernel. In fact, about two thirds of the patch > is just for the tools/ subdirectory, most of it due to some late perf > tool updates. The people involved promise they're done. Hmph. I'm still looking for the patch that restores the various CONFIG_DEFAULT_ kconfig options to be merged. https://lore.kernel.org/linux-security-module/2bf23acd-22c4-a260-7648-845887a40...@i-love.sakura.ne.jp/ since commit 70b62c25665f636c9f6c700b26af7df296b0887e dropped them somehow. -- ~Randy
Re: pick_next_task() picking the wrong task [v4.9.163]
On Sat, 2019-03-23 at 11:15 +0100, Peter Zijlstra wrote:
> On Fri, Mar 22, 2019 at 05:57:59PM -0400, Radu Rendec wrote:
> > Hi Everyone,
> >
> > I believe I'm seeing a weird behavior of pick_next_task() where it
> > chooses a lower priority task over a higher priority one. The scheduling
> > class of the two tasks is also different ('fair' vs. 'rt'). The culprit
> > seems to be the optimization at the beginning of the function, where
> > fair_sched_class.pick_next_task() is called directly. I'm running
> > v4.9.163, but that piece of code is very similar in recent kernels.
> >
> > My use case is quite simple: I have a real-time thread that is woken up
> > by a GPIO hardware interrupt. The thread sleeps most of the time in
> > poll(), waiting for gpio_sysfs_irq() to wake it. The latency between the
> > interrupt and the thread being woken up/scheduled is very important for
> > the application. Note that I backported my own commit 03c0a9208bb1, so
> > the thread is always woken up synchronously from HW interrupt context.
> >
> > Most of the time things work as expected, but sometimes the scheduler
> > picks kworker and even the idle task before my real-time thread. I used
> > the trace infrastructure to figure out what happens and I'm including a
> > snippet below (I apologize for the wide lines).
>
> If only they were wide :/ I had to unwrap them myself..
Sorry about that! Wonders of using the gmail web interface. I'll pay
more attention in the future.
> > -0 [000] d.h2 161.202970: gpio_sysfs_irq
> > <-__handle_irq_event_percpu
> > -0 [000] d.h2 161.202981: kernfs_notify <-gpio_sysfs_irq
> > -0 [000] d.h4 161.202998: sched_waking: comm=irqWorker
> > pid=1141 prio=9 target_cpu=000
> > -0 [000] d.h5 161.203025: sched_wakeup: comm=irqWorker
> > pid=1141 prio=9 target_cpu=000
>
> weird how the next line doesn't have 'n/N' set:
>
> > -0 [000] d.h3 161.203047: workqueue_queue_work: work
> > struct=806506b8 function=kernfs_notify_workfn workqueue=8f5dae60 req_cpu=1
> > cpu=0
> > -0 [000] d.h3 161.203049: workqueue_activate_work: work
> > struct 806506b8
> > -0 [000] d.h4 161.203061: sched_waking: comm=kworker/0:1
> > pid=134 prio=120 target_cpu=000
> > -0 [000] d.h5 161.203083: sched_wakeup: comm=kworker/0:1
> > pid=134 prio=120 target_cpu=000
>
> There's that kworker wakeup.
>
> > -0 [000] d..2 161.203201: sched_switch: prev_comm=swapper
> > prev_pid=0 prev_prio=120 prev_state=R+ ==> next_comm=kworker/0:1
> > next_pid=134 next_prio=120
>
> And I agree that that is weird.
>
> > kworker/0:1-134 [000] 161.203222: workqueue_execute_start: work
> > struct 806506b8: function kernfs_notify_workfn
> > kworker/0:1-134 [000] ...1 161.203286: schedule <-worker_thread
> > kworker/0:1-134 [000] d..2 161.203329: sched_switch:
> > prev_comm=kworker/0:1 prev_pid=134 prev_prio=120 prev_state=S ==>
> > next_comm=swapper next_pid=0 next_prio=120
> > -0 [000] .n.1 161.230287: schedule
> > <-schedule_preempt_disabled
>
> Only here do I see 'n'.
Looking at other captures I can see 'n' starting at sched_wakeup for
irqWorker. Perhaps there was something wrong with this one or I copied
the wrong line.
> > -0 [000] d..2 161.230310: sched_switch: prev_comm=swapper
> > prev_pid=0 prev_prio=120 prev_state=R+ ==> next_comm=irqWorker
> > next_pid=1141 next_prio=9
> > irqWorker-1141 [000] d..3 161.230316: finish_task_switch <-schedule
> >
> > The system is Freescale MPC8378 (PowerPC, single processor).
> >
> > I instrumented pick_next_task() with trace_printk() and I am sure that
> > every time the wrong task is picked, flow goes through the optimization
>
> That's weird, because when you wake a RT task, the:
>
> rq->nr_running == rq->cfs.h_nr_running
>
> condition should not be true. Maybe try adding trace_printk() to all
> rq->nr_running manipulation to see what goes wobbly?
Sure, I will try that and come back with the results.
FWIW, I tried to comment out the entire optimization and force the
"slow" path that goes through every scheduling class. Surprisingly,
rt_sched_class.pick_next_task() returns NULL.
> > path and idle_sched_class.pick_next_task() is called directly. When the
> > right task is eventually picked, flow goes through the bottom block that
> > iterates over all scheduling classes. This probably makes sense: when
> > the scheduler runs in the context of the idle task, prev->sched_class is
> > no longer fair_sched_class, so the bottom block with the full iteration
> > is used. Note that in v4.9.163 the optimization path is taken only when
> > prev->sched_class is fair_sched_class, whereas in recent kernels it is
> > taken for both fair_sched_class and idle_sched_class.
> >
> > Any help or feedback would be much appreciated. In the meantime, I will
> > experiment with commenting out the optimization (at the expense of a
> > slower scheduler, of
BUG: KASAN: stack-out-of-bounds in unwind_next_frame (*Reproducible*)
Hi, I think I found a reproducible kernel bug in version 5.0.4. Source file: arch/x86/kernel/unwind_orc.c:505 The KASAN output is as following: [ 26.095365] BUG: KASAN: stack-out-of-bounds in unwind_next_frame+0x1403/0x19e0 [ 26.095365] Read of size 8 at addr 88805cc67d18 by task syz-executor.0/2296 [ 26.095365] [ 26.098418] CPU: 0 PID: 2296 Comm: syz-executor.0 Not tainted 5.0.4 #1 [ 26.098418] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 [ 26.098418] Call Trace: [ 26.098418] dump_stack+0xca/0x13e [ 26.098418] ? unwind_next_frame+0x1403/0x19e0 [ 26.098418] print_address_description+0x67/0x237 [ 26.098418] ? unwind_next_frame+0x1403/0x19e0 [ 26.098418] ? unwind_next_frame+0x1403/0x19e0 [ 26.098418] kasan_report.cold.3+0x1a/0x3b [ 26.098418] ? error_entry+0x40/0xf0 [ 26.098418] ? unwind_next_frame+0x1403/0x19e0 [ 26.098418] unwind_next_frame+0x1403/0x19e0 [ 26.098418] ? retint_kernel+0x10/0x10 [ 26.098418] ? deref_stack_reg+0xe0/0xe0 [ 26.098418] ? retint_kernel+0x10/0x10 [ 26.098418] perf_callchain_kernel+0x400/0x5b0 [ 26.098418] ? arch_perf_update_userpage+0x370/0x370 [ 26.110600] ? put_callchain_buffers+0x70/0x70 [ 26.110600] get_perf_callchain+0x370/0x800 [ 26.110600] ? put_callchain_buffers+0x70/0x70 [ 26.110600] ? perf_callchain+0x171/0x1c0 [ 26.110600] perf_callchain+0x163/0x1c0 [ 26.110600] perf_prepare_sample+0x88d/0x15a0 [ 26.115655] ? perf_callchain+0x1c0/0x1c0 [ 26.115655] ? perf_prepare_sample+0x15a0/0x15a0 [ 26.115655] ? perf_event_output_forward+0x1bf/0x2a0 [ 26.115655] perf_event_output_forward+0x108/0x2a0 [ 26.115655] ? perf_prepare_sample+0x15a0/0x15a0 [ 26.115655] ? __perf_event_overflow+0x1e7/0x360 [ 26.115655] ? perf_swevent_overflow+0x8d/0x140 [ 26.115655] __perf_event_overflow+0x13f/0x360 [ 26.115655] perf_swevent_overflow+0xa7/0x140 [ 26.115655] perf_swevent_event+0x14d/0x2e0 [ 26.115655] perf_tp_event+0x26a/0x880 [ 26.115655] ? perf_swevent_event+0x2e0/0x2e0 [ 26.115655] ? perf_pmu_nop_int+0x5/0x10 [ 26.115655] ? group_sched_in+0x177/0x3f0 [ 26.115655] ? flexible_sched_in+0xbc/0x5f0 [ 26.115655] ? __lock_acquire+0x5d6/0x4630 [ 26.115655] ? perf_trace_run_bpf_submit+0x112/0x1b0 [ 26.115655] ? perf_trace_run_bpf_submit+0x112/0x1b0 [ 26.115655] perf_trace_run_bpf_submit+0x112/0x1b0 [ 26.115655] ? memset+0x1f/0x40 [ 26.115655] perf_trace_lock_acquire+0x374/0x630 [ 26.115655] ? trace_hardirqs_on_thunk+0x1a/0x1c [ 26.115655] ? perf_trace_lock+0x520/0x520 [ 26.115655] ? retint_kernel+0x10/0x10 [ 26.115655] lock_acquire+0x1ed/0x2e0 [ 26.115655] ? posix_ktime_get_ts+0x11/0x20 [ 26.115655] ktime_get_ts64+0x187/0x2e0 [ 26.115655] ? posix_ktime_get_ts+0x11/0x20 [ 26.115655] ? __x64_sys_futex+0x35b/0x4e0 [ 26.115655] posix_ktime_get_ts+0x11/0x20 [ 26.115655] __x64_sys_clock_gettime+0x152/0x240 [ 26.115655] ? __x64_sys_timer_create+0x1b0/0x1b0 [ 26.115655] ? trace_hardirqs_on_thunk+0x1a/0x1c [ 26.115655] ? trace_hardirqs_off_caller+0x55/0x1c0 [ 26.115655] ? do_syscall_64+0x1a/0x4e0 [ 26.115655] do_syscall_64+0xbc/0x4e0 [ 26.115655] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 26.115655] RIP: 0033:0x45b37a [ 26.115655] Code: 31 f6 31 ff e8 27 fe ff ff b8 40 6b a4 00 48 83 c4 08 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 48 63 ff b8 e4 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 02 f3 c3 48 c7 c2 d4 ff ff ff f7 d8 64 89 02 [ 26.115655] RSP: 002b:7f2d0f4d3c78 EFLAGS: 0202 ORIG_RAX: 00e4 [ 26.115655] RAX: ffda RBX: 0072bf00 RCX: 0045b37a [ 26.115655] RDX: 004b587f RSI: 7f2d0f4d3c80 RDI: 0001 [ 26.115655] RBP: R08: R09: 7f2d0f4d4700 [ 26.115655] R10: 0003 R11: 0202 R12: 004b587f [ 26.115655] R13: 004c9050 R14: 7f2d0f4d49c0 R15: 7f2d0f4d4700 [ 26.115655] [ 26.115655] The buggy address belongs to the page: [ 26.115655] page:ea00017319c0 count:0 mapcount:0 mapping: index:0x0 [ 26.115655] flags: 0x100() [ 26.115655] raw: 0100 ea00017319c8 ea00017319c8 [ 26.115655] raw: [ 26.115655] page dumped because: kasan: bad access detected [ 26.115655] [ 26.115655] Memory state around the buggy address: [ 26.115655] 88805cc67c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 26.115655] 88805cc67c80: 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 04 [ 26.115655] >88805cc67d00: f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 00 00 00 00 00 [ 26.115655] ^ [ 26.115655] 88805cc67d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 26.115655] 88805cc67e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 And the c reproducer is: #define
Re: [PATCH 11/17] x86/kprobes: Make trampoline_handler global and visible
On Sat, 23 Mar 2019 07:35:18 -0700 Andi Kleen wrote: > On Sat, Mar 23, 2019 at 06:45:21PM +0900, Masami Hiramatsu wrote: > > On Thu, 21 Mar 2019 15:00:03 -0700 > > Andi Kleen wrote: > > > > > From: Andi Kleen > > > > > > This function is referenced from assembler, so in LTO > > > it needs to be global and visible to not be optimized away. > > > > > > > I got it. > > > > Acked-by: Masami Hiramatsu > > > > Andi, out of curiousity, that is not only for x86, but > > does all arch have to care it? > > Yes all architectures need it for LTO, but I currently > only test x86. There are some other people who made it work > on ARM / MIPS / PowerPC before. That's good to know! I worried that similar mistake I made on another arch :) Thank you, > > -Andi -- Masami Hiramatsu
LET ME KNOW
Dear Beloved One, I am Mrs Ragnhild Lilly Button, it's true we do not know one another but My spirit led me to write this email, so please don't be annoyed or embarrased. I write you with heavy heart and great joy of sorrow because I am shocked today when finally I was informed by my doctor that It will take only the will of God for me to survive due to my Complicated health issues (CANCER). And for mercy of God to fall on me , I decided to go through the net to share my problem, look for any possible solution and do whatever that will make me achieve a happy end if I eventually have to die. I have visited some orphanage homes around me and done some help to them but my instinct directed me to touch some lives that has no relationship with me. Please ,I need people that will encourage me and have a happy end while we also engage in discussion on how to dispose some of my material acquisitions to less privilege around you.I hope my mail get to you in good faith. Do good so that goods will in turn follow you. Kindly contact me on this below email, My regards, Mrs Ragnhild Lilly Button.
Re: [PATCH 1/3] staging: erofs: fix error handling when failed to read compresssed data
Hi,
On 2019/3/25 8:38, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a "Fixes:" tag,
> fixing commit: 3883a79abd02 staging: erofs: introduce VLE decompression
> support.
>
> The bot has tested the following trees: v5.0.3, v4.19.30.
>
> v5.0.3: Build OK!
> v4.19.30: Failed to apply! Possible dependencies:
> 390c642e1264 ("staging: erofs: fix integer overflow on 32-bit platform")
> 42d40b4ad840 ("staging: erofs: unzip_vle.c: Replace comparison to NULL.")
> 6e78901a9f23 ("staging: erofs: separate erofs_get_meta_page")
> 7dd68b147d60 ("staging: erofs: use explicit unsigned int type")
> 8be31270362b ("staging: erofs: introduce erofs_grab_bio")
> 9248fce714d5 ("staging: erofs: revisit the page submission flow")
> a07eeddf5b63 ("staging: erofs: clean up z_erofs_map_blocks_iter")
> ab47dd2b0819 ("staging: erofs: cleanup z_erofs_vle_work_{lookup,
> register}")
> b27661cf99c2 ("staging: erofs: fold in `__update_workgrp_llen'")
> c1448fa88025 ("staging: erofs: introduce MNGD_MAPPING helper")
>
>
> How should we proceed with this patch?
I will do the 4.19 backport patch after get a "Reviewed-by: " tag,
thanks for the reminder.
Thanks,
Gao Xiang
>
> --
> Thanks,
> Sasha
>
Re: KASAN: use-after-free Read in path_lookupat
On Sun, Mar 24, 2019 at 5:44 PM syzbot wrote: > > syzbot has bisected this bug to: > > commit a435393acafbf0ecff4deb3e3cb554b34f0d0664 That's wrong. It might change some timing or something to make the race hit, but it looks entirely unrelated to the bpf path_lookupat problem. Linus
Re: KASAN: use-after-free Read in path_lookupat
Hmm. Al, this one seems real and also seems pretty nasty from a vfs interface standpoint. On Wed, Nov 28, 2018 at 9:40 AM syzbot wrote: > > BUG: KASAN: use-after-free in lookup_last fs/namei.c:2269 [inline] > BUG: KASAN: use-after-free in path_lookupat.isra.43+0x9f8/0xc00 > fs/namei.c:2318 > ... > lookup_last fs/namei.c:2269 [inline] > path_lookupat.isra.43+0x9f8/0xc00 fs/namei.c:2318 Ok, path lookup using RCU. > Allocated by task 9424: > kstrdup+0x39/0x70 mm/util.c:49 > bpf_symlink+0x26/0x140 kernel/bpf/inode.c:356 It's the symlink data for the bpf filesystem. Fair enough. > Freed by task 9425: > kfree+0xcf/0x230 mm/slab.c:3817 > bpf_evict_inode+0x11f/0x150 kernel/bpf/inode.c:565 > evict+0x4b9/0x980 fs/inode.c:558 > iput_final fs/inode.c:1550 [inline] > iput+0x674/0xa90 fs/inode.c:1576 > do_unlinkat+0x733/0xa30 fs/namei.c:4069 .. and the path lookup is racing with the final unlink. We actually RCU-delay the inode freeing itself, but when we do the final iput(), the "evict()" function is called synchronously. Now, the simple fix would seem to just RCU-delay the kfree() of the symlink data in bpf_evict_inode(). Maybe that's the right thing to do. I'd call it trivial, except you'd need to have that rcu head to attach it to, making it slightly less trivial. I guess the kmalloc could just malloc that too. But it does strike me that this might be a generic issue. I wonder how many other filesystems do this? Alexei, Daniel - the "proper" fix right is probably one of four cases: (a) rcu-delay the freeing, and use simple_symlink_inode_operations(). No set_delayed_call() needed, because it stays around for the inode lifetime, but the RCU-delaying is still needed for lookup. or (b) put the symlink in a page, and use page_symlink_inode_operations for that inode, where we have a "struct delayed_call" and get a page ref or (c) put the symlink in the inode itself, and then use that simple_symlink_inode_operations (and now the RCU-delaying of the inode protects it). of (d) make a special getlink() that does "copy symlink, set_delayed_call(done, kfree_link, copy)" but I do wonder if we should perhaps just make simple_symlink_inode_operations do that (d) case for people. Al, comments? At the very least, if we don't make simple_symlink_inode_operations() do that, we should have a *big* comment that if it's not part of the inode data, it needs to be RCU-delayed. Or maybe we could add a final inode callback function for "rcu_free" that is called as the RCU-delayed freeing of the inode itself happens? And then people could hook into that for freeing the inode->i_link data. So many choices.. But the current situation seems unnecessarily complex for the filesystem, and isn't really documented. Our documentation currently says for get_link(): "If the body won't go away until the inode is gone, nothing else is needed", which is wrong (or at least very misleading, since the last "inode is gone" callback we have is that evict() function). Linus
Re: [PATCH 1/6] x86, mm: remove second argument of split_mem_range()
On Sun, Mar 24, 2019 at 03:38:24PM +0100, Thomas Gleixner wrote: >Wei, > >On Tue, 12 Feb 2019, Wei Yang wrote: > >Vs. the subject line. 'x86, mm:' is not the proper prefix. > ># git log path/to/file > >gives you usually a pretty good hint, i.e. in this case: 'x86/mm:' > >Also the sentence after the colon starts with an upper case letter. So the >full subject would be: > > x86/mm: Remove .. > Ah, thanks for your comment! Will change this in next version. >Other than that. This looks good. > >Thanks, > > tglx -- Wei Yang Help you, Help me
Re: [RFC PATCH] random: add get_random_max() function
P.S. The cited paper calls your algorithm the "OpenBSD algorithm"
and has a bunch of benchmarks comparing it to others in Fisher-Yates
shuffles of sizes 1e3..1e9.
Including all overhead (base PRNG, shuffle), it's 3x slower for
32-bit operations and 8x slower for 64-bit up to arrays of size
1e6, after which cache misses slow all algorithms, reducing the
ratio.
If you want a faster division-based agorithm, the "Java algorithm"
does 1+retries divides:
unsigned long java(unsigned long s)
{
unsigned long x, r;
do {
x = random_integer();
r = x % s;
} while (x - r > -s);
return r;
}
Re: KASAN: use-after-free Read in path_lookupat
syzbot has bisected this bug to:
commit a435393acafbf0ecff4deb3e3cb554b34f0d0664
Author: Sagi Grimberg
Date: Thu Jul 13 08:09:40 2017 +
mlx5: move affinity hints assignments to generic code
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=12df1ba320
start commit: 442b8cea Add linux-next specific files for 20181109
git tree: linux-next
final crash:https://syzkaller.appspot.com/x/report.txt?x=11df1ba320
console output: https://syzkaller.appspot.com/x/log.txt?x=16df1ba320
kernel config: https://syzkaller.appspot.com/x/.config?x=2f72bdb11df9fbe8
dashboard link: https://syzkaller.appspot.com/bug?extid=7a8ba368b47fdefca61e
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=132815f540
Reported-by: syzbot+7a8ba368b47fdefca...@syzkaller.appspotmail.com
Fixes: a435393acafb ("mlx5: move affinity hints assignments to generic
code")
For information about bisection process see: https://goo.gl/tpsmEJ#bisection
Re: [RFC PATCH] random: add get_random_max() function
On Sun, 24 Mar 2019 at 21:47:50 +0100, Jason A. Donenfeld wrote:
> I generally use a slightly simpler algorithm in various different projects:
>
> //[0, bound)
> static unsigned long random_bounded(unsigned long bound)
> {
>unsigned long ret;
>const unsigned long max_mod_bound = (1 + ~bound) % bound;
>
>if (bound < 2)
>return 0;
>do
>ret = random_integer();
>while (ret < max_mod_bound);
>return ret % bound;
> }
>
> Is the motivation behind using Lemire that you avoid the division (via
> the modulo) in favor of a multiplication?
Yes. If we define eps = max_mod_bound * ldexp(1.0, -BITS_PER_LONG) as
the probability of one retry, and retries = eps / (1 - eps) as the
expected number of retries, then both algorithms take 1+retries
random_integer()s.
The above agorithm takes 2 divisions, always. Divides are slow, and
usually not pipelined, so two in short succession gets a latency penalty.
Lemire's mutiplicative algorithm takes 1 multiplication on the fast
path (probability 1 - 2*eps on average), 1 additional division on the slow
path (probability 2*eps), and 1 multiplication per retry.
In the common case when bound is much less than ULONG_MAX, eps is
tiny and the fast path is taken almost all the time, and it's
a huge win.
Even in the absolute worst case of bound = ULONG_MAX/2 + 2 when
eps ~ 0.5 (2 multiplies, 0.5 divide; there's no 2*eps penalty in
this case), it's faster as long as 2 mutiplies cost less than 1.5
divides.
I you want simpler code, we could omit the fast path and stil get
a speedup. But a predictable branch for a divide seemed like
a worthwhile trade.
(FYI, this all came about as a side project of a kernel-janitor project
to replace "prandom_u32() % range" by "prandom_u32() * range >> 32".
I'm also annoyed that get_random_u32() and get_random_u64() have
separate buffers, even if EFFICIENT_UNALIGNED_ACCESS, but that's
a separate complaint.)
Re: [PATCH 2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip
Hi Yash,
Just a few brief comments here:
On Wed, 20 Mar 2019, Yash Shah wrote:
> This EDAC driver supports:
> - Initial configuration reporting on bootup via debug logs
> - ECC event monitoring and reporting through the EDAC framework
> - ECC event injection
>
It's probably worth mentioning here, as you did in the subject line, that
this is for the FU540-C000 platform.
> This driver is partially based on pnd2_edac.c and altera_edac.c
>
> Initially L2 Cache controller is added as a subcomponent to
> this EDAC driver.
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/Kconfig | 1 +
> drivers/edac/Kconfig | 13 ++
> drivers/edac/Makefile | 1 +
> drivers/edac/sifive_edac.c | 297
> +
> 4 files changed, 312 insertions(+)
> create mode 100644 drivers/edac/sifive_edac.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 515fc3c..fede4b6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -49,6 +49,7 @@ config RISCV
> select RISCV_TIMER
> select GENERIC_IRQ_MULTI_HANDLER
> select ARCH_HAS_PTE_SPECIAL
> + select EDAC_SUPPORT
>
> config MMU
> def_bool y
This part of the patch either needs to get an ack from Palmer, or should
be split into a final, separate patch that Palmer can merge separately.
That way it will avoid unexpected merge conflicts if anything that Palmer
merges changes this file.
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index e286b5b..112d9d1 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -440,6 +440,19 @@ config EDAC_ALTERA_SDMMC
> Support for error detection and correction on the
> Altera SDMMC FIFO Memory for Altera SoCs.
>
> +config EDAC_SIFIVE
> + tristate "Sifive ECC"
> + depends on RISCV
> + help
> + Support for error detection and correction on the SiFive SoCs.
> +
> +config EDAC_SIFIVE_L2
> + bool "SiFive L2 Cache ECC"
> + depends on EDAC_SIFIVE=y
> + help
> + Support for error detection and correction of the L2 cache
> + memory on SiFive SoCs.
> +
> config EDAC_SYNOPSYS
> tristate "Synopsys DDR Memory Controller"
> depends on ARCH_ZYNQ || ARCH_ZYNQMP
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 716096d..b16dce8 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -74,6 +74,7 @@ obj-$(CONFIG_EDAC_OCTEON_PCI) +=
> octeon_edac-pci.o
> obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o
>
> obj-$(CONFIG_EDAC_ALTERA)+= altera_edac.o
> +obj-$(CONFIG_EDAC_SIFIVE)+= sifive_edac.o
> obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
> obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
> obj-$(CONFIG_EDAC_TI)+= ti_edac.o
> diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> new file mode 100644
> index 000..e11ae6b5
> --- /dev/null
> +++ b/drivers/edac/sifive_edac.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive EDAC Driver
> + *
> + * Copyright (C) 2018-2019 SiFive, Inc.
> + *
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "edac_module.h"
> +
> +#define SIFIVE_EDAC_DIRFIX_LOW 0x100
> +#define SIFIVE_EDAC_DIRFIX_HIGH 0x104
> +#define SIFIVE_EDAC_DIRFIX_COUNT 0x108
> +
> +#define SIFIVE_EDAC_DATFIX_LOW 0x140
> +#define SIFIVE_EDAC_DATFIX_HIGH 0x144
> +#define SIFIVE_EDAC_DATFIX_COUNT 0x148
> +
> +#define SIFIVE_EDAC_DATFAIL_LOW 0x160
> +#define SIFIVE_EDAC_DATFAIL_HIGH 0x164
> +#define SIFIVE_EDAC_DATFAIL_COUNT 0x168
> +
> +#define SIFIVE_EDAC_ECCINJECTERR 0x40
> +#define SIFIVE_EDAC_CONFIG 0x00
> +
> +#define SIFIVE_EDAC_MAX_INTR 3
> +
> +/* EDAC Parent Probe */
> +
> +static const struct of_device_id sifive_edac_device_of_match[];
> +
> +static const struct of_device_id sifive_edac_of_match[] = {
> + { .compatible = "sifive,ecc-manager" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, sifive_edac_of_match);
> +
> +static int sifive_edac_probe(struct platform_device *pdev)
> +{
> + of_platform_populate(pdev->dev.of_node, sifive_edac_device_of_match,
> + NULL, >dev);
> + return 0;
> +}
> +
> +static struct platform_driver sifive_edac_driver = {
> + .probe = sifive_edac_probe,
> + .driver = {
> + .name = "ecc_manager",
As mentioned before we don't have an ECC manager IP block, so we probably
should figure out a different approach here, if possible.
> + .of_match_table = sifive_edac_of_match,
> + },
> +};
> +module_platform_driver(sifive_edac_driver);
> +
> +struct sifive_edac_device_prv {
> + void (*setup)(struct edac_device_ctl_info *dci);
> + irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
> + const struct file_operations *inject_fops;
> +};
> +
> +struct sifive_edac_device_dev {
Re: [PATCH 1/2] edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent
Hi Yash,
On Wed, 20 Mar 2019, Yash Shah wrote:
> DT documentation for EDAC driver added.
> DT documentation for subcomponent L2 cache controller also added.
>
> Signed-off-by: Yash Shah
> ---
> .../devicetree/bindings/edac/sifive-edac.txt | 40
> ++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac.txt
>
> diff --git a/Documentation/devicetree/bindings/edac/sifive-edac.txt
> b/Documentation/devicetree/bindings/edac/sifive-edac.txt
> new file mode 100644
> index 000..c0e3ac7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/sifive-edac.txt
> @@ -0,0 +1,40 @@
> +SiFive ECC Manager
> +This driver uses the EDAC framework to implement the SiFive ECC Manager.
> +
> +Required Properties:
> +- compatible : Should be "sifive,ecc-manager"
As you've probably seen, this is being discussed in a separate thread with
Borislav, but it would be ideal if we could avoid adding DT nodes for
non-existent hardware. Let's see what the outcome of that other thread
will be.
> +L2 Cache ECC
> +Required Properties:
> +- compatible: Should be "sifive,-ccache" and "sifive,ccache".
We should only use chip-specific compatible strings for this IP block,
like "sifive,fu540-c000-ccache". Let's not use "sifive,ccache*" here for
now.
> + Supported compatible strings are:
> + "sifive,fu540-c000-ccache" for the SiFive cache controller v0 as integrated
> + onto the SiFive FU540 chip, and "sifive,ccache0" for the SiFive
> + cache controller v0 IP block with no chip integration tweaks.
Same comment here.
> + Please refer to sifive-blocks-ip-versioning.txt for details
> +- interrupt-parent: Must be core interrupt controller
> +- interrupts: Must contain 3 entries (DirError, DataError and DataFail
> signals
> +- reg: Physical base address and size of L2 cache controller registers map
> + A second range can indicate L2 Loosely Integrated Memory
> +
> +Example:
> +
> +eccmgr: eccmgr {
> + compatible = "sifive,ecc-manager";
See above
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + l2-ecc@201 {
> + compatible = "sifive,fu540-c000-ccache", "sifive,ccache0";
And as above
> + interrupt-parent = <>;
> + interrupts = <1 2 3>;
> + reg = <0x0 0x201 0x0 0x1000 0x0 0x800 0x0 0x200>;
> + };
> +};
- Paul
Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
On Tue, 12 Mar 2019, Borislav Petkov wrote: > Please no EDAC drivers for a single functional unit with RAS > capabilities. Rather, a sifive_edac or riscv_edac driver which covers > the whole platform or even architecture and contains support for all the > RAS functionality there. See altera_edac, for example. Looking at the Synopsys, Highbank, PowerPC 4xx, and TI EDAC drivers, all of those are clearly for IP block error management, rather than platform error management. Has the upstream guidance changed since those drivers were merged? The core issue for us is that we don't have a generalized "ECC management" IP block. And I would just as soon not fake one in the DT data, since the general DT guidance is that the data in DT is meant to describe the actual hardware. Would it make more sense to put this driver outside of drivers/edac? - Paul
Re: [tip:ras/core 2/2] drivers/ras/debugfs.c:9:5: error: redefinition of 'ras_userspace_consumers'
On Mon, 25 Mar 2019 06:41:49 +0800, kbuild test robot said: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git ras/core > head: 56baf8bd6c92819b1d89210fbfac2c6327a1271b > commit: 56baf8bd6c92819b1d89210fbfac2c6327a1271b [2/2] ras/debugfs: Fix > -Wmissing-prototypes warnings > config: x86_64-randconfig-x003-201912 (attached as .config) > compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 OK. Now to figure out why gcc-7.3 on Debian complains and gcc-9.0.1 on Fedora is perfectly happy with the patch, or if there's something I didn't expect in that randconfig, or if there's some other skew between what the test robot tree has in it, and next-20190318 (the last linux-next I built, which didn't complain...)
Re: [rcu:dev.2019.03.20b 59/83] kernel/rcu/tree_plugin.h:612:8: error: 'rcu_softirq_enabled' undeclared; did you mean 'trace_softirqs_enabled'?
On Sat, Mar 23, 2019 at 10:16:23AM +0800, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
> dev.2019.03.20b
> head: 6d4434b4b4df791620743178e1419de882b44c7b
> commit: d0f41d341df0520e900cac03de05bbbd11abdcd9 [59/83] rcu: Enable
> elimination of Tree-RCU softirq processing
> config: i386-randconfig-x002-201911 (attached as .config)
> compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
> reproduce:
> git checkout d0f41d341df0520e900cac03de05bbbd11abdcd9
> # save the attached .config to linux build tree
> make ARCH=i386
>
> Note: the rcu/dev.2019.03.20b HEAD 6d4434b4b4df791620743178e1419de882b44c7b
> builds fine.
> It only hurts bisectibility.
>
> All errors (new ones prefixed by >>):
>
>In file included from kernel/rcu/tree.c:3489:0:
>kernel/rcu/tree_plugin.h: In function 'rcu_read_unlock_special':
> >> kernel/rcu/tree_plugin.h:612:8: error: 'rcu_softirq_enabled' undeclared
> >> (first use in this function); did you mean 'trace_softirqs_enabled'?
>if (rcu_softirq_enabled)
>^~~
>trace_softirqs_enabled
>kernel/rcu/tree_plugin.h:612:8: note: each undeclared identifier is
> reported only once for each function it appears in
This commit has been superseced by 132e805a28dc, which I believe has fixed
this. (Famous last words!)
Thanx, Paul
> vim +612 kernel/rcu/tree_plugin.h
>
>588
>589/*
>590 * Handle special cases during rcu_read_unlock(), such as
> needing to
>591 * notify RCU core processing or task having blocked during the
> RCU
>592 * read-side critical section.
>593 */
>594static void rcu_read_unlock_special(struct task_struct *t)
>595{
>596unsigned long flags;
>597bool preempt_bh_were_disabled =
>598!!(preempt_count() & (PREEMPT_MASK |
> SOFTIRQ_MASK));
>599bool irqs_were_disabled;
>600
>601/* NMI handlers cannot block and cannot safely
> manipulate state. */
>602if (in_nmi())
>603return;
>604
>605local_irq_save(flags);
>606irqs_were_disabled = irqs_disabled_flags(flags);
>607if (preempt_bh_were_disabled || irqs_were_disabled) {
>608
> WRITE_ONCE(t->rcu_read_unlock_special.b.exp_hint, false);
>609/* Need to defer quiescent state until
> everything is enabled. */
>610if (irqs_were_disabled) {
>611/* Enabling irqs does not reschedule,
> so... */
> > 612if (rcu_softirq_enabled)
>613
> raise_softirq_irqoff(RCU_SOFTIRQ);
>614else
>615invoke_rcu_core();
>616} else {
>617/* Enabling BH or preempt does
> reschedule, so... */
>618set_tsk_need_resched(current);
>619set_preempt_need_resched();
>620}
>621local_irq_restore(flags);
>622return;
>623}
>624WRITE_ONCE(t->rcu_read_unlock_special.b.exp_hint,
> false);
>625rcu_preempt_deferred_qs_irqrestore(t, flags);
>626}
>627
>
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
Re: [RFC 2/2] rcutree: Add checks for dynticks counters in rcu_is_cpu_rrupt_from_idle
On Fri, Mar 22, 2019 at 11:02:51PM -0400, Joel Fernandes wrote:
> On Fri, Mar 22, 2019 at 09:29:39PM -0400, Joel Fernandes (Google) wrote:
> > In the future we would like to combine the dynticks and dynticks_nesting
> > counters thus leading to simplifying the code. At the moment we cannot
> > do that due to concerns about usermode upcalls appearing to RCU as half
> > of an interrupt. Byungchul tried to do it in [1] but the
> > "half-interrupt" concern was raised. It is half because, what RCU
> > expects is rcu_irq_enter() and rcu_irq_exit() pairs when the usermode
> > exception happens. However, only rcu_irq_enter() is observed. This
> > concern may not be valid anymore, but at least it used to be the case.
> >
> > Out of abundance of caution, Paul added warnings [2] in the RCU code
> > which if not fired by 2021 may allow us to assume that such
> > half-interrupt scenario cannot happen any more, which can lead to
> > simplification of this code.
> >
> > Summary of the changes are the following:
> >
> > (1) In preparation for this combination of counters in the future, we
> > first need to first be sure that rcu_rrupt_from_idle cannot be called
> > from anywhere but a hard-interrupt because previously, the comments
> > suggested otherwise so let us be sure. We discussed this here [3]. We
> > use the services of lockdep to accomplish this.
> >
> > (2) Further rcu_rrupt_from_idle() is not explicit about how it is using
> > the counters which can lead to weird future bugs. This patch therefore
> > makes it more explicit about the specific counter values being tested
> >
> > (3) Lastly, we check for counter underflows just to be sure these are
> > not happening, because the previous code in rcu_rrupt_from_idle() was
> > allowing the case where the counters can underflow, and the function
> > would still return true. Now we are checking for specific values so let
> > us be confident by additional checking, that such underflows don't
> > happen. Any case, if they do, we should fix them and the screaming
> > warning is appropriate. All these checks checks are NOOPs if PROVE_RCU
> > and PROVE_LOCKING are disabled.
> >
> > [1] https://lore.kernel.org/patchwork/patch/952349/
> > [2] Commit e11ec65cc8d6 ("rcu: Add warning to detect half-interrupts")
> > [3] https://lore.kernel.org/lkml/20190312150514.gb249...@google.com/
> >
> > Cc: byungchul.p...@lge.com
> > Cc: kernel-t...@android.com
> > Cc: r...@vger.kernel.org
> > Signed-off-by: Joel Fernandes (Google)
> > ---
> > kernel/rcu/tree.c | 21 +
> > 1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> > index 9180158756d2..d94c8ed29f6b 100644
> > --- a/kernel/rcu/tree.c
> > +++ b/kernel/rcu/tree.c
> > @@ -381,16 +381,29 @@ static void __maybe_unused
> > rcu_momentary_dyntick_idle(void)
> > }
> >
> > /**
> > - * rcu_is_cpu_rrupt_from_idle - see if idle or immediately interrupted
> > from idle
> > + * rcu_is_cpu_rrupt_from_idle - see if interrupted from idle
> > *
> > - * If the current CPU is idle or running at a first-level (not nested)
> > + * If the current CPU is idle and running at a first-level (not nested)
> > * interrupt from idle, return true. The caller must have at least
> > * disabled preemption.
> > */
> > static int rcu_is_cpu_rrupt_from_idle(void)
> > {
> > - return __this_cpu_read(rcu_data.dynticks_nesting) <= 0 &&
> > - __this_cpu_read(rcu_data.dynticks_nmi_nesting) <= 1;
> > + /* Called only from within the scheduling-clock interrupt */
> > + lockdep_assert_in_irq();
> > +
> > + /* Check for counter underflows */
> > + RCU_LOCKDEP_WARN(
> > + (__this_cpu_read(rcu_data.dynticks_nesting) < 0) &&
> > + (__this_cpu_read(rcu_data.dynticks_nmi_nesting) < 0),
>
>
> This condition for the warning is supposed to be || instead of &&. Sorry.
>
> Or, I will just use 2 RCU_LOCKDEP_WARN(s) here, that's better.
Also, the dynticks_nmi_nesting being zero is a bug given that we know
we are in an interrupt handler, right? Or am I off by one again?
Thanx, Paul
Re: [PATCH v3] rcu: Allow to eliminate softirq processing from rcutree
On Sat, Mar 23, 2019 at 09:10:02AM -0700, Paul E. McKenney wrote:
> On Fri, Mar 22, 2019 at 05:25:19PM -0700, Paul E. McKenney wrote:
> > On Fri, Mar 22, 2019 at 07:48:19PM -0400, Joel Fernandes wrote:
> > > On Wed, Mar 20, 2019 at 10:13:33PM +0100, Sebastian Andrzej Siewior wrote:
> > > > Running RCU out of softirq is a problem for some workloads that would
> > > > like to manage RCU core processing independently of other softirq
> > > > work, for example, setting kthread priority. This commit therefore
> > > > introduces the `rcunosoftirq' option which moves the RCU core work
> > > > from softirq to a per-CPU/per-flavor SCHED_OTHER kthread named rcuc.
> > > > The SCHED_OTHER approach avoids the scalability problems that appeared
> > > > with the earlier attempt to move RCU core processing to from softirq
> > > > to kthreads. That said, kernels built with RCU_BOOST=y will run the
> > > > rcuc kthreads at the RCU-boosting priority.
> > > [snip]
> > > > diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> > > > index 0f31b79eb6761..05a1e42fdaf10 100644
> > > > --- a/kernel/rcu/tree.c
> > > > +++ b/kernel/rcu/tree.c
> > > > @@ -51,6 +51,12 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include "../time/tick-internal.h"
> > > >
> > > > #include "tree.h"
> > > > #include "rcu.h"
> > > > @@ -92,6 +98,9 @@ struct rcu_state rcu_state = {
> > > > /* Dump rcu_node combining tree at boot to verify correct setup. */
> > > > static bool dump_tree;
> > > > module_param(dump_tree, bool, 0444);
> > > > +/* Move RCU_SOFTIRQ to rcuc kthreads. */
> > > > +static bool use_softirq = 1;
> > > > +module_param(use_softirq, bool, 0444);
> > > > /* Control rcu_node-tree auto-balancing at boot time. */
> > > > static bool rcu_fanout_exact;
> > > > module_param(rcu_fanout_exact, bool, 0444);
> > > > @@ -2253,7 +2262,7 @@ void rcu_force_quiescent_state(void)
> > > > EXPORT_SYMBOL_GPL(rcu_force_quiescent_state);
> > > >
> > > > /* Perform RCU core processing work for the current CPU. */
> > > > -static __latent_entropy void rcu_core(struct softirq_action *unused)
> > > > +static __latent_entropy void rcu_core(void)
> > > > {
> > > > unsigned long flags;
> > > > struct rcu_data *rdp = raw_cpu_ptr(_data);
> > > > @@ -2295,6 +2304,34 @@ static __latent_entropy void rcu_core(struct
> > > > softirq_action *unused)
> > > > trace_rcu_utilization(TPS("End RCU core"));
> > > > }
> > > >
> > > > +static void rcu_core_si(struct softirq_action *h)
> > > > +{
> > > > + rcu_core();
> > > > +}
> > > > +
> > > > +static void rcu_wake_cond(struct task_struct *t, int status)
> > > > +{
> > > > + /*
> > > > +* If the thread is yielding, only wake it when this
> > > > +* is invoked from idle
> > > > +*/
> > > > + if (t && (status != RCU_KTHREAD_YIELDING ||
> > > > is_idle_task(current)))
> > > > + wake_up_process(t);
> > > > +}
> > > > +
> > > > +static void invoke_rcu_core_kthread(void)
> > > > +{
> > > > + struct task_struct *t;
> > > > + unsigned long flags;
> > > > +
> > > > + local_irq_save(flags);
> > > > + __this_cpu_write(rcu_data.rcu_cpu_has_work, 1);
> > > > + t = __this_cpu_read(rcu_data.rcu_cpu_kthread_task);
> > > > + if (t != NULL && t != current)
> > > > + rcu_wake_cond(t,
> > > > __this_cpu_read(rcu_data.rcu_cpu_kthread_status));
> > > > + local_irq_restore(flags);
> > > > +}
> > > > +
> > > > /*
> > > > * Schedule RCU callback invocation. If the running implementation of
> > > > RCU
> > > > * does not support RCU priority boosting, just do a direct call,
> > > > otherwise
> > > > @@ -2306,19 +2343,95 @@ static void invoke_rcu_callbacks(struct
> > > > rcu_data *rdp)
> > > > {
> > > > if (unlikely(!READ_ONCE(rcu_scheduler_fully_active)))
> > > > return;
> > > > - if (likely(!rcu_state.boost)) {
> > > > - rcu_do_batch(rdp);
> > > > - return;
> > > > - }
> > > > - invoke_rcu_callbacks_kthread();
> > > > + if (rcu_state.boost || !use_softirq)
> > > > + invoke_rcu_core_kthread();
> > > > + rcu_do_batch(rdp);
> > >
> > > Shouldn't there be an else before the rcu_do_batch? If we are waking up
> > > the
> > > rcuc thread, then that will do the rcu_do_batch when it runs right?
> > >
> > > Something like:
> > > if (rcu_state.boost || !use_softirq)
> > > invoke_rcu_core_kthread();
> > > else
> > > rcu_do_batch(rdp);
> > >
> > > Previous code similarly had a return; also.
> >
> > I believe that you are correct, so I will give it a shot. Good eyes!
>
> Yet rcutorture disagrees. Actually, if we are using rcuc kthreads, this
> is only ever invoked from within tha thread, so the only check we need is
> for the scheduler being operational. I am
RESPONSE
Compensation Funds of 800,000 Euro Valid for claim contact Mr . Wu Guofa for claim
Re: [PATCH v3] rcu: Allow to eliminate softirq processing from rcutree
On Fri, Mar 22, 2019 at 05:25:19PM -0700, Paul E. McKenney wrote:
> On Fri, Mar 22, 2019 at 07:48:19PM -0400, Joel Fernandes wrote:
> > On Wed, Mar 20, 2019 at 10:13:33PM +0100, Sebastian Andrzej Siewior wrote:
> > > Running RCU out of softirq is a problem for some workloads that would
> > > like to manage RCU core processing independently of other softirq
> > > work, for example, setting kthread priority. This commit therefore
> > > introduces the `rcunosoftirq' option which moves the RCU core work
> > > from softirq to a per-CPU/per-flavor SCHED_OTHER kthread named rcuc.
> > > The SCHED_OTHER approach avoids the scalability problems that appeared
> > > with the earlier attempt to move RCU core processing to from softirq
> > > to kthreads. That said, kernels built with RCU_BOOST=y will run the
> > > rcuc kthreads at the RCU-boosting priority.
> > [snip]
> > > diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> > > index 0f31b79eb6761..05a1e42fdaf10 100644
> > > --- a/kernel/rcu/tree.c
> > > +++ b/kernel/rcu/tree.c
> > > @@ -51,6 +51,12 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include "../time/tick-internal.h"
> > >
> > > #include "tree.h"
> > > #include "rcu.h"
> > > @@ -92,6 +98,9 @@ struct rcu_state rcu_state = {
> > > /* Dump rcu_node combining tree at boot to verify correct setup. */
> > > static bool dump_tree;
> > > module_param(dump_tree, bool, 0444);
> > > +/* Move RCU_SOFTIRQ to rcuc kthreads. */
> > > +static bool use_softirq = 1;
> > > +module_param(use_softirq, bool, 0444);
> > > /* Control rcu_node-tree auto-balancing at boot time. */
> > > static bool rcu_fanout_exact;
> > > module_param(rcu_fanout_exact, bool, 0444);
> > > @@ -2253,7 +2262,7 @@ void rcu_force_quiescent_state(void)
> > > EXPORT_SYMBOL_GPL(rcu_force_quiescent_state);
> > >
> > > /* Perform RCU core processing work for the current CPU. */
> > > -static __latent_entropy void rcu_core(struct softirq_action *unused)
> > > +static __latent_entropy void rcu_core(void)
> > > {
> > > unsigned long flags;
> > > struct rcu_data *rdp = raw_cpu_ptr(_data);
> > > @@ -2295,6 +2304,34 @@ static __latent_entropy void rcu_core(struct
> > > softirq_action *unused)
> > > trace_rcu_utilization(TPS("End RCU core"));
> > > }
> > >
> > > +static void rcu_core_si(struct softirq_action *h)
> > > +{
> > > + rcu_core();
> > > +}
> > > +
> > > +static void rcu_wake_cond(struct task_struct *t, int status)
> > > +{
> > > + /*
> > > + * If the thread is yielding, only wake it when this
> > > + * is invoked from idle
> > > + */
> > > + if (t && (status != RCU_KTHREAD_YIELDING || is_idle_task(current)))
> > > + wake_up_process(t);
> > > +}
> > > +
> > > +static void invoke_rcu_core_kthread(void)
> > > +{
> > > + struct task_struct *t;
> > > + unsigned long flags;
> > > +
> > > + local_irq_save(flags);
> > > + __this_cpu_write(rcu_data.rcu_cpu_has_work, 1);
> > > + t = __this_cpu_read(rcu_data.rcu_cpu_kthread_task);
> > > + if (t != NULL && t != current)
> > > + rcu_wake_cond(t,
> > > __this_cpu_read(rcu_data.rcu_cpu_kthread_status));
> > > + local_irq_restore(flags);
> > > +}
> > > +
> > > /*
> > > * Schedule RCU callback invocation. If the running implementation of
> > > RCU
> > > * does not support RCU priority boosting, just do a direct call,
> > > otherwise
> > > @@ -2306,19 +2343,95 @@ static void invoke_rcu_callbacks(struct rcu_data
> > > *rdp)
> > > {
> > > if (unlikely(!READ_ONCE(rcu_scheduler_fully_active)))
> > > return;
> > > - if (likely(!rcu_state.boost)) {
> > > - rcu_do_batch(rdp);
> > > - return;
> > > - }
> > > - invoke_rcu_callbacks_kthread();
> > > + if (rcu_state.boost || !use_softirq)
> > > + invoke_rcu_core_kthread();
> > > + rcu_do_batch(rdp);
> >
> > Shouldn't there be an else before the rcu_do_batch? If we are waking up the
> > rcuc thread, then that will do the rcu_do_batch when it runs right?
> >
> > Something like:
> > if (rcu_state.boost || !use_softirq)
> > invoke_rcu_core_kthread();
> > else
> > rcu_do_batch(rdp);
> >
> > Previous code similarly had a return; also.
>
> I believe that you are correct, so I will give it a shot. Good eyes!
Yet rcutorture disagrees. Actually, if we are using rcuc kthreads, this
is only ever invoked from within tha thread, so the only check we need is
for the scheduler being operational. I am therefore trying this one out.
Thoughts?
Thanx, Paul
diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
index 76d6c0902f66..8d6ebc0944ec 100644
--- a/kernel/rcu/tree.c
+++ b/kernel/rcu/tree.c
@@ -2333,18 +2333,16 @@ static void invoke_rcu_core_kthread(void)
}
/*
- * Schedule RCU callback invocation. If the running implementation of RCU
-
[PATCH] sound: codecs: fix a missing check for regmap_update_bits
regmap_update_bits could fail. The fix checks its status and if
it fails, returns its error code upstream.
Signed-off-by: Kangjie Lu
---
sound/soc/codecs/cs35l34.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/codecs/cs35l34.c b/sound/soc/codecs/cs35l34.c
index 5063c05afa27..a456b1ac9019 100644
--- a/sound/soc/codecs/cs35l34.c
+++ b/sound/soc/codecs/cs35l34.c
@@ -262,6 +262,8 @@ static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
}
ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
CS35L34_PDN_ALL, CS35L34_PDN_ALL);
+ if (ret < 0)
+ return ret;
break;
default:
pr_err("Invalid event = 0x%x\n", event);
--
2.17.1
Re: [PATCH 3.16 00/16] 3.16.64-rc1 review
On Fri, 2019-03-22 at 21:43 -0700, Guenter Roeck wrote: > On 3/22/19 6:44 AM, Guenter Roeck wrote: > > On 3/21/19 10:20 PM, Ben Hutchings wrote: > > > This is the start of the stable review cycle for the 3.16.64 release. > > > There are 16 patches in this series, which will be posted as responses > > > to this one. If anyone has any issues with these being applied, please > > > let me know. > > > > > > Responses should be made by Mon Mar 25 18:00:00 UTC 2019. > > > Anything received after that time might be too late. > > > > > > > Build results: > > total: 137 pass: 136 fail: 1 > > Failed builds: > > i386:tools/perf > > Qemu test results: > > total: 222 pass: 221 fail: 1 > > Failed tests: > > arm:midway:multi_v7_defconfig:mem2G:ecx-2000:initrd > > > > The failed qemu test simply hangs. The test passes with v3.16.63. > > I started a bisect. > > > > False positive. > > Sorry for the noise. Thanks a lot for testing. Ben. -- Ben Hutchings Larkinson's Law: All laws are basically false. signature.asc Description: This is a digitally signed message part
Re: [PATCH] gpio: fix a potential NULL pointer dereference
On Mon, 25 Mar 2019, at 09:40, Kangjie Lu wrote: > In case devm_kzalloc, the patch returns ENOMEM to avoid potential > NULL pointer dereference. > > Signed-off-by: Kangjie Lu Reviewed-by: Andrew Jeffery > --- > drivers/gpio/gpio-aspeed.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c > index 854bce4fb9e7..217507002dbc 100644 > --- a/drivers/gpio/gpio-aspeed.c > +++ b/drivers/gpio/gpio-aspeed.c > @@ -1224,6 +1224,8 @@ static int __init aspeed_gpio_probe(struct > platform_device *pdev) > > gpio->offset_timer = > devm_kzalloc(>dev, gpio->chip.ngpio, GFP_KERNEL); > + if (!gpio->offset_timer) > + return -ENOMEM; > > return aspeed_gpio_setup_irqs(gpio, pdev); > } > -- > 2.17.1 > >
[PATCH] sound: codecs: fix a potential NULL pointer dereference
In case devm_kzalloc fails, the patch returns -ENOMEM to avoid potential NULL pointer dereference. Signed-off-by: Kangjie Lu --- sound/soc/codecs/rt5663.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c index da6647015708..909ab99a1995 100644 --- a/sound/soc/codecs/rt5663.c +++ b/sound/soc/codecs/rt5663.c @@ -3480,6 +3480,8 @@ static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) table_size = sizeof(struct impedance_mapping_table) * rt5663->pdata.impedance_sensing_num; rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL); + if (!rt5663->imp_table) + return -ENOMEM; device_property_read_u32_array(dev, "realtek,impedance_sensing_table", (u32 *)rt5663->imp_table, table_size); -- 2.17.1
[PATCH] gpio: fix a potential NULL pointer dereference
In case devm_kzalloc, the patch returns ENOMEM to avoid potential NULL pointer dereference. Signed-off-by: Kangjie Lu --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 854bce4fb9e7..217507002dbc 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -1224,6 +1224,8 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) gpio->offset_timer = devm_kzalloc(>dev, gpio->chip.ngpio, GFP_KERNEL); + if (!gpio->offset_timer) + return -ENOMEM; return aspeed_gpio_setup_irqs(gpio, pdev); } -- 2.17.1
[PATCH] platform: uv: fix missing checks for kcalloc
In case kcalloc fails, the patch return an error to avoid
potential NULL pointer dereference.
Signed-off-by: Kangjie Lu
---
arch/x86/platform/uv/tlb_uv.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 2c53b0f19329..1ac777f14846 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -2140,7 +2140,13 @@ static int __init init_per_cpu(int nuvhubs, int
base_part_pnode)
timeout_us = calculate_destination_timeout();
uvhub_descs = kcalloc(nuvhubs, sizeof(struct uvhub_desc), GFP_KERNEL);
+ if (!uvhub_descs)
+ return 1;
uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
+ if (!uvhub_mask) {
+ kfree(uvhub_descs);
+ return 1;
+ }
if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
goto fail;
--
2.17.1
[PATCH] thunderbolt: property: fix a buffer overflow and a missing check
First, no memory is allocated for "property->value.text"; the
following strcpy will lead to a buffer overflow.
Second, no check is enforced for the return value of kzalloc,
which may lead to NULL-pointer dereference.
The patch fixes the two issues.
Signed-off-by: Kangjie Lu
---
drivers/thunderbolt/property.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/thunderbolt/property.c b/drivers/thunderbolt/property.c
index 841314deb446..d5b0cdb8f0b1 100644
--- a/drivers/thunderbolt/property.c
+++ b/drivers/thunderbolt/property.c
@@ -587,7 +587,12 @@ int tb_property_add_text(struct tb_property_dir *parent,
const char *key,
return -ENOMEM;
property->length = size / 4;
- property->value.data = kzalloc(size, GFP_KERNEL);
+ property->value.text = kzalloc(size, GFP_KERNEL);
+ if (!property->value.text) {
+ kfree(property);
+ return -ENOMEM;
+ }
+
strcpy(property->value.text, text);
list_add_tail(>list, >properties);
--
2.17.1
[PATCH] vc04_services: vchiq_arm: fix a NULL pointer dereference
When kzalloc fails, "platform_state->inited = 1" is a NULL pointer dereference. The fix returns VCHIQ_ERROR in case it failed to avoid NULL pointer dereference. Signed-off-by: Kangjie Lu --- .../staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c index dd4898861b83..0f12fe617575 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c @@ -209,6 +209,8 @@ vchiq_platform_init_state(struct vchiq_state *state) struct vchiq_2835_state *platform_state; state->platform_state = kzalloc(sizeof(*platform_state), GFP_KERNEL); + if (!state->platform_state) + return VCHIQ_ERROR; platform_state = (struct vchiq_2835_state *)state->platform_state; platform_state->inited = 1; -- 2.17.1
[tip:ras/core 2/2] drivers/ras/debugfs.c:9:5: error: redefinition of 'ras_userspace_consumers'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git ras/core
head: 56baf8bd6c92819b1d89210fbfac2c6327a1271b
commit: 56baf8bd6c92819b1d89210fbfac2c6327a1271b [2/2] ras/debugfs: Fix
-Wmissing-prototypes warnings
config: x86_64-randconfig-x003-201912 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
git checkout 56baf8bd6c92819b1d89210fbfac2c6327a1271b
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
>> drivers/ras/debugfs.c:9:5: error: redefinition of 'ras_userspace_consumers'
int ras_userspace_consumers(void)
^~~
In file included from drivers/ras/debugfs.c:2:0:
include/linux/ras.h:14:19: note: previous definition of
'ras_userspace_consumers' was here
static inline int ras_userspace_consumers(void) { return 0; }
^~~
>> drivers/ras/debugfs.c:39:12: error: redefinition of 'ras_add_daemon_trace'
int __init ras_add_daemon_trace(void)
^~~~
In file included from drivers/ras/debugfs.c:2:0:
include/linux/ras.h:16:19: note: previous definition of
'ras_add_daemon_trace' was here
static inline int ras_add_daemon_trace(void) { return 0; }
^~~~
>> drivers/ras/debugfs.c:55:13: error: redefinition of 'ras_debugfs_init'
void __init ras_debugfs_init(void)
^~~~
In file included from drivers/ras/debugfs.c:2:0:
include/linux/ras.h:15:20: note: previous definition of 'ras_debugfs_init'
was here
static inline void ras_debugfs_init(void) { }
^~~~
vim +/ras_userspace_consumers +9 drivers/ras/debugfs.c
d963cd95 Chen, Gong 2014-06-11 8
d963cd95 Chen, Gong 2014-06-11 @9 int ras_userspace_consumers(void)
d963cd95 Chen, Gong 2014-06-11 10 {
d963cd95 Chen, Gong 2014-06-11 11 return atomic_read(_count);
d963cd95 Chen, Gong 2014-06-11 12 }
d963cd95 Chen, Gong 2014-06-11 13 EXPORT_SYMBOL_GPL(ras_userspace_consumers);
d963cd95 Chen, Gong 2014-06-11 14
d963cd95 Chen, Gong 2014-06-11 15 static int trace_show(struct seq_file *m,
void *v)
d963cd95 Chen, Gong 2014-06-11 16 {
d963cd95 Chen, Gong 2014-06-11 17 return atomic_read(_count);
d963cd95 Chen, Gong 2014-06-11 18 }
d963cd95 Chen, Gong 2014-06-11 19
d963cd95 Chen, Gong 2014-06-11 20 static int trace_open(struct inode *inode,
struct file *file)
d963cd95 Chen, Gong 2014-06-11 21 {
d963cd95 Chen, Gong 2014-06-11 22 atomic_inc(_count);
d963cd95 Chen, Gong 2014-06-11 23 return single_open(file, trace_show,
NULL);
d963cd95 Chen, Gong 2014-06-11 24 }
d963cd95 Chen, Gong 2014-06-11 25
d963cd95 Chen, Gong 2014-06-11 26 static int trace_release(struct inode
*inode, struct file *file)
d963cd95 Chen, Gong 2014-06-11 27 {
d963cd95 Chen, Gong 2014-06-11 28 atomic_dec(_count);
d963cd95 Chen, Gong 2014-06-11 29 return single_release(inode, file);
d963cd95 Chen, Gong 2014-06-11 30 }
d963cd95 Chen, Gong 2014-06-11 31
d963cd95 Chen, Gong 2014-06-11 32 static const struct file_operations
trace_fops = {
d963cd95 Chen, Gong 2014-06-11 33 .open= trace_open,
d963cd95 Chen, Gong 2014-06-11 34 .read= seq_read,
d963cd95 Chen, Gong 2014-06-11 35 .llseek = seq_lseek,
d963cd95 Chen, Gong 2014-06-11 36 .release = trace_release,
d963cd95 Chen, Gong 2014-06-11 37 };
d963cd95 Chen, Gong 2014-06-11 38
d963cd95 Chen, Gong 2014-06-11 @39 int __init ras_add_daemon_trace(void)
d963cd95 Chen, Gong 2014-06-11 40 {
d963cd95 Chen, Gong 2014-06-11 41 struct dentry *fentry;
d963cd95 Chen, Gong 2014-06-11 42
d963cd95 Chen, Gong 2014-06-11 43 if (!ras_debugfs_dir)
d963cd95 Chen, Gong 2014-06-11 44 return -ENOENT;
d963cd95 Chen, Gong 2014-06-11 45
d963cd95 Chen, Gong 2014-06-11 46 fentry =
debugfs_create_file("daemon_active", S_IRUSR, ras_debugfs_dir,
d963cd95 Chen, Gong 2014-06-11 47 NULL,
_fops);
d963cd95 Chen, Gong 2014-06-11 48 if (!fentry)
d963cd95 Chen, Gong 2014-06-11 49 return -ENODEV;
d963cd95 Chen, Gong 2014-06-11 50
d963cd95 Chen, Gong 2014-06-11 51 return 0;
d963cd95 Chen, Gong 2014-06-11 52
d963cd95 Chen, Gong 2014-06-11 53 }
d963cd95 Chen, Gong 2014-06-11 54
d963cd95 Chen, Gong 2014-06-11 @55 void __init ras_debugfs_init(void)
:: The code at line 9 was first introduced by commit
:: d963cd95bea93b7db9390a71d1e2cabbb3b2c3ea RAS, debugfs: Add debugfs
interface for RAS subsystem
:: TO: Chen, Gong
:: CC: Tony Luck
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
[PATCH v2] mtd: rawnand: ams-delta: Drop board specific partition info
After recent modifications, only a hardcoded partition info makes
the driver device specific. Other than that, the driver uses GPIO
exclusively and can be used on any hardware.
Drop the partition info and use MTD partition parser with default list
of parser names instead. For the OF parser to work correctly, pass
device of_node to mtd.
Amstrad Delta users should append the following partition info to their
kernel command line, possibly by embedding it in CONFIG_CMDLINE:
mtdparts=ams-delta-nand:3584k(Kernel),256k(u-boot),256k(u-boot_params),\
256k(Amstrad_LDR),27m(File_system),768k(PBL_reserved).
For their convenience, CONFIG_MTD_CMDLINE_PARTS symbol is selected
automatically from that board Kconfig if this NAND driver is also
selected.
Signed-off-by: Janusz Krzysztofik
Cc: Tony Lindgren
---
CHangelog:
v1->v2:
- fix a typo poined out by Aaro - thanks!
- fix device_node not passed to OF parser via mtd_info
- commit message reworded and reformatted a bit for better readability
arch/arm/mach-omap1/Kconfig | 1 +
drivers/mtd/nand/raw/ams-delta.c | 29 ++---
2 files changed, 3 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index c4694f26b5c4..62cf20f22828 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -171,6 +171,7 @@ config MACH_AMS_DELTA
select LEDS_GPIO_REGISTER
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
+ select MTD_CMDLINE_PARTS if MTD_NAND_AMS_DELTA
help
Support for the Amstrad E3 (codename Delta) videophone. Say Y here
if you have such a device.
diff --git a/drivers/mtd/nand/raw/ams-delta.c b/drivers/mtd/nand/raw/ams-delta.c
index 8312182088c1..e0f09179bbda 100644
--- a/drivers/mtd/nand/raw/ams-delta.c
+++ b/drivers/mtd/nand/raw/ams-delta.c
@@ -41,31 +41,6 @@ struct ams_delta_nand {
booldata_in;
};
-/*
- * Define partitions for flash devices
- */
-
-static const struct mtd_partition partition_info[] = {
- { .name = "Kernel",
- .offset = 0,
- .size = 3 * SZ_1M + SZ_512K },
- { .name = "u-boot",
- .offset = 3 * SZ_1M + SZ_512K,
- .size = SZ_256K },
- { .name = "u-boot params",
- .offset = 3 * SZ_1M + SZ_512K + SZ_256K,
- .size = SZ_256K },
- { .name = "Amstrad LDR",
- .offset = 4 * SZ_1M,
- .size = SZ_256K },
- { .name = "File system",
- .offset = 4 * SZ_1M + 1 * SZ_256K,
- .size = 27 * SZ_1M },
- { .name = "PBL reserved",
- .offset = 32 * SZ_1M - 3 * SZ_256K,
- .size = 3 * SZ_256K },
-};
-
static void ams_delta_write_commit(struct ams_delta_nand *priv)
{
gpiod_set_value(priv->gpiod_nwe, 0);
@@ -238,6 +213,7 @@ static int ams_delta_init(struct platform_device *pdev)
mtd->dev.parent = >dev;
nand_set_controller_data(this, priv);
+ nand_set_flash_node(this, pdev->dev.of_node);
priv->gpiod_rdy = devm_gpiod_get_optional(>dev, "rdy", GPIOD_IN);
if (IS_ERR(priv->gpiod_rdy)) {
@@ -315,8 +291,7 @@ static int ams_delta_init(struct platform_device *pdev)
return err;
/* Register the partitions */
- err = mtd_device_register(mtd, partition_info,
- ARRAY_SIZE(partition_info));
+ err = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
if (err)
goto err_nand_cleanup;
--
2.19.2
