Re: [PATCH v4 2/2] PCI/ERR: Split the fatal and non-fatal error recovery handling
On 10/13/20 10:44 PM, Ethan Zhao wrote: This patch only reverts the commit bdb5ac85777d ? or you'd better separate the revert and code you added. We cannot revert the commit as it is. pcie_do_recovery() function and Documentation/* folder changed a lot since fatal and non-fatal error recovery paths were merged. So I modified the revert so that it can be applied to the latest kernel version. -- Sathyanarayanan Kuppuswamy Linux Kernel Developer
[PATCH] i2c: designware: fix slave omitted IC_INTR_STOP_DET
When an I2C slave works, sometimes both IC_INTR_RX_FULL and
IC_INTR_STOP_DET are rising during an IRQ handle, especially when system
is busy or too late to handle interrupts.
If IC_INTR_RX_FULL is rising and the system doesn't handle immediately,
IC_INTR_STOP_DET may be rising and the system has to handle these two
events. For this there may be two problems:
1. IC_INTR_STOP_DET is rising after i2c_dw_read_clear_intrbits_slave()
done: It seems invalidated because WRITE_REQUESTED is done after the
1st WRITE_RECEIVED.
$ i2cset -f -y 2 0x42 0x00 0x41; dmesg -c
[0][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
[1][irq_handler ]0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
WRITE_RECEIVED
[0][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
[1][irq_handler ]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x714 :
INTR_STAT=0x204
WRITE_REQUESTED
WRITE_RECEIVED
[0][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x710 :
INTR_STAT=0x200
[1][irq_handler ]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x510 :
INTR_STAT=0x0
STOP
[2][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x510 :
INTR_STAT=0x0
t1: ISR with the 1st IC_INTR_RX_FULL.
t2: Clear listed IC_INTR bits by i2c_dw_read_clear_intrbits_slave().
t3: Enter i2c_dw_irq_handler_slave() and then do
i2c_slave_event(WRITE_RECEIVED) because
if (stat & DW_IC_INTR_RX_FULL).
t4: ISR with the 2nd IC_INTR_RX_FULL.
t5: Clear listed IC_INTR bits by i2c_dw_read_clear_intrbits_slave(),
while IC_INTR_STOP_DET has not risen yet.
t6: Enter i2c_dw_irq_handler_slave() and then IC_INTR_STOP_DET is
rising. i2c_slave_event(WRITE_REQUESTED) will be done first because
if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET)) and
then doing i2c_slave_event(WRITE_RECEIVED).
t7: do i2c_slave_event(STOP) due to IC_INTR_STOP_DET not be cleared yet.
2. Both IC_INTR_STOP_DET and IC_INTR_RX_FULL are rising before
i2c_dw_read_clear_intrbits_slave(): STOP cannot wait because
IC_INTR_STOP_DET is cleared by i2c_dw_read_clear_intrbits_slave().
$ i2cset -f -y 2 0x42 0x00 0x41; dmesg -c
[0][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
[1][irq_handler ]0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
WRITE_RECEIVED
[0][clear_intrbits]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x714 :
INTR_STAT=0x204
[1][irq_handler ]0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x514 :
INTR_STAT=0x4
WRITE_RECEIVED
t1: ISR with the 1st IC_INTR_RX_FULL.
t2: Clear listed IC_INTR bits by i2c_dw_read_clear_intrbits_slave().
t3: Enter i2c_dw_irq_handler_slave() and then do
i2c_slave_event(WRITE_RECEIVED) because
if (stat & DW_IC_INTR_RX_FULL).
t4: ISR with both IC_INTR_STOP_DET and the 2nd IC_INTR_RX_FULL.
t5: Clear listed IC_INTR bits by i2c_dw_read_clear_intrbits_slave(). The
current IC_INTR_STOP_DET is cleared by this
i2c_dw_read_clear_intrbits_slave().
t6: Enter i2c_dw_irq_handler_slave() and then do
i2c_slave_event(WRITE_RECEIVED) because
if (stat & DW_IC_INTR_RX_FULL).
t7: i2c_slave_event(STOP) never be done because IC_INTR_STOP_DET was
cleared in t5.
In order to resolve these problems, i2c_dw_read_clear_intrbits_slave()
should be called only one time in ISR and take the returned stat to handle
those occurred events.
Signed-off-by: Michael Wu
---
drivers/i2c/busses/i2c-designware-slave.c | 79 ---
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware-slave.c
b/drivers/i2c/busses/i2c-designware-slave.c
index 44974b53a626..8b3047fb2eae 100644
--- a/drivers/i2c/busses/i2c-designware-slave.c
+++ b/drivers/i2c/busses/i2c-designware-slave.c
@@ -159,7 +159,6 @@ static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
u32 raw_stat, stat, enabled, tmp;
u8 val = 0, slave_activity;
- regmap_read(dev->map, DW_IC_INTR_STAT, );
regmap_read(dev->map, DW_IC_ENABLE, );
regmap_read(dev->map, DW_IC_RAW_INTR_STAT, _stat);
regmap_read(dev->map, DW_IC_STATUS, );
@@ -168,58 +167,61 @@ static int i2c_dw_irq_handler_slave(struct dw_i2c_dev
*dev)
if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
return 0;
+ stat = i2c_dw_read_clear_intrbits_slave(dev);
dev_dbg(dev->dev,
"%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x :
INTR_STAT=%#x\n",
enabled, slave_activity, raw_stat, stat);
- if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET))
- i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, );
+ if (stat & DW_IC_INTR_RX_FULL) {
+ if (dev->status != STATUS_WRITE_IN_PROGRESS) {
+ if (dev->status != STATUS_IDLE)
+
[tip:auto-latest] BUILD SUCCESS f1fd159ac6fa12cc197caae397b36060f41cacef
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git auto-latest branch HEAD: f1fd159ac6fa12cc197caae397b36060f41cacef Merge branch 'core/rcu' elapsed time: 1230m configs tested: 151 configs skipped: 2 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig sh polaris_defconfig powerpc allyesconfig mipsmaltaup_xpa_defconfig powerpc mpc83xx_defconfig powerpc mpc837x_mds_defconfig powerpc tqm5200_defconfig arc nps_defconfig arm versatile_defconfig powerpcmpc7448_hpc2_defconfig mipsomega2p_defconfig arm stm32_defconfig shmigor_defconfig arm orion5x_defconfig arc nsimosci_hs_defconfig armspear3xx_defconfig armvt8500_v6_v7_defconfig mips rt305x_defconfig armkeystone_defconfig m68k sun3_defconfig powerpc stx_gp3_defconfig sh rsk7203_defconfig powerpc powernv_defconfig shedosk7760_defconfig armmvebu_v7_defconfig sh se7619_defconfig m68k atari_defconfig arm cns3420vb_defconfig xtensa defconfig sh ecovec24_defconfig m68k multi_defconfig powerpc holly_defconfig mips capcella_defconfig powerpc katmai_defconfig armhisi_defconfig arm iop32x_defconfig powerpc mgcoge_defconfig arm zx_defconfig powerpc currituck_defconfig xtensa alldefconfig microblaze mmu_defconfig sh rts7751r2d1_defconfig mips pnx8335_stb225_defconfig sparc sparc32_defconfig powerpcicon_defconfig powerpc mpc836x_rdk_defconfig arm axm55xx_defconfig arm aspeed_g5_defconfig shecovec24-romimage_defconfig mips mpc30x_defconfig arc haps_hs_smp_defconfig sh alldefconfig powerpc g5_defconfig riscvnommu_virt_defconfig m68kmac_defconfig microblaze defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig parisc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allmodconfig powerpc allnoconfig x86_64 randconfig-a004-20201013 x86_64 randconfig-a002-20201013 x86_64 randconfig-a006-20201013 x86_64 randconfig-a001-20201013 x86_64 randconfig-a003-20201013 x86_64 randconfig-a005-20201013 i386 randconfig-a005-20201014 i386 randconfig-a006-20201014 i386 randconfig-a001-20201014 i386 randconfig-a003-20201014
RE: [PATCH 1/1] clk: aspeed: modify some default clks are critical
> -Original Message- > From: Joel Stanley > Sent: Wednesday, October 14, 2020 1:28 PM > To: Stephen Boyd > Cc: Andrew Jeffery ; Michael Turquette > ; Ryan Chen ; > BMC-SW ; Linux ARM > ; linux-aspeed > ; linux-...@vger.kernel.org; Linux Kernel > Mailing List > Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical > > On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote: > > > > Quoting Ryan Chen (2020-09-28 00:01:08) > > > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 > > > are default for Host SuperIO UART device, eSPI clk for Host eSPI bus > > > access eSPI slave channel, those clks can't be disable should keep > > > default, otherwise will affect Host side access SuperIO and SPI slave > > > device. > > > > > > Signed-off-by: Ryan Chen > > > --- > > > > Is there resolution on this thread? > > Not yet. > > We have a system where the BMC (management controller) controls some > clocks, but the peripherals that it's clocking are outside the BMC's control. > In > this case, the host processor us using some UARTs and what not independent of > any code running on the BMC. > > Ryan wants to have them marked as critical so the BMC never powers them > down. > > However, there are systems that don't use this part of the soc, so for those > implementations they are not critical and Linux on the BMC can turn them off. > Take an example, conflict thought about ASPEED_CLK_GATE_BCLK is CLK_IS_CRITICAL in clk-ast2600.c In my opinion, the driver should keep the SoC default clk setting. It is original chip feature. > Do you have any thoughts? Has anyone solved a similar problem already? >
[GIT PULL] xen: branch for v5.10-rc1
Linus, Please git pull the following tag: git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-5.10b-rc1-tag xen: branch for v5.10-rc1 It contains: - 2 small cleanup patches - A fix for avoiding error messages when initializing MCA banks in a Xen dom0 - A small series for converting the Xen gntdev driver to use pin_user_pages*() instead of get_user_pages*() - An intermediate fix for running as a Xen guest on Arm with KPTI enabled (the final solution will need a new Xen functionality) Thanks. Juergen arch/arm/include/asm/xen/page.h | 5 + arch/arm/xen/enlighten.c | 6 -- arch/arm64/include/asm/xen/page.h | 6 ++ arch/x86/xen/enlighten_pv.c | 9 + arch/x86/xen/mmu_pv.c | 2 +- drivers/xen/gntdev.c | 17 + drivers/xen/pvcalls-front.c | 2 +- 7 files changed, 35 insertions(+), 12 deletions(-) Hui Su (1): x86/xen: Fix typo in xen_pagetable_p2m_free() Jing Xiangfeng (1): xen: remove redundant initialization of variable ret Juergen Gross (1): x86/xen: disable Firmware First mode for correctable memory errors Souptick Joarder (2): xen/gntdev.c: Mark pages as dirty xen/gntdev.c: Convert get_user_pages*() to pin_user_pages*() Stefano Stabellini (1): xen/arm: do not setup the runstate info page if kpti is enabled
Re: [External] Re: [PATCH] mm: proc: add Sock to /proc/meminfo
On Tue, Oct 13, 2020 at 08:21:13AM -0700, Randy Dunlap wrote: > On 10/13/20 8:12 AM, Mike Rapoport wrote: > > On Tue, Oct 13, 2020 at 07:43:59AM -0700, Randy Dunlap wrote: > >> On 10/13/20 1:09 AM, Mike Rapoport wrote: > >>> On Mon, Oct 12, 2020 at 05:53:01PM +0800, Muchun Song wrote: > On Mon, Oct 12, 2020 at 5:24 PM Eric Dumazet > wrote: > > > > On 10/12/20 10:39 AM, Muchun Song wrote: > >> On Mon, Oct 12, 2020 at 3:42 PM Eric Dumazet > >> wrote: > > We are not complaining about TCP using too much memory, but how do > we know that TCP uses a lot of memory. When I firstly face this problem, > I do not know who uses the 25GB memory and it is not shown in the > /proc/meminfo. > If we can know the amount memory of the socket buffer via /proc/meminfo, > we > may not need to spend a lot of time troubleshooting this problem. Not > everyone > knows that a lot of memory may be used here. But I believe many people > should know /proc/meminfo to confirm memory users. > >>> > >>> If I undestand correctly, the problem you are trying to solve is to > >>> simplify troubleshooting of memory usage for people who may not be aware > >>> that networking stack can be a large memory consumer. > >>> > >>> For that a paragraph in 'man 5 proc' maybe a good start: > >>> > >>> >From ddbcf38576d1a2b0e36fe25a27350d566759b664 Mon Sep 17 00:00:00 2001 > >>> From: Mike Rapoport > >>> Date: Tue, 13 Oct 2020 11:07:35 +0300 > >>> Subject: [PATCH] proc.5: meminfo: add not anout network stack memory > >>> consumption > >>> > >>> Signed-off-by: Mike Rapoport > >>> --- > >>> man5/proc.5 | 8 > >>> 1 file changed, 8 insertions(+) > >>> > >>> diff --git a/man5/proc.5 b/man5/proc.5 > >>> index ed309380b..8414676f1 100644 > >>> --- a/man5/proc.5 > >>> +++ b/man5/proc.5 > >>> @@ -3478,6 +3478,14 @@ Except as noted below, > >>> all of the fields have been present since at least Linux 2.6.0. > >>> Some fields are displayed only if the kernel was configured > >>> with various options; those dependencies are noted in the list. > >>> +.IP > >>> +Note that significant part of memory allocated by the network stack > >>> +is not accounted in the file. > >>> +The memory consumption of the network stack can be queried > >>> +using > >>> +.IR /proc/net/sockstat > >>> +or > >>> +.BR ss (8) > >>> .RS > >>> .TP > >>> .IR MemTotal " %lu" > >> > >> Hi Mike, > >> > >> Could you tell us what units those values are in? > >> or is that already explained somewhere else? > > > > It is described a few lines above and anyway, "MemTotal" is a part of > > the diff context ;-) > > with no units AFAICT. > > But I was unclear. I wasn't referring to /proc/meminfo, but instead > to /proc/net/sockstat and its units: > > sockets: used 1224 > TCP: inuse 11 orphan 1 tw 1 alloc 26 mem 3 > UDP: inuse 4 mem 2 > UDPLITE: inuse 0 > RAW: inuse 0 > FRAG: inuse 0 memory 0 > > E.g., for TCP and UDP, are those socket counts or some unit of memory? > If units of memory, what unit size? Ah, these are in 4k pages, AFAIU. And, as it seems /proc/net/sockstat lacks a description in proc.5 at all... > thanks. > -- > ~Randy > > -- Sincerely yours, Mike.
[PATCH v2] x86/unwind/orc: fix inactive tasks with stack pointer in %sp
gcc 10 optimizes the scheduler code differently than its predecessors.
When DEBUG_SECTION_MISMATCH config is enabled, Makefile forces gcc not
to inline some functions (-fno-inline-functions-called-once). Before gcc
10, "no-inlined" __schedule starts with the usual prologue (push %bp; mov
%sp,%bp). So ORC unwinder simply picks stack pointer from %bp and
unwinds from __schedule just perfectly:
$ cat /proc/1/stack
[<0>] ep_poll+0x3e9/0x450
[<0>] do_epoll_wait+0xaa/0xc0
[<0>] __x64_sys_epoll_wait+0x1a/0x20
[<0>] do_syscall_64+0x33/0x40
[<0>] entry_SYSCALL_64_after_hwframe+0x44/0xa9
But now, with gcc 10, there is no %bp prologue in __schedule:
$ cat /proc/1/stack
The orc entry of the point in __schedule is:
sp:sp+88 bp:last_sp-48 type:call end:0
In this case, nobody subtracts sizeof "struct inactive_task_frame" in
__unwind_start. The struct is put on the stack by __switch_to_asm and
only then __switch_to_asm stores %sp to task->thread.sp. But we start
unwinding from a point in __schedule (stored in frame->ret_addr by
'call') and not in __switch_to_asm.
So for these example values in __unwind_start:
sp=94b50001fdc8 bp=8e1f41d29340 ip=__schedule+0x1f0
The stack is:
94b50001fdc8: 8e1f41578000 # struct inactive_task_frame
94b50001fdd0:
94b50001fdd8: 8e1f41d29340
94b50001fde0: 8e1f41611d40 # ...
94b50001fde8: 93c41920 # bx
94b50001fdf0: 8e1f41d29340 # bp
94b50001fdf8: 9376cad0 # ret_addr (and end of the struct)
0x9376cad0 is __schedule+0x1f0 (after the call to
__switch_to_asm). Now follow those 88 bytes from the ORC entry (sp+88).
The entry is correct, __schedule really pushes 48 bytes (8*7) + 32 bytes
via subq to store some local values (like 4U below). So to unwind, look
at the offset 88-sizeof(long) = 0x50 from here:
94b50001fe00: 8e1f41578618
94b50001fe08: 0cc00255
94b50001fe10: 00050004
94b50001fe18: 7793fab6956b2d00 # NOTE (see below)
94b50001fe20: 8e1f41578000
94b50001fe28: 8e1f41578000
94b50001fe30: 8e1f41578000
94b50001fe38: 8e1f41578000
94b50001fe40: 94b50001fed8
94b50001fe48: 8e1f41577ff0
94b50001fe50: 9376cf12
Here is the correct ret addr from
__schedule. It translates to schedule+0x42 (insn after a call to
__schedule).
BUT, unwind_next_frame tries to take the address starting from
0x94b50001fdc8. That is exactly from thread.sp+88-sizeof(long) =
0x94b50001fdc8+88-8 = 0x94b50001fe18, which is garbage marked as
NOTE above. So this quits the unwinding as 7793fab6956b2d00 is obviously
not a kernel address.
There was a fix to skip 'struct inactive_task_frame' in
unwind_get_return_address_ptr in commit 187b96db5ca7 ("x86/unwind/orc:
Fix unwind_get_return_address_ptr() for inactive tasks").
But we need to skip the struct already in the unwinder proper. So
subtract the size (increase the stack pointer) of the structure in
__unwind_start directly. This allows for removal of the code added by
commit 187b96db5ca7 completely, as the address is now at
'(unsigned long *)state->sp - 1', the same as in the generic case.
Fixes: ee9f8fce9964 ("x86/unwind: Add the ORC unwinder")
Bug: https://bugzilla.suse.com/show_bug.cgi?id=1176907
Signed-off-by: Jiri Slaby
Cc: Miroslav Benes
Cc: Josh Poimboeuf
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Cc: live-patch...@vger.kernel.org
---
[v2]
* Remove comment from __unwind_start.
* Cc more parties
* Polish the commitlog
arch/x86/kernel/unwind_orc.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c
index 6a339ce328e0..73f800100066 100644
--- a/arch/x86/kernel/unwind_orc.c
+++ b/arch/x86/kernel/unwind_orc.c
@@ -321,19 +321,12 @@ EXPORT_SYMBOL_GPL(unwind_get_return_address);
unsigned long *unwind_get_return_address_ptr(struct unwind_state *state)
{
- struct task_struct *task = state->task;
-
if (unwind_done(state))
return NULL;
if (state->regs)
return >regs->ip;
- if (task != current && state->sp == task->thread.sp) {
- struct inactive_task_frame *frame = (void *)task->thread.sp;
- return >ret_addr;
- }
-
if (state->sp)
return (unsigned long *)state->sp - 1;
@@ -663,7 +656,7 @@ void __unwind_start(struct unwind_state *state, struct
task_struct *task,
} else {
struct inactive_task_frame *frame = (void *)task->thread.sp;
- state->sp = task->thread.sp;
+ state->sp = task->thread.sp + sizeof(*frame);
state->bp = READ_ONCE_NOCHECK(frame->bp);
state->ip = READ_ONCE_NOCHECK(frame->ret_addr);
state->signal = (void *)state->ip == ret_from_fork;
--
2.28.0
Re: disabling CONFIG_LED_CLASS
On 14-10-2020 07:07, Randy Dunlap wrote: > On 10/13/20 9:56 PM, Udo van den Heuvel wrote: >> I.e.: it looks like I will lose some funcionality when I disable >> SND_HDA_CODEC_REALTEK. > > OK. At present you can't have it both ways, i.e., SND_HDA_CODEC_REALTEK > with no LEDS. That driver apparently wants LEDS. Thanks but why have I gone for years without LEDS? I do not need LEDS, I do not want LEDS, I do not have LEDS (that are visible, usable, etc). Please make this selectable instead of forcing more bulk into my kernel. Kind regards, Udo
Re: [PATCH] x86/unwind/orc: fix inactive tasks with sp in sp
On 07. 10. 20, 16:54, Josh Poimboeuf wrote:
-ENOPARSE on $SUBJECT.
Also please address it to x...@kernel.org, I think the tip maintainers
can pick up the fix directly.
Hmm, weird, I must have sent an older version as my current patch in the
tree has:
Cc: Miroslav Benes
Cc: Josh Poimboeuf
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Also it might be a good idea to Cc the live-patching mailing list, I
presume this causes a livepatch stall?
On Wed, Oct 07, 2020 at 10:19:09AM +0200, Jiri Slaby wrote:
gcc-10 optimizes the scheduler code differently than its predecessors,
depending on DEBUG_SECTION_MISMATCH=y config -- the config sets
-fno-inline-functions-called-once.
Weird. Was GCC ignoring this flag before?
gcc 7 generated the earlier mentioned prologue (push bp; mov sp,bp). So
we extract stack pointer from bp. gcc 10 no longer generates the
prologue in some of the standalone functions. That's the difference. So
we started extracting stack pointer from sp which contains more than we
expect.
And the problem also (obviously) dismisses when gcc (even 10) inlines
the function.
@@ -663,7 +656,13 @@ void __unwind_start(struct unwind_state *state, struct
task_struct *task,
} else {
struct inactive_task_frame *frame = (void *)task->thread.sp;
- state->sp = task->thread.sp;
+ /*
+* @ret_addr is in __schedule _before_ the @frame is pushed to
+* the stack, but @thread.sp is saved in __switch_to_asm only
+* _after_ saving the @frame, so subtract the @frame size, i.e.
+* add it to @thread.sp.
+*/
+ state->sp = task->thread.sp + sizeof(*frame);
IMO, the code speaks for itself and the comment may be superfluous.
Otherwise it looks good to me. Thanks for fixing it!
OK, will resend the correct and fixed version.
thanks,
--
js
suse labs
Re: [PATCH] arm64/mm: Validate hotplug range before creating linear mapping
On 10/12/2020 12:59 PM, Ard Biesheuvel wrote:
> On Tue, 6 Oct 2020 at 08:36, Anshuman Khandual
> wrote:
>>
>>
>>
>> On 09/30/2020 01:32 PM, Anshuman Khandual wrote:
>>> But if __is_lm_address() checks against the effective linear range instead
>>> i.e [_PAGE_OFFSET(vabits_actual)..(PAGE_END - 1)], it can be used for hot
>>> plug physical range check there after. Perhaps something like this, though
>>> not tested properly.
>>>
>>> diff --git a/arch/arm64/include/asm/memory.h
>>> b/arch/arm64/include/asm/memory.h
>>> index afa722504bfd..6da046b479d4 100644
>>> --- a/arch/arm64/include/asm/memory.h
>>> +++ b/arch/arm64/include/asm/memory.h
>>> @@ -238,7 +238,10 @@ static inline const void *__tag_set(const void *addr,
>>> u8 tag)
>>> * space. Testing the top bit for the start of the region is a
>>> * sufficient check and avoids having to worry about the tag.
>>> */
>>> -#define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1)))
>>> +static inline bool __is_lm_address(unsigned long addr)
>>> +{
>>> + return ((addr >= _PAGE_OFFSET(vabits_actual)) && (addr <= (PAGE_END
>>> - 1)));
>>> +}
>>>
>>> #define __lm_to_phys(addr) (((addr) + physvirt_offset))
>>> #define __kimg_to_phys(addr) ((addr) - kimage_voffset)
>>> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
>>> index d59ffabb9c84..5750370a7e8c 100644
>>> --- a/arch/arm64/mm/mmu.c
>>> +++ b/arch/arm64/mm/mmu.c
>>> @@ -1451,8 +1451,7 @@ static bool inside_linear_region(u64 start, u64 size)
>>> * address range mapped by the linear map, the start address should
>>> * be calculated using vabits_actual.
>>> */
>>> - return ((start >= __pa(_PAGE_OFFSET(vabits_actual)))
>>> - && ((start + size) <= __pa(PAGE_END - 1)));
>>> + return __is_lm_address(__va(start)) && __is_lm_address(__va(start +
>>> size));
>>> }
>>>
>>> int arch_add_memory(int nid, u64 start, u64 size,
>>
>> Will/Ard,
>>
>> Any thoughts about this ? __is_lm_address() now checks for a range instead
>> of a bit. This will be compatible later on, even if linear mapping range
>> changes from current lower half scheme.
>>
>
> As I'm sure you have noticed, I sent out some patches that get rid of
> physvirt_offset, and which simplify __is_lm_address() to only take
> compile time constants into account (unless KASAN is enabled). This
> means that in the 52-bit VA case, __is_lm_address() does not
> distinguish between virtual addresses that can be mapped by the
> hardware and ones that cannot.
Yeah, though was bit late in getting to the series. So with that change
there might be areas in the linear mapping which cannot be addressed by
the hardware and hence should also need be checked apart from proposed
linear mapping coverage test, during memory hotplug ?
>
> In the memory hotplug case, we need to decide whether the added memory
> will appear in the addressable area, which is a different question. So
> it makes sense to duplicate some of the logic that exists in
> arm64_memblock_init() (or factor it out) to decide whether this newly
> added memory will appear in the addressable window or not.
It seems unlikely that any hotplug agent (e.g. firmware) will ever push
through a memory range which is not accessible in the hardware but then
it is not impossible either. In summary, arch_add_memory() should check
1. Range can be covered inside linear mapping
2. Range is accessible by the hardware
Before the VA space organization series, (2) was not necessary as it was
contained inside (1) ?
>
> So I think your original approach makes more sense here, although I
> think you want '(start + size - 1) <= __pa(PAGE_END - 1)' in the
> comparison above (and please drop the redundant parens)
>
Sure, will accommodate these changes.
[PATCH] Add support for mv88e6393x family of Marvell.
The Marvell 88E6393X device is a single-chip integration of a 11-port
Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers
and three 10-Gigabit interfaces.
This patch adds functionalities specific to mv88e6393x family (88E6393X,
88E6193X and 88E6191X)
Signed-off-by: Pavana Sharma
---
drivers/net/dsa/mv88e6xxx/chip.c| 90 +
drivers/net/dsa/mv88e6xxx/chip.h| 2 +
drivers/net/dsa/mv88e6xxx/global1.h | 2 +
drivers/net/dsa/mv88e6xxx/global2.c | 7 +
drivers/net/dsa/mv88e6xxx/global2.h | 8 +
drivers/net/dsa/mv88e6xxx/port.c| 302
drivers/net/dsa/mv88e6xxx/port.h| 39 +++-
drivers/net/dsa/mv88e6xxx/serdes.c | 242 ++
drivers/net/dsa/mv88e6xxx/serdes.h | 39
9 files changed, 730 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index f0dbc05e30a4..241ff788b0b1 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -634,6 +634,23 @@ static void mv88e6390x_phylink_validate(struct
mv88e6xxx_chip *chip, int port,
mv88e6390_phylink_validate(chip, port, mask, state);
}
+static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
+ unsigned long *mask,
+ struct phylink_link_state *state)
+{
+ if (port == 0 || port >= 9) {
+ phylink_set(mask, 1baseT_Full);
+ phylink_set(mask, 1baseKR_Full);
+ phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 2500baseT_Full);
+ }
+
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
+
+ mv88e6065_phylink_validate(chip, port, mask, state);
+}
+
static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
unsigned long *supported,
struct phylink_link_state *state)
@@ -4141,6 +4158,56 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
.phylink_validate = mv88e6390_phylink_validate,
};
+static const struct mv88e6xxx_ops mv88e6193x_ops = {
+ /* MV88E6XXX_FAMILY_6393X */
+ .setup_errata = mv88e6393x_setup_errata,
+ .irl_init_all = mv88e6390_g2_irl_init_all,
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_tag_remap = mv88e6390_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_floods = mv88e6352_port_set_egress_floods,
+ .port_set_ether_type = mv88e6393x_port_set_ether_type,
+ .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_limit = mv88e6390_port_pause_limit,
+ .port_set_cmode = mv88e6393x_port_set_cmode,
+ .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
+ .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
+ .port_get_cmode = mv88e6352_port_get_cmode,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .set_cpu_port = mv88e6393x_port_set_cpu_dest,
+ .set_egress_port = mv88e6393x_set_egress_port,
+ .watchdog_ops = _watchdog_ops,
+ .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
+ .pot_clear = mv88e6xxx_g2_pot_clear,
+ .reset = mv88e6352_g1_reset,
+ .rmu_disable = mv88e6390_g1_rmu_disable,
+ .vtu_getnext = mv88e6390_g1_vtu_getnext,
+ .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
+ .serdes_power = mv88e6393x_serdes_power,
+ .serdes_get_lane = mv88e6393x_serdes_get_lane,
+ /* Check status register pause & lpa register */
+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
+ .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
+ .serdes_irq_status = mv88e6393x_serdes_irq_status,
+ .gpio_ops = _gpio_ops,
+ .avb_ops = _avb_ops,
+ .ptp_ops = _ptp_ops,
+ .phylink_validate = mv88e6393x_phylink_validate,
+};
+
static const struct mv88e6xxx_ops mv88e6240_ops = {
/* MV88E6XXX_FAMILY_6352 */
.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
@@ -5073,6 +5140,29 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = _ops,
Re: disabling CONFIG_LED_CLASS
On 14-10-2020 06:49, Randy Dunlap wrote: > If you disable SND_HDA_CODEC_REALTEK, then the rest of the > LED kconfig symbols can be disabled. Sure, but: # dmesg|grep audi (...) [ 19.971537] snd_hda_codec_generic hdaudioC0D0: ignore pin 0x7, too many assigned pins [ 19.973547] snd_hda_codec_generic hdaudioC0D0: autoconfig for Generic: line_outs=0 (0x0/0x0/0x0/0x0/0x0) type:line [ 19.975642] snd_hda_codec_generic hdaudioC0D0:speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 19.94] snd_hda_codec_generic hdaudioC0D0:hp_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 19.980176] snd_hda_codec_generic hdaudioC0D0:mono: mono_out=0x0 [ 19.982257] snd_hda_codec_generic hdaudioC0D0:dig-out=0x3/0x5 [ 19.984412] snd_hda_codec_generic hdaudioC0D0:inputs: [ 20.035088] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC1220: line_outs=3 (0x14/0x15/0x16/0x0/0x0) type:line [ 20.036940] snd_hda_codec_realtek hdaudioC1D0:speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 20.039579] snd_hda_codec_realtek hdaudioC1D0:hp_outs=1 (0x1b/0x0/0x0/0x0/0x0) [ 20.041690] snd_hda_codec_realtek hdaudioC1D0:mono: mono_out=0x0 [ 20.044076] snd_hda_codec_realtek hdaudioC1D0:dig-out=0x1e/0x0 [ 20.046173] snd_hda_codec_realtek hdaudioC1D0:inputs: [ 20.049252] snd_hda_codec_realtek hdaudioC1D0: Front Mic=0x19 [ 20.051287] snd_hda_codec_realtek hdaudioC1D0: Rear Mic=0x18 [ 20.053084] snd_hda_codec_realtek hdaudioC1D0: Line=0x1a [ 20.427487] usbcore: registered new interface driver snd-usb-audio I.e.: it looks like I will lose some funcionality when I disable SND_HDA_CODEC_REALTEK. Kind regards, Udo
Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema
Hi, Chunfeng:
On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: fix binding check warning of reg in example
> ---
> .../display/mediatek/mediatek,hdmi.txt| 17 +---
> .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++
> 2 files changed, 91 insertions(+), 16 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> index 7b124242b0c5..edac18951a75 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> @@ -50,22 +50,7 @@ Required properties:
>
> HDMI PHY
>
> -
> -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> -output and drives the HDMI pads.
> -
> -Required properties:
> -- compatible: "mediatek,-hdmi-phy"
> -- reg: Physical base address and length of the module's registers
> -- clocks: PLL reference clock
> -- clock-names: must contain "pll_ref"
> -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> -- #phy-cells: must be <0>
> -- #clock-cells: must be <0>
> -
> -Optional properties:
> -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +See phy/mediatek,hdmi-phy.yaml
>
> Example:
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> new file mode 100644
> index ..77df50204606
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> +
> +maintainers:
> + - CK Hu
I think you should remove "CK Hu " and add latest
mediatek drm maintainer:
DRM DRIVERS FOR MEDIATEK
M: Chun-Kuang Hu
M: Philipp Zabel
L: dri-de...@lists.freedesktop.org
S: Supported
F: Documentation/devicetree/bindings/display/mediatek/
F: drivers/gpu/drm/mediatek/
Regards,
CK
> + - Chunfeng Yun
> +
> +description: |
> + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> + output and drives the HDMI pads.
> +
> +properties:
> + $nodename:
> +pattern: "^hdmi-phy@[0-9a-f]+$"
> +
> + compatible:
> +enum:
> + - mediatek,mt2701-hdmi-phy
> + - mediatek,mt8173-hdmi-phy
> +
> + reg:
> +maxItems: 1
> +
> + clocks:
> +items:
> + - description: PLL reference clock
> +
> + clock-names:
> +items:
> + - const: pll_ref
> +
> + clock-output-names:
> +items:
> + - const: hdmitx_dig_cts
> +
> + "#phy-cells":
> +const: 0
> +
> + "#clock-cells":
> +const: 0
> +
> + mediatek,ibias:
> +description:
> + TX DRV bias current for < 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0xa
> +
> + mediatek,ibias_up:
> +description:
> + TX DRV bias current for >= 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0x1c
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - clock-output-names
> + - "#phy-cells"
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +hdmi_phy: hdmi-phy@10209100 {
> +compatible = "mediatek,mt8173-hdmi-phy";
> +reg = <0x10209100 0x24>;
> +clocks = < CLK_APMIXED_HDMI_REF>;
> +clock-names = "pll_ref";
> +clock-output-names = "hdmitx_dig_cts";
> +mediatek,ibias = <0xa>;
> +mediatek,ibias_up = <0x1c>;
> +#clock-cells = <0>;
> +#phy-cells = <0>;
> +};
> +
> +...
Re: [PATCH] DMA: PL330: Remove unreachable code
On 13-10-20, 17:17, Surendran K wrote:
> _setup_req(..) never returns negative value.
> Hence the condition ret < 0 is never met
The subsystem is "dmaengine", git log would tell you the tags to use
>
> Signed-off-by: Surendran K
> ---
> drivers/dma/pl330.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
> index e9f0101d92fa..8355586c9788 100644
> --- a/drivers/dma/pl330.c
> +++ b/drivers/dma/pl330.c
> @@ -1527,8 +1527,6 @@ static int pl330_submit_req(struct pl330_thread *thrd,
>
> /* First dry run to check if req is acceptable */
> ret = _setup_req(pl330, 1, thrd, idx, );
> - if (ret < 0)
> - goto xfer_exit;
>
> if (ret > pl330->mcbufsz / 2) {
> dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz
> (%i/%i)\n",
> --
> 2.17.1
--
~Vinod
Re: disabling CONFIG_LED_CLASS
On 13-10-2020 18:03, Randy Dunlap wrote: > On 10/13/20 8:53 AM, Randy Dunlap wrote: >> [adding LED people + list] >> >> On 10/13/20 6:24 AM, Udo van den Heuvel wrote: (...) So how do I disable this stuff? > > I was able to disable LEDS_CLASS and NEW_LEDS after I disabled the following > config symbols: > > > --- xx64/config-def64 2020-10-13 08:53:56.050501724 -0700 > +++ xx64/.config 2020-10-13 08:58:12.439205389 -0700 > -CONFIG_MAC80211_LEDS=y > -CONFIG_RFKILL_LEDS=y > -# CONFIG_LED_TRIGGER_PHY is not set > -CONFIG_INPUT_LEDS=y > -# CONFIG_HID_LED is not set > -# CONFIG_USB_LED_TRIG is not set > -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set > -CONFIG_LEDS_TRIGGERS=y > -CONFIG_EEEPC_LAPTOP=y > +# CONFIG_EEEPC_LAPTOP is not set > > This last one was the biggest problem for me. > I started with x86_64 defconfig. # grep LED .config # grep LEDS .config # grep EEPC .config # make oldconfig (...) * * LED Support * LED Support (NEW_LEDS) [Y/?] (NEW) y LED Class Support (LEDS_CLASS) [M/y/?] (NEW) n So we still are stuck. Udo
GREETINGS....
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Re: [PATCH 1/2] Asoc: qcom: lpass-cpu: Fix clock disable failure
Thanks Mark Brown for your time !!!
On 10/13/2020 8:45 PM, Mark Brown wrote:
On Tue, Oct 13, 2020 at 07:09:46PM +0530, Srinivasa Rao Mandadapu wrote:
From: V Sujith Kumar Reddy
Disable MI2S bit clock from PAUSE/STOP/SUSPEND usecase
instead of shutdown time. Acheive this by invoking
clk_disable_unprepare API from cpu daiops shutdown to
cpu daiops trigger.
I'm missing patch 2 here?
No.. It's a single patch. By mistake I sent with wrong header.
This Fix is update to the below patch.
https://lore.kernel.org/patchwork/patch/1308101/
Fixes should be specified using tags like this:
Fixes: commit 30fb9454ab23 ("selftests/vm: hmm-tests: remove the libhugetlbfs
dependency")
in the changelog.
Thanks for your guidance. I will take care of it next time.
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v3 09/15] arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop
I will add a dt-bindings commit for this change.
Thanks for review.
JC
On 9/28/20 9:18 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:35PM +0800, JC Kuo wrote:
>> PMC driver provides USB sleepwalk registers access to XUSB PADCTL
>> driver. This commit adds a "nvidia,pmc" property which points to
>> PMC node to XUSB PADCTL device node.
>>
>> Signed-off-by: JC Kuo
>> ---
>> v3:
>>no change
>>
>> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> index 829f786af133..67c90a0ea32e 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> @@ -1040,6 +1040,7 @@ padctl: padctl@7009f000 {
>> reg = <0x0 0x7009f000 0x0 0x1000>;
>> resets = <_car 142>;
>> reset-names = "padctl";
>> +nvidia,pmc = <_pmc>;
>
> I hadn't noticed before but it looks like the DT bindings haven't been
> updated with this new property.
>
> Thierry
>
Re: [PATCH v3 08/15] soc/tegra: pmc: Provide usb sleepwalk register map
I will amend commit accordingly and submit a new patch.
Thanks for review.
JC
On 9/28/20 9:17 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:34PM +0800, JC Kuo wrote:
>> This commit implements a register map which grants USB (UTMI and HSIC)
>> sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
>> is in PMC hardware block but USB PHY drivers have the best knowledge
>> of proper programming sequence. This approach prevents using custom
>> pmc APIs.
>
> I don't think this final sentence is useful. The commit message should
> explain what you're doing, but there's no need to enumerate any other
> inferior solution you didn't choose to implement.
>
> If you do want to keep it: s/pmc/PMC/.
>
> While at it, perhaps replace "usb" by "USB" in the subject as well.
>
>>
>> Signed-off-by: JC Kuo
>> ---
>> v3:
>>commit message improvement
>>drop regmap_reg() usage
>>rename 'reg' with 'offset'
>>rename 'val' with 'value'
>>drop '__force' when invokes devm_regmap_init()
>>print error code of devm_regmap_init()
>>move devm_regmap_init() a litter bit earlier
>>explicitly set '.has_usb_sleepwalk=false'
>>
>> drivers/soc/tegra/pmc.c | 95 +
>> 1 file changed, 95 insertions(+)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index d332e5d9abac..ff24891ce9ca 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -43,6 +43,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #include
>> #include
>> @@ -102,6 +103,9 @@
>>
>> #define PMC_PWR_DET_VALUE 0xe4
>>
>> +#define PMC_USB_DEBOUNCE_DEL0xec
>> +#define PMC_USB_AO 0xf0
>> +
>> #define PMC_SCRATCH41 0x140
>>
>> #define PMC_WAKE2_MASK 0x160
>> @@ -133,6 +137,13 @@
>> #define IO_DPD2_STATUS 0x1c4
>> #define SEL_DPD_TIM 0x1c8
>>
>> +#define PMC_UTMIP_UHSIC_TRIGGERS0x1ec
>> +#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
>> +
>> +#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
>> +#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
>> +#define PMC_UTMIP_UHSIC_FAKE0x218
>> +
>> #define PMC_SCRATCH54 0x258
>> #define PMC_SCRATCH54_DATA_SHIFT 8
>> #define PMC_SCRATCH54_ADDR_SHIFT 0
>> @@ -145,8 +156,18 @@
>> #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
>> #define PMC_SCRATCH55_I2CSLV1_SHIFT0
>>
>> +#define PMC_UTMIP_UHSIC_LINE_WAKEUP0x26c
>> +
>> +#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
>> +#define PMC_UTMIP_MASTER_CONFIG 0x274
>> +#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
>> +#define PMC_UTMIP_MASTER2_CONFIG0x29c
>> +
>> #define GPU_RG_CNTRL0x2d4
>>
>> +#define PMC_UTMIP_PAD_CFG0 0x4c0
>> +#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
>> +#define PMC_UTMIP_SLEEPWALK_P3 0x4e0
>> /* Tegra186 and later */
>> #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
>> #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
>> @@ -334,6 +355,7 @@ struct tegra_pmc_soc {
>> const struct pmc_clk_init_data *pmc_clks_data;
>> unsigned int num_pmc_clks;
>> bool has_blink_output;
>> +bool has_usb_sleepwalk;
>> };
>>
>> static const char * const tegra186_reset_sources[] = {
>> @@ -2495,6 +2517,68 @@ static void tegra_pmc_clock_register(struct tegra_pmc
>> *pmc,
>> err);
>> }
>>
>> +static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
>> +regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
>> +regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
>> +regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
>> +regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP,
>> PMC_UTMIP_UHSIC_LINE_WAKEUP),
>> +regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
>> +regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
>> +regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
>> +regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
>> +};
>> +
>> +static const struct regmap_access_table pmc_usb_sleepwalk_table = {
>> +.yes_ranges = pmc_usb_sleepwalk_ranges,
>> +.n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
>> +};
>> +
>> +static int tegra_pmc_regmap_readl(void *context, unsigned int offset,
>> unsigned int *value)
>> +{
>> +struct tegra_pmc *pmc = context;
>> +
>> +*value = tegra_pmc_readl(pmc, offset);
>> +return 0;
>> +}
>> +
>> +static int tegra_pmc_regmap_writel(void *context, unsigned int offset,
>> unsigned int value)
>> +{
>> +struct tegra_pmc *pmc = context;
>> +
>> +tegra_pmc_writel(pmc, value, offset);
>> +return 0;
>> +}
>> +
>> +static const struct regmap_config usb_sleepwalk_regmap_config = {
>> +.name = "usb_sleepwalk",
>> +.reg_bits = 32,
>> +.val_bits =
iwlwifi: spaces in procfs filenames ?
commit 64fa3aff89785b5a924ce3934f6595c35b4dffee
Author: Sharon Dvir
Date: Wed Aug 17 15:35:09 2016 +0300
iwlwifi: pcie: give a meaningful name to interrupt request
perhaps unintentionally for file:
drivers/net/wireless/intel/iwlwifi/pcie/internal.h
in function static inline const char *queue_name
creates spaces in procfs filenames.
drivers/net/wireless/intel/iwlwifi/pcie/internal.h:static inline const char
*queue_name(struct device *dev,
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
struct iwl_trans_pcie *trans_p, int i)
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-{
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- if
(trans_p->shared_vec_mask) {
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- int vec =
trans_p->shared_vec_mask &
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- if (i == 0)
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- return
DRV_NAME ": shared IRQ";
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- return
devm_kasprintf(dev, GFP_KERNEL,
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
DRV_NAME ": queue %d", i + vec);
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- }
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- if (i == 0)
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- return DRV_NAME
": default queue";
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- if (i ==
trans_p->alloc_vecs - 1)
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- return DRV_NAME
": exception";
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h- return
devm_kasprintf(dev, GFP_KERNEL,
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-
DRV_NAME ": queue %d", i);
drivers/net/wireless/intel/iwlwifi/pcie/internal.h-}
# find /proc/ | grep " "
/proc/irq/130/iwlwifi: default queue
/proc/irq/131/iwlwifi: queue 1
/proc/irq/132/iwlwifi: queue 2
/proc/irq/133/iwlwifi: queue 3
/proc/irq/134/iwlwifi: queue 4
/proc/irq/135/iwlwifi: exception
Can these names be changed back or collapsed
to avoid the space use in procfs?
[PATCH] perf: Improve PT documentation slightly
Document the higher level --insn-trace etc. perf script options. Include the howto how to build xed into the manpage Cc: adrian.hun...@intel.com Signed-off-by: Andi Kleen --- tools/perf/Documentation/perf-intel-pt.txt | 30 ++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/Documentation/perf-intel-pt.txt b/tools/perf/Documentation/perf-intel-pt.txt index d5a266d7f15b..cc2a8b2be31a 100644 --- a/tools/perf/Documentation/perf-intel-pt.txt +++ b/tools/perf/Documentation/perf-intel-pt.txt @@ -112,6 +112,32 @@ The flags are "bcrosyiABEx" which stand for branch, call, return, conditional, system, asynchronous, interrupt, transaction abort, trace begin, trace end, and in transaction, respectively. +perf script also supports higher level ways to dump instruction traces: + + perf script --insn-trace --xed + +Dump all instructions. This requires installing the xed tool (see XED below) +Dumping all instructions in a long trace can be fairly slow. It is usually better +to start with higher level decoding, like + + perf script --call-trace + +or + + perf script --call-ret-trace + +and then select a time range of interest. The time range can then be examined +in detail with + + perf script --time starttime,stoptime --insn-trace --xed + +While examining the trace it's also useful to filter on specific CPUs using +the -C option + + perf script --time starttime,stoptime --insn-trace --xed -C 1 + +Dump all instructions in time range on CPU 1. + Another interesting field that is not printed by default is 'ipc' which can be displayed as follows: @@ -1093,6 +1119,10 @@ To display PEBS events from the Intel PT trace, use the itrace 'o' option e.g. perf script --itrace=oe +XED +--- + +include::build-xed.txt[] SEE ALSO -- 2.28.0
[PATCH] perf: Add support for exclusive groups/events
Peter suggested that using the exclusive mode in perf could
avoid some problems with bad scheduling of groups. Exclusive
is implemented in the kernel, but wasn't exposed by the perf tool,
so hard to use without custom low level API users.
Add support for marking groups or events with :e for exclusive
in the perf tool. The implementation is basically the same as the
existing pinned attribute.
Cc: pet...@infradead.org
Signed-off-by: Andi Kleen
---
tools/perf/Documentation/perf-list.txt | 1 +
tools/perf/tests/parse-events.c| 58 +-
tools/perf/util/parse-events.c | 9 +++-
tools/perf/util/parse-events.l | 2 +-
4 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/tools/perf/Documentation/perf-list.txt
b/tools/perf/Documentation/perf-list.txt
index 10ed539a8859..4c7db1da8fcc 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -58,6 +58,7 @@ counted. The following modifiers exist:
S - read sample value (PERF_SAMPLE_READ)
D - pin the event to the PMU
W - group is weak and will fallback to non-group if not schedulable,
+ e - group or event are exclusive and do not share the PMU
The 'p' modifier can be used for specifying how precise the instruction
address should be. The 'p' modifier can be specified multiple times:
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 7f9f87a470c3..7411dd4d76cf 100644
--- a/tools/perf/tests/parse-events.c
+++ b/tools/perf/tests/parse-events.c
@@ -557,6 +557,7 @@ static int test__checkevent_pmu_events(struct evlist
*evlist)
TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv);
TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip);
TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned);
+ TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive);
return 0;
}
@@ -575,6 +576,7 @@ static int test__checkevent_pmu_events_mix(struct evlist
*evlist)
TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv);
TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip);
TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned);
+ TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive);
/* cpu/pmu-event/u*/
evsel = evsel__next(evsel);
@@ -587,6 +589,7 @@ static int test__checkevent_pmu_events_mix(struct evlist
*evlist)
TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv);
TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip);
TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned);
+ TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.pinned);
return 0;
}
@@ -1277,6 +1280,49 @@ static int test__pinned_group(struct evlist *evlist)
return 0;
}
+static int test__checkevent_exclusive_modifier(struct evlist *evlist)
+{
+ struct evsel *evsel = evlist__first(evlist);
+
+ TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user);
+ TEST_ASSERT_VAL("wrong exclude_kernel",
evsel->core.attr.exclude_kernel);
+ TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv);
+ TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip);
+ TEST_ASSERT_VAL("wrong exclusive", evsel->core.attr.exclusive);
+
+ return test__checkevent_symbolic_name(evlist);
+}
+
+static int test__exclusive_group(struct evlist *evlist)
+{
+ struct evsel *evsel, *leader;
+
+ TEST_ASSERT_VAL("wrong number of entries", 3 ==
evlist->core.nr_entries);
+
+ /* cycles - group leader */
+ evsel = leader = evlist__first(evlist);
+ TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE ==
evsel->core.attr.type);
+ TEST_ASSERT_VAL("wrong config",
+ PERF_COUNT_HW_CPU_CYCLES == evsel->core.attr.config);
+ TEST_ASSERT_VAL("wrong group name", !evsel->group_name);
+ TEST_ASSERT_VAL("wrong leader", evsel->leader == leader);
+ TEST_ASSERT_VAL("wrong exclusive", evsel->core.attr.exclusive);
+
+ /* cache-misses - can not be pinned, but will go on with the leader */
+ evsel = evsel__next(evsel);
+ TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE ==
evsel->core.attr.type);
+ TEST_ASSERT_VAL("wrong config",
+ PERF_COUNT_HW_CACHE_MISSES == evsel->core.attr.config);
+ TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive);
+
+ /* branch-misses - ditto */
+ evsel = evsel__next(evsel);
+ TEST_ASSERT_VAL("wrong config",
+ PERF_COUNT_HW_BRANCH_MISSES == evsel->core.attr.config);
+ TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive);
+
+ return 0;
+}
static int test__checkevent_breakpoint_len(struct evlist *evlist)
{
struct evsel *evsel = evlist__first(evlist);
@@ -1765,7 +1811,17 @@ static struct evlist_test
Re: [PATCH v2 1/2] extcon: add driver for TI TUSB320
Hi,
Looks good to me. I add some comment. Please check them.
On 10/12/20 11:47 PM, Michael Auchter wrote:
> This patch adds an extcon driver for the TI TUSB320 USB Type-C device.
> This can be used to detect whether the port is configured as a
> downstream or upstream facing port.
>
> Signed-off-by: Michael Auchter
> ---
> Changes since v1:
> - Drop license text that's redundant with SPDX tag
> - Cleanup, sort list of includes
> - Add additional register defines
> - Switch to use regmap API
> - Fix Kconfig to depend on I2C, not GPIOLIB
>
> drivers/extcon/Kconfig | 8 ++
> drivers/extcon/Makefile | 1 +
> drivers/extcon/extcon-usbc-tusb320.c | 191 +++
> 3 files changed, 200 insertions(+)
> create mode 100644 drivers/extcon/extcon-usbc-tusb320.c
>
> diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
> index aac507bff135..af58ebca2bf6 100644
> --- a/drivers/extcon/Kconfig
> +++ b/drivers/extcon/Kconfig
> @@ -186,4 +186,12 @@ config EXTCON_USBC_CROS_EC
> Say Y here to enable USB Type C cable detection extcon support when
> using Chrome OS EC based USB Type-C ports.
>
> +config EXTCON_USBC_TUSB320
> + tristate "TI TUSB320 USB-C extcon support"
> + depends on I2C
> + select REGMAP_I2C
> + help
> + Say Y here to enable support for USB Type C cable detection extcon
> + support using a TUSB320.
> +
> endif
> diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
> index 52096fd8a216..fe10a1b7d18b 100644
> --- a/drivers/extcon/Makefile
> +++ b/drivers/extcon/Makefile
> @@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_RT8973A)+= extcon-rt8973a.o
> obj-$(CONFIG_EXTCON_SM5502) += extcon-sm5502.o
> obj-$(CONFIG_EXTCON_USB_GPIO)+= extcon-usb-gpio.o
> obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o
> +obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o
> diff --git a/drivers/extcon/extcon-usbc-tusb320.c
> b/drivers/extcon/extcon-usbc-tusb320.c
> new file mode 100644
> index ..93f1843ca89b
> --- /dev/null
> +++ b/drivers/extcon/extcon-usbc-tusb320.c
> @@ -0,0 +1,191 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * drivers/extcon/extcon-tusb320.c - TUSB320 extcon driver
> + *
> + * Copyright (C) 2020 National Instruments Corporation
> + * Author: Michael Auchter
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
irq.h doesn't be needed. Better to remove irq.h.
> +#include
> +#include
> +#include
> +
> +#define TUSB320_REG9 0x9
> +#define TUSB320_REG9_ATTACHED_STATE_SHIFT6
> +#define TUSB320_REG9_ATTACHED_STATE_MASK 0x3
> +#define TUSB320_REG9_CABLE_DIRECTION BIT(5)
> +#define TUSB320_REG9_INTERRUPT_STATUSBIT(4)
> +#define TUSB320_ATTACHED_STATE_NONE 0x0
> +#define TUSB320_ATTACHED_STATE_DFP 0x1
> +#define TUSB320_ATTACHED_STATE_UFP 0x2
> +#define TUSB320_ATTACHED_STATE_ACC 0x3
Above definition contain the 'space' for indentation.
Please edit it as following:
-#define TUSB320_ATTACHED_STATE_DFP 0x1
-#define TUSB320_ATTACHED_STATE_UFP 0x2
-#define TUSB320_ATTACHED_STATE_ACC 0x3
+#define TUSB320_ATTACHED_STATE_DFP 0x1
+#define TUSB320_ATTACHED_STATE_UFP 0x2
+#define TUSB320_ATTACHED_STATE_ACC 0x3
> +
> +struct tusb320_priv {
> + struct device *dev;
> + struct regmap *regmap;
> + struct extcon_dev *edev;
> +};
> +
> +static const char * const tusb_attached_states[] = {
> + [TUSB320_ATTACHED_STATE_NONE] = "not attached",
> + [TUSB320_ATTACHED_STATE_DFP] = "downstream facing port",
> + [TUSB320_ATTACHED_STATE_UFP] = "upstream facing port",
> + [TUSB320_ATTACHED_STATE_ACC] = "accessory",
> +};
> +
> +static const unsigned int tusb320_extcon_cable[] = {
> + EXTCON_USB,
> + EXTCON_USB_HOST,
> + EXTCON_NONE,
> +};
> +
> +static int tusb320_check_signature(struct tusb320_priv *priv)
> +{
> + static const char sig[] = { '\0', 'T', 'U', 'S', 'B', '3', '2', '0' };
> + unsigned val;
> + int i, ret;
> +
> + for (i = 0; i < sizeof(sig); i++) {
> + ret = regmap_read(priv->regmap, sizeof(sig) - 1 - i, );
> + if (ret < 0)
> + return ret;
> + if (val != sig[i]) {
> + dev_err(priv->dev, "signature mismatch!\n");
> + return -ENODEV;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static irqreturn_t tusb320_irq_handler(int irq, void *dev_id)
> +{
> + struct tusb320_priv *priv = dev_id;
> + int state, polarity;
> + unsigned reg;
> +
> + if (regmap_read(priv->regmap, TUSB320_REG9, )) {
> + dev_err(priv->dev, "error during i2c read!\n");
> + return IRQ_NONE;
> + }
> +
> + if (!(reg & TUSB320_REG9_INTERRUPT_STATUS))
> + return IRQ_NONE;
> +
> + state
Re: [PATCH] tracing: Check return value of __create_val_fields() before using its result
On Tue, 13 Oct 2020 15:48:52 -0400
Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> After having a typo for writing a histogram trigger.
>
> Wrote:
> echo 'hist:key=pid:ts=common_timestamp.usec' >
> events/sched/sched_waking/trigger
>
> Instead of:
> echo 'hist:key=pid:ts=common_timestamp.usecs' >
> events/sched/sched_waking/trigger
>
> and the following crash happened:
>
> BUG: kernel NULL pointer dereference, address: 0008
> #PF: supervisor read access in kernel mode
> #PF: error_code(0x) - not-present page
> PGD 0 P4D 0
> Oops: [#1] PREEMPT SMP PTI
> CPU: 4 PID: 1641 Comm: sh Not tainted 5.9.0-rc5-test+ #549
> Hardware name: Hewlett-Packard HP Compaq Pro 6300 SFF/339A, BIOS K01 v03.03
> 07/14/2016
> RIP: 0010:event_hist_trigger_func+0x70b/0x1ee0
> Code: 24 08 89 d5 49 89 cc e9 8c 00 00 00 4c 89 f2 41 b9 00 10 00 00 4c 89
> e1 44 89 ee 4c 89 ff e8 dc d3 ff ff 45 89 ea 4b 8b 14 d7 42 08 04 74 17
> 41 8b 8f c0 00 00 00 8d 71 01 41 89 b7 c0 00 00
> RSP: 0018:959213d53db0 EFLAGS: 00010202
> RAX: ffea RBX: RCX: 00084c04
> RDX: RSI: df7326aefebd174c RDI: 00031080
> RBP: 0002 R08: 0001 R09: 0001
> R10: 0001 R11: 0046 R12: 959211dcf690
> R13: 0001 R14: 95925a36e370 R15: 959251c89800
> FS: 7fb9ea934740() GS:95925ab0() knlGS:
> CS: 0010 DS: ES: CR0: 80050033
> CR2: 0008 CR3: c976c005 CR4: 001706e0
> Call Trace:
> ? trigger_process_regex+0x78/0x110
> trigger_process_regex+0xc5/0x110
> event_trigger_write+0x71/0xd0
> vfs_write+0xca/0x210
> ksys_write+0x70/0xf0
> do_syscall_64+0x33/0x40
> entry_SYSCALL_64_after_hwframe+0x44/0xa9
> RIP: 0033:0x7fb9eaa29487
> Code: 64 89 02 48 c7 c0 ff ff ff ff eb bb 0f 1f 80 00 00 00 00 f3 0f 1e fa
> 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff
> 77 51 c3 48 83 ec 28 48 89 54 24 18 48 89 74 24
>
> This was caused by accessing the hlist_data fields after the call to
> __create_val_fields() without checking if the creation succeed.
>
This looks good to me.
Reviewed-by: Masami Hiramatsu
Thank you,
> Fixes: 63a1e5de3006 ("tracing: Save normal string variables")
> Signed-off-by: Steven Rostedt (VMware)
> ---
> kernel/trace/trace_events_hist.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/kernel/trace/trace_events_hist.c
> b/kernel/trace/trace_events_hist.c
> index c74a7d157306..96c3f86b81c5 100644
> --- a/kernel/trace/trace_events_hist.c
> +++ b/kernel/trace/trace_events_hist.c
> @@ -3687,7 +3687,7 @@ static int create_var_field(struct hist_trigger_data
> *hist_data,
>
> ret = __create_val_field(hist_data, val_idx, file, var_name, expr_str,
> flags);
>
> - if (hist_data->fields[val_idx]->flags & HIST_FIELD_FL_STRING)
> + if (!ret && hist_data->fields[val_idx]->flags & HIST_FIELD_FL_STRING)
> hist_data->fields[val_idx]->var_str_idx =
> hist_data->n_var_str++;
>
> return ret;
> --
> 2.25.4
>
--
Masami Hiramatsu
Re: [PATCH v3 04/15] phy: tegra: xusb: tegra210: Do not reset UPHY PLL
Asserting reset to a PLL when it's managed by hardware power sequencer would break sequencer's state machine. Putting PLL in reset doesn't save some extra power. Thanks for review. JC On 9/28/20 9:06 PM, Thierry Reding wrote: > On Wed, Sep 09, 2020 at 04:10:30PM +0800, JC Kuo wrote: >> Once UPHY PLL hardware power sequencer is enabled, do not assert >> reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken. >> This commit removes reset_control_assert(pcie->rst) and >> reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure. >> >> Signed-off-by: JC Kuo >> --- >> v3: >>new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210" >> >> drivers/phy/tegra/xusb-tegra210.c | 2 -- >> 1 file changed, 2 deletions(-) >> >> diff --git a/drivers/phy/tegra/xusb-tegra210.c >> b/drivers/phy/tegra/xusb-tegra210.c >> index f06e7bc7a51b..ef4bbcbed60b 100644 >> --- a/drivers/phy/tegra/xusb-tegra210.c >> +++ b/drivers/phy/tegra/xusb-tegra210.c >> @@ -504,7 +504,6 @@ static void tegra210_pex_uphy_disable(struct >> tegra_xusb_padctl *padctl) >> if (--pcie->enable > 0) >> goto unlock; >> >> -reset_control_assert(pcie->rst); >> clk_disable_unprepare(pcie->pll); >> >> unlock: >> @@ -746,7 +745,6 @@ static void tegra210_sata_uphy_disable(struct >> tegra_xusb_padctl *padctl) >> if (--sata->enable > 0) >> goto unlock; >> >> -reset_control_assert(sata->rst); >> clk_disable_unprepare(sata->pll); >> >> unlock: > > Does this mean that we can no longer reset these PLLs anymore? Is that > safe? Would we ever need to reset them for recovery or similar? For > power saving, is disabling the clock enough, or could we save some extra > power by putting the PLLs into reset? > > Thierry >
Re: [PATCH] powerpc/features: Remove CPU_FTR_NODSISRALIGN
On 10/13/20 3:45 PM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 13/10/2020 à 09:23, Aneesh Kumar K.V a écrit :
Christophe Leroy writes:
CPU_FTR_NODSISRALIGN has not been used since
commit 31bfdb036f12 ("powerpc: Use instruction emulation
infrastructure to handle alignment faults")
Remove it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/cputable.h | 22 ++
arch/powerpc/kernel/dt_cpu_ftrs.c | 8
arch/powerpc/kernel/prom.c | 2 +-
3 files changed, 11 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 1098863e17ee..c598961d9f15 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -273,13 +273,6 @@ static int __init feat_enable_idle_nap(struct
dt_cpu_feature *f)
return 1;
}
-static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
-{
- cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
-
- return 1;
-}
-
static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
{
u64 lpcr;
@@ -641,7 +634,6 @@ static struct dt_cpu_feature_match __initdata
{"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
{"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
{"idle-nap", feat_enable_idle_nap, 0},
- {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
Rather than removing it entirely, I'd rather we left a comment, so that
it's obvious that we are ignoring that feature on purpose, not because
we forget about it.
eg:
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index f204ad79b6b5..45cb7e59bd13 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -640,7 +640,7 @@ static struct dt_cpu_feature_match __initdata
{"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
{"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
{"idle-nap", feat_enable_idle_nap, 0},
- {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
+ // "alignment-interrupt-dsisr" ignored
{"idle-stop", feat_enable_idle_stop, 0},
{"machine-check-power8", feat_enable_mce_power8, 0},
{"performance-monitor-power8", feat_enable_pmu_power8, 0},
why not do it as
static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
{
/* This feature should not be enabled */
#ifdef DEBUG
WARN(1);
#endif
return 1;
}
-aneesh
[PATCH v1 5/6] i2c: iproc: handle master read request
On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
>
> - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> - /* Start of SMBUS for Master Read */
> + I2C_SLAVE_WRITE_REQUESTED, _data);
> + iproc_i2c->rx_start_rcvd = true;
> + iproc_i2c->slave_read_complete = false;
> + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> +iproc_i2c->rx_start_rcvd) {
> + /* Middle of SMBUS Master write */
> i2c_slave_event(iproc_i2c->slave,
> - I2C_SLAVE_READ_REQUESTED, );
> - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> + I2C_SLAVE_WRITE_RECEIVED, _data);
> + } else if (rx_status == I2C_SLAVE_RX_END &&
> +iproc_i2c->rx_start_rcvd) {
> + /* End of SMBUS Master write */
> + if (iproc_i2c->slave_rx_only)
> + i2c_slave_event(iproc_i2c->slave,
> + I2C_SLAVE_WRITE_RECEIVED,
> + _data);
> +
> + i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
> + _data);
> + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> + iproc_i2c->rx_start_rcvd = false;
> + iproc_i2c->slave_read_complete = true;
> + break;
> + }
>
> - val = BIT(S_CMD_START_BUSY_SHIFT);
> - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> + rx_bytes++;
rx_bytes should be incremented only along with I2C_SLAVE_WRITE_RECEIVED event?
>
> +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
> + u32 status)
> +{
> + u32 val;
> + u8 value;
> +
> + /*
> + * Slave events in case of master-write, master-write-read and,
> + * master-read
> + *
> + * Master-write : only IS_S_RX_EVENT_SHIFT event
> + * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + *events
> + * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + *events or only IS_S_RD_EVENT_SHIFT
> + */
> + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> + /* disable slave interrupts */
> + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> + val &= ~iproc_i2c->slave_int_mask;
> + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> +
> + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> + /* Master-write-read request */
> + iproc_i2c->slave_rx_only = false;
> + else
> + /* Master-write request only */
> + iproc_i2c->slave_rx_only = true;
> +
> + /* schedule tasklet to read data later */
> + tasklet_schedule(_i2c->slave_rx_tasklet);
> +
> + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> + BIT(IS_S_RX_EVENT_SHIFT));
>
Both tasklet and isr are writing to status (IS_OFFSET) reg.
The tasklet seems to be batching up rx fifo reads because of time-sensitive
Master-write-read transaction? Linux I2C framework is byte interface anyway.
Can the need to batch reads be avoided by setting slave rx threshold for
interrupt (S_FIFO_RX_THLD) to 1-byte?
Also, wouldn't tasklets be susceptible to other interrupts? If fifo reads
have to be batched up, can it be changed to threaded irq?
[PATCH v7 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei
Reviewed-by: Nicolas Boichat
---
drivers/mmc/host/mtk-sd.c | 74 +--
1 file changed, 56 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index a704745e5882..c7df7510f120 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -35,6 +35,7 @@
#include "cqhci.h"
#define MAX_BD_NUM 1024
+#define MSDC_NR_CLOCKS 3
/*--*/
/* Common Definition*/
@@ -425,6 +426,8 @@ struct msdc_host {
struct clk *h_clk; /* msdc h_clk */
struct clk *bus_clk;/* bus clock which used to access register */
struct clk *src_clk_cg; /* msdc source clock control gate */
+ struct clk *sys_clk_cg; /* msdc subsys clock control gate */
+ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
unsigned char timing;
@@ -784,6 +787,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host,
u64 ns, u64 clks)
static void msdc_gate_clock(struct msdc_host *host)
{
+ clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
clk_disable_unprepare(host->src_clk_cg);
clk_disable_unprepare(host->src_clk);
clk_disable_unprepare(host->bus_clk);
@@ -792,10 +796,18 @@ static void msdc_gate_clock(struct msdc_host *host)
static void msdc_ungate_clock(struct msdc_host *host)
{
+ int ret;
+
clk_prepare_enable(host->h_clk);
clk_prepare_enable(host->bus_clk);
clk_prepare_enable(host->src_clk);
clk_prepare_enable(host->src_clk_cg);
+ ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
+ if (ret) {
+ dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
+ return;
+ }
+
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
}
@@ -2366,6 +2378,48 @@ static void msdc_of_property_parse(struct
platform_device *pdev,
host->cqhci = false;
}
+static int msdc_of_clock_parse(struct platform_device *pdev,
+ struct msdc_host *host)
+{
+ int ret;
+
+ host->src_clk = devm_clk_get(>dev, "source");
+ if (IS_ERR(host->src_clk))
+ return PTR_ERR(host->src_clk);
+
+ host->h_clk = devm_clk_get(>dev, "hclk");
+ if (IS_ERR(host->h_clk))
+ return PTR_ERR(host->h_clk);
+
+ host->bus_clk = devm_clk_get_optional(>dev, "bus_clk");
+ if (IS_ERR(host->bus_clk))
+ host->bus_clk = NULL;
+
+ /*source clock control gate is optional clock*/
+ host->src_clk_cg = devm_clk_get_optional(>dev, "source_cg");
+ if (IS_ERR(host->src_clk_cg))
+ host->src_clk_cg = NULL;
+
+ host->sys_clk_cg = devm_clk_get_optional(>dev, "sys_cg");
+ if (IS_ERR(host->sys_clk_cg))
+ host->sys_clk_cg = NULL;
+
+ /* If present, always enable for this clock gate */
+ clk_prepare_enable(host->sys_clk_cg);
+
+ host->bulk_clks[0].id = "pclk_cg";
+ host->bulk_clks[1].id = "axi_cg";
+ host->bulk_clks[2].id = "ahb_cg";
+ ret = devm_clk_bulk_get_optional(>dev, MSDC_NR_CLOCKS,
+host->bulk_clks);
+ if (ret) {
+ dev_err(>dev, "Cannot get pclk/axi/ahb clock gates\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int msdc_drv_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
@@ -2405,25 +2459,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
if (ret)
goto host_free;
- host->src_clk = devm_clk_get(>dev, "source");
- if (IS_ERR(host->src_clk)) {
- ret = PTR_ERR(host->src_clk);
- goto host_free;
- }
-
- host->h_clk = devm_clk_get(>dev, "hclk");
- if (IS_ERR(host->h_clk)) {
- ret = PTR_ERR(host->h_clk);
+ ret = msdc_of_clock_parse(pdev, host);
+ if (ret)
goto host_free;
- }
-
- host->bus_clk = devm_clk_get(>dev, "bus_clk");
- if (IS_ERR(host->bus_clk))
- host->bus_clk = NULL;
- /*source clock control gate is optional clock*/
- host->src_clk_cg = devm_clk_get(>dev, "source_cg");
- if (IS_ERR(host->src_clk_cg))
- host->src_clk_cg = NULL;
host->reset = devm_reset_control_get_optional_exclusive(>dev,
"hrst");
--
2.18.0
[PATCH v7 3/4] arm64: dts: mt8192: add mmc device node
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 34
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837fa698..a4279fa87c2b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -27,3 +28,91 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <_pins_default>;
+ pinctrl-1 = <_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <_vemc_1_ldo_reg>;
+ vqmmc-supply = <_vufs_ldo_reg>;
+ assigned-clocks = < CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = < CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ input-enable;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = ;
+ drive-strenth = <3>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = ;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
+ pins_cmd_dat {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ input-enable;
+ drive-strenth = <4>;
+ mediatek,pull-up-adv = <1>;
+ };
+
+ pins_clk {
+ pinmux = ;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_ds {
+ pinmux = ;
+ drive-strenth = <4>;
+ mediatek,pull-down-adv = <2>;
+ };
+
+ pins_rst {
+ pinmux = ;
+ drive-strenth = <3>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index faea0d97c2a9..de3d10c0eeef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -760,6 +760,40 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11f6 {
+ compatible = "mediatek,mt8192-mmc",
"mediatek,mt8183-mmc";
+ reg = <0 0x11f6 0 0x1000>,
+ <0 0x11f5 0 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC50_0_SEL>,
+<_top CLK_MSDC_TOP_H_MST_0P>,
+<_top CLK_MSDC_TOP_SRC_0P>,
+<_top CLK_MSDC_TOP_P_CFG>,
+<_top CLK_MSDC_TOP_P_MSDC0>,
+<_top CLK_MSDC_TOP_AXI>,
+<_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f7 {
+ compatible = "mediatek,mt8192-mmc",
"mediatek,mt8183-mmc";
+ reg = <0 0x11f7 0 0x1000>,
+ <0 0x11c7 0 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC30_1_SEL>,
+<_top CLK_MSDC_TOP_H_MST_1P>,
+<_top CLK_MSDC_TOP_SRC_1P>,
+
[PATCH v7 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mmc/mtk-sd.txt| 75
.../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++
2 files changed, 165 insertions(+), 75 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
deleted file mode 100644
index 26a8f320a156..
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-* MTK MMC controller
-
-The MTK MSDC can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the msdc driver.
-
-Required properties:
-- compatible: value should be either of the following.
- "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
- "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
- "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
- "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
- "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
- "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
- "mediatek,mt7622-mmc": for MT7622 SoC
- "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- "mediatek,mt7620-mmc", for MT7621 SoC (and others)
-
-- reg: physical base address of the controller and length
-- interrupts: Should contain MSDC interrupt number
-- clocks: Should contain phandle for the clock feeding the MMC controller
-- clock-names: Should contain the following:
- "source" - source clock (required)
- "hclk" - HCLK which used for host (required)
- "source_cg" - independent source clock gate (required for MT2712)
- "bus_clk" - bus clock used for internal register access (required for
MT2712 MSDC0/3)
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin ctrl
-- pinctrl-1: should contain uhs mode pin ctrl
-- vmmc-supply: power to the Core
-- vqmmc-supply: power to the IO
-
-Optional properties:
-- assigned-clocks: PLL of the source clock
-- assigned-clock-parents: parent of source clock, used for HS400 mode to get
400Mhz source clock
-- hs400-ds-delay: HS400 DS delay setting
-- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
- If present,HS400 command responses are
sampled on rising edges.
- If not present,HS400 command responses
are sampled on falling edges.
-- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct
latch-ck to avoid data crc
-error caused by stop clock(fifo full)
-Valid range = [0:0x7]. if not present, default value is 0.
-applied to compatible "mediatek,mt2701-mmc".
-- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
-- reset-names: Should be "hrst".
-
-Examples:
-mmc0: mmc@1123 {
- compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
- reg = <0 0x1123 0 0x108>;
- interrupts = ;
- vmmc-supply = <_vemc_3v3_reg>;
- vqmmc-supply = <_vio18_reg>;
- clocks = < CLK_PERI_MSDC30_0>,
-< CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <_pins_default>;
- pinctrl-1 = <_pins_uhs>;
- assigned-clocks = < CLK_TOP_MSDC50_0_SEL>;
- assigned-clock-parents = < CLK_TOP_MSDCPLL_D2>;
- hs400-ds-delay = <0x14015>;
- mediatek,hs200-cmd-int-delay = <26>;
- mediatek,hs400-cmd-int-delay = <14>;
- mediatek,hs400-cmd-resp-sel-rising;
-};
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
new file mode 100644
index ..79905df75f1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTK MSDC Storage Host Controller Binding
+
+maintainers:
+ -
[PATCH v7 2/4] mmc: dt-bindings: add support for MT8192 SoC
MT8192 mmc host ip is compatible with MT8183. Add support for this. Signed-off-by: Wenbin Mei --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 79905df75f1d..030e3fdce492 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -29,26 +29,37 @@ properties: - items: - const: mediatek,mt7623-mmc - const: mediatek,mt2701-mmc + - items: +- const: mediatek,mt8192-mmc +- const: mediatek,mt8183-mmc clocks: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 -maxItems: 4 +maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). - description: independent source clock gate (required for MT2712). - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + - description: msdc subsys clock gate (required for MT8192). + - description: peripheral bus clock gate (required for MT8192). + - description: AXI bus clock gate (required for MT8192). + - description: AHB bus clock gate (required for MT8192). clock-names: minItems: 2 -maxItems: 4 +maxItems: 8 items: - const: source - const: hclk - const: source_cg - const: bus_clk + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg pinctrl-names: items: -- 2.18.0
[PATCH v7 0/4] Add mmc support for MT8192 SoC
Change in v7: 1)add "unevaluatedProperties" in mtk-sd.yaml 2)add Reviewed-by tag Change in v6: 1)use devm_clk_get function for required clocks Change in v5: 1)remove Reviewed-by tag 2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional for bulk clks Change in v4: 1)drop "vmmc" and "vqmmc" desciption in mtk-sd.yaml 2)add vmmq/vqmmc supplies and the pinctrls to required properties 3)change dbg level and exit this function 4)use devm_clk_get_optional instead of devm_clk_get function 5)remove else branch for sys_clk_cg Change in v3: 1)change maintainers name in mtk-sd.yaml 2)change "compatible" properties to enum type and sort it 3)drop these properties: "reg" and "interrupts" 4)add "maxItems" constraints on these properties: "vmmc-supply", "vqmmc-supply", "assigned-clocks", "assigned-clock-parents" 5)add "minimum" and "maximum" constraints on these properties: "mediatek,hs400-cmd-int-delay", "mediatek,latch-ck", "hs400-ds-delay", "mediatek,hs200-cmd-int-delay" Change in v2: Convert mtk-sd to json-schema Wenbin Mei (4): dt-bindings: mmc: Convert mtk-sd to json-schema mmc: dt-bindings: add support for MT8192 SoC arm64: dts: mt8192: add mmc device node mmc: mediatek: Add subsys clock control for MT8192 msdc --- This patch depends on [v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile [v3,1/9] dt-bindings: ARM: Mediatek: Document bindings for MT8192 BSP [v3,6/9] clk: mediatek: Add dt-bindings for MT8192 clocks [v3,9/9] clk: mediatek: Add MT8192 clock support [v3,1/3] dt-bindings: pinctrl: mt8192: add pinctrl file [v3,2/3] dt-bindings: pinctrl: mt8192: add binding document [v3,3/3] pinctrl: add pinctrl driver on mt8192 [v2,1/4] soc: mediatek: pwrap: use BIT() macro [v2,2/4] soc: mediatek: pwrap: add arbiter capability [v2,3/4] dt-bindings: mediatek: add compatible for MT6873/8192 pwrap [v2,4/4] soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs [2/8] dt-bindings: mfd: Add compatible for the MediaTek MT6359 PMIC [3/8] dt-bindings: regulator: Add document for MT6359 regulator [4/8] mfd: Add support for the MediaTek MT6359 PMIC [5/8] regulator: mt6359: Add support for MT6359 regulator [7/8] regulator: mt6359: Add support for MT6359P regulator [8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes Please also accept this patch together with [1][2][3][4][5] to avoid build and dt binding check error. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=332621 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=342593 [3] https://patchwork.kernel.org/project/linux-mediatek/list/?series=330017 [4] https://patchwork.kernel.org/project/linux-mediatek/list/?series=322937 [5] https://patchwork.kernel.org/project/linux-mediatek/list/?series=323171 --- .../devicetree/bindings/mmc/mtk-sd.txt| 75 .../devicetree/bindings/mmc/mtk-sd.yaml | 176 ++ arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 drivers/mmc/host/mtk-sd.c | 74 ++-- 5 files changed, 355 insertions(+), 93 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml -- 2.18.0
Re: [PATCH 1/5] clk: ingenic: Use to_clk_info() macro for all clocks
Quoting Paul Cercueil (2020-09-02 18:50:44) > The to_clk_info() previously had a BUG_ON() to check that it was only > called for PLL clocks. Yet, all the other clocks were doing the exact > same thing the macro does, in-line. > > Move the to_clk_info() macro to the top of the file, remove the > hardcoded BUG_ON(), and use it everywhere it makes sense. > > Signed-off-by: Paul Cercueil > --- Applied to clk-next
Re: [PATCH 2/5] clk: ingenic: Use readl_poll_timeout instead of custom loop
Quoting Paul Cercueil (2020-09-02 18:50:45) > Use the readl_poll_timeout() function instead of rolling our own > busy-wait loops. This makes the code simpler. > > Signed-off-by: Paul Cercueil > --- Applied to clk-next
Re: [PATCH 4/5] clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
Quoting Paul Cercueil (2020-09-02 18:50:47) > The custom clocks have custom functions to round, get or set their rate. > Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag. > > Signed-off-by: Paul Cercueil > --- Applied to clk-next
Re: [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
Quoting Paul Cercueil (2020-09-02 18:50:46) > CLK_SET_RATE_GATE means that the clock must be gated when being > reclocked. This is not the case for the PLLs in Ingenic SoCs. > > Signed-off-by: Paul Cercueil > --- Applied to clk-next
Re: [PATCH 5/5] clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Quoting Paul Cercueil (2020-09-02 18:50:48) > Clocks that don't have a divider are in our case all marked with the > CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation > should modify the value pointed to by parent_rate, in order to propagate > the rate change to the parent, as explained in the documentation of > clk_set_rate(). > > Signed-off-by: Paul Cercueil > --- Applied to clk-next
Re: [PATCH] clk: bcm2835: add missing release if devm_clk_hw_register fails
Quoting Navid Emamdoost (2020-08-09 16:11:58) > In the implementation of bcm2835_register_pll(), the allocated pll is > leaked if devm_clk_hw_register() fails to register hw. Release pll if > devm_clk_hw_register() fails. > > Signed-off-by: Navid Emamdoost > --- Applied to clk-next
Re: [PATCH v2 3/3] clk: at91: clk-sam9x60-pll: remove unused variable
Quoting Claudiu Beznea (2020-08-24 23:59:11)
> Fix variable set but not used compilation warning.
>
> Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls
> with multiple outputs")
> Reported-by: kernel test robot
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Re: [PATCH v2 1/3] clk: at91: remove the checking of parent_name
Quoting Claudiu Beznea (2020-08-24 23:59:09)
> There is no need to check parent_name variable while assigning it to
> init.parent_names. parent_name variable is already checked at
> the beginning of at91_clk_register_peripheral() function.
>
> Fixes: 6114067e437eb ("clk: at91: add PMC peripheral clocks")
> Signed-off-by: Claudiu Beznea
> Reviewed-by: Alexandre Belloni
> ---
Applied to clk-next
Re: [PATCH v2 2/3] clk: at91: clk-main: update key before writing AT91_CKGR_MOR
Quoting Claudiu Beznea (2020-08-24 23:59:10)
> SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
> Main Oscillator Register) that writing any value other than
> 0x37 on KEY field aborts the write operation. Use the key when
> selecting main clock parent.
>
> Fixes: 27cb1c2083373 ("clk: at91: rework main clk implementation")
> Signed-off-by: Claudiu Beznea
> Reviewed-by: Alexandre Belloni
> ---
Applied to clk-next
Re: [PATCH] clk: clk-prima2: fix return value check in prima2_clk_init()
Quoting Xu Wang (2020-09-20 20:45:22) > In case of error, the function clk_register() returns ERR_PTR() > and never returns NULL. The NULL test in the return value check > should be replaced with IS_ERR(). > > Signed-off-by: Xu Wang > --- Applied to clk-next
Re: [PATCH] clk: mmp2: Fix the display clock divider base
Quoting Lubomir Rintel (2020-09-25 16:39:14) > The LCD clock dividers are apparently based on one. No datasheet, > determined empirically, but seems to be confirmed by line 19 of lcd.fth in > OLPC laptop's Open Firmware [1]: > >h# 0700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz > > [1] > https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth > > Signed-off-by: Lubomir Rintel > --- Applied to clk-next
Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
Quoting Ryan Chen (2020-09-28 00:01:08) > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are > default for Host SuperIO UART device, eSPI clk for Host eSPI bus access > eSPI slave channel, those clks can't be disable should keep default, > otherwise will affect Host side access SuperIO and SPI slave device. > > Signed-off-by: Ryan Chen > --- Is there resolution on this thread?
Re: [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
Quoting Qiang Zhao (2020-09-15 20:03:10) > From: Zhao Qiang > > On LS2088A, Watchdog need clk divided by 32, > so modify MAX_PLL_DIV to 32 > > Signed-off-by: Zhao Qiang > --- Applied to clk-next
Re: [PATCH] clk: baikal-t1: Mark Ethernet PLL as critical
Quoting Serge Semin (2020-09-20 04:03:35) > We've discovered that disabling the so called Ethernet PLL causes reset of > the devices consuming its outgoing clock. The resets happen automatically > even if each underlying clock gate is turned off. Due to that we can't > disable the Ethernet PLL until the kernel is prepared for the corresponding > resets. So for now just mark the PLL clock provider as critical. > > Signed-off-by: Serge Semin > Cc: Alexey Malahov > Cc: linux-m...@vger.kernel.org > --- Applied to clk-next
[PATCH stable-5.4] backport enospc issues during balance
Patch 1 is a preparatory patch to reduce conflicts. Patch 2 fixes balance failure due to ENOSPC in btrfs/156 on arm64 systems with pagesize=64k. Minor conflicts in fs/btrfs/block-group.c are resolved. Thanks. Josef Bacik (2): btrfs: don't pass system_chunk into can_overcommit btrfs: take overcommit into account in inc_block_group_ro fs/btrfs/block-group.c | 38 ++-- fs/btrfs/space-info.c | 50 +- fs/btrfs/space-info.h | 3 +++ 3 files changed, 49 insertions(+), 42 deletions(-) -- 2.18.4
Re: [PATCH 1/2] clk: axi-clkgen: Add support for fractional dividers
Quoting Alexandru Ardelean (2020-10-01 01:59:47) > From: Lars-Peter Clausen > > The axi-clkgen has (optional) fractional dividers on the output clock > divider and feedback clock divider path. Utilizing the fractional dividers > allows for a better resolution of the output clock, being able to > synthesize more frequencies. > > Rework the driver support to support the fractional register fields, both > for setting a new rate as well as reading back the current rate from the > hardware. > > For setting the rate if no perfect divider settings were found in > non-fractional mode try again in fractional mode and see if better settings > can be found. This appears to be the recommended mode of operation. > > Signed-off-by: Lars-Peter Clausen > Signed-off-by: Alexandru Ardelean > --- Applied to clk-next
Re: [PATCH 2/2] clk: axi-clkgen: Set power bits for fractional mode
Quoting Alexandru Ardelean (2020-10-01 01:59:48) > From: Lars-Peter Clausen > > Using the fractional dividers requires some additional power bits to be > set. > > The fractional power bits are not documented and the current heuristic > for setting them seems be insufficient for some cases. Just always set all > the fractional power bits when in fractional mode. > > Signed-off-by: Lars-Peter Clausen > Signed-off-by: Alexandru Ardelean > --- Applied to clk-next
[PATCH stable-5.4 1/2] btrfs: don't pass system_chunk into can_overcommit
From: Josef Bacik
commit 9f246926b4d5db4c5e8c78e4897757de26c95be6 upstream
We have the space_info, we can just check its flags to see if it's the
system chunk space info.
Reviewed-by: Nikolay Borisov
Reviewed-by: Qu Wenruo
Reviewed-by: Johannes Thumshirn
Signed-off-by: Josef Bacik
Reviewed-by: David Sterba
Signed-off-by: David Sterba
Signed-off-by: Anand Jain
---
fs/btrfs/space-info.c | 42 +++---
1 file changed, 15 insertions(+), 27 deletions(-)
diff --git a/fs/btrfs/space-info.c b/fs/btrfs/space-info.c
index 6f484f0d347e..e19e538d05f9 100644
--- a/fs/btrfs/space-info.c
+++ b/fs/btrfs/space-info.c
@@ -162,8 +162,7 @@ static inline u64 calc_global_rsv_need_space(struct
btrfs_block_rsv *global)
static int can_overcommit(struct btrfs_fs_info *fs_info,
struct btrfs_space_info *space_info, u64 bytes,
- enum btrfs_reserve_flush_enum flush,
- bool system_chunk)
+ enum btrfs_reserve_flush_enum flush)
{
u64 profile;
u64 avail;
@@ -174,7 +173,7 @@ static int can_overcommit(struct btrfs_fs_info *fs_info,
if (space_info->flags & BTRFS_BLOCK_GROUP_DATA)
return 0;
- if (system_chunk)
+ if (space_info->flags & BTRFS_BLOCK_GROUP_SYSTEM)
profile = btrfs_system_alloc_profile(fs_info);
else
profile = btrfs_metadata_alloc_profile(fs_info);
@@ -228,8 +227,7 @@ void btrfs_try_granting_tickets(struct btrfs_fs_info
*fs_info,
/* Check and see if our ticket can be satisified now. */
if ((used + ticket->bytes <= space_info->total_bytes) ||
- can_overcommit(fs_info, space_info, ticket->bytes, flush,
- false)) {
+ can_overcommit(fs_info, space_info, ticket->bytes, flush)) {
btrfs_space_info_update_bytes_may_use(fs_info,
space_info,
ticket->bytes);
@@ -634,8 +632,7 @@ static void flush_space(struct btrfs_fs_info *fs_info,
static inline u64
btrfs_calc_reclaim_metadata_size(struct btrfs_fs_info *fs_info,
-struct btrfs_space_info *space_info,
-bool system_chunk)
+struct btrfs_space_info *space_info)
{
struct reserve_ticket *ticket;
u64 used;
@@ -651,13 +648,12 @@ btrfs_calc_reclaim_metadata_size(struct btrfs_fs_info
*fs_info,
to_reclaim = min_t(u64, num_online_cpus() * SZ_1M, SZ_16M);
if (can_overcommit(fs_info, space_info, to_reclaim,
- BTRFS_RESERVE_FLUSH_ALL, system_chunk))
+ BTRFS_RESERVE_FLUSH_ALL))
return 0;
used = btrfs_space_info_used(space_info, true);
- if (can_overcommit(fs_info, space_info, SZ_1M,
- BTRFS_RESERVE_FLUSH_ALL, system_chunk))
+ if (can_overcommit(fs_info, space_info, SZ_1M, BTRFS_RESERVE_FLUSH_ALL))
expected = div_factor_fine(space_info->total_bytes, 95);
else
expected = div_factor_fine(space_info->total_bytes, 90);
@@ -673,7 +669,7 @@ btrfs_calc_reclaim_metadata_size(struct btrfs_fs_info
*fs_info,
static inline int need_do_async_reclaim(struct btrfs_fs_info *fs_info,
struct btrfs_space_info *space_info,
- u64 used, bool system_chunk)
+ u64 used)
{
u64 thresh = div_factor_fine(space_info->total_bytes, 98);
@@ -681,8 +677,7 @@ static inline int need_do_async_reclaim(struct
btrfs_fs_info *fs_info,
if ((space_info->bytes_used + space_info->bytes_reserved) >= thresh)
return 0;
- if (!btrfs_calc_reclaim_metadata_size(fs_info, space_info,
- system_chunk))
+ if (!btrfs_calc_reclaim_metadata_size(fs_info, space_info))
return 0;
return (used >= thresh && !btrfs_fs_closing(fs_info) &&
@@ -805,8 +800,7 @@ static void btrfs_async_reclaim_metadata_space(struct
work_struct *work)
space_info = btrfs_find_space_info(fs_info, BTRFS_BLOCK_GROUP_METADATA);
spin_lock(_info->lock);
- to_reclaim = btrfs_calc_reclaim_metadata_size(fs_info, space_info,
- false);
+ to_reclaim = btrfs_calc_reclaim_metadata_size(fs_info, space_info);
if (!to_reclaim) {
space_info->flush = 0;
spin_unlock(_info->lock);
@@ -825,8 +819,7 @@ static void btrfs_async_reclaim_metadata_space(struct
work_struct *work)
return;
}
to_reclaim =
[PATCH stable-5.4 2/2] btrfs: take overcommit into account in inc_block_group_ro
From: Josef Bacik
commit a30a3d2067536cbcce26c055e70cc3a6ae4fd45c upstream
inc_block_group_ro does a calculation to see if we have enough room left
over if we mark this block group as read only in order to see if it's ok
to mark the block group as read only.
The problem is this calculation _only_ works for data, where our used is
always less than our total. For metadata we will overcommit, so this
will almost always fail for metadata.
Fix this by exporting btrfs_can_overcommit, and then see if we have
enough space to remove the remaining free space in the block group we
are trying to mark read only. If we do then we can mark this block
group as read only.
Reviewed-by: Qu Wenruo
Signed-off-by: Josef Bacik
Reviewed-by: David Sterba
Signed-off-by: David Sterba
Signed-off-by: Anand Jain
---
fs/btrfs/block-group.c | 38 ++
fs/btrfs/space-info.c | 18 ++
fs/btrfs/space-info.h | 3 +++
3 files changed, 39 insertions(+), 20 deletions(-)
diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c
index b167649f5f5d..ace49a999ece 100644
--- a/fs/btrfs/block-group.c
+++ b/fs/btrfs/block-group.c
@@ -1186,7 +1186,6 @@ static int inc_block_group_ro(struct
btrfs_block_group_cache *cache, int force)
{
struct btrfs_space_info *sinfo = cache->space_info;
u64 num_bytes;
- u64 sinfo_used;
u64 min_allocable_bytes;
int ret = -ENOSPC;
@@ -1213,20 +1212,38 @@ static int inc_block_group_ro(struct
btrfs_block_group_cache *cache, int force)
num_bytes = cache->key.offset - cache->reserved - cache->pinned -
cache->bytes_super - btrfs_block_group_used(>item);
- sinfo_used = btrfs_space_info_used(sinfo, true);
/*
-* sinfo_used + num_bytes should always <= sinfo->total_bytes.
-*
-* Here we make sure if we mark this bg RO, we still have enough
-* free space as buffer (if min_allocable_bytes is not 0).
+* Data never overcommits, even in mixed mode, so do just the straight
+* check of left over space in how much we have allocated.
*/
- if (sinfo_used + num_bytes + min_allocable_bytes <=
- sinfo->total_bytes) {
+ if (force) {
+ ret = 0;
+ } else if (sinfo->flags & BTRFS_BLOCK_GROUP_DATA) {
+ u64 sinfo_used = btrfs_space_info_used(sinfo, true);
+
+ /*
+* Here we make sure if we mark this bg RO, we still have enough
+* free space as buffer.
+*/
+ if (sinfo_used + num_bytes <= sinfo->total_bytes)
+ ret = 0;
+ } else {
+ /*
+* We overcommit metadata, so we need to do the
+* btrfs_can_overcommit check here, and we need to pass in
+* BTRFS_RESERVE_NO_FLUSH to give ourselves the most amount of
+* leeway to allow us to mark this block group as read only.
+*/
+ if (btrfs_can_overcommit(cache->fs_info, sinfo, num_bytes,
+BTRFS_RESERVE_NO_FLUSH))
+ ret = 0;
+ }
+
+ if (!ret) {
sinfo->bytes_readonly += num_bytes;
cache->ro++;
list_add_tail(>ro_list, >ro_bgs);
- ret = 0;
}
out:
spin_unlock(>lock);
@@ -1235,9 +1252,6 @@ static int inc_block_group_ro(struct
btrfs_block_group_cache *cache, int force)
btrfs_info(cache->fs_info,
"unable to make block group %llu ro",
cache->key.objectid);
- btrfs_info(cache->fs_info,
- "sinfo_used=%llu bg_num_bytes=%llu min_allocable=%llu",
- sinfo_used, num_bytes, min_allocable_bytes);
btrfs_dump_space_info(cache->fs_info, cache->space_info, 0, 0);
}
return ret;
diff --git a/fs/btrfs/space-info.c b/fs/btrfs/space-info.c
index e19e538d05f9..90500b6c41fc 100644
--- a/fs/btrfs/space-info.c
+++ b/fs/btrfs/space-info.c
@@ -160,9 +160,9 @@ static inline u64 calc_global_rsv_need_space(struct
btrfs_block_rsv *global)
return (global->size << 1);
}
-static int can_overcommit(struct btrfs_fs_info *fs_info,
- struct btrfs_space_info *space_info, u64 bytes,
- enum btrfs_reserve_flush_enum flush)
+int btrfs_can_overcommit(struct btrfs_fs_info *fs_info,
+struct btrfs_space_info *space_info, u64 bytes,
+enum btrfs_reserve_flush_enum flush)
{
u64 profile;
u64 avail;
@@ -227,7 +227,8 @@ void btrfs_try_granting_tickets(struct btrfs_fs_info
*fs_info,
/* Check and see if our ticket can be satisified now. */
if ((used + ticket->bytes <= space_info->total_bytes) ||
- can_overcommit(fs_info,
Re: [PATCH 1/2] soc: samsung: exynos-pmu: instantiate clkout driver as MFD
Quoting Krzysztof Kozlowski (2020-10-01 09:56:45) > The Exynos clock output (clkout) driver uses same register address space > (Power Management Unit address space) as Exynos PMU driver and same set > of compatibles. It was modeled as clock provider instantiated with > CLK_OF_DECLARE_DRIVE(). > > This however brings ordering problems and lack of probe deferral, > therefore clkout driver should be converted to a regular module and > instantiated as a child of PMU driver to be able to use existing > compatibles and address space. > > Signed-off-by: Krzysztof Kozlowski > --- Reviewed-by: Stephen Boyd
Re: [PATCH 2/2] clk: samsung: exynos-clkout: convert to module driver
Quoting Krzysztof Kozlowski (2020-10-01 09:56:46)
> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c
> b/drivers/clk/samsung/clk-exynos-clkout.c
> index 34ccb1d23bc3..68af082d4716 100644
> --- a/drivers/clk/samsung/clk-exynos-clkout.c
> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
> @@ -28,41 +31,103 @@ struct exynos_clkout {
[...]
> + if (!match) {
> + dev_err(dev, "cannot match parent device\n");
> + return -EINVAL;
> + }
> + variant = match->data;
> +
> + *mux_mask = variant->mux_mask;
> + dev_err(dev, "MATCH: %x\n", variant->mux_mask);
Is this a debug print?
> +
> + return 0;
> +}
>
[PATCH v4 0/5] clk: rockchip: Support for some new features
1. Support for some new features 2. fix up some error Chang in V4: [PATCH v3 1/5] : Update the commit message. [PATCH v3 2/5] : Update the commit message. Chang in V3: [PATCH v2 3/6] : It's been merged So rebased and resubmit. Chang in V2: [PATCH v2 5/6] : fix up the Register error, and add delay. Elaine Zhang (5): clk: rockchip: Add supprot to limit input rate for fractional divider clk: rockchip: fix up the frac clk get rate error clk: rockchip: add a clock-type for muxes based in the pmugrf clk: rockchip: add pll up and down when change pll freq clk: rockchip: support pll setting by auto drivers/clk/rockchip/clk-pll.c| 236 -- drivers/clk/rockchip/clk-px30.c | 29 ++-- drivers/clk/rockchip/clk-rk3036.c | 13 +- drivers/clk/rockchip/clk-rk3128.c | 15 +- drivers/clk/rockchip/clk-rk3188.c | 24 +-- drivers/clk/rockchip/clk-rk3228.c | 18 ++- drivers/clk/rockchip/clk-rk3288.c | 19 ++- drivers/clk/rockchip/clk-rk3308.c | 46 +++--- drivers/clk/rockchip/clk-rk3328.c | 17 ++- drivers/clk/rockchip/clk-rk3368.c | 17 ++- drivers/clk/rockchip/clk-rk3399.c | 32 ++-- drivers/clk/rockchip/clk-rv1108.c | 14 +- drivers/clk/rockchip/clk.c| 39 - drivers/clk/rockchip/clk.h| 27 +++- include/linux/clk-provider.h | 2 + 15 files changed, 422 insertions(+), 126 deletions(-) -- 2.17.1
[PATCH v4 2/5] clk: rockchip: fix up the frac clk get rate error
support fractional divider with one level and two level parent clock
.i.e:
normal fractional divider is:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /|
|mux|--[GATE]--[UART0]
|--/ |--[GATE]--[FRACDIV]--| /
|--/
but rk3399 uart is special:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--|--[GATE]--[DIV]---| \
---[NPLL]---| / ||
|mux|--[GATE]--[UART1]
|--/ ||--[GATE]--[FRACDIV]--| /
| |--/
|
| |--\
|--[GATE]--[DIV]---| \
||
|mux|--[GATE]--[UART2]
||--[GATE]--[FRACDIV]--| /
| |--/
|
| |--\
|--[GATE]--[DIV]---| \
|
|mux|--[GATE]--[UART3]
|--[GATE]--[FRACDIV]--| /
|--/
The special fractional divider, there are two levels of clock between FRACDIV
and PLL.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct
clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {
- pr_err("%s parent_rate(%ld) is low than rate(%ld)*20,
fractional div is not allowed\n",
- clk_hw_get_name(hw), *parent_rate, rate);
+ pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use
integer or half-div\n",
+ clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
--
2.17.1
[PATCH v4 5/5] clk: rockchip: support pll setting by auto
If setting freq is not support in rockchip_pll_rate_table,
It can calculate and set pll params by auto.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 215 ++---
1 file changed, 200 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 8adc6f54a605..e8ca86f5b7d1 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include "clk.h"
#define PLL_MODE_MASK 0x3
@@ -47,6 +48,198 @@ struct rockchip_clk_pll {
#define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
+#define MHZ(1000UL * 1000UL)
+#define KHZ(1000UL)
+
+/* CLK_PLL_TYPE_RK3066_AUTO type ops */
+#define PLL_FREF_MIN (269 * KHZ)
+#define PLL_FREF_MAX (2200 * MHZ)
+
+#define PLL_FVCO_MIN (440 * MHZ)
+#define PLL_FVCO_MAX (2200 * MHZ)
+
+#define PLL_FOUT_MIN (27500 * KHZ)
+#define PLL_FOUT_MAX (2200 * MHZ)
+
+#define PLL_NF_MAX (4096)
+#define PLL_NR_MAX (64)
+#define PLL_NO_MAX (16)
+
+/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
+#define MIN_FOUTVCO_FREQ (800 * MHZ)
+#define MAX_FOUTVCO_FREQ (2000 * MHZ)
+
+static struct rockchip_pll_rate_table auto_table;
+
+static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
+{
+ return _table;
+}
+
+static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
+ u32 *postdiv1,
+ u32 *postdiv2,
+ u32 *foutvco)
+{
+ unsigned long freq;
+
+ if (fout_hz < MIN_FOUTVCO_FREQ) {
+ for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
+ for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
+ freq = fout_hz * (*postdiv1) * (*postdiv2);
+ if (freq >= MIN_FOUTVCO_FREQ &&
+ freq <= MAX_FOUTVCO_FREQ) {
+ *foutvco = freq;
+ return 0;
+ }
+ }
+ }
+ pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M
to 2000M,fout = %lu\n",
+ fout_hz);
+ } else {
+ *postdiv1 = 1;
+ *postdiv2 = 1;
+ }
+ return 0;
+}
+
+static struct rockchip_pll_rate_table *
+rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
+unsigned long fin_hz,
+unsigned long fout_hz)
+{
+ struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
+ /* FIXME set postdiv1/2 always 1*/
+ u32 foutvco = fout_hz;
+ u64 fin_64, frac_64;
+ u32 f_frac, postdiv1, postdiv2;
+ unsigned long clk_gcd = 0;
+
+ if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
+ return NULL;
+
+ rockchip_pll_clk_set_postdiv(fout_hz, , , );
+ rate_table->postdiv1 = postdiv1;
+ rate_table->postdiv2 = postdiv2;
+ rate_table->dsmpd = 1;
+
+ if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
+ fin_hz /= MHZ;
+ foutvco /= MHZ;
+ clk_gcd = gcd(fin_hz, foutvco);
+ rate_table->refdiv = fin_hz / clk_gcd;
+ rate_table->fbdiv = foutvco / clk_gcd;
+
+ rate_table->frac = 0;
+
+ pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u,
fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
+fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
+rate_table->fbdiv, rate_table->postdiv1,
+rate_table->postdiv2, rate_table->frac);
+ } else {
+ pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu,
fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
+fin_hz, fout_hz,
+fin_hz / MHZ * MHZ,
+fout_hz / MHZ * MHZ);
+ pr_debug("frac get postdiv1 = %u, postdiv2 = %u, foutvco =
%u\n",
+rate_table->postdiv1, rate_table->postdiv2, foutvco);
+ clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
+ rate_table->refdiv = fin_hz / MHZ / clk_gcd;
+ rate_table->fbdiv = foutvco / MHZ / clk_gcd;
+ pr_debug("frac get refdiv = %u, fbdiv = %u\n",
+rate_table->refdiv, rate_table->fbdiv);
+
+ rate_table->frac = 0;
+
+ f_frac = (foutvco % MHZ);
+ fin_64 = fin_hz;
+ do_div(fin_64, (u64)rate_table->refdiv);
+ frac_64 = (u64)f_frac <<
Re: [PATCH 1/7] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
Can you check your get_maintainers script invocation? Not sure why arm64
maintainers are Cced on a clk patch.
Quoting Varadarajan Narayanan (2020-09-27 22:15:34)
> Add programming sequence support for managing the Stromer
> PLLs.
>
> Signed-off-by: Varadarajan Narayanan
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 156
> ++-
> drivers/clk/qcom/clk-alpha-pll.h | 5 ++
> 2 files changed, 160 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..ce3257f 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -116,6 +116,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_OPMODE] = 0x38,
> [PLL_OFF_ALPHA_VAL] = 0x40,
> },
> +
Nitpick: Drop this newline.
> + [CLK_ALPHA_PLL_TYPE_STROMER] = {
> + [PLL_OFF_L_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL] = 0x10,
> + [PLL_OFF_ALPHA_VAL_U] = 0x14,
> + [PLL_OFF_USER_CTL] = 0x18,
> + [PLL_OFF_USER_CTL_U] = 0x1c,
> + [PLL_OFF_CONFIG_CTL] = 0x20,
> + [PLL_OFF_CONFIG_CTL_U] = 0xff,
> + [PLL_OFF_TEST_CTL] = 0x30,
> + [PLL_OFF_TEST_CTL_U] = 0x34,
> + [PLL_OFF_STATUS] = 0x28,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> @@ -127,6 +140,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define ALPHA_BITWIDTH 32U
> #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
>
> +#definePLL_STATUS_REG_SHIFT8
This should have an ALPHA_ prefix.
> +
> #define PLL_HUAYRA_M_WIDTH 8
> #define PLL_HUAYRA_M_SHIFT 8
> #define PLL_HUAYRA_M_MASK 0xff
> @@ -240,14 +255,143 @@ void clk_alpha_pll_configure(struct clk_alpha_pll
> *pll, struct regmap *regmap,
> mask |= config->pre_div_mask;
> mask |= config->post_div_mask;
> mask |= config->vco_mask;
> + mask |= config->alpha_en_mask;
> + mask |= config->alpha_mode_mask;
>
> regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
>
> + /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it
> */
> + val_u = config->status_reg_val << PLL_STATUS_REG_SHIFT;
> + val_u |= config->lock_det;
> +
> + mask_u = config->status_reg_mask;
> + mask_u |= config->lock_det;
> +
> + if (val_u != 0)
if (val_u) is more canonical.
> + regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u,
> val_u);
> +
> + if (config->test_ctl_val != 0)
Same comment
> + regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val != 0)
Same comment
> + regmap_write(regmap, PLL_TEST_CTL_U(pll),
> config->test_ctl_hi_val);
> +
> if (pll->flags & SUPPORTS_FSM_MODE)
> qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
> }
> EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
>
> +static unsigned long
> +alpha_pll_stromer_calc_rate(u64 prate, u32 l, u64 a)
> +{
> + return (prate * l) + ((prate * a) >> ALPHA_REG_BITWIDTH);
Is this not already in this file? Why can't we use
alpha_pll_calc_rate()?
> +}
> +
> +static unsigned long
> +alpha_pll_stromer_round_rate(unsigned long rate, unsigned long prate, u32
> *l, u64 *a)
> +{
> + u64 remainder;
> + u64 quotient;
> +
> + quotient = rate;
> + remainder = do_div(quotient, prate);
> + *l = quotient;
> +
> + if (!remainder) {
> + *a = 0;
> + return rate;
> + }
> +
> + quotient = remainder << ALPHA_REG_BITWIDTH;
> +
> + remainder = do_div(quotient, prate);
> +
> + if (remainder)
> + quotient++;
> +
> + *a = quotient;
> + return alpha_pll_stromer_calc_rate(prate, *l, *a);
> +}
> +
> +static unsigned long
> +clk_alpha_pll_stromer_recalc_rate(struct clk_hw *hw, unsigned long
> parent_rate)
> +{
> + u32 l, low, high, ctl;
> + u64 a = 0, prate = parent_rate;
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> +
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), );
> +
> + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), );
> + if (ctl & PLL_ALPHA_EN) {
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), );
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
> + );
> + a = (u64)high << ALPHA_BITWIDTH | low;
> + }
> +
> + return alpha_pll_stromer_calc_rate(prate, l, a);
> +}
> +
> +static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
> +struct clk_rate_request *req)
> +{
> + unsigned long rate = req->rate;
> + u32 l;
> + u64 a;
> +
> + rate = alpha_pll_stromer_round_rate(rate,
[PATCH v4 3/5] clk: rockchip: add a clock-type for muxes based in the pmugrf
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 9 +
drivers/clk/rockchip/clk.h | 17 +
2 files changed, 26 insertions(+)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 8f77c3f9fab7..4f238f2851ac 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -407,6 +407,8 @@ struct rockchip_clk_provider * __init
rockchip_clk_init(struct device_node *np,
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
+ ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+ "rockchip,pmugrf");
return ctx;
@@ -482,6 +484,13 @@ void __init rockchip_clk_register_branches(
list->mux_shift, list->mux_width,
list->mux_flags);
break;
+ case branch_muxpmugrf:
+ clk = rockchip_clk_register_muxgrf(list->name,
+ list->parent_names, list->num_parents,
+ flags, ctx->pmugrf, list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags);
+ break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 0d401ce09a54..ae059b7744f9 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -238,6 +238,7 @@ struct rockchip_clk_provider {
struct clk_onecell_data clk_data;
struct device_node *cru_node;
struct regmap *grf;
+ struct regmap *pmugrf;
spinlock_t lock;
};
@@ -390,6 +391,7 @@ enum rockchip_clk_branch_type {
branch_composite,
branch_mux,
branch_muxgrf,
+ branch_muxpmugrf,
branch_divider,
branch_fraction_divider,
branch_gate,
@@ -662,6 +664,21 @@ struct rockchip_clk_branch {
.gate_offset= -1, \
}
+#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
+ { \
+ .id = _id, \
+ .branch_type= branch_muxpmugrf, \
+ .name = cname,\
+ .parent_names = pnames, \
+ .num_parents= ARRAY_SIZE(pnames), \
+ .flags = f,\
+ .muxdiv_offset = o,\
+ .mux_shift = s,\
+ .mux_width = w,\
+ .mux_flags = mf, \
+ .gate_offset= -1, \
+ }
+
#define DIV(_id, cname, pname, f, o, s, w, df) \
{ \
.id = _id, \
--
2.17.1
[PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
wait_pll_lock: timeout waiting for pll to lock
pll_set_params: pll update unsucessful,
trying to restore old params
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4c6c9167ef50..8adc6f54a605 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -210,6 +210,11 @@ static int rockchip_rk3036_pll_set_params(struct
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
+ /* set pll power down */
+ writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
+RK3036_PLLCON1_PWRDOWN, 0),
+ pll->reg_base + RK3036_PLLCON(1));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
RK3036_PLLCON0_FBDIV_SHIFT) |
@@ -231,6 +236,11 @@ static int rockchip_rk3036_pll_set_params(struct
rockchip_clk_pll *pll,
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
+ /* set pll power up */
+ writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
+ pll->reg_base + RK3036_PLLCON(1));
+ udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_rk3036_pll_wait_lock(pll);
if (ret) {
@@ -692,6 +702,11 @@ static int rockchip_rk3399_pll_set_params(struct
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
+ /* set pll power down */
+ writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+RK3399_PLLCON3_PWRDOWN, 0),
+ pll->reg_base + RK3399_PLLCON(3));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
RK3399_PLLCON0_FBDIV_SHIFT),
@@ -715,6 +730,12 @@ static int rockchip_rk3399_pll_set_params(struct
rockchip_clk_pll *pll,
RK3399_PLLCON3_DSMPD_SHIFT),
pll->reg_base + RK3399_PLLCON(3));
+ /* set pll power up */
+ writel(HIWORD_UPDATE(0,
+RK3399_PLLCON3_PWRDOWN, 0),
+ pll->reg_base + RK3399_PLLCON(3));
+ udelay(1);
+
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
--
2.17.1
[PATCH v4 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider
>From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
.i.e:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /| |mux|--[GATE]--
|--/ |--[GATE]--[FRACDIV]--| /
|--/
The FRACDIV frequency is designed to be only 300M(Different SOC
implementations are different).But the GPLL or CPLL may be 1200M.
Must be added to limit to ensure that the design is not exceeded.
Signed-off-by: Finley Xiao
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-px30.c | 29 +--
drivers/clk/rockchip/clk-rk3036.c | 13 +
drivers/clk/rockchip/clk-rk3128.c | 15 ++
drivers/clk/rockchip/clk-rk3188.c | 24 +---
drivers/clk/rockchip/clk-rk3228.c | 18 +++-
drivers/clk/rockchip/clk-rk3288.c | 19 +++--
drivers/clk/rockchip/clk-rk3308.c | 46 +--
drivers/clk/rockchip/clk-rk3328.c | 17 +++-
drivers/clk/rockchip/clk-rk3368.c | 17 +++-
drivers/clk/rockchip/clk-rk3399.c | 32 -
drivers/clk/rockchip/clk-rv1108.c | 14 ++
drivers/clk/rockchip/clk.c| 21 --
drivers/clk/rockchip/clk.h| 10 +--
include/linux/clk-provider.h | 2 ++
14 files changed, 168 insertions(+), 109 deletions(-)
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index 6fb9c98b7d24..f075eb922bab 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -13,6 +13,7 @@
#include "clk.h"
#define PX30_GRF_SOC_STATUS0 0x480
+#define PX30_FRAC_MAX_PRATE6
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
@@ -424,7 +425,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(6), 0,
PX30_CLKGATE_CON(2), 3, GFLAGS,
- _dclk_vopb_fracmux),
+ _dclk_vopb_fracmux, 0),
GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
@@ -433,7 +434,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(9), 0,
PX30_CLKGATE_CON(2), 7, GFLAGS,
- _dclk_vopl_fracmux),
+ _dclk_vopl_fracmux, 0),
GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 8, GFLAGS),
@@ -591,7 +592,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
- _pdm_fracmux),
+ _pdm_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),
@@ -601,7 +602,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(29), 0,
PX30_CLKGATE_CON(9), 13, GFLAGS,
- _i2s0_tx_fracmux),
+ _i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p,
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
@@ -617,7 +618,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(59), 0,
PX30_CLKGATE_CON(17), 1, GFLAGS,
- _i2s0_rx_fracmux),
+ _i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p,
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
PX30_CLKGATE_CON(17), 2, GFLAGS),
@@ -633,7 +634,7 @@ static struct rockchip_clk_branch px30_clk_branches[]
__initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src",
CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(31),
Re: [PATCH v3] Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst
Reviewed-by: Alex Shi 在 2020/10/14 上午10:20, Bailu Lin 写道: > This is a Chinese translated version of > Documentation/arm64/hugetlbpage.rst > > Signed-off-by: Bailu Lin > --- > Changes in v3: > - Modify a translation as Alex sugguested. > Changes in v2: > - Fix Sphinx 2.4.4's waring by increasing underline' size. > --- > Documentation/arm64/hugetlbpage.rst | 2 + > .../translations/zh_CN/arm64/hugetlbpage.rst | 45 +++ > .../translations/zh_CN/arm64/index.rst| 1 + > 3 files changed, 48 insertions(+) > create mode 100644 Documentation/translations/zh_CN/arm64/hugetlbpage.rst > > diff --git a/Documentation/arm64/hugetlbpage.rst > b/Documentation/arm64/hugetlbpage.rst > index b44f939e5210..a110124c11e3 100644 > --- a/Documentation/arm64/hugetlbpage.rst > +++ b/Documentation/arm64/hugetlbpage.rst > @@ -1,3 +1,5 @@ > +.. _hugetlbpage_index: > + > > HugeTLBpage on ARM64 > > diff --git a/Documentation/translations/zh_CN/arm64/hugetlbpage.rst > b/Documentation/translations/zh_CN/arm64/hugetlbpage.rst > new file mode 100644 > index ..13304d269d0b > --- /dev/null > +++ b/Documentation/translations/zh_CN/arm64/hugetlbpage.rst > @@ -0,0 +1,45 @@ > +.. include:: ../disclaimer-zh_CN.rst > + > +:Original: :ref:`Documentation/arm64/hugetlbpage.rst ` > + > +Translator: Bailu Lin > + > += > +ARM64中的 HugeTLBpage > += > + > +大页依靠有效利用 TLBs 来提高地址翻译的性能。这取决于以下 > +两点 - > + > + - 大页的大小 > + - TLBs 支持的条目大小 > + > +ARM64 接口支持2种大页方式。 > + > +1) pud/pmd 级别的块映射 > +--- > + > +这是常规大页，他们的 pmd 或 pud 页面表条目指向一个内存块。 > +不管 TLB 中支持的条目大小如何，块映射可以减少翻译大页地址 > +所需遍历的页表深度。 > + > +2) 使用连续位 > +- > + > +架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续 > +位告诉 MMU 这个条目是一个连续条目集的一员，它可以被缓存在单 > +个 TLB 条目中。 > + > +在 Linux 中连续位用来增加 pmd 和 pte(最后一级)级别映射的大 > +小。受支持的连续页表条目数量因页面大小和页表级别而异。 > + > + > +支持以下大页尺寸配置 - > + > + == === > + - CONT PTEPMDCONT PMDPUD > + == === > + 4K: 64K 2M 32M 1G > + 16K: 2M32M 1G > + 64K: 2M 512M 16G > + == === > diff --git a/Documentation/translations/zh_CN/arm64/index.rst > b/Documentation/translations/zh_CN/arm64/index.rst > index 646ed1f7aea3..e31a6090384d 100644 > --- a/Documentation/translations/zh_CN/arm64/index.rst > +++ b/Documentation/translations/zh_CN/arm64/index.rst > @@ -14,3 +14,4 @@ ARM64 架构 > :maxdepth: 2 > > amu > +hugetlbpage >
Re: [PATCH v6 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
On Tue, 2020-10-13 at 17:10 +0200, Matthias Brugger wrote:
>
> On 12/10/2020 14:45, Wenbin Mei wrote:
> > MT8192 msdc is an independent sub system, we need control more bus
> > clocks for it.
> > Add support for the additional subsys clocks to allow it to be
> > configured appropriately.
> >
> > Signed-off-by: Wenbin Mei
> > ---
> > drivers/mmc/host/mtk-sd.c | 74 +--
> > 1 file changed, 56 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> > index a704745e5882..c7df7510f120 100644
> > --- a/drivers/mmc/host/mtk-sd.c
> > +++ b/drivers/mmc/host/mtk-sd.c
> [...]
> > +static int msdc_of_clock_parse(struct platform_device *pdev,
> > + struct msdc_host *host)
> > +{
> > + int ret;
> > +
> > + host->src_clk = devm_clk_get(>dev, "source");
> > + if (IS_ERR(host->src_clk))
> > + return PTR_ERR(host->src_clk);
> > +
> > + host->h_clk = devm_clk_get(>dev, "hclk");
> > + if (IS_ERR(host->h_clk))
> > + return PTR_ERR(host->h_clk);
> > +
> > + host->bus_clk = devm_clk_get_optional(>dev, "bus_clk");
> > + if (IS_ERR(host->bus_clk))
> > + host->bus_clk = NULL;
> > +
> > + /*source clock control gate is optional clock*/
> > + host->src_clk_cg = devm_clk_get_optional(>dev, "source_cg");
> > + if (IS_ERR(host->src_clk_cg))
> > + host->src_clk_cg = NULL;
> > +
> > + host->sys_clk_cg = devm_clk_get_optional(>dev, "sys_cg");
> > + if (IS_ERR(host->sys_clk_cg))
> > + host->sys_clk_cg = NULL;
> > +
> > + /* If present, always enable for this clock gate */
> > + clk_prepare_enable(host->sys_clk_cg);
> > +
> > + host->bulk_clks[0].id = "pclk_cg";
> > + host->bulk_clks[1].id = "axi_cg";
> > + host->bulk_clks[2].id = "ahb_cg";
>
> That looks at least suspicious. The pointers of id point to some strings
> defined
> in the function. Aren't they out of scope once msdc_of_clock_parse() has
> returned?
>
These constants are not in stack range, so they will not be lost.
And I have confirmed it after msdc_of_clock_parse() has returned, these
ids still exist.
> Regards,
> Matthias
Re: [PATCH 3/7] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
Quoting Varadarajan Narayanan (2020-09-27 22:15:36)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0583273..d1a2504 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -155,6 +155,14 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc. Select this for the root clock
> of ipq8074.
>
> +config IPQ_GCC_5018
> + tristate "IPQ5018 Global Clock Controller"
> + help
> +Support for global clock controller on ipq5018 devices.
> +Say Y if you want to use peripheral devices such as UART, SPI,
> +i2c, USB, SD/eMMC, etc. Select this for the root clock
> +of ipq5018.
What is the root clock of ipq5018? Please drop that last sentence.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
> new file mode 100644
> index ..9056386
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq5018.c
> @@ -0,0 +1,3833 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
Why is this attached to dt-bindings? Please remove that newline above
and move this away from dt-bindings below.
> +#include
> +#include
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
This is in clk-rcg.h already.
> +
> +static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
> + "usb3phy_0_cc_pipe_clk",
> + "xo",
> +};
All these names structures need to change, see next comment.
> +
> +static struct clk_rcg2 apss_ahb_clk_src = {
> + .cmd_rcgr = 0x46000,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .freq_tbl = ftbl_apss_ahb_clk_src,
> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "apss_ahb_clk_src",
> + .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
> + .num_parents = 3,
Please migrate to the new way of specifying clks with
clk_init_data::clk_parent_data
> + .ops = _rcg2_ops,
> + .flags = CLK_IS_CRITICAL | CLK_IGNORE_UNUSED,
Why is it critical and ignore unused? Do you need this clk to be here at
all? Can we just enable it when this driver probes with a register write
and then ignore it from there on out?
> + },
> +};
> +
> +static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
> + .reg = 0x46018,
> + .shift = 4,
> + .width = 4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "apss_ahb_postdiv_clk_src",
> + .parent_names = (const char *[]){
> + "apss_ahb_clk_src"
> + },
> + .num_parents = 1,
> + .ops = _regmap_div_ops,
> + },
> + },
> +};
> +
[...]
> +
> +static struct clk_branch gcc_qdss_dap_clk = {
> + .halt_reg = 0x29084,
> + .clkr = {
> + .enable_reg = 0x29084,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_dap_clk",
> + .parent_names = (const char *[]){
> + "qdss_tsctr_clk_src"
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Whenever CLK_IS_CRITICAL is there please document why it is needed. And
if possible remove the clk structure and hit the clk on in driver probe
so we don't waste memory modeling something that never matters.
Typically that can only be done if nothing references this clk as a
parent or if we're willing to break the clk tree and ignore describing
parents. In this case it's a branch so probably nothing else is under it
so we can just turn it on during probe and stop caring.
> + .ops = _branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_cfg_ahb_clk = {
> + .halt_reg = 0x29008,
> + .clkr = {
> + .enable_reg = 0x29008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_cfg_ahb_clk",
> + .parent_names = (const char *[]){
> + "pcnoc_clk_src"
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = _branch2_ops,
> +
Re: [PATCH v3 00/15] Tegra XHCI controller ELPG support
Yes, it's safe to apply "clk: tegra: Don't enable PLLE HW sequencer at init" before the others have applied. Disabling PLLE hardware power sequencer will not cause any functionality problem to XUSB/PCIE/SATA. The only thing changed is PLLE won't be powered off by hardware when all clients are in low power state, i.e., software has to explicitly power off PLLE. Thanks for review. JC On 9/28/20 8:54 PM, Thierry Reding wrote: > On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote: >> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated) >> state for power saving when all of the connected USB devices are in >> suspended state. This patch series includes clk, phy and pmc changes >> that are required for properly place controller in ELPG and bring >> controller out of ELPG. >> >> JC Kuo (15): >> clk: tegra: Add PLLE HW power sequencer control >> clk: tegra: Don't enable PLLE HW sequencer at init > > Is it safe to apply this second patch before the others have applied? > Since we now need to explicitly enable the HW sequencer, it won't be > enabled before the corresponding patch does that. So applying patch 2 > before the others sounds like it would break existing users of the HW > sequencer. > > Thierry >
RE: [PATCH] rtw88: fix fw_fifo_addr check
> On Sun, Oct 11, 2020 at 08:54:38AM -0700, t...@redhat.com wrote:
> > From: Tom Rix
> >
> > The clang build reports this warning
> >
> > fw.c:1485:21: warning: address of array 'rtwdev->chip->fw_fifo_addr'
> > will always evaluate to 'true'
> > if (!rtwdev->chip->fw_fifo_addr) {
> >
> > fw_fifo_addr is an array in rtw_chip_info so it is always nonzero. A
> > better check is if the first element of the array is nonzero. In the
> > cases where fw_fifo_addr is initialized by rtw88b and rtw88c, the
> > first array element is 0x780.
> >
> > Signed-off-by: Tom Rix
>
> Reviewed-by: Nathan Chancellor
>
Thanks for your fix,
Acked-by: Tzu-En Huang
> > ---
> > drivers/net/wireless/realtek/rtw88/fw.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/wireless/realtek/rtw88/fw.c
> > b/drivers/net/wireless/realtek/rtw88/fw.c
> > index 042015bc8055..b2fd87834f23 100644
> > --- a/drivers/net/wireless/realtek/rtw88/fw.c
> > +++ b/drivers/net/wireless/realtek/rtw88/fw.c
> > @@ -1482,7 +1482,7 @@ static bool rtw_fw_dump_check_size(struct
> > rtw_dev *rtwdev, int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8
> fifo_sel, u32 addr, u32 size,
> > u32 *buffer)
> > {
> > - if (!rtwdev->chip->fw_fifo_addr) {
> > + if (!rtwdev->chip->fw_fifo_addr[0]) {
> > rtw_dbg(rtwdev, RTW_DBG_FW, "chip not support dump fw fifo\n");
> > return -ENOTSUPP;
> > }
> > --
> > 2.18.1
> >
>
> --Please consider the environment before printing this e-mail.
[PATCH v3] Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst
This is a Chinese translated version of Documentation/arm64/hugetlbpage.rst Signed-off-by: Bailu Lin --- Changes in v3: - Modify a translation as Alex sugguested. Changes in v2: - Fix Sphinx 2.4.4's waring by increasing underline' size. --- Documentation/arm64/hugetlbpage.rst | 2 + .../translations/zh_CN/arm64/hugetlbpage.rst | 45 +++ .../translations/zh_CN/arm64/index.rst| 1 + 3 files changed, 48 insertions(+) create mode 100644 Documentation/translations/zh_CN/arm64/hugetlbpage.rst diff --git a/Documentation/arm64/hugetlbpage.rst b/Documentation/arm64/hugetlbpage.rst index b44f939e5210..a110124c11e3 100644 --- a/Documentation/arm64/hugetlbpage.rst +++ b/Documentation/arm64/hugetlbpage.rst @@ -1,3 +1,5 @@ +.. _hugetlbpage_index: + HugeTLBpage on ARM64 diff --git a/Documentation/translations/zh_CN/arm64/hugetlbpage.rst b/Documentation/translations/zh_CN/arm64/hugetlbpage.rst new file mode 100644 index ..13304d269d0b --- /dev/null +++ b/Documentation/translations/zh_CN/arm64/hugetlbpage.rst @@ -0,0 +1,45 @@ +.. include:: ../disclaimer-zh_CN.rst + +:Original: :ref:`Documentation/arm64/hugetlbpage.rst ` + +Translator: Bailu Lin + += +ARM64中的 HugeTLBpage += + +大页依靠有效利用 TLBs 来提高地址翻译的性能。这取决于以下 +两点 - + + - 大页的大小 + - TLBs 支持的条目大小 + +ARM64 接口支持2种大页方式。 + +1) pud/pmd 级别的块映射 +--- + +这是常规大页，他们的 pmd 或 pud 页面表条目指向一个内存块。 +不管 TLB 中支持的条目大小如何，块映射可以减少翻译大页地址 +所需遍历的页表深度。 + +2) 使用连续位 +- + +架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续 +位告诉 MMU 这个条目是一个连续条目集的一员，它可以被缓存在单 +个 TLB 条目中。 + +在 Linux 中连续位用来增加 pmd 和 pte(最后一级)级别映射的大 +小。受支持的连续页表条目数量因页面大小和页表级别而异。 + + +支持以下大页尺寸配置 - + + == === + - CONT PTEPMDCONT PMDPUD + == === + 4K: 64K 2M 32M 1G + 16K: 2M32M 1G + 64K: 2M 512M 16G + == === diff --git a/Documentation/translations/zh_CN/arm64/index.rst b/Documentation/translations/zh_CN/arm64/index.rst index 646ed1f7aea3..e31a6090384d 100644 --- a/Documentation/translations/zh_CN/arm64/index.rst +++ b/Documentation/translations/zh_CN/arm64/index.rst @@ -14,3 +14,4 @@ ARM64 架构 :maxdepth: 2 amu +hugetlbpage -- 2.20.1
Re: [PATCH 1/1] watchdog: remove unneeded inclusion of
On 2020/9/8 11:34, Leizhen (ThunderTown) wrote:
>
>
> On 2020/9/8 10:40, Guenter Roeck wrote:
>> On 9/7/20 12:50 AM, Leizhen (ThunderTown) wrote:
>>> Hi, Wim Van Sebroeck, Guenter Roeck:
>>> What's your opinion? Guenter Roeck given "Reviewed-by" two weeks ago.
>>>
>>
>> The patch is in my watchdog-next branch, and Wim usually picks it up
>> from there.
>
Hi, Guenter:
Have you sent [GIT PULL] updates for 5.10, I don't see this patch in
linux-next.
> Oh, thanks.
>
>>
>> Guenter
>>
>>>
>>> On 2020/8/27 21:40, Guenter Roeck wrote:
On 8/26/20 11:21 PM, Zhen Lei wrote:
> There has been no reference to "struct sched_param" since
> commit 94beddacb53c ("sched,watchdog: Convert to sched_set_fifo()"), so
> there's no need to include any more, delete
> it.
>
> Signed-off-by: Zhen Lei
Reviewed-by: Guenter Roeck
> ---
> drivers/watchdog/watchdog_dev.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/watchdog/watchdog_dev.c
> b/drivers/watchdog/watchdog_dev.c
> index 6798addabd5a067..0f18fa2433310b0 100644
> --- a/drivers/watchdog/watchdog_dev.c
> +++ b/drivers/watchdog/watchdog_dev.c
> @@ -43,8 +43,6 @@
> #include /* For watchdog specific items */
> #include/* For copy_to_user/put_user/... */
>
> -#include /* For struct sched_param */
> -
> #include "watchdog_core.h"
> #include "watchdog_pretimeout.h"
>
>
>>>
>>
>>
>>
[RFC v2 2/7] KVM: VMX: Expose IA32_PKRS MSR
Protection Keys for Supervisor Pages (PKS) uses IA32_PKRS MSR (PKRS) at
index 0x6E1 to allow software to manage supervisor protection key
rights. For performance consideration, PKRS intercept will be disabled
so that the guest can access the PKRS without VM exits.
PKS introduces dedicated control fields in VMCS to switch PKRS, which
only does the retore part. In addition, every VM exit saves PKRS into
the guest-state area in VMCS, while VM enter won't save the host value
due to the expectation that the host won't change the MSR often. Update
the host's value in VMCS manually if the MSR has been changed by the
kernel since the last time the VMCS was run.
The function get_current_pkrs() in arch/x86/mm/pkeys.c exports the
per-cpu variable pkrs_cache to avoid frequent rdmsr of PKRS.
Signed-off-by: Chenyi Qiang
---
arch/x86/include/asm/pkeys.h| 1 +
arch/x86/kvm/vmx/capabilities.h | 6 +++
arch/x86/kvm/vmx/nested.c | 1 +
arch/x86/kvm/vmx/vmcs.h | 1 +
arch/x86/kvm/vmx/vmx.c | 66 -
arch/x86/kvm/x86.h | 6 +++
arch/x86/mm/pkeys.c | 6 +++
include/linux/pkeys.h | 4 ++
8 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/pkeys.h b/arch/x86/include/asm/pkeys.h
index cae0153a5480..2e666dd2ea31 100644
--- a/arch/x86/include/asm/pkeys.h
+++ b/arch/x86/include/asm/pkeys.h
@@ -142,6 +142,7 @@ u32 update_pkey_val(u32 pk_reg, int pkey, unsigned int
flags);
#ifdef CONFIG_ARCH_HAS_SUPERVISOR_PKEYS
int pks_key_alloc(const char *const pkey_user);
void pks_key_free(int pkey);
+u32 get_current_pkrs(void);
void pks_mknoaccess(int pkey, bool global);
void pks_mkread(int pkey, bool global);
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 4bbd8b448d22..7099e3105f48 100644
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -103,6 +103,12 @@ static inline bool cpu_has_load_perf_global_ctrl(void)
(vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
}
+static inline bool cpu_has_load_ia32_pkrs(void)
+{
+ return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PKRS) &&
+ (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PKRS);
+}
+
static inline bool cpu_has_vmx_mpx(void)
{
return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 1bb6b31eb646..14f56e8dd060 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -294,6 +294,7 @@ static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
dest->ds_sel = src->ds_sel;
dest->es_sel = src->es_sel;
#endif
+ dest->pkrs = src->pkrs;
}
static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index 7a3675fddec2..39ec3d0c844b 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -40,6 +40,7 @@ struct vmcs_host_state {
#ifdef CONFIG_X86_64
u16 ds_sel, es_sel;
#endif
+ u32 pkrs;
};
struct vmcs_controls_shadow {
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 96979c09ebd1..e5da5dbe19d4 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1147,6 +1147,7 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
#endif
unsigned long fs_base, gs_base;
u16 fs_sel, gs_sel;
+ u32 host_pkrs;
int i;
vmx->req_immediate_exit = false;
@@ -1179,6 +1180,20 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
*/
host_state->ldt_sel = kvm_read_ldt();
+ /*
+* Update the host pkrs vmcs field before vcpu runs.
+* The setting of VM_EXIT_LOAD_IA32_PKRS can ensure
+* kvm_cpu_cap_has(X86_FEATURE_PKS) &&
+* guest_cpuid_has(vcpu, X86_FEATURE_VMX).
+*/
+ if (vm_exit_controls_get(vmx) & VM_EXIT_LOAD_IA32_PKRS) {
+ host_pkrs = get_current_pkrs();
+ if (unlikely(host_pkrs != host_state->pkrs)) {
+ vmcs_write64(HOST_IA32_PKRS, host_pkrs);
+ host_state->pkrs = host_pkrs;
+ }
+ }
+
#ifdef CONFIG_X86_64
savesegment(ds, host_state->ds_sel);
savesegment(es, host_state->es_sel);
@@ -1967,6 +1982,13 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct
msr_data *msr_info)
else
msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
break;
+ case MSR_IA32_PKRS:
+ if (!kvm_cpu_cap_has(X86_FEATURE_PKS) ||
+ (!msr_info->host_initiated &&
+ !guest_cpuid_has(vcpu, X86_FEATURE_PKS)))
+ return 1;
+ msr_info->data = vmcs_read64(GUEST_IA32_PKRS);
+ break;
case MSR_TSC_AUX:
if
[RFC v2 3/7] KVM: MMU: Rename the pkru to pkr
PKRU represents the PKU register utilized in the protection key rights
check for user pages. Protection Keys for Superviosr Pages (PKS) extends
the protection key architecture to cover supervisor pages.
Rename the *pkru* related variables and functions to *pkr* which stands
for both of the PKRU and PKRS. It makes sense because both registers
have the same format. PKS and PKU can also share the same bitmap to
cache the conditions where protection key checks are needed.
Signed-off-by: Chenyi Qiang
---
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/kvm/mmu.h | 12 ++--
arch/x86/kvm/mmu/mmu.c | 18 +-
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 5303dbc5c9bc..dd3af15e109f 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -381,7 +381,7 @@ struct kvm_mmu {
* with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
* Each domain has 2 bits which are ANDed with AD and WD from PKRU.
*/
- u32 pkru_mask;
+ u32 pkr_mask;
u64 *pae_root;
u64 *lm_root;
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 5efc6081ca13..306608248594 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -195,8 +195,8 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
u32 errcode = PFERR_PRESENT_MASK;
WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
- if (unlikely(mmu->pkru_mask)) {
- u32 pkru_bits, offset;
+ if (unlikely(mmu->pkr_mask)) {
+ u32 pkr_bits, offset;
/*
* PKRU defines 32 bits, there are 16 domains and 2
@@ -204,15 +204,15 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
* index of the protection domain, so pte_pkey * 2 is
* is the index of the first bit for the domain.
*/
- pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
offset = (pfec & ~1) +
((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT -
PT_USER_SHIFT));
- pkru_bits &= mmu->pkru_mask >> offset;
- errcode |= -pkru_bits & PFERR_PK_MASK;
- fault |= (pkru_bits != 0);
+ pkr_bits &= mmu->pkr_mask >> offset;
+ errcode |= -pkr_bits & PFERR_PK_MASK;
+ fault |= (pkr_bits != 0);
}
return -(u32)fault & errcode;
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 71aa3da2a0b7..834a95cf49fa 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4695,20 +4695,20 @@ static void update_permission_bitmask(struct kvm_vcpu
*vcpu,
* away both AD and WD. For all reads or if the last condition holds, WD
* only will be masked away.
*/
-static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
+static void update_pkr_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
bool ept)
{
unsigned bit;
bool wp;
if (ept) {
- mmu->pkru_mask = 0;
+ mmu->pkr_mask = 0;
return;
}
/* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
- mmu->pkru_mask = 0;
+ mmu->pkr_mask = 0;
return;
}
@@ -4742,7 +4742,7 @@ static void update_pkru_bitmask(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
/* PKRU.WD stops write access. */
pkey_bits |= (!!check_write) << 1;
- mmu->pkru_mask |= (pkey_bits & 3) << pfec;
+ mmu->pkr_mask |= (pkey_bits & 3) << pfec;
}
}
@@ -4764,7 +4764,7 @@ static void paging64_init_context_common(struct kvm_vcpu
*vcpu,
reset_rsvds_bits_mask(vcpu, context);
update_permission_bitmask(vcpu, context, false);
- update_pkru_bitmask(vcpu, context, false);
+ update_pkr_bitmask(vcpu, context, false);
update_last_nonleaf_level(vcpu, context);
MMU_WARN_ON(!is_pae(vcpu));
@@ -4794,7 +4794,7 @@ static void paging32_init_context(struct kvm_vcpu *vcpu,
reset_rsvds_bits_mask(vcpu, context);
update_permission_bitmask(vcpu, context, false);
- update_pkru_bitmask(vcpu, context, false);
+ update_pkr_bitmask(vcpu, context, false);
update_last_nonleaf_level(vcpu, context);
context->page_fault = paging32_page_fault;
@@ -4913,7 +4913,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
}
update_permission_bitmask(vcpu, context, false);
- update_pkru_bitmask(vcpu,
[kvm-unit-tests PATCH] x86: Add tests for PKS
This unit-test is intended to test the KVM support for Protection Keys
for Supervisor Pages (PKS). If CR4.PKS is set in long mode, supervisor
pkeys are checked in addition to normal paging protections and Access or
Write can be disabled via a MSR update without TLB flushes when
permissions change.
Signed-off-by: Chenyi Qiang
---
lib/x86/msr.h | 1 +
lib/x86/processor.h | 2 +
x86/Makefile.x86_64 | 1 +
x86/pks.c | 146
x86/unittests.cfg | 5 ++
5 files changed, 155 insertions(+)
create mode 100644 x86/pks.c
diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index 6ef5502..e36934b 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -209,6 +209,7 @@
#define MSR_IA32_EBL_CR_POWERON0x002a
#define MSR_IA32_FEATURE_CONTROL0x003a
#define MSR_IA32_TSC_ADJUST0x003b
+#define MSR_IA32_PKRS 0x06e1
#define FEATURE_CONTROL_LOCKED (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index 74a2498..985fdd0 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -50,6 +50,7 @@
#define X86_CR4_SMEP 0x0010
#define X86_CR4_SMAP 0x0020
#define X86_CR4_PKE0x0040
+#define X86_CR4_PKS0x0100
#define X86_EFLAGS_CF0x0001
#define X86_EFLAGS_FIXED 0x0002
@@ -157,6 +158,7 @@ static inline u8 cpuid_maxphyaddr(void)
#defineX86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22))
#defineX86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26))
#defineX86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29))
+#defineX86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31))
#defineX86_FEATURE_NX (CPUID(0x8001, 0, EDX, 20))
#defineX86_FEATURE_RDPRU (CPUID(0x8008, 0, EBX, 4))
diff --git a/x86/Makefile.x86_64 b/x86/Makefile.x86_64
index af61d85..3a353df 100644
--- a/x86/Makefile.x86_64
+++ b/x86/Makefile.x86_64
@@ -20,6 +20,7 @@ tests += $(TEST_DIR)/tscdeadline_latency.flat
tests += $(TEST_DIR)/intel-iommu.flat
tests += $(TEST_DIR)/vmware_backdoors.flat
tests += $(TEST_DIR)/rdpru.flat
+tests += $(TEST_DIR)/pks.flat
include $(SRCDIR)/$(TEST_DIR)/Makefile.common
diff --git a/x86/pks.c b/x86/pks.c
new file mode 100644
index 000..a3044cf
--- /dev/null
+++ b/x86/pks.c
@@ -0,0 +1,146 @@
+#include "libcflat.h"
+#include "x86/desc.h"
+#include "x86/processor.h"
+#include "x86/vm.h"
+#include "x86/msr.h"
+
+#define CR0_WP_MASK (1UL << 16)
+#define PTE_PKEY_BIT 59
+#define SUPER_BASE(1 << 24)
+#define SUPER_VAR(v) (*((__typeof__(&(v))) (((unsigned long)) +
SUPER_BASE)))
+
+volatile int pf_count = 0;
+volatile unsigned save;
+volatile unsigned test;
+
+static void set_cr0_wp(int wp)
+{
+unsigned long cr0 = read_cr0();
+
+cr0 &= ~CR0_WP_MASK;
+if (wp)
+cr0 |= CR0_WP_MASK;
+write_cr0(cr0);
+}
+
+void do_pf_tss(unsigned long error_code);
+void do_pf_tss(unsigned long error_code)
+{
+printf("#PF handler, error code: 0x%lx\n", error_code);
+pf_count++;
+save = test;
+wrmsr(MSR_IA32_PKRS, 0);
+}
+
+extern void pf_tss(void);
+
+asm ("pf_tss: \n\t"
+#ifdef __x86_64__
+// no task on x86_64, save/restore caller-save regs
+"push %rax; push %rcx; push %rdx; push %rsi; push %rdi\n"
+"push %r8; push %r9; push %r10; push %r11\n"
+"mov 9*8(%rsp), %rdi\n"
+#endif
+"call do_pf_tss \n\t"
+#ifdef __x86_64__
+"pop %r11; pop %r10; pop %r9; pop %r8\n"
+"pop %rdi; pop %rsi; pop %rdx; pop %rcx; pop %rax\n"
+#endif
+"add $"S", %"R "sp\n\t" // discard error code
+"iret"W" \n\t"
+"jmp pf_tss\n\t"
+);
+
+static void init_test(void)
+{
+pf_count = 0;
+
+invlpg();
+invlpg(_VAR(test));
+wrmsr(MSR_IA32_PKRS, 0);
+set_cr0_wp(0);
+}
+
+int main(int ac, char **av)
+{
+unsigned long i;
+unsigned int pkey = 0x2;
+unsigned int pkrs_ad = 0x10;
+unsigned int pkrs_wd = 0x20;
+
+if (!this_cpu_has(X86_FEATURE_PKS)) {
+printf("PKS not enabled\n");
+return report_summary();
+}
+
+setup_vm();
+setup_alt_stack();
+set_intr_alt_stack(14, pf_tss);
+wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_LMA);
+
+// First 16MB are user pages
+for (i = 0; i < SUPER_BASE; i += PAGE_SIZE) {
+*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned
long)pkey << PTE_PKEY_BIT);
+invlpg((void *)i);
+}
+
+// Present the same 16MB as supervisor pages in the 16MB-32MB range
+for (i = SUPER_BASE; i < 2 * SUPER_BASE; i += PAGE_SIZE) {
+*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~SUPER_BASE;
+*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~PT_USER_MASK;
+*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned
long)pkey << PTE_PKEY_BIT);
+invlpg((void *)i);
+
[RFC v2 7/7] KVM: VMX: Enable PKS for nested VM
PKS MSR passes through guest directly. Configure the MSR to match the L0/L1 settings so that nested VM runs PKS properly. Signed-off-by: Chenyi Qiang --- arch/x86/kvm/vmx/nested.c | 37 +++-- arch/x86/kvm/vmx/vmcs12.c | 2 ++ arch/x86/kvm/vmx/vmcs12.h | 6 +- arch/x86/kvm/vmx/vmx.c| 10 ++ arch/x86/kvm/vmx/vmx.h| 1 + 5 files changed, 53 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 14f56e8dd060..66c74d10dda5 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -652,6 +652,12 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W); + if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PKRS)) + nested_vmx_disable_intercept_for_msr( + msr_bitmap_l1, msr_bitmap_l0, + MSR_IA32_PKRS, + MSR_TYPE_R | MSR_TYPE_W); + kvm_vcpu_unmap(vcpu, _vmx(vcpu)->nested.msr_bitmap_map, false); return true; @@ -2433,6 +2439,10 @@ static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) if (kvm_mpx_supported() && vmx->nested.nested_run_pending && (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); + + if (vmx->nested.nested_run_pending && + (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PKRS)) + vmcs_write64(GUEST_IA32_PKRS, vmcs12->guest_ia32_pkrs); } if (nested_cpu_has_xsaves(vmcs12)) @@ -2521,6 +2531,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending || !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))) vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs); + + if (kvm_cpu_cap_has(X86_FEATURE_PKS) && + (!vmx->nested.nested_run_pending || +!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PKRS))) + vmcs_write64(GUEST_IA32_PKRS, vmx->nested.vmcs01_guest_pkrs); vmx_set_rflags(vcpu, vmcs12->guest_rflags); /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the @@ -2861,6 +2876,10 @@ static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, vmcs12->host_ia32_perf_global_ctrl))) return -EINVAL; + if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PKRS) && + CC(!kvm_pkrs_valid(vmcs12->host_ia32_pkrs))) + return -EINVAL; + #ifdef CONFIG_X86_64 ia32e = !!(vcpu->arch.efer & EFER_LMA); #else @@ -3010,6 +3029,10 @@ static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, if (nested_check_guest_non_reg_state(vmcs12)) return -EINVAL; + if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PKRS) && + CC(!kvm_pkrs_valid(vmcs12->guest_ia32_pkrs))) + return -EINVAL; + return 0; } @@ -3320,6 +3343,9 @@ enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, if (kvm_mpx_supported() && !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); + if (kvm_cpu_cap_has(X86_FEATURE_PKS) && + !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PKRS)) + vmx->nested.vmcs01_guest_pkrs = vmcs_read64(GUEST_IA32_PKRS); /* * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and* @@ -3913,6 +3939,7 @@ static bool is_vmcs12_ext_field(unsigned long field) case GUEST_IDTR_BASE: case GUEST_PENDING_DBG_EXCEPTIONS: case GUEST_BNDCFGS: + case GUEST_IA32_PKRS: return true; default: break; @@ -3964,6 +3991,8 @@ static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); if (kvm_mpx_supported()) vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); + if (guest_cpuid_has(vcpu, X86_FEATURE_PKS)) + vmcs12->guest_ia32_pkrs = vmcs_read64(GUEST_IA32_PKRS); vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false; } @@ -4199,6 +4228,9 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->host_ia32_perf_global_ctrl)); + if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PKRS) + vmcs_write64(GUEST_IA32_PKRS, vmcs12->host_ia32_pkrs); + /* Set L1 segment info according to Intel SDM
[RFC v2 4/7] KVM: MMU: Refactor pkr_mask to cache condition
pkr_mask bitmap indicates if protection key checks are needed for user
pages currently. It is indexed by page fault error code bits [4:1] with
PFEC.RSVD replaced by the ACC_USER_MASK from the page tables. Refactor
it by reverting to the use of PFEC.RSVD. After that, PKS and PKU can
share the same bitmap.
Signed-off-by: Chenyi Qiang
---
arch/x86/kvm/mmu.h | 10 ++
arch/x86/kvm/mmu/mmu.c | 16 ++--
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 306608248594..597b9159c10b 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -204,11 +204,13 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
* index of the protection domain, so pte_pkey * 2 is
* is the index of the first bit for the domain.
*/
- pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ if (pte_access & PT_USER_MASK)
+ pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ else
+ pkr_bits = 0;
- /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
- offset = (pfec & ~1) +
- ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT -
PT_USER_SHIFT));
+ /* clear present bit */
+ offset = (pfec & ~1);
pkr_bits &= mmu->pkr_mask >> offset;
errcode |= -pkr_bits & PFERR_PK_MASK;
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 834a95cf49fa..f9814ab0596d 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4716,21 +4716,25 @@ static void update_pkr_bitmask(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
unsigned pfec, pkey_bits;
- bool check_pkey, check_write, ff, uf, wf, pte_user;
+ bool check_pkey, check_write, ff, uf, wf, rsvdf;
pfec = bit << 1;
ff = pfec & PFERR_FETCH_MASK;
uf = pfec & PFERR_USER_MASK;
wf = pfec & PFERR_WRITE_MASK;
- /* PFEC.RSVD is replaced by ACC_USER_MASK. */
- pte_user = pfec & PFERR_RSVD_MASK;
+ /*
+* PFERR_RSVD_MASK bit is not set if the
+* access is subject to PK restrictions.
+*/
+ rsvdf = pfec & PFERR_RSVD_MASK;
/*
-* Only need to check the access which is not an
-* instruction fetch and is to a user page.
+* need to check the access which is not an
+* instruction fetch and is not a rsvd fault.
*/
- check_pkey = (!ff && pte_user);
+ check_pkey = (!ff && !rsvdf);
+
/*
* write access is controlled by PKRU if it is a
* user access or CR0.WP = 1.
--
2.17.1
[RFC v2 1/7] KVM: VMX: Introduce PKS VMCS fields
PKS(Protection Keys for Supervisor Pages) is a feature that extends the
Protection Key architecture to support thread-specific permission
restrictions on supervisor pages.
A new PKS MSR(PKRS) is defined in kernel to support PKS, which holds a
set of permissions associated with each protection domian.
Two VMCS fields {HOST,GUEST}_IA32_PKRS are introduced in
{host,guest}-state area to store the value of PKRS.
Every VM exit saves PKRS into guest-state area.
If VM_EXIT_LOAD_IA32_PKRS = 1, VM exit loads PKRS from the host-state
area.
If VM_ENTRY_LOAD_IA32_PKRS = 1, VM entry loads PKRS from the guest-state
area.
Signed-off-by: Chenyi Qiang
Reviewed-by: Jim Mattson
---
arch/x86/include/asm/vmx.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index cd7de4b401fe..425cf81dd722 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -94,6 +94,7 @@
#define VM_EXIT_CLEAR_BNDCFGS 0x0080
#define VM_EXIT_PT_CONCEAL_PIP 0x0100
#define VM_EXIT_CLEAR_IA32_RTIT_CTL0x0200
+#define VM_EXIT_LOAD_IA32_PKRS 0x2000
#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
@@ -107,6 +108,7 @@
#define VM_ENTRY_LOAD_BNDCFGS 0x0001
#define VM_ENTRY_PT_CONCEAL_PIP0x0002
#define VM_ENTRY_LOAD_IA32_RTIT_CTL0x0004
+#define VM_ENTRY_LOAD_IA32_PKRS0x0040
#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x11ff
@@ -243,12 +245,16 @@ enum vmcs_field {
GUEST_BNDCFGS_HIGH = 0x2813,
GUEST_IA32_RTIT_CTL = 0x2814,
GUEST_IA32_RTIT_CTL_HIGH= 0x2815,
+ GUEST_IA32_PKRS = 0x2818,
+ GUEST_IA32_PKRS_HIGH= 0x2819,
HOST_IA32_PAT = 0x2c00,
HOST_IA32_PAT_HIGH = 0x2c01,
HOST_IA32_EFER = 0x2c02,
HOST_IA32_EFER_HIGH = 0x2c03,
HOST_IA32_PERF_GLOBAL_CTRL = 0x2c04,
HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x2c05,
+ HOST_IA32_PKRS = 0x2c06,
+ HOST_IA32_PKRS_HIGH = 0x2c07,
PIN_BASED_VM_EXEC_CONTROL = 0x4000,
CPU_BASED_VM_EXEC_CONTROL = 0x4002,
EXCEPTION_BITMAP= 0x4004,
--
2.17.1
[RFC v2 0/7] KVM: PKS Virtualization support
Protection Keys for Supervisor Pages(PKS) is a feature that extends the
Protection Keys architecture to support thread-specific permission
restrictions on supervisor pages.
PKS works similar to an existing feature named PKU(protecting user pages).
They both perform an additional check after all legacy access
permissions checks are done. If violated, #PF occurs and PFEC.PK bit will
be set. PKS introduces MSR IA32_PKRS to manage supervisor protection key
rights. The MSR contains 16 pairs of ADi and WDi bits. Each pair
advertises on a group of pages with the same key which is set in the
leaf paging-structure entries(bits[62:59]). Currently, IA32_PKRS is not
supported by XSAVES architecture.
This patchset aims to add the virtualization of PKS in KVM. It
implemented PKS CPUID enumeration, vmentry/vmexit configuration, MSR
exposure, nested supported etc. Currently, PKS is not yet supported for
shadow paging.
Detailed information about PKS can be found in the latest Intel 64 and
IA-32 Architectures Software Developer's Manual.
---
Changelogs:
v1->v2:
- rebase on the latest PKS kernel support:
https://github.com/weiny2/linux-kernel/tree/pks-rfc-v3
- add a kvm-unit-tests for PKS
- add the check in kvm_init_msr_list for PKRS
- place the X86_CR4_PKS in mmu_role_bits in kvm_set_cr4
- add the support to expose VM_{ENTRY, EXIT}_LOAD_IA32_PKRS in nested
VMX MSR
- RFC v1:
https://lore.kernel.org/lkml/20200807084841.7112-1-chenyi.qi...@intel.com/
---
Chenyi Qiang (7):
KVM: VMX: Introduce PKS VMCS fields
KVM: VMX: Expose IA32_PKRS MSR
KVM: MMU: Rename the pkru to pkr
KVM: MMU: Refactor pkr_mask to cache condition
KVM: MMU: Add support for PKS emulation
KVM: X86: Expose PKS to guest and userspace
KVM: VMX: Enable PKS for nested VM
arch/x86/include/asm/kvm_host.h | 13 ++---
arch/x86/include/asm/pkeys.h| 1 +
arch/x86/include/asm/vmx.h | 6 +++
arch/x86/kvm/cpuid.c| 3 +-
arch/x86/kvm/mmu.h | 36 +++--
arch/x86/kvm/mmu/mmu.c | 78 +++-
arch/x86/kvm/vmx/capabilities.h | 6 +++
arch/x86/kvm/vmx/nested.c | 38 +-
arch/x86/kvm/vmx/vmcs.h | 1 +
arch/x86/kvm/vmx/vmcs12.c | 2 +
arch/x86/kvm/vmx/vmcs12.h | 6 ++-
arch/x86/kvm/vmx/vmx.c | 91 +++--
arch/x86/kvm/vmx/vmx.h | 1 +
arch/x86/kvm/x86.c | 9 +++-
arch/x86/kvm/x86.h | 6 +++
arch/x86/mm/pkeys.c | 6 +++
include/linux/pkeys.h | 4 ++
17 files changed, 239 insertions(+), 68 deletions(-)
--
2.17.1
[RFC v2 5/7] KVM: MMU: Add support for PKS emulation
Advertise pkr_mask to cache the conditions where pretection key checks
for supervisor pages are needed. When the accessed pages are those with
a translation for which the U/S flag is 0 in at least one
paging-structure entry controlling the translation, they are the
supervisor pages and PKRS enforces the access rights check.
Signed-off-by: Chenyi Qiang
---
arch/x86/include/asm/kvm_host.h | 8 +++---
arch/x86/kvm/mmu.h | 12 ++---
arch/x86/kvm/mmu/mmu.c | 44 +
3 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index dd3af15e109f..d5f0c3a71a41 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -376,10 +376,10 @@ struct kvm_mmu {
u8 permissions[16];
/*
- * The pkru_mask indicates if protection key checks are needed. It
- * consists of 16 domains indexed by page fault error code bits [4:1],
- * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
- * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
+ * The pkr_mask indicates if protection key checks are needed.
+ * It consists of 16 domains indexed by page fault error code
+ * bits[4:1]. Each domain has 2 bits which are ANDed with AD
+ * and WD from PKRU/PKRS.
*/
u32 pkr_mask;
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 597b9159c10b..aca1fc7f1ad7 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -197,15 +197,19 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu,
struct kvm_mmu *mmu,
WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
if (unlikely(mmu->pkr_mask)) {
u32 pkr_bits, offset;
+ u64 pkrs;
/*
- * PKRU defines 32 bits, there are 16 domains and 2
- * attribute bits per domain in pkru. pte_pkey is the
- * index of the protection domain, so pte_pkey * 2 is
- * is the index of the first bit for the domain.
+ * PKRU and PKRS both define 32 bits. There are 16 domains
+ * and 2 attribute bits per domain in them. pte_key is the
+ * index of the protection domain, so pte_pkey * 2 is the
+ * index of the first bit for the domain. The choice of
+ * PKRU and PKRS is determined by the accessed pages.
*/
if (pte_access & PT_USER_MASK)
pkr_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
+ else if (!kvm_get_msr(vcpu, MSR_IA32_PKRS, ))
+ pkr_bits = (pkrs >> (pte_pkey * 2)) & 3;
else
pkr_bits = 0;
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index f9814ab0596d..3614952a8c7e 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4672,28 +4672,29 @@ static void update_permission_bitmask(struct kvm_vcpu
*vcpu,
}
/*
-* PKU is an additional mechanism by which the paging controls access to
-* user-mode addresses based on the value in the PKRU register. Protection
-* key violations are reported through a bit in the page fault error code.
+* Protection Keys (PKEY) is an additional mechanism by which
+* the paging controls access to user-mode/supervisor-mode address
+* based on the values in PKEY registers (PKRU/PKRS). Protection key
+* violations are reported through a bit in the page fault error code.
* Unlike other bits of the error code, the PK bit is not known at the
* call site of e.g. gva_to_gpa; it must be computed directly in
-* permission_fault based on two bits of PKRU, on some machine state (CR4,
-* CR0, EFER, CPL), and on other bits of the error code and the page tables.
+* permission_fault based on two bits of PKRU/PKRS, on some machine
+* state (CR4, CR0, EFER, CPL), and on other bits of the error code
+* and the page tables.
*
* In particular the following conditions come from the error code, the
* page tables and the machine state:
-* - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
+* - PK is always zero unless CR4.PKE=1/CR4.PKS=1 and EFER.LMA=1
* - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
-* - PK is always zero if U=0 in the page tables
-* - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
+* - (PKRU/PKRS).WD is ignored if CR0.WP=0 and the access is a supervisor
access.
*
-* The PKRU bitmask caches the result of these four conditions. The error
-* code (minus the P bit) and the page table's U bit form an index into the
-* PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
-* with the two bits of the PKRU register corresponding to the protection key.
-* For the first three conditions above the bits will be 00, thus masking
-* away both AD and WD. For all reads or if the last condition holds, WD
-* only
[RFC v2 6/7] KVM: X86: Expose PKS to guest and userspace
Existence of PKS is enumerated via CPUID.(EAX=7H,ECX=0):ECX[31]. It is
enabled by setting CR4.PKS when long mode is active. PKS is only
implemented when EPT is enabled and requires the support of VM_{ENTRY,
EXIT}_LOAD_IA32_PKRS currently.
Signed-off-by: Chenyi Qiang
---
arch/x86/include/asm/kvm_host.h | 3 ++-
arch/x86/kvm/cpuid.c| 3 ++-
arch/x86/kvm/vmx/vmx.c | 15 ---
arch/x86/kvm/x86.c | 9 +++--
4 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index d5f0c3a71a41..d798433a2117 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -99,7 +99,8 @@
| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR |
X86_CR4_PCIDE \
| X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
- | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
+ | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
+ | X86_CR4_PKS))
#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 3fd6eec202d7..6b725a3e84ec 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -354,7 +354,8 @@ void kvm_set_cpu_caps(void)
F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
- F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/
+ F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
+ 0 /*PKS*/
);
/* Set LA57 based on hardware capability. */
if (cpuid_ecx(7) & F(LA57))
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index e5da5dbe19d4..ce24226e1aa3 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -3228,7 +3228,7 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
}
/*
-* SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
+* SMEP/SMAP/PKU/PKS is disabled if CPU is in non-paging mode in
* hardware. To emulate this behavior, SMEP/SMAP/PKU needs
* to be manually disabled when guest switches to non-paging
* mode.
@@ -3236,10 +3236,11 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long
cr4)
* If !enable_unrestricted_guest, the CPU is always running
* with CR0.PG=1 and CR4 needs to be modified.
* If enable_unrestricted_guest, the CPU automatically
-* disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
+* disables SMEP/SMAP/PKU/PKS when the guest sets CR0.PG=0.
*/
if (!is_paging(vcpu))
- hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
+ hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE |
+ X86_CR4_PKS);
}
vmcs_writel(CR4_READ_SHADOW, cr4);
@@ -7430,6 +7431,14 @@ static __init void vmx_set_cpu_caps(void)
if (vmx_pt_mode_is_host_guest())
kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
+ /*
+* PKS is not yet implemented for shadow paging.
+* If not support VM_{ENTRY, EXIT}_LOAD_IA32_PKRS,
+* don't expose the PKS as well.
+*/
+ if (enable_ept && cpu_has_load_ia32_pkrs())
+ kvm_cpu_cap_check_and_set(X86_FEATURE_PKS);
+
if (vmx_umip_emulated())
kvm_cpu_cap_set(X86_FEATURE_UMIP);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index ce856e0ece84..93ac708e951d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -976,7 +976,8 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
unsigned long old_cr4 = kvm_read_cr4(vcpu);
unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
X86_CR4_SMEP;
- unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE;
+ unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE |
+ X86_CR4_PKS;
if (kvm_valid_cr4(vcpu, cr4))
return 1;
@@ -1207,7 +1208,7 @@ static const u32 msrs_to_save_all[] = {
MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
- MSR_IA32_UMWAIT_CONTROL,
+ MSR_IA32_UMWAIT_CONTROL, MSR_IA32_PKRS,
MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
@@ -5426,6 +5427,10 @@
Re: [PATCH v2 2/3] dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings.
Quoting Taniya Das (2020-10-13 10:11:49) > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml > b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml > new file mode 100644 > index 000..07bd38e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Camera Clock & Reset Controller Binding for SC7180 > + > +maintainers: > + - Taniya Das > + > +description: | > + Qualcomm camera clock control module which supports the clocks, resets and > + power domains on SC7180. > + > + See also: > + - dt-bindings/clock/qcom,camcc-sc7180.h. Maybe just - dt-bindings/clock/qcom,camcc-sc7180.h so that us copy/pasters don't have to delete anything. > + > +properties: > + compatible: > +const: qcom,sc7180-camcc > + > + clocks: > +items: > + - description: Board XO source > + - description: Camera_ahb clock from GCC > + - description: Camera XO clock from GCC > +
Re: [PATCH RFC V3 3/9] x86/pks: Enable Protection Keys Supervisor (PKS)
On Tue, Oct 13, 2020 at 11:23:08AM -0700, Dave Hansen wrote:
> On 10/9/20 12:42 PM, ira.we...@intel.com wrote:
> > +/*
> > + * PKS is independent of PKU and either or both may be supported on a CPU.
> > + * Configure PKS if the cpu supports the feature.
> > + */
>
> Let's at least be consistent about CPU vs. cpu in a single comment. :)
Sorry, done.
>
> > +static void setup_pks(void)
> > +{
> > + if (!IS_ENABLED(CONFIG_ARCH_HAS_SUPERVISOR_PKEYS))
> > + return;
> > + if (!cpu_feature_enabled(X86_FEATURE_PKS))
> > + return;
>
> If you put X86_FEATURE_PKS in disabled-features.h, you can get rid of
> the explicit CONFIG_ check.
Done.
>
> > + cr4_set_bits(X86_CR4_PKS);
> > +}
> > +
> > /*
> > * This does the hard work of actually picking apart the CPU stuff...
> > */
> > @@ -1544,6 +1558,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
> >
> > x86_init_rdrand(c);
> > setup_pku(c);
> > + setup_pks();
> >
> > /*
> > * Clear/Set all flags overridden by options, need do it
> > diff --git a/mm/Kconfig b/mm/Kconfig
> > index 6c974888f86f..1b9bc004d9bc 100644
> > --- a/mm/Kconfig
> > +++ b/mm/Kconfig
> > @@ -822,6 +822,8 @@ config ARCH_USES_HIGH_VMA_FLAGS
> > bool
> > config ARCH_HAS_PKEYS
> > bool
> > +config ARCH_HAS_SUPERVISOR_PKEYS
> > + bool
> >
> > config PERCPU_STATS
> > bool "Collect percpu memory statistics"
> >
>
Re: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Quoting Taniya Das (2020-10-13 10:11:48)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..17e1fc0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops =
> {
> .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
> +
> +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap
> *regmap,
> + const struct alpha_pll_config *config)
> +{
> + if (config->l)
> + regmap_write(regmap, PLL_L_VAL(pll), config->l);
Maybe make a helper function for this too. That way we can't mix up the
if condition with the value in the write.
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
static void clk_alpha_pll_write_config(struct regmap *regmap,
unsigned int reg,
unsigned int val) {
if (val)
regmap_write(regmap, reg, val);
}
and how are we so lucky that zero isn't a value that we may need to
write?
> +
> + if (config->alpha)
> + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> + if (config->user_ctl_val)
> + regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
> +
> + if (config->config_ctl_val)
> + regmap_write(regmap, PLL_CONFIG_CTL(pll),
> + config->config_ctl_val);
> +
> + if (config->config_ctl_hi_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> + config->config_ctl_hi_val);
> +
> + if (config->test_ctl_val)
> + regmap_write(regmap, PLL_TEST_CTL(pll),
> + config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val)
> + regmap_write(regmap, PLL_TEST_CTL_U(pll),
> + config->test_ctl_hi_val);
> +}
> +EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
> +
> +static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long
> rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l, alpha_width = pll_alpha_width(pll);
> + unsigned long rrate, max = rate + PLL_RATE_MARGIN;
> + u64 a;
> +
> + rrate = alpha_pll_round_rate(rate, prate, , , alpha_width);
> +
> + /*
> +* Due to limited number of bits for fractional rate programming, the
> +* rounded up rate could be marginally higher than the requested rate.
> +*/
> + if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
> + pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
> + clk_hw_get_name(hw), rrate, rate, max);
> + return -EINVAL;
> + }
Can this be extracted into a helper function?
> +
> + /* change L_VAL without having to go through the power on sequence */
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> +
> + if (clk_hw_is_enabled(hw))
> + return wait_for_pll_enable_lock(pll);
> +
> + return 0;
> +}
> +
Re: [PATCH v3 7/7] selftests/ftrace: Add test case for synthetic event syntax errors
Hi Tom,
On Tue, 13 Oct 2020 09:17:58 -0500
Tom Zanussi wrote:
> Add a selftest that verifies that the syntax error messages and caret
> positions are correct for most of the possible synthetic event syntax
> error cases.
>
> Signed-off-by: Tom Zanussi
> ---
> .../trigger-synthetic_event_syntax_errors.tc | 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644
> tools/testing/selftests/ftrace/test.d/trigger/inter-event/trigger-synthetic_event_syntax_errors.tc
>
> diff --git
> a/tools/testing/selftests/ftrace/test.d/trigger/inter-event/trigger-synthetic_event_syntax_errors.tc
>
> b/tools/testing/selftests/ftrace/test.d/trigger/inter-event/trigger-synthetic_event_syntax_errors.tc
> new file mode 100644
> index ..ada594fe16cb
> --- /dev/null
> +++
> b/tools/testing/selftests/ftrace/test.d/trigger/inter-event/trigger-synthetic_event_syntax_errors.tc
> @@ -0,0 +1,19 @@
> +#!/bin/sh
> +# SPDX-License-Identifier: GPL-2.0
> +# description: event trigger - test synthetic_events syntax parser errors
> +# requires: synthetic_events error_log
This also requires dynamic strings support. So, its "requires" line should be
# requires: synthetic_events error_log "char name[]' >> synthetic_events":README
> +
> +check_error() { # command-with-error-pos-by-^
> +ftrace_errlog_check 'synthetic_events' "$1" 'synthetic_events'
> +}
> +
BTW, some errors looks a bit odd.
> +check_error 'myevent ^chr arg' # INVALID_TYPE
> +check_error 'myevent ^char str[];; int v'# INVALID_TYPE
I think there is a wrong "void" argument between ";", instead of invalid type.
> +check_error 'myevent char ^str]; int v' # INVALID_NAME
> +check_error 'myevent char ^str;[]' # INVALID_NAME
This is also not an invalid name but '[]' is an invalid type.
> +check_error 'myevent ^char str[; int v' # INVALID_TYPE
> +check_error '^mye;vent char str[]' # BAD_NAME
> +check_error 'myevent char str[]; ^int' # INVALID_FIELD
Isn't it an incomplete command?
> +check_error '^myevent' # INCOMPLETE_CMD
> +
> +exit 0
Thank you,
> --
> 2.17.1
>
--
Masami Hiramatsu
Re: [PATCH v2 3/3] clk: qcom: camcc: Add camera clock controller driver for SC7180
Quoting Taniya Das (2020-10-13 10:11:50)
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> new file mode 100644
> index 000..e954d21
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> @@ -0,0 +1,1737 @@
[...]
> +
> +enum {
> + P_BI_TCXO,
> + P_CAM_CC_PLL0_OUT_EVEN,
> + P_CAM_CC_PLL1_OUT_EVEN,
> + P_CAM_CC_PLL2_OUT_AUX,
> + P_CAM_CC_PLL2_OUT_EARLY,
> + P_CAM_CC_PLL3_OUT_MAIN,
> + P_CORE_BI_PLL_TEST_SE,
> +};
> +
> +static struct pll_vco agera_vco[] = {
Can this be const?
> + { 6, 33, 0 },
> +};
> +
> +static struct pll_vco fabia_vco[] = {
Can this be const?
> + { 24960, 20, 0 },
> +};
> +
[...]
> +
> +static int cam_cc_sc7180_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + pm_runtime_enable(>dev);
> + ret = pm_clk_create(>dev);
> + if (ret)
> + return ret;
> +
> + ret = pm_clk_add(>dev, "xo");
> + if (ret < 0) {
> + dev_err(>dev, "Failed to acquire XO clock\n");
> + goto disable_pm_runtime;
> + }
> +
> + ret = pm_clk_add(>dev, "iface");
> + if (ret < 0) {
> + dev_err(>dev, "Failed to acquire iface clock\n");
> + goto disable_pm_runtime;
> + }
> +
> + ret = pm_clk_runtime_resume(>dev);
> + if (ret) {
> + dev_err(>dev, "pm runtime resume failed\n");
> + goto destroy_pm_clk;
> + }
> +
> + regmap = qcom_cc_map(pdev, _cc_sc7180_desc);
> + if (IS_ERR(regmap)) {
> + ret = PTR_ERR(regmap);
> + goto destroy_pm_clk;
> + }
> +
> + clk_fabia_pll_configure(_cc_pll0, regmap, _cc_pll0_config);
> + clk_fabia_pll_configure(_cc_pll1, regmap, _cc_pll1_config);
> + clk_agera_pll_configure(_cc_pll2, regmap, _cc_pll2_config);
> + clk_fabia_pll_configure(_cc_pll3, regmap, _cc_pll3_config);
> +
> + ret = qcom_cc_really_probe(pdev, _cc_sc7180_desc, regmap);
> + if (ret) {
> + dev_err(>dev, "Failed to register CAM CC clocks\n");
> + goto suspend_pm_runtime;
ret is non-zero here
> + }
> +
> +suspend_pm_runtime:
> + ret = pm_clk_runtime_suspend(>dev);
But then it is overwritten here.
> + if (ret)
> + dev_err(>dev, "pm runtime suspend failed\n");
> +
> + return 0;
And we return 0 when there was a failure to probe the clks?
> +
> +destroy_pm_clk:
> + pm_clk_destroy(>dev);
> +
> +disable_pm_runtime:
> + pm_runtime_disable(>dev);
> +
> + return ret;
> +}
Re: [PATCH v2 02/24] tools: docs: memory-model: fix references for some files
On Tue, Oct 13, 2020 at 12:38:36PM -0400, Alan Stern wrote: > On Tue, Oct 13, 2020 at 09:33:54AM -0700, Paul E. McKenney wrote: > > On Tue, Oct 13, 2020 at 02:14:29PM +0200, Mauro Carvalho Chehab wrote: > > > - The sysfs.txt file was converted to ReST and renamed; > > > - The control-dependencies.txt is not at > > > Documentation/control-dependencies.txt. As it is at the > > > same dir as the README file, which mentions it, just > > > remove Documentation/. > > > > > > With that, ./scripts/documentation-file-ref-check script > > > is now happy again for files under tools/. > > > > > > Signed-off-by: Mauro Carvalho Chehab > > > > Queued for review and testing, likely target v5.11. > > Instead of changing the path in the README reference, shouldn't > tools/memory-model/control-dependencies.txt be moved to its proper > position in .../Documentation? You are of course quite right. My thought is to let Mauro go ahead, given his short deadline. We can then make this "git mv" change once v5.10-rc1 comes out, given that it should have Mauro's patches. I have added a reminder to my calendar. Thanx, Paul
Re: [PATCH v6 70/80] rcu/tree: docs: document bkvcache new members at struct kfree_rcu_cpu
On Tue, Oct 13, 2020 at 10:46:08PM +0200, Mauro Carvalho Chehab wrote:
> Em Tue, 13 Oct 2020 09:34:04 -0700
> "Paul E. McKenney" escreveu:
>
> > On Tue, Oct 13, 2020 at 01:54:25PM +0200, Mauro Carvalho Chehab wrote:
> > > Changeset 53c72b590b3a ("rcu/tree: cache specified number of objects")
> > > added new members for struct kfree_rcu_cpu, but didn't add the
> > > corresponding at the kernel-doc markup, as repoted when doing
> > > "make htmldocs":
> > > ./kernel/rcu/tree.c:3113: warning: Function parameter or member
> > > 'bkvcache' not described in 'kfree_rcu_cpu'
> > > ./kernel/rcu/tree.c:3113: warning: Function parameter or member
> > > 'nr_bkv_objs' not described in 'kfree_rcu_cpu'
> > >
> > > So, move the description for bkvcache to kernel-doc, and add a
> > > description for nr_bkv_objs.
> > >
> > > Fixes: 53c72b590b3a ("rcu/tree: cache specified number of objects")
> > > Signed-off-by: Mauro Carvalho Chehab
> >
> > Queued for review and testing, likely target v5.11.
>
> Hi Paul,
>
> I would prefer if we could get those on 5.10, if possible.
> We're aiming to have 5.10 free of docs warnings ;-)
>
> If you prefer, I can send those patches to Linus with your
> ack.
That sounds easier:
Acked-by: Paul E. McKenney
Alan's objection is quite valid, but we will address that issue in a
follow-on patch that will not be on the fast track.
Thanx, Paul
> Regards,
> Mauro
>
> >
> > Thanx, Paul
> >
> > > ---
> > > kernel/rcu/tree.c | 14 ++
> > > 1 file changed, 6 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> > > index f78ee759af9c..03c54c3478b7 100644
> > > --- a/kernel/rcu/tree.c
> > > +++ b/kernel/rcu/tree.c
> > > @@ -3022,6 +3022,12 @@ struct kfree_rcu_cpu_work {
> > > * @monitor_todo: Tracks whether a @monitor_work delayed work is pending
> > > * @initialized: The @rcu_work fields have been initialized
> > > * @count: Number of objects for which GP not started
> > > + * @bkvcache:
> > > + * A simple cache list that contains objects for reuse purpose.
> > > + * In order to save some per-cpu space the list is singular.
> > > + * Even though it is lockless an access has to be protected by the
> > > + * per-cpu lock.
> > > + * @nr_bkv_objs: number of allocated objects at @bkvcache.
> > > *
> > > * This is a per-CPU structure. The reason that it is not included in
> > > * the rcu_data structure is to permit this code to be extracted from
> > > @@ -3037,14 +3043,6 @@ struct kfree_rcu_cpu {
> > > bool monitor_todo;
> > > bool initialized;
> > > int count;
> > > -
> > > - /*
> > > - * A simple cache list that contains objects for
> > > - * reuse purpose. In order to save some per-cpu
> > > - * space the list is singular. Even though it is
> > > - * lockless an access has to be protected by the
> > > - * per-cpu lock.
> > > - */
> > > struct llist_head bkvcache;
> > > int nr_bkv_objs;
> > > };
> > > --
> > > 2.26.2
> > >
>
>
>
> Thanks,
> Mauro
Re: [PATCH 2/6] dt-bindings: mfd: google,cros-ec: explicitly allow additional properties
On 2020/10/14 1:53, Dan Murphy wrote: > Zhen > > On 10/13/20 11:08 AM, Zhen Lei wrote: >> There are so many properties have not been described in this yaml file, >> and a lot of errors will be reported. Especially, some yaml files such as >> google,cros-ec-typec.yaml, extcon-usbc-cros-ec.yaml can not pass the >> self-check, because of the examples. So temporarily allow additional >> properties to keep the comprehensive dt_binding_check result clean. > > My preference is to fix the binding to pass the checks and not just work > around the issues. Working around the issues may mean the issues never get > fixed. I agree with your first sentence：don't just work around the issues. But these errors are so annoying. Hope someone can add the description of the missing properties. I'm not familiar with this module anyway. And I don't fully agree with your last sentence. After all, the main properties are listed, and the ones that are not listed should be minor ones. > > Dan > > > . >
Re: [PATCH v2 3/4] clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
Quoting Srinivas Kandagatla (2020-09-25 03:31:14)
> GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros.
> This patch adds support to these muxes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/clk/qcom/Kconfig| 6 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/lpass-gfm-sm8250.c | 260
> 3 files changed, 267 insertions(+)
> create mode 100644 drivers/clk/qcom/lpass-gfm-sm8250.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 058327310c25..08078f4b0591 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -475,4 +475,10 @@ config KRAITCC
> Support for the Krait CPU clocks on Qualcomm devices.
> Say Y if you want to support CPU frequency scaling.
>
> +config CLK_GFM_LPASS_SM8250
> + tristate "GFM LPASS Clocks"
Can we get SM8250 in the name? And also sort this into the other SoC
compatible strings with a name that matches how it's been done
otherwise. I guess CONFIG_SM_LPASS_8250? GFM for Glitch Free Mux doesn't
seem very important unless it is actually part of the device name?
> + help
> + Support for the GFM Glitch Free Mux LPASS clock. Say Y
I'd write "Support for the Glitch Free Mux (GFM) Low power audio
subsystem (LPASS) clocks found on SM8250 SoCs."
> + if you want to support GFM Clocks on LPASS for SM8250 SoC.
> +
> endif
> diff --git a/drivers/clk/qcom/lpass-gfm-sm8250.c
> b/drivers/clk/qcom/lpass-gfm-sm8250.c
> new file mode 100644
> index ..c79854e1494d
> --- /dev/null
> +++ b/drivers/clk/qcom/lpass-gfm-sm8250.c
> @@ -0,0 +1,260 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * LPASS Audio CC and Always ON CC Glitch Free Mux clock driver
> + *
> + * Copyright (c) 2020 Linaro Ltd.
> + * Author: Srinivas Kandagatla
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
Is this include used?
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static struct clk_gfm lpass_gfm_wsa_mclk = {
> + .mux_reg = 0x220d8,
> + .mux_mask = BIT(0),
> + .hw.init = &(struct clk_init_data) {
> + .name = "WSA_MCLK",
> + .ops = _gfm_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> + .parent_data = (const struct clk_parent_data[]){
> + {
> + .index = 0,
> + .name = "LPASS_CLK_ID_TX_CORE_MCLK",
Can these use .fw_name instead of .name? The .fw_name is the future and
.name is for drivers that don't use DT bindings or existed before we
parsed clks from DT in the core.
> + }, {
> + .index = 1,
> + .name = "LPASS_CLK_ID_WSA_CORE_MCLK",
> + },
> + },
> + .num_parents = 2,
> + },
> +};
> +
[...]
> +static int lpass_gfm_clk_driver_probe(struct platform_device *pdev)
> +{
> + const struct lpass_gfm_data *data;
> + struct device *dev = >dev;
> + struct resource *res;
> + struct clk_gfm *gfm;
> + struct lpass_gfm *cc;
> + int err, i;
> +
> + data = of_device_get_match_data(dev);
> + if (!data)
> + return -EINVAL;
> +
> + cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
> + if (!cc)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + cc->base = devm_ioremap_resource(dev, res);
devm_platform_ioremap_resource()
> + if (IS_ERR(cc->base))
> + return PTR_ERR(cc->base);
> +
> + pm_runtime_enable(dev);
> + err = pm_clk_create(dev);
> + if (err)
> + goto pm_clk_err;
> +
> + err = of_pm_clk_add_clks(dev);
> + if (err < 0) {
> + dev_dbg(dev, "Failed to get lpass core voting clocks\n");
> + goto clk_reg_err;
> + }
> +
> + for (i = 0; i < data->onecell_data->num; i++) {
> + if (!data->gfm_clks[i])
> + continue;
> +
> + gfm = data->gfm_clks[i];
> + gfm->priv = cc;
> + gfm->gfm_mux = cc->base;
> + gfm->gfm_mux = gfm->gfm_mux + data->gfm_clks[i]->mux_reg;
> +
> + err = devm_clk_hw_register(dev, >gfm_clks[i]->hw);
> + if (err)
> + goto clk_reg_err;
> +
> + }
> +
> + err = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + data->onecell_data);
> + if (err)
> + goto clk_reg_err;
> +
> + return 0;
> +
> +clk_reg_err:
> + pm_clk_destroy(dev);
> +pm_clk_err:
> + pm_runtime_disable(dev);
> + return err;
> +}
> +
Re: [PATCH v2] drm/of: Consider the state in which the ep is disabled
Hi Maintainers,
Does this patch ready to merge?
On 2020/7/7 下午7:25, Sandy Huang wrote:
don't mask possible_crtcs if remote-point is disabled.
Signed-off-by: Sandy Huang
---
drivers/gpu/drm/drm_of.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index fdb05fbf72a0..565f05f5f11b 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -66,6 +66,9 @@ uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
uint32_t possible_crtcs = 0;
for_each_endpoint_of_node(port, ep) {
+ if (!of_device_is_available(ep))
+ continue;
+
remote_port = of_graph_get_remote_port(ep);
if (!remote_port) {
of_node_put(ep);
Looks good to me.
Reviewed-by: Kever Yang
Thanks,
- Kever
Re: [PATCH v2 0/4] clk: qcom : add sm8250 LPASS GFM drivers
Quoting Srinivas Kandagatla (2020-09-25 03:31:11) > This patchset adds support for GFM Muxes found in LPASS > (Low Power Audio SubSystem) IP in Audio Clock Controller > and Always ON clock controller. > > Clocks derived from these muxes are consumed by LPASS Digital Codec. > Currently the driver for Audio and Always ON clock controller only > supports GFM Muxes, however it should be easy to add more clock > support when required > > Changes since v1: > -removed unnecessary Kconfig dependencies > - cleaned up header includes. > - moved to using pm_clk > - Moved to right place in Makefile > - moved to use module_platform_driver instead of builtin_platform_driver > - add null check for of_device_get_match_data > > verified dt_binding_check to pass on linux next > https://paste.ubuntu.com/p/6nVzjRwvsW/ Rob's bot complained again. Can you run with make DT_SCHEMA_FILES= dt_binding_check and make sure the schema is up to date?
[tip:sched/urgent] BUILD SUCCESS da912c29a4a552588cbfa895487d9d5523b6faa7
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git sched/urgent branch HEAD: da912c29a4a552588cbfa895487d9d5523b6faa7 sched/features: Fix !CONFIG_JUMP_LABEL case elapsed time: 724m configs tested: 103 configs skipped: 2 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm64 defconfig arm defconfig arm64allyesconfig arm allyesconfig arm allmodconfig sh kfr2r09_defconfig mips bmips_be_defconfig m68kmvme147_defconfig openrisc simple_smp_defconfig shsh7763rdp_defconfig powerpc tqm8555_defconfig powerpc eiger_defconfig ia64 alldefconfig powerpc mpc866_ads_defconfig shtitan_defconfig armhisi_defconfig powerpc ppa8548_defconfig m68k atari_defconfig arm cns3420vb_defconfig xtensa defconfig sh ecovec24_defconfig m68k multi_defconfig arm davinci_all_defconfig arm pxa3xx_defconfig armdove_defconfig sh shx3_defconfig arm lpd270_defconfig ia64 allmodconfig powerpc mpc8272_ads_defconfig mipsqi_lb60_defconfig arm h5000_defconfig powerpc tqm8540_defconfig armmini2440_defconfig sparc sparc32_defconfig powerpc mpc836x_mds_defconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig parisc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a005-20201013 i386 randconfig-a006-20201013 i386 randconfig-a001-20201013 i386 randconfig-a003-20201013 i386 randconfig-a004-20201013 i386 randconfig-a002-20201013 i386 randconfig-a016-20201013 i386 randconfig-a015-20201013 i386 randconfig-a013-20201013 i386 randconfig-a012-20201013 i386 randconfig-a011-20201013 i386 randconfig-a014-20201013 x86_64 randconfig-a004-20201013 x86_64 randconfig-a002-20201013 x86_64 randconfig-a006-20201013 x86_64 randconfig-a001-20201013 x86_64 randconfig-a003-20201013 x86_64 randconfig-a005-20201013 riscvnommu_k210_defconfig riscvallyesconfig riscvnommu_virt_defconfig riscv allnoconfig riscv defconfig riscv rv32_defconfig riscvallmodconfig x86_64 rhel x86_64 allyesconfig x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 kexec clang tested configs: x86_64 randconfig-a016-20201013 x86_64 randconfig-a015-20201013 x86_64 randconfig-a012-20201013 x86_64
[tip:x86/asm] BUILD SUCCESS 3e626682046e30282979f7d71e054cd4c00069a7
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm branch HEAD: 3e626682046e30282979f7d71e054cd4c00069a7 x86/asm: Replace __force_order with a memory clobber elapsed time: 724m configs tested: 132 configs skipped: 84 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig sh se7206_defconfig m68k m5249evb_defconfig archsdk_defconfig h8300h8300h-sim_defconfig microblazenommu_defconfig shsh7763rdp_defconfig powerpc tqm8555_defconfig powerpc eiger_defconfig ia64 alldefconfig powerpc tqm5200_defconfig arc nps_defconfig arm versatile_defconfig powerpcmpc7448_hpc2_defconfig powerpc mpc866_ads_defconfig shtitan_defconfig armhisi_defconfig powerpc ppa8548_defconfig parisc defconfig powerpc holly_defconfig mips capcella_defconfig powerpc katmai_defconfig arm iop32x_defconfig arm pxa3xx_defconfig sh rsk7203_defconfig powerpc ep88xc_defconfig powerpc linkstation_defconfig arm pxa168_defconfig sh magicpanelr2_defconfig sh allmodconfig sh sdk7786_defconfig mips pistachio_defconfig shsh7785lcr_defconfig shedosk7705_defconfig arm hackkit_defconfig sh ap325rxa_defconfig arm corgi_defconfig arm h3600_defconfig ia64defconfig armmulti_v7_defconfig powerpc mgcoge_defconfig arm zx_defconfig powerpc currituck_defconfig xtensa alldefconfig microblaze mmu_defconfig arm davinci_all_defconfig armdove_defconfig sh shx3_defconfig arm lpd270_defconfig xtensageneric_kc705_defconfig c6xevmc6474_defconfig mipsbcm63xx_defconfig ia64 allmodconfig powerpc mpc8272_ads_defconfig mipsqi_lb60_defconfig arm h5000_defconfig powerpc tqm8540_defconfig armmini2440_defconfig sparc sparc32_defconfig powerpc mpc836x_mds_defconfig arm bcm2835_defconfig powerpc pasemi_defconfig mips bmips_be_defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig x86_64 randconfig-a004-20201013 x86_64 randconfig-a002-20201013 x86_64 randconfig-a006-20201013 x86_64 randconfig-a001-20201013 x86_64 randconfig-a003-20201013 x86_64
[tip:objtool/core] BUILD SUCCESS ab0a40ea88204e1291b56da8128e2845fec8ee88
defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig parisc defconfig s390 allyesconfig parisc allyesconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig x86_64 randconfig-a004-20201013 x86_64 randconfig-a002-20201013 x86_64 randconfig-a006-20201013 x86_64 randconfig-a001-20201013 x86_64 randconfig-a003-20201013 x86_64 randconfig-a005-20201013 i386 randconfig-a005-20201013 i386 randconfig-a006-20201013 i386 randconfig-a001-20201013 i386 randconfig-a003-20201013 i386 randconfig-a004-20201013 i386 randconfig-a002-20201013 i386 randconfig-a016-20201013 i386 randconfig-a015-20201013 i386 randconfig-a013-20201013 i386 randconfig-a012-20201013 i386 randconfig-a011-20201013 i386 randconfig-a014-20201013 riscvnommu_k210_defconfig riscvallyesconfig riscvnommu_virt_defconfig riscv allnoconfig riscv defconfig riscv rv32_defconfig riscvallmodconfig x86_64 rhel x86_64 allyesconfig x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 kexec clang tested configs: x86_64 randconfig-a016-20201013 x86_64 randconfig-a015-20201013 x86_64 randconfig-a012-20201013 x86_64 randconfig-a013-20201013 x86_64 randconfig-a014-20201013 x86_64 randconfig-a011-20201013 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[tip:master] BUILD SUCCESS 2c8a2700c3256eefe1e783a104b420af09424e54
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git master branch HEAD: 2c8a2700c3256eefe1e783a104b420af09424e54 Merge branch 'objtool/core' elapsed time: 724m configs tested: 93 configs skipped: 2 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm defconfig arm64allyesconfig arm allyesconfig arm allmodconfig arm64 defconfig sh kfr2r09_defconfig mips bmips_be_defconfig m68kmvme147_defconfig openrisc simple_smp_defconfig m68k atari_defconfig arm cns3420vb_defconfig xtensa defconfig sh ecovec24_defconfig m68k multi_defconfig powerpc mgcoge_defconfig arm zx_defconfig powerpc currituck_defconfig xtensa alldefconfig microblaze mmu_defconfig arc haps_hs_smp_defconfig sh alldefconfig powerpc g5_defconfig riscvnommu_virt_defconfig m68kmac_defconfig microblaze defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig parisc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a005-20201013 i386 randconfig-a006-20201013 i386 randconfig-a001-20201013 i386 randconfig-a003-20201013 i386 randconfig-a004-20201013 i386 randconfig-a002-20201013 x86_64 randconfig-a004-20201013 x86_64 randconfig-a002-20201013 x86_64 randconfig-a006-20201013 x86_64 randconfig-a001-20201013 x86_64 randconfig-a003-20201013 x86_64 randconfig-a005-20201013 i386 randconfig-a016-20201013 i386 randconfig-a015-20201013 i386 randconfig-a013-20201013 i386 randconfig-a012-20201013 i386 randconfig-a011-20201013 i386 randconfig-a014-20201013 riscvnommu_k210_defconfig riscvallyesconfig riscv allnoconfig riscv defconfig riscv rv32_defconfig riscvallmodconfig x86_64 rhel x86_64 allyesconfig x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 kexec clang tested configs: x86_64 randconfig-a016-20201013 x86_64 randconfig-a015-20201013 x86_64 randconfig-a012-20201013 x86_64 randconfig-a013-20201013 x86_64 randconfig-a014-20201013 x86_64 randconfig-a011-20201013 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [PATCH v5 3/5] counter: Add character device interface
On 9/26/20 9:18 PM, William Breathitt Gray wrote:
This patch introduces a character device interface for the Counter
subsystem. Device data is exposed through standard character device read
operations. Device data is gathered when a Counter event is pushed by
the respective Counter device driver. Configuration is handled via ioctl
operations on the respective Counter character device node.
Probably don't need to duplicate the full documentation in the commit
message.
diff --git a/drivers/counter/counter-chrdev.c b/drivers/counter/counter-chrdev.c
new file mode 100644
index ..2be3846e4105
--- /dev/null
+++ b/drivers/counter/counter-chrdev.c
+
+static int counter_set_event_node(struct counter_device *const counter,
+ struct counter_watch *const watch,
+ const struct counter_comp_node *const cfg)
+{
+ struct counter_event_node *event_node;
+ int err;
+ struct counter_comp_node *comp_node;
+
+ /* Search for event in the list */
+ list_for_each_entry(event_node, >next_events_list, l)
+ if (event_node->event == watch->event &&
+ event_node->channel == watch->channel)
+ break;
+
+ /* If event is not already in the list */
+ if (_node->l == >next_events_list) {
+ /* Allocate new event node */
+ event_node = kmalloc(sizeof(*event_node), GFP_ATOMIC);
+ if (!event_node)
+ return -ENOMEM;
+
+ /* Configure event node and add to the list */
+ event_node->event = watch->event;
+ event_node->channel = watch->channel;
+ INIT_LIST_HEAD(_node->comp_list);
+ list_add(_node->l, >next_events_list);
+ }
+
+ /* Check if component watch has already been set before */
+ list_for_each_entry(comp_node, _node->comp_list, l)
+ if (comp_node->parent == cfg->parent &&
+ comp_node->comp.count_u8_read == cfg->comp.count_u8_read)
+ return -EINVAL;
There are already enough things that could cause EINVAL, we could
probably skip this duplicate check to make troubleshooting easier.
+
+ /* Allocate component node */
+ comp_node = kmalloc(sizeof(*comp_node), GFP_ATOMIC);
+ if (!comp_node) {
+ err = -ENOMEM;
+ goto err_comp_node;
Since there is only one goto, we could just handle the error and
return here instead.
+ }
+ *comp_node = *cfg;
+
+ /* Add component node to event node */
+ list_add_tail(_node->l, _node->comp_list);
+
+ return 0;
+
+err_comp_node:
A comment explaining the list_empty() check would be nice.
It makes sense if you think about it, but it is not super
obvious.
+ if (list_empty(_node->comp_list)) {
+ list_del(_node->l);
+ kfree(event_node);
+ }
+ return err;
+}
+
+static int counter_set_watch(struct counter_device *const counter,
+const unsigned long arg)
+{
+ void __user *const uwatch = (void __user *)arg;
+ struct counter_watch watch;
+ struct counter_comp_node comp_node;
+ size_t parent, id;
+ struct counter_comp *ext;
+ size_t num_ext;
+
+ if (copy_from_user(, uwatch, sizeof(watch)))
+ return -EFAULT;
+ parent = watch.component.parent;
+ id = watch.component.id;
+
+ /* Configure parent component info for comp node */
+ switch (watch.component.scope) {
+ case COUNTER_SCOPE_DEVICE:
+ comp_node.parent = NULL;
+
+ ext = counter->ext;
+ num_ext = counter->num_ext;
+ break;
+ case COUNTER_SCOPE_SIGNAL:
+ if (counter->num_signals < parent + 1)
I think it would be more conventional this way:
if (parent >= counter->num_signals)
+ return -EINVAL;
+
+ comp_node.parent = counter->signals + parent;
+
+ ext = counter->signals[parent].ext;
+ num_ext = counter->signals[parent].num_ext;
+ break;
+ case COUNTER_SCOPE_COUNT:
+ if (counter->num_counts < parent + 1)
Same here.
+ return -EINVAL;
+
+ comp_node.parent = counter->counts + parent;
+
+ ext = counter->counts[parent].ext;
+ num_ext = counter->counts[parent].num_ext;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Configure component info for comp node */
+ switch (watch.component.type) {
+ case COUNTER_COMPONENT_SIGNAL:
+ if (watch.component.scope != COUNTER_SCOPE_SIGNAL)
+ return -EINVAL;
+
+ comp_node.comp.type = COUNTER_COMP_SIGNAL_LEVEL;
+ comp_node.comp.signal_u8_read =
[PATCH v2] thunderbolt: Add the missed ida_simple_remove() in ring_request_msix()
ring_request_msix() misses to call ida_simple_remove() in an error path.
Add a label 'err_ida_remove' and jump to it.
Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support")
Signed-off-by: Jing Xiangfeng
---
drivers/thunderbolt/nhi.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
index 5f7489fa1327..e066888c4b41 100644
--- a/drivers/thunderbolt/nhi.c
+++ b/drivers/thunderbolt/nhi.c
@@ -406,11 +406,22 @@ static int ring_request_msix(struct tb_ring *ring, bool
no_suspend)
ring->vector = ret;
ring->irq = pci_irq_vector(ring->nhi->pdev, ring->vector);
- if (ring->irq < 0)
- return ring->irq;
+ if (ring->irq < 0) {
+ ret = ring->irq;
+ goto err_ida_remove;
+ }
irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
- return request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
+ ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
+ if (ret)
+ goto err_ida_remove;
+
+ return 0;
+
+err_ida_remove:
+ ida_simple_remove(>msix_ida, ring->vector);
+
+ return ret;
}
static void ring_release_msix(struct tb_ring *ring)
--
2.17.1
Re: [PATCH] interconnect: qcom: Simplify the vcd compare function
On 10/13/2020 10:19 AM, Georgi Djakov wrote:
Let's simplify the cmp_vcd() function and replace the conditionals
with just a single statement, which also improves readability.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/qcom/bcm-voter.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/interconnect/qcom/bcm-voter.c
b/drivers/interconnect/qcom/bcm-voter.c
index 887d13721e52..1cc565bce2f4 100644
--- a/drivers/interconnect/qcom/bcm-voter.c
+++ b/drivers/interconnect/qcom/bcm-voter.c
@@ -41,17 +41,10 @@ struct bcm_voter {
static int cmp_vcd(void *priv, struct list_head *a, struct list_head *b)
{
- const struct qcom_icc_bcm *bcm_a =
- list_entry(a, struct qcom_icc_bcm, list);
- const struct qcom_icc_bcm *bcm_b =
- list_entry(b, struct qcom_icc_bcm, list);
-
- if (bcm_a->aux_data.vcd < bcm_b->aux_data.vcd)
- return -1;
- else if (bcm_a->aux_data.vcd == bcm_b->aux_data.vcd)
- return 0;
- else
- return 1;
+ const struct qcom_icc_bcm *bcm_a = list_entry(a, struct qcom_icc_bcm,
list);
+ const struct qcom_icc_bcm *bcm_b = list_entry(b, struct qcom_icc_bcm,
list);
+
+ return bcm_a->aux_data.vcd - bcm_b->aux_data.vcd;
}
static u64 bcm_div(u64 num, u32 base)
Reviewed-by: Mike Tipton
Re: [PATCH v1 08/10] bus: mhi: core: Move to an error state on any firmware load failure
On 2020-10-09 09:42, Manivannan Sadhasivam wrote: On Fri, Sep 18, 2020 at 07:02:33PM -0700, Bhaumik Bhatt wrote: Move MHI to a firmware download error state for a failure to find the firmware files or to load SBL or EBL image using BHI/BHIe. This helps detect an error state sooner and shortens the wait for a synchronous power up timeout. Signed-off-by: Bhaumik Bhatt --- drivers/bus/mhi/core/boot.c | 43 +-- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c index 92b8dd3..fcc71f2 100644 --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c [...] -error_read: +error_ready_state: mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); mhi_cntrl->fbc_image = NULL; -error_alloc_fw_table: - release_firmware(firmware); +error_fw_load: + write_lock_irq(_cntrl->pm_lock); + mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR; + wake_up_all(_cntrl->state_event); Do you really need pm_lock for this? Thanks, Mani Not really, the underlying usage does not matter if this lock is used or not. We just want to error out so removing it. + write_unlock_irq(_cntrl->pm_lock); } -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
[PATCH] ARM: dts: imx: add usb alias
From: Peng Fan
Add usb alias for bootloader emulator the controller in correct order.
Signed-off-by: Peng Fan
---
arch/arm/boot/dts/imx6qdl.dtsi | 4
arch/arm/boot/dts/imx6sl.dtsi | 3 +++
arch/arm/boot/dts/imx6sll.dtsi | 2 ++
arch/arm/boot/dts/imx6sx.dtsi | 3 +++
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
arch/arm/boot/dts/imx7d.dtsi | 6 ++
arch/arm/boot/dts/imx7s.dtsi | 2 ++
7 files changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 7a8837cbe21b..947584b40b1f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -45,6 +45,10 @@ aliases {
spi1 =
spi2 =
spi3 =
+ usb0 =
+ usb1 =
+ usb2 =
+ usb3 =
usbphy0 =
usbphy1 =
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 91a8c54d5e11..997b96c1c47b 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -39,6 +39,9 @@ aliases {
spi1 =
spi2 =
spi3 =
+ usb0 =
+ usb1 =
+ usb2 =
usbphy0 =
usbphy1 =
};
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 0b622201a1f3..04f8d637a501 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -36,6 +36,8 @@ aliases {
spi1 =
spi3 =
spi4 =
+ usb0 =
+ usb1 =
usbphy0 =
usbphy1 =
};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index dfdca1804f9f..343f2a3170bb 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -49,6 +49,9 @@ aliases {
spi2 =
spi3 =
spi4 =
+ usb0 =
+ usb1 =
+ usb2 =
usbphy0 =
usbphy1 =
};
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index d7d9f3e46b92..09021a35c266 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -47,6 +47,8 @@ aliases {
spi1 =
spi2 =
spi3 =
+ usb0 =
+ usb1 =
usbphy0 =
usbphy1 =
};
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index cff875b80b60..b0bcfa9094a3 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -7,6 +7,12 @@
#include
/ {
+ aliases {
+ usb0 =
+ usb1 =
+ usb2 =
+ };
+
cpus {
cpu0: cpu@0 {
clock-frequency = <99600>;
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 84d9cc13afb9..358ef453ce14 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -47,6 +47,8 @@ aliases {
spi1 =
spi2 =
spi3 =
+ usb0 =
+ usb1 =
};
cpus {
--
2.28.0
Re: [PATCH v4 2/2] clk: qcom: Add display clock controller driver for SM8150 and SM8250
Quoting Jonathan Marek (2020-09-27 12:06:51) > Add support for the display clock controller found on SM8150 and SM8250. > > Signed-off-by: Jonathan Marek > Tested-by: Dmitry Baryshkov (SM8250) > --- Applied to clk-next
Re: [PATCH v4 1/2] dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
Quoting Jonathan Marek (2020-09-27 12:06:50) > Add device tree bindings for display clock controller for > Qualcomm Technology Inc's SM8150 and SM8250 SoCs. > > Signed-off-by: Jonathan Marek > Tested-by: Dmitry Baryshkov (SM8250) > --- Applied to clk-next
Re: [PATCH 6/6] dt-bindings: misc: correct the property name cmd-gpios to cmd-gpio
On 2020/10/14 1:32, Dan Murphy wrote: > Zhen > > On 10/13/20 11:08 AM, Zhen Lei wrote: >> The property name used in arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts is >> cmd-gpio. >> >> arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:235: >> cmd-gpio = < 155 GPIO_ACTIVE_HIGH>; >> >> Signed-off-by: Zhen Lei >> --- >> Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml >> b/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml >> index b3c45c046ba5e37..c7a06a9650db2ed 100644 >> --- a/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml >> +++ b/Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml >> @@ -24,7 +24,7 @@ properties: >> compatible: >> const: olpc,xo1.75-ec >> - cmd-gpios: >> + cmd-gpio: > > Preference is gpios not gpio. But Rob H accept or reject Look at the search result below. It seems that the driver have not been merged into mainline. But the property name is really used as cmd-gpio at mmp2-olpc-xo-1-75.dts:235, I don't think the mmp2-olpc-xo-1-75.dts can make a mistake. Otherwise, the driver will not work properly. Meanwhile, Both names cmd-gpios and cmd-gpio seem to be in use. But I prefer cmd-gpio, after all, only one gpio is assigned now. The motorola,cmd-gpios add "s" because it contains 3 gpio. Without this patch: git grep -wn "cmd-gpios" Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml:27: cmd-gpios: Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml:35: - cmd-gpios Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml:52:cmd-gpios = < 155 GPIO_ACTIVE_HIGH>; Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt:10:- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600 Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt:22: motorola,cmd-gpios = < 7 GPIO_ACTIVE_HIGH>, arch/arm/boot/dts/motorola-mapphone-common.dtsi:78: motorola,cmd-gpios = < 7 GPIO_ACTIVE_HIGH>, git grep -wn "cmd-gpio" Documentation/devicetree/bindings/leds/leds-ns2.txt:9:- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification. Documentation/devicetree/bindings/leds/leds-ns2.txt:12: the corresponding cmd-gpio/slow-gpio values. All the GPIO values combinations Documentation/devicetree/bindings/leds/leds-ns2.txt:29: cmd-gpio = < 30 0>; arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts:90: cmd-gpio = < 1 GPIO_ACTIVE_HIGH>; arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts:100: cmd-gpio = < 4 GPIO_ACTIVE_HIGH>; arch/arm/boot/dts/kirkwood-d2net.dts:29:cmd-gpio = < 30 GPIO_ACTIVE_HIGH>; arch/arm/boot/dts/kirkwood-is2.dts:31: cmd-gpio = < 30 0>; arch/arm/boot/dts/kirkwood-ns2.dts:31: cmd-gpio = < 30 0>; arch/arm/boot/dts/kirkwood-ns2max.dts:50: cmd-gpio = < 30 0>; arch/arm/boot/dts/kirkwood-ns2mini.dts:51: cmd-gpio = < 30 0>; arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:235:cmd-gpio = < 155 GPIO_ACTIVE_HIGH>; > > Dan > > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > >
RE: [PATCH] vfio/platform: Replace spin_lock_irqsave by spin_lock in hard IRQ
> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Wednesday, October 14, 2020 1:50 PM
> To: Song Bao Hua (Barry Song)
> Cc: tiantao (H) ; eric.au...@redhat.com;
> coh...@redhat.com; k...@vger.kernel.org; linux-kernel@vger.kernel.org;
> Linuxarm
> Subject: Re: [PATCH] vfio/platform: Replace spin_lock_irqsave by spin_lock in
> hard IRQ
>
> On Wed, 14 Oct 2020 00:15:13 +
> "Song Bao Hua (Barry Song)" wrote:
>
> > > -Original Message-
> > > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > > Sent: Wednesday, October 14, 2020 10:32 AM
> > > To: tiantao (H)
> > > Cc: eric.au...@redhat.com; coh...@redhat.com; k...@vger.kernel.org;
> > > linux-kernel@vger.kernel.org; Song Bao Hua (Barry Song)
> > > ; Linuxarm
> > > Subject: Re: [PATCH] vfio/platform: Replace spin_lock_irqsave by spin_lock
> in
> > > hard IRQ
> > >
> > > On Tue, 13 Oct 2020 10:00:58 +0800
> > > Tian Tao wrote:
> > >
> > > > It is redundant to do irqsave and irqrestore in hardIRQ context.
> > >
> > > But this function is also called from non-IRQ context. Thanks,
> >
> > It seems you mean
> > vfio_platform_set_irqs_ioctl() ->
> > vfio_platform_set_irq_trigger ->
> > handler() ?
>
> Yes.
>
> > so, will it be better to move the irqsave out of the
> vfio_automasked_irq_handler()
> > and put it to where the function is called in non-IRQ context?
> >
> > I mean:
> >
> > irqhandler()
> > {
> > spin_lock() //without irqsave
> > spin_unlock()
> > }
> >
> > Non-irq context which is calling this handler:
> > irqsave();
> > irqhandler();
> > irqrestore();
> >
> > Anyway, if it is called in IRQ context, it is redundant to do irqsave.
>
> What's the advantage? You're saying it's redundant, is it also wrong?
It is not wrong and it doesn't make any malfunction. It just takes a couple of
instruction cycles to do save/restore and irq-disable/enable of cpu, which
is useless in irq context.
So the advantage is that we are going to remove some redundant instruction
cycles. And if the irq handler is called very often, we speed up the system.
> If it's not wrong and only redundant, what's the tangible latency
> difference in maintaining a separate IRQ context handler without the
> irqsave/restore? Thanks,
For this question, maybe need some benchmark to get answer. If the irqhandler
is not called that often, I agree it might be not worth to maintain two pieces
of
code.
>
> Alex
>
> > > > Signed-off-by: Tian Tao
> > > > ---
> > > > drivers/vfio/platform/vfio_platform_irq.c | 5 ++---
> > > > 1 file changed, 2 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/vfio/platform/vfio_platform_irq.c
> > > b/drivers/vfio/platform/vfio_platform_irq.c
> > > > index c5b09ec..24fd6c5 100644
> > > > --- a/drivers/vfio/platform/vfio_platform_irq.c
> > > > +++ b/drivers/vfio/platform/vfio_platform_irq.c
> > > > @@ -139,10 +139,9 @@ static int vfio_platform_set_irq_unmask(struct
> > > vfio_platform_device *vdev,
> > > > static irqreturn_t vfio_automasked_irq_handler(int irq, void *dev_id)
> > > > {
> > > > struct vfio_platform_irq *irq_ctx = dev_id;
> > > > - unsigned long flags;
> > > > int ret = IRQ_NONE;
> > > >
> > > > - spin_lock_irqsave(_ctx->lock, flags);
> > > > + spin_lock(_ctx->lock);
> > > >
> > > > if (!irq_ctx->masked) {
> > > > ret = IRQ_HANDLED;
> > > > @@ -152,7 +151,7 @@ static irqreturn_t
> vfio_automasked_irq_handler(int
> > > irq, void *dev_id)
> > > > irq_ctx->masked = true;
> > > > }
> > > >
> > > > - spin_unlock_irqrestore(_ctx->lock, flags);
> > > > + spin_unlock(_ctx->lock);
> > > >
> > > > if (ret == IRQ_HANDLED)
> > > > eventfd_signal(irq_ctx->trigger, 1);
> >
Thanks
Barry
