RE: [PATCH] PCI: endpoint: functions: Use kmemdup instead of duplicating its function

[Alan Douglas]

Hi,

On 06 December 2018 10:21, Wen Yang wrote:
> kmemdup has implemented the function that kmalloc() + memcpy().
> We prefer to kmemdup rather than code opened implementation.
> 
> This issue was detected with the help of coccinelle.
> 
> Signed-off-by: Wen Yang 
> CC: Bob Copeland 
> 
> CC: Kishon Vijay Abraham I 
> CC: Lorenzo Pieralisi 
> CC: Bjorn Helgaas 
> CC: Gustavo Pimentel 
> CC: Niklas Cassel 
> CC: Greg Kroah-Hartman 
> CC: Cyrille Pitchen 
> CC: linux-...@vger.kernel.org (open list:PCI ENDPOINT SUBSYSTEM)
> CC: linux-kernel@vger.kernel.org (open list)
> ---
>  drivers/pci/endpoint/functions/pci-epf-test.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c 
> b/drivers/pci/endpoint/functions/pci-epf-test.c
> index 3e86fa3c7da3..6e42daa2a651 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -169,14 +169,12 @@ static int pci_epf_test_read(struct pci_epf_test 
> *epf_test)
>   goto err_addr;
>   }
> 
> - buf = kzalloc(reg->size, GFP_KERNEL);
> + buf = kzalloc(src_addr, reg->size, GFP_KERNEL);
Looks like a typo - kmemdup instead of kzalloc?

>   if (!buf) {
>   ret = -ENOMEM;
>   goto err_map_addr;
>   }
> 
> - memcpy(buf, src_addr, reg->size);
> -
>   crc32 = crc32_le(~0, buf, reg->size);
>   if (crc32 != reg->checksum)
>   ret = -EIO;
> --
> 2.19.1

Regards,
Alan

RE: [PATCH] PCI: endpoint: functions: Use kmemdup instead of duplicating its function

[Alan Douglas]

Hi,

On 06 December 2018 10:21, Wen Yang wrote:
> kmemdup has implemented the function that kmalloc() + memcpy().
> We prefer to kmemdup rather than code opened implementation.
> 
> This issue was detected with the help of coccinelle.
> 
> Signed-off-by: Wen Yang 
> CC: Bob Copeland 
> 
> CC: Kishon Vijay Abraham I 
> CC: Lorenzo Pieralisi 
> CC: Bjorn Helgaas 
> CC: Gustavo Pimentel 
> CC: Niklas Cassel 
> CC: Greg Kroah-Hartman 
> CC: Cyrille Pitchen 
> CC: linux-...@vger.kernel.org (open list:PCI ENDPOINT SUBSYSTEM)
> CC: linux-kernel@vger.kernel.org (open list)
> ---
>  drivers/pci/endpoint/functions/pci-epf-test.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c 
> b/drivers/pci/endpoint/functions/pci-epf-test.c
> index 3e86fa3c7da3..6e42daa2a651 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -169,14 +169,12 @@ static int pci_epf_test_read(struct pci_epf_test 
> *epf_test)
>   goto err_addr;
>   }
> 
> - buf = kzalloc(reg->size, GFP_KERNEL);
> + buf = kzalloc(src_addr, reg->size, GFP_KERNEL);
Looks like a typo - kmemdup instead of kzalloc?

>   if (!buf) {
>   ret = -ENOMEM;
>   goto err_map_addr;
>   }
> 
> - memcpy(buf, src_addr, reg->size);
> -
>   crc32 = crc32_le(~0, buf, reg->size);
>   if (crc32 != reg->checksum)
>   ret = -EIO;
> --
> 2.19.1

Regards,
Alan

[PATCH v3 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/cadence/Kconfig  |   9 +-
 drivers/phy/cadence/Makefile |   1 +
 drivers/phy/cadence/phy-cadence-sierra.c | 395 +++
 3 files changed, 404 insertions(+), 1 deletion(-)
 create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c

diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 57fff7d..2b8c085 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -1,5 +1,5 @@
 #
-# Phy driver for Cadence MHDP DisplayPort controller
+# Phy drivers for Cadence PHYs
 #
 config PHY_CADENCE_DP
tristate "Cadence MHDP DisplayPort PHY driver"
@@ -8,3 +8,10 @@ config PHY_CADENCE_DP
select GENERIC_PHY
help
  Support for Cadence MHDP DisplayPort PHY.
+
+config PHY_CADENCE_SIERRA
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
\ No newline at end of file
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
index e5b0a11..412349a 100644
--- a/drivers/phy/cadence/Makefile
+++ b/drivers/phy/cadence/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_PHY_CADENCE_DP)   += phy-cadence-dp.o
+obj-$(CONFIG_PHY_CADENCE_SIERRA)   += phy-cadence-sierra.o
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c 
b/drivers/phy/cadence/phy-cadence-sierra.c
new file mode 100644
index 000..de10402
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2)
+#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2)
+#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2)
+#define SIERRA_CTLELUT_CTRL(0x4098 << 2)
+#define SIERRA_DFE_ECMP_RATESEL(0x40C0 << 2)
+#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2)
+#define SIERRA_DEQ_VGATUNE_CTRL(0x40E1 << 2)
+#define SIERRA_TMRVAL_MODE3(0x416E << 2)
+#define SIERRA_TMRVAL_MODE2(0x416F << 2)
+#define SIERRA_TMRVAL_MODE1(0x4170 << 2)
+#define SIERRA_TMRVAL_MODE0(0x4171 << 2)
+#define SIERRA_PICNT_MODE1 (0x4174 << 2)
+#define SIERRA_CPI_OUTBUF_RATESEL  (0x417C << 2)
+#define SIERRA_LFPSFILT_NS (0x418A << 2)
+#define SIERRA_LFPSFILT_RD (0x418B << 2)
+#define SIERRA_LF

[PATCH v3 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/cadence/Kconfig  |   9 +-
 drivers/phy/cadence/Makefile |   1 +
 drivers/phy/cadence/phy-cadence-sierra.c | 395 +++
 3 files changed, 404 insertions(+), 1 deletion(-)
 create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c

diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 57fff7d..2b8c085 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -1,5 +1,5 @@
 #
-# Phy driver for Cadence MHDP DisplayPort controller
+# Phy drivers for Cadence PHYs
 #
 config PHY_CADENCE_DP
tristate "Cadence MHDP DisplayPort PHY driver"
@@ -8,3 +8,10 @@ config PHY_CADENCE_DP
select GENERIC_PHY
help
  Support for Cadence MHDP DisplayPort PHY.
+
+config PHY_CADENCE_SIERRA
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
\ No newline at end of file
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
index e5b0a11..412349a 100644
--- a/drivers/phy/cadence/Makefile
+++ b/drivers/phy/cadence/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_PHY_CADENCE_DP)   += phy-cadence-dp.o
+obj-$(CONFIG_PHY_CADENCE_SIERRA)   += phy-cadence-sierra.o
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c 
b/drivers/phy/cadence/phy-cadence-sierra.c
new file mode 100644
index 000..de10402
--- /dev/null
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ_CCLKDET_MODE01 (0x408E << 2)
+#define SIERRA_RX_CTLE_MAINTENANCE (0x4091 << 2)
+#define SIERRA_CREQ_FSMCLK_SEL (0x4092 << 2)
+#define SIERRA_CTLELUT_CTRL(0x4098 << 2)
+#define SIERRA_DFE_ECMP_RATESEL(0x40C0 << 2)
+#define SIERRA_DFE_SMP_RATESEL (0x40C1 << 2)
+#define SIERRA_DEQ_VGATUNE_CTRL(0x40E1 << 2)
+#define SIERRA_TMRVAL_MODE3(0x416E << 2)
+#define SIERRA_TMRVAL_MODE2(0x416F << 2)
+#define SIERRA_TMRVAL_MODE1(0x4170 << 2)
+#define SIERRA_TMRVAL_MODE0(0x4171 << 2)
+#define SIERRA_PICNT_MODE1 (0x4174 << 2)
+#define SIERRA_CPI_OUTBUF_RATESEL  (0x417C << 2)
+#define SIERRA_LFPSFILT_NS (0x418A << 2)
+#define SIERRA_LFPSFILT_RD (0x418B << 2)
+#define SIERRA_LF

[PATCH v3 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/phy-cadence-sierra.txt | 67 ++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt 
b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
new file mode 100644
index 000..6e1b47b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
@@ -0,0 +1,67 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb".
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+- reg: The master lane number.  This is the lowest numbered lane
+   in the lane group.
+- resets:  Must contain one entry which controls the reset line for the
+   master lane of the sub-node.
+   See ../reset/reset.txt for details.
+
+Sub-node optional properties:
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>;
+   reset-names = "sierra_reset", "sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   resets = < 2>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   resets = < 4>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
-- 
1.9.0

[PATCH v3 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/phy-cadence-sierra.txt | 67 ++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt 
b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
new file mode 100644
index 000..6e1b47b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
@@ -0,0 +1,67 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb".
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+- reg: The master lane number.  This is the lowest numbered lane
+   in the lane group.
+- resets:  Must contain one entry which controls the reset line for the
+   master lane of the sub-node.
+   See ../reset/reset.txt for details.
+
+Sub-node optional properties:
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>;
+   reset-names = "sierra_reset", "sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   resets = < 2>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   resets = < 4>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
-- 
1.9.0

[PATCH v3 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since v2:
* Rebased on 4.20-rc1
* Renamed cdns-sierra-phy.txt to phy-cadence-sierra.txt, to match DP PHY
* Renamed phy-cdns-sierra.c to phy-cadence-sierra.c, to match DP PHY
* Removed blank line at end of devicetree bindings description

Changes since v1:
* Moved subnode resets into each subnode in devicetree bindings
* Modified driver to put subnode resets on exit
* Changed driver filename to phy-cdns-sierra.c

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/phy-cadence-sierra.txt |  67 
 drivers/phy/cadence/Kconfig|   9 +-
 drivers/phy/cadence/Makefile   |   1 +
 drivers/phy/cadence/phy-cadence-sierra.c   | 395 +
 4 files changed, 471 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
 create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c

-- 
1.9.0

[PATCH v3 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since v2:
* Rebased on 4.20-rc1
* Renamed cdns-sierra-phy.txt to phy-cadence-sierra.txt, to match DP PHY
* Renamed phy-cdns-sierra.c to phy-cadence-sierra.c, to match DP PHY
* Removed blank line at end of devicetree bindings description

Changes since v1:
* Moved subnode resets into each subnode in devicetree bindings
* Modified driver to put subnode resets on exit
* Changed driver filename to phy-cdns-sierra.c

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/phy-cadence-sierra.txt |  67 
 drivers/phy/cadence/Kconfig|   9 +-
 drivers/phy/cadence/Makefile   |   1 +
 drivers/phy/cadence/phy-cadence-sierra.c   | 395 +
 4 files changed, 471 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
 create mode 100644 drivers/phy/cadence/phy-cadence-sierra.c

-- 
1.9.0

[PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/phy-cdns-sierra.c | 395 ++
 5 files changed, 408 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/phy-cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..0ef6752
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += phy-cdns-sierra.o
diff --git a/drivers/phy/cadence/phy-cdns-sierra.c 
b/drivers/phy/cadence/phy-cdns-sierra.c
new file mode 100644
index 000..de10402
--- /dev/null
+++ b/drivers/phy/cadence/phy-cdns-sierra.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 <<

[PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/phy-cdns-sierra.c | 395 ++
 5 files changed, 408 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/phy-cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..0ef6752
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += phy-cdns-sierra.o
diff --git a/drivers/phy/cadence/phy-cdns-sierra.c 
b/drivers/phy/cadence/phy-cdns-sierra.c
new file mode 100644
index 000..de10402
--- /dev/null
+++ b/drivers/phy/cadence/phy-cdns-sierra.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 <<

[PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..67efdb4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,68 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb".
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+- reg: The master lane number.  This is the lowest numbered lane
+   in the lane group.
+- resets:  Must contain one entry which controls the reset line for the
+   master lane of the sub-node.
+   See ../reset/reset.txt for details.
+
+Sub-node optional properties:
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>;
+   reset-names = "sierra_reset", "sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   resets = < 2>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   resets = < 4>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..67efdb4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,68 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb".
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+- reg: The master lane number.  This is the lowest numbered lane
+   in the lane group.
+- resets:  Must contain one entry which controls the reset line for the
+   master lane of the sub-node.
+   See ../reset/reset.txt for details.
+
+Sub-node optional properties:
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>;
+   reset-names = "sierra_reset", "sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   resets = < 2>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   resets = < 4>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[PATCH v2 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since v1:
* Moved subnode resets into each subnode in devicetree bindings
* Modified driver to put subnode resets on exit
* Changed driver filename to phy-cdns-sierra.c

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  68 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/phy-cdns-sierra.c  | 395 +
 6 files changed, 476 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/phy-cdns-sierra.c

-- 
1.9.0

[PATCH v2 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since v1:
* Moved subnode resets into each subnode in devicetree bindings
* Modified driver to put subnode resets on exit
* Changed driver filename to phy-cdns-sierra.c

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  68 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/phy-cdns-sierra.c  | 395 +
 6 files changed, 476 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/phy-cdns-sierra.c

-- 
1.9.0

RE: [PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

On 15 October 2018 20:09, Rob Herring wrote:
> On Wed, Oct 03, 2018 at 05:02:25PM +0100, Alan Douglas wrote:
> > Add DT binding documentation for Sierra PHY.  The PHY supports
> > a number of different protocols, including PCIe and USB.
> >
> > The PHY lanes may be configured as single or multi-lane links.
> > Each link is treated as a separate sub-node.  For example, if
> > there are 4 lanes in total the first 2 might be configured as
> > a multi-lane PCIe link while the other two are single lane
> > USB links, and in this case there would be 3 sub-nodes.
> >
> > There are two resets for the PHY block (one for APB register
> > access, one for the PHY link) and separate resets for each
> > link.  For multi-lane links, the reset corresponds to the
> > reset line on the master lane, the resets on other lanes
> > have no effect.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 
> > ++
> >  1 file changed, 68 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
> > b/Documentation/devicetree/bindings/phy/cdns-sierra-
> phy.txt
> > new file mode 100644
> > index 000..0e2f3e3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> > @@ -0,0 +1,68 @@
> > +Cadence Sierra PHY
> > +---
> > +
> > +Required properties:
> > +- compatible:  cdns,sierra-phy-t0
> > +- clocks:  Must contain an entry in clock-names.
> > +   See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must be "phy_clk"
> > +- resets:  Must contain an entry for each in reset-names.
> > +   See ../reset/reset.txt for details.
> > +- reset-names: Must include "sierra_reset" and "sierra_apb" and one 
> > for each
> > +   sub-node.
> > +   "sierra_reset" must control the reset line to the PHY.
> > +   "sierra_apb" must control the reset line to the APB PHY
> > +   interface.
> > +   The name of the reset for each sub-node should match the full
> > +   name of the sub-node.  The sub-node resets must control the
> > +   reset line for the master lane of the sub-node.
> 
> Add a resets property to the sub-nodes instead.
> 
Will do.  As far as I can see it prevents me using devm_reset_control_get()
though, so I need to work out the best way to put these resets on remove()

> > +- reg: register range for the PHY.
> > +- #address-cells: Must be 1
> > +- #size-cells: Must be 0
> > +
> > +Optional properties:
> > +- cdns,autoconf:   A boolean property whose presence indicates that the
> > +   PHY registers will be configured by hardware. If not
> > +   present, all sub-node optional properties must be
> > +   provided.
> > +
> > +Sub-nodes:
> > +  Each group of PHY lanes with a single master lane should be represented 
> > as
> > +  a sub-node. Note that the actual configuration of each lane is 
> > determined by
> > +  hardware strapping, and must match the configuration specified here.
> > +
> > +Sub-node required properties:
> > +- #phy-cells:  Generic PHY binding; must be 0.
> > +
> > +Sub-node optional properties:
> > +- reg: The master lane number.  This is the lowest 
> > numbered
> > +   lane in the lane group.
> 
> How do you name the nodes if this is optional?
> 
I'll change this to be required.

Thanks for your comments,
Alan

> > +- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
> > +   group is made up of consecutive lanes.
> > +- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
> > +   configuration of lanes.
> > +
> > +Example:
> > +   pcie_phy4: pcie-phy@fd24 {
> > +   compatible = "cdns,sierra-phy-t0";
> > +   reg = <0x0 0xfd24 0x0 0x4>;
> > +   resets = < 0>, < 1>, < 2>, < 4>;
> > +   reset-names = "sierra_reset", "sierra_apb",
> > +   "pcie_phy@0", "pcie_phy@2";
> > +   clocks = <>;
> > +   clock-names = "phy_clk";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   pcie0_phy0: pcie-phy@0 {
> > +   reg = <0>;
> > +   cdns,num-lanes = <2>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +   pcie0_phy1: pcie-phy@2 {
> > +   reg = <2>;
> > +   cdns,num-lanes = <1>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +
> > --
> > 1.9.0
> >

RE: [PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

On 15 October 2018 20:09, Rob Herring wrote:
> On Wed, Oct 03, 2018 at 05:02:25PM +0100, Alan Douglas wrote:
> > Add DT binding documentation for Sierra PHY.  The PHY supports
> > a number of different protocols, including PCIe and USB.
> >
> > The PHY lanes may be configured as single or multi-lane links.
> > Each link is treated as a separate sub-node.  For example, if
> > there are 4 lanes in total the first 2 might be configured as
> > a multi-lane PCIe link while the other two are single lane
> > USB links, and in this case there would be 3 sub-nodes.
> >
> > There are two resets for the PHY block (one for APB register
> > access, one for the PHY link) and separate resets for each
> > link.  For multi-lane links, the reset corresponds to the
> > reset line on the master lane, the resets on other lanes
> > have no effect.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 
> > ++
> >  1 file changed, 68 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
> > b/Documentation/devicetree/bindings/phy/cdns-sierra-
> phy.txt
> > new file mode 100644
> > index 000..0e2f3e3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> > @@ -0,0 +1,68 @@
> > +Cadence Sierra PHY
> > +---
> > +
> > +Required properties:
> > +- compatible:  cdns,sierra-phy-t0
> > +- clocks:  Must contain an entry in clock-names.
> > +   See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must be "phy_clk"
> > +- resets:  Must contain an entry for each in reset-names.
> > +   See ../reset/reset.txt for details.
> > +- reset-names: Must include "sierra_reset" and "sierra_apb" and one 
> > for each
> > +   sub-node.
> > +   "sierra_reset" must control the reset line to the PHY.
> > +   "sierra_apb" must control the reset line to the APB PHY
> > +   interface.
> > +   The name of the reset for each sub-node should match the full
> > +   name of the sub-node.  The sub-node resets must control the
> > +   reset line for the master lane of the sub-node.
> 
> Add a resets property to the sub-nodes instead.
> 
Will do.  As far as I can see it prevents me using devm_reset_control_get()
though, so I need to work out the best way to put these resets on remove()

> > +- reg: register range for the PHY.
> > +- #address-cells: Must be 1
> > +- #size-cells: Must be 0
> > +
> > +Optional properties:
> > +- cdns,autoconf:   A boolean property whose presence indicates that the
> > +   PHY registers will be configured by hardware. If not
> > +   present, all sub-node optional properties must be
> > +   provided.
> > +
> > +Sub-nodes:
> > +  Each group of PHY lanes with a single master lane should be represented 
> > as
> > +  a sub-node. Note that the actual configuration of each lane is 
> > determined by
> > +  hardware strapping, and must match the configuration specified here.
> > +
> > +Sub-node required properties:
> > +- #phy-cells:  Generic PHY binding; must be 0.
> > +
> > +Sub-node optional properties:
> > +- reg: The master lane number.  This is the lowest 
> > numbered
> > +   lane in the lane group.
> 
> How do you name the nodes if this is optional?
> 
I'll change this to be required.

Thanks for your comments,
Alan

> > +- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
> > +   group is made up of consecutive lanes.
> > +- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
> > +   configuration of lanes.
> > +
> > +Example:
> > +   pcie_phy4: pcie-phy@fd24 {
> > +   compatible = "cdns,sierra-phy-t0";
> > +   reg = <0x0 0xfd24 0x0 0x4>;
> > +   resets = < 0>, < 1>, < 2>, < 4>;
> > +   reset-names = "sierra_reset", "sierra_apb",
> > +   "pcie_phy@0", "pcie_phy@2";
> > +   clocks = <>;
> > +   clock-names = "phy_clk";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   pcie0_phy0: pcie-phy@0 {
> > +   reg = <0>;
> > +   cdns,num-lanes = <2>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +   pcie0_phy1: pcie-phy@2 {
> > +   reg = <2>;
> > +   cdns,num-lanes = <1>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +
> > --
> > 1.9.0
> >

[PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/cdns-sierra.c | 380 ++
 5 files changed, 393 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..c396c69
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..598e512
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ

[PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/cdns-sierra.c | 380 ++
 5 files changed, 393 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..c396c69
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..598e512
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ

[PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..0e2f3e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,68 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb" and one for each
+   sub-node.
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+   The name of the reset for each sub-node should match the full
+   name of the sub-node.  The sub-node resets must control the
+   reset line for the master lane of the sub-node.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+
+Sub-node optional properties:
+- reg: The master lane number.  This is the lowest numbered
+   lane in the lane group.
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>, < 2>, < 4>;
+   reset-names = "sierra_reset", "sierra_apb",
+   "pcie_phy@0", "pcie_phy@2";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[PATCH 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  68 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/cdns-sierra.c  | 380 +
 6 files changed, 461 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

[PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node.  For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.

There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link.  For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..0e2f3e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,68 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb" and one for each
+   sub-node.
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+   The name of the reset for each sub-node should match the full
+   name of the sub-node.  The sub-node resets must control the
+   reset line for the master lane of the sub-node.
+- reg: register range for the PHY.
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Optional properties:
+- cdns,autoconf:   A boolean property whose presence indicates that the
+   PHY registers will be configured by hardware. If not
+   present, all sub-node optional properties must be
+   provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+
+Sub-node optional properties:
+- reg: The master lane number.  This is the lowest numbered
+   lane in the lane group.
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.  The
+   group is made up of consecutive lanes.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   resets = < 0>, < 1>, < 2>, < 4>;
+   reset-names = "sierra_reset", "sierra_apb",
+   "pcie_phy@0", "pcie_phy@2";
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy@0 {
+   reg = <0>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy@2 {
+   reg = <2>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[PATCH 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes since RFC v2:
* Devicetree bindings modified as suggested by Rob Herring.
* Tidy up and correction of return paths in probe function.

Changes since RFC v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  68 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/cdns-sierra.c  | 380 +
 6 files changed, 461 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

RE: [RFC PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

On 25 September 2018 22:02, Rob Herring wrote:
> On Thu, Sep 06, 2018 at 03:42:29PM +0100, Alan Douglas wrote:
> > Add DT binding documentation for Sierra PHY.  The PHY supports
> > a number of different protocols, including PCIe and USB.
> >
> > The PHY lanes may be configured as single or multi-lane links.
> > Each link is treated as a separate subnode.  For example, if
> > there are 4 lanes in total the first 2 may be configured as
> > a multi-lane PCIe link while the other two are single lane
> > USB links, and in this case there would be 3 subnodes.
> >
> > There are two resets for the PHY block, and additional resets,
> > one for each lane.  For multi-lane links, only the reset for
> > the master lane is required, the resets on other lanes have no
> > effect.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  .../devicetree/bindings/phy/cdns-sierra-phy.txt| 65 
> > ++
> >  1 file changed, 65 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
> > b/Documentation/devicetree/bindings/phy/cdns-sierra-
> phy.txt
> > new file mode 100644
> > index 000..94a8a7f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> > @@ -0,0 +1,65 @@
> > +Cadence Sierra PHY
> > +---
> > +
> > +Required properties:
> > +- compatible:  cdns,sierra-phy-t0
> > +- clocks:  Must contain an entry in clock-names.
> > +   See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must be "phy_clk"
> > +- resets:  Must contain an entry for each in reset-names.
> > +   See ../reset/reset.txt for details.
> > +- reset-names: Must include "sierra_reset" and "sierra_apb" and one 
> > for each
> > +   sub-node.
> > +   "sierra_reset" must control the reset line to the PHY.
> > +   "sierra_apb" must control the reset line to the APB PHY
> > +   interface.
> > +   Resets for each subnode must control the master lane for the
> > +   subnode lane group.
> 
> What are the names?
> 
I'll update this to use the full name of the subnode, e.g. for subnodes:
  pcie0_phy0: pcie-phy@0
  pcie0_phy1: pcie-phy@2
then the reset names would be: "pcie-phy@0" and "pcie-phy@2"

> > +- reg: register range for the PHY.
> > +- reg-names:   Must be "reg".
> 
> Kind of pointless with only 1.
> 
I will remove reg-names.

> > +- #address-cells: Should be 1
> > +- #size-cells: Should be 0
> > +
> > +Optional properties:
> > +- cdns,autoconf:   If present, indicates that the PHY registers will
> > +   be configured by hardware.  If not present, all
> > +   sub-node optional properties must be provided.
> 
> boolean?
Yes, will update the description

> 
> > +
> > +Sub-nodes:
> > +  Each group of PHY lanes with a single master lane should be represented 
> > as
> > +  a sub-node. Note that the actual configuration of each lane is 
> > determined by
> > +  hardware strapping, and must match the configuration specified here.
> > +
> > +Sub-node required properties:
> > +- #phy-cells:  Generic PHY binding; must be 0.
> > +
> > +Sub-node optional properties:
> > +- reg: The master lane number.
> > +- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.
> > +- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
> > +   configuration of lanes.
> > +
> > +Example:
> > +   pcie_phy4: pcie-phy4@fd24 {
> 
> pcie-phy@fd24
> 
I'll change as suggested.

> > +   compatible = "cdns,sierra-phy-t0";
> > +   reg = <0x0 0xfd24 0x0 0x4>;
> > +   reg-names = "reg";
> > +   resets = < 0>, < 1>,< 2>,< 4>;
> > +   reset-names = "sierra_reset","sierra_apb","pcie_phy0",pcie_phy1;
> 
> spaces and quotes missing.
> 
I'll reformat.

> > +   clocks = <>;
> > +   clock-names = "phy_clk";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   pcie0_phy0: pcie-phy0@0 {
> 
> pcie-phy@0
> 
I'll change as suggested.

> > +   reg = <0>;
> > +   cdns,num-lanes = <2>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +   pcie0_phy1: pcie-phy1@0 {
> 
> pcie-phy@2
> 
> Or reg should be 1?
> 
reg is the master lane number, and in this case must be 2 or higher,
since the subnode with master lane number 0 has 2 lanes.
I'll change to pcie-phy@2, and add an explanation.

Thanks for your comments

> > +   reg = <2>;
> > +   cdns,num-lanes = <1>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +
> > --
> > 1.9.0
> >

RE: [RFC PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

On 25 September 2018 22:02, Rob Herring wrote:
> On Thu, Sep 06, 2018 at 03:42:29PM +0100, Alan Douglas wrote:
> > Add DT binding documentation for Sierra PHY.  The PHY supports
> > a number of different protocols, including PCIe and USB.
> >
> > The PHY lanes may be configured as single or multi-lane links.
> > Each link is treated as a separate subnode.  For example, if
> > there are 4 lanes in total the first 2 may be configured as
> > a multi-lane PCIe link while the other two are single lane
> > USB links, and in this case there would be 3 subnodes.
> >
> > There are two resets for the PHY block, and additional resets,
> > one for each lane.  For multi-lane links, only the reset for
> > the master lane is required, the resets on other lanes have no
> > effect.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  .../devicetree/bindings/phy/cdns-sierra-phy.txt| 65 
> > ++
> >  1 file changed, 65 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
> > b/Documentation/devicetree/bindings/phy/cdns-sierra-
> phy.txt
> > new file mode 100644
> > index 000..94a8a7f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
> > @@ -0,0 +1,65 @@
> > +Cadence Sierra PHY
> > +---
> > +
> > +Required properties:
> > +- compatible:  cdns,sierra-phy-t0
> > +- clocks:  Must contain an entry in clock-names.
> > +   See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must be "phy_clk"
> > +- resets:  Must contain an entry for each in reset-names.
> > +   See ../reset/reset.txt for details.
> > +- reset-names: Must include "sierra_reset" and "sierra_apb" and one 
> > for each
> > +   sub-node.
> > +   "sierra_reset" must control the reset line to the PHY.
> > +   "sierra_apb" must control the reset line to the APB PHY
> > +   interface.
> > +   Resets for each subnode must control the master lane for the
> > +   subnode lane group.
> 
> What are the names?
> 
I'll update this to use the full name of the subnode, e.g. for subnodes:
  pcie0_phy0: pcie-phy@0
  pcie0_phy1: pcie-phy@2
then the reset names would be: "pcie-phy@0" and "pcie-phy@2"

> > +- reg: register range for the PHY.
> > +- reg-names:   Must be "reg".
> 
> Kind of pointless with only 1.
> 
I will remove reg-names.

> > +- #address-cells: Should be 1
> > +- #size-cells: Should be 0
> > +
> > +Optional properties:
> > +- cdns,autoconf:   If present, indicates that the PHY registers will
> > +   be configured by hardware.  If not present, all
> > +   sub-node optional properties must be provided.
> 
> boolean?
Yes, will update the description

> 
> > +
> > +Sub-nodes:
> > +  Each group of PHY lanes with a single master lane should be represented 
> > as
> > +  a sub-node. Note that the actual configuration of each lane is 
> > determined by
> > +  hardware strapping, and must match the configuration specified here.
> > +
> > +Sub-node required properties:
> > +- #phy-cells:  Generic PHY binding; must be 0.
> > +
> > +Sub-node optional properties:
> > +- reg: The master lane number.
> > +- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.
> > +- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
> > +   configuration of lanes.
> > +
> > +Example:
> > +   pcie_phy4: pcie-phy4@fd24 {
> 
> pcie-phy@fd24
> 
I'll change as suggested.

> > +   compatible = "cdns,sierra-phy-t0";
> > +   reg = <0x0 0xfd24 0x0 0x4>;
> > +   reg-names = "reg";
> > +   resets = < 0>, < 1>,< 2>,< 4>;
> > +   reset-names = "sierra_reset","sierra_apb","pcie_phy0",pcie_phy1;
> 
> spaces and quotes missing.
> 
I'll reformat.

> > +   clocks = <>;
> > +   clock-names = "phy_clk";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   pcie0_phy0: pcie-phy0@0 {
> 
> pcie-phy@0
> 
I'll change as suggested.

> > +   reg = <0>;
> > +   cdns,num-lanes = <2>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +   pcie0_phy1: pcie-phy1@0 {
> 
> pcie-phy@2
> 
> Or reg should be 1?
> 
reg is the master lane number, and in this case must be 2 or higher,
since the subnode with master lane number 0 has 2 lanes.
I'll change to pcie-phy@2, and add an explanation.

Thanks for your comments

> > +   reg = <2>;
> > +   cdns,num-lanes = <1>;
> > +   #phy-cells = <0>;
> > +   cdns,phy-type = ;
> > +   };
> > +
> > --
> > 1.9.0
> >

RE: [RFC PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Hi,

On 20 September 2018 11:10, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 September 2018 08:12 PM, Alan Douglas wrote:
> > Add a Sierra PHY driver with PCIe and USB support.
> >
> > The PHY has multiple lanes, which can be configured into
> > groups, and a generic PHY device is created for each group.
> >
> > There are two resets controlling the overall PHY block, one
> > to enable the APB interface for programming registers, and
> > another to enable the PHY itself.  Additionally there are
> > resets for each PHY lane.
> >
> > The PHY can be configured in hardware to read register
> > settings from ROM, or they can be written by the driver.
> >
> > The sequence of operation on startup is to enable the APB
> > bus, write the PHY registers (if required)  for each lane
> > group, and then enable the PHY.  Each group of lanes
> > can then be individually controlled using the power_on()/
> > power_off() function for that generic PHY
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  drivers/phy/Kconfig   |   1 +
> >  drivers/phy/Makefile  |   1 +
> >  drivers/phy/cadence/Kconfig   |   9 +
> >  drivers/phy/cadence/Makefile  |   2 +
> >  drivers/phy/cadence/cdns-sierra.c | 385 
> > ++
> >  5 files changed, 398 insertions(+)
> >  create mode 100644 drivers/phy/cadence/Kconfig
> >  create mode 100644 drivers/phy/cadence/Makefile
> >  create mode 100644 drivers/phy/cadence/cdns-sierra.c
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 5c8d452..cc47f85 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -43,6 +43,7 @@ config PHY_XGENE
> >  source "drivers/phy/allwinner/Kconfig"
> >  source "drivers/phy/amlogic/Kconfig"
> >  source "drivers/phy/broadcom/Kconfig"
> > +source "drivers/phy/cadence/Kconfig"
> >  source "drivers/phy/hisilicon/Kconfig"
> >  source "drivers/phy/lantiq/Kconfig"
> >  source "drivers/phy/marvell/Kconfig"
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index 84e3bd9..ba48acd 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
> >  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
> >  obj-$(CONFIG_ARCH_TEGRA)   += tegra/
> >  obj-y  += broadcom/\
> > +  cadence/ \
> >hisilicon/   \
> >marvell/ \
> >motorola/\
> > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
> > new file mode 100644
> > index 000..098df0f
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Kconfig
> > @@ -0,0 +1,9 @@
> > +#
> > +# Phy drivers for Cadence PHYs
> > +#
> > +config CDNS_SIERRA_PHY
> > +   tristate "Cadence Sierra PHY Driver"
> > +   depends on OF && HAS_IOMEM && RESET_CONTROLLER
> > +   select GENERIC_PHY
> > +   help
> > + Enable this to support the Cadence Sierra PHY driver
> > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
> > new file mode 100644
> > index 000..c396c69
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
> > diff --git a/drivers/phy/cadence/cdns-sierra.c 
> > b/drivers/phy/cadence/cdns-sierra.c
> > new file mode 100644
> > index 000..83568b4
> > --- /dev/null
> > +++ b/drivers/phy/cadence/cdns-sierra.c
> > @@ -0,0 +1,385 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Cadence Sierra PHY Driver
> > + *
> > + * Copyright (c) 2018 Cadence Design Systems
> > + * Author: Alan Douglas 
> > + *
> > + */
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* PHY register offsets */
> > +#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
> > +#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
> 

RE: [RFC PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Hi,

On 20 September 2018 11:10, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 September 2018 08:12 PM, Alan Douglas wrote:
> > Add a Sierra PHY driver with PCIe and USB support.
> >
> > The PHY has multiple lanes, which can be configured into
> > groups, and a generic PHY device is created for each group.
> >
> > There are two resets controlling the overall PHY block, one
> > to enable the APB interface for programming registers, and
> > another to enable the PHY itself.  Additionally there are
> > resets for each PHY lane.
> >
> > The PHY can be configured in hardware to read register
> > settings from ROM, or they can be written by the driver.
> >
> > The sequence of operation on startup is to enable the APB
> > bus, write the PHY registers (if required)  for each lane
> > group, and then enable the PHY.  Each group of lanes
> > can then be individually controlled using the power_on()/
> > power_off() function for that generic PHY
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  drivers/phy/Kconfig   |   1 +
> >  drivers/phy/Makefile  |   1 +
> >  drivers/phy/cadence/Kconfig   |   9 +
> >  drivers/phy/cadence/Makefile  |   2 +
> >  drivers/phy/cadence/cdns-sierra.c | 385 
> > ++
> >  5 files changed, 398 insertions(+)
> >  create mode 100644 drivers/phy/cadence/Kconfig
> >  create mode 100644 drivers/phy/cadence/Makefile
> >  create mode 100644 drivers/phy/cadence/cdns-sierra.c
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 5c8d452..cc47f85 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -43,6 +43,7 @@ config PHY_XGENE
> >  source "drivers/phy/allwinner/Kconfig"
> >  source "drivers/phy/amlogic/Kconfig"
> >  source "drivers/phy/broadcom/Kconfig"
> > +source "drivers/phy/cadence/Kconfig"
> >  source "drivers/phy/hisilicon/Kconfig"
> >  source "drivers/phy/lantiq/Kconfig"
> >  source "drivers/phy/marvell/Kconfig"
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index 84e3bd9..ba48acd 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
> >  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
> >  obj-$(CONFIG_ARCH_TEGRA)   += tegra/
> >  obj-y  += broadcom/\
> > +  cadence/ \
> >hisilicon/   \
> >marvell/ \
> >motorola/\
> > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
> > new file mode 100644
> > index 000..098df0f
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Kconfig
> > @@ -0,0 +1,9 @@
> > +#
> > +# Phy drivers for Cadence PHYs
> > +#
> > +config CDNS_SIERRA_PHY
> > +   tristate "Cadence Sierra PHY Driver"
> > +   depends on OF && HAS_IOMEM && RESET_CONTROLLER
> > +   select GENERIC_PHY
> > +   help
> > + Enable this to support the Cadence Sierra PHY driver
> > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
> > new file mode 100644
> > index 000..c396c69
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
> > diff --git a/drivers/phy/cadence/cdns-sierra.c 
> > b/drivers/phy/cadence/cdns-sierra.c
> > new file mode 100644
> > index 000..83568b4
> > --- /dev/null
> > +++ b/drivers/phy/cadence/cdns-sierra.c
> > @@ -0,0 +1,385 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Cadence Sierra PHY Driver
> > + *
> > + * Copyright (c) 2018 Cadence Design Systems
> > + * Author: Alan Douglas 
> > + *
> > + */
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* PHY register offsets */
> > +#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
> > +#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
> 

[RFC PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate subnode.  For example, if
there are 4 lanes in total the first 2 may be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 subnodes.

There are two resets for the PHY block, and additional resets,
one for each lane.  For multi-lane links, only the reset for
the master lane is required, the resets on other lanes have no
effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 65 ++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..94a8a7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,65 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb" and one for each
+   sub-node.
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+   Resets for each subnode must control the master lane for the
+   subnode lane group.
+- reg: register range for the PHY.
+- reg-names:   Must be "reg".
+- #address-cells: Should be 1
+- #size-cells: Should be 0
+
+Optional properties:
+- cdns,autoconf:   If present, indicates that the PHY registers will
+   be configured by hardware.  If not present, all
+   sub-node optional properties must be provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+
+Sub-node optional properties:
+- reg: The master lane number.
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy4@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   reg-names = "reg";
+   resets = < 0>, < 1>,< 2>,< 4>;
+   reset-names = "sierra_reset","sierra_apb","pcie_phy0",pcie_phy1;
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy0@0 {
+   reg = <0>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy1@0 {
+   reg = <2>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[RFC PATCH v2 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.

The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate subnode.  For example, if
there are 4 lanes in total the first 2 may be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 subnodes.

There are two resets for the PHY block, and additional resets,
one for each lane.  For multi-lane links, only the reset for
the master lane is required, the resets on other lanes have no
effect.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 65 ++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..94a8a7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,65 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+- compatible:  cdns,sierra-phy-t0
+- clocks:  Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+- clock-names: Must be "phy_clk"
+- resets:  Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+- reset-names: Must include "sierra_reset" and "sierra_apb" and one for each
+   sub-node.
+   "sierra_reset" must control the reset line to the PHY.
+   "sierra_apb" must control the reset line to the APB PHY
+   interface.
+   Resets for each subnode must control the master lane for the
+   subnode lane group.
+- reg: register range for the PHY.
+- reg-names:   Must be "reg".
+- #address-cells: Should be 1
+- #size-cells: Should be 0
+
+Optional properties:
+- cdns,autoconf:   If present, indicates that the PHY registers will
+   be configured by hardware.  If not present, all
+   sub-node optional properties must be provided.
+
+Sub-nodes:
+  Each group of PHY lanes with a single master lane should be represented as
+  a sub-node. Note that the actual configuration of each lane is determined by
+  hardware strapping, and must match the configuration specified here.
+
+Sub-node required properties:
+- #phy-cells:  Generic PHY binding; must be 0.
+
+Sub-node optional properties:
+- reg: The master lane number.
+- cdns,num-lanes:  Number of lanes in this group.  From 1 to 4.
+- cdns,phy-type:   Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
+   configuration of lanes.
+
+Example:
+   pcie_phy4: pcie-phy4@fd24 {
+   compatible = "cdns,sierra-phy-t0";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   reg-names = "reg";
+   resets = < 0>, < 1>,< 2>,< 4>;
+   reset-names = "sierra_reset","sierra_apb","pcie_phy0",pcie_phy1;
+   clocks = <>;
+   clock-names = "phy_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pcie0_phy0: pcie-phy0@0 {
+   reg = <0>;
+   cdns,num-lanes = <2>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+   pcie0_phy1: pcie-phy1@0 {
+   reg = <2>;
+   cdns,num-lanes = <1>;
+   #phy-cells = <0>;
+   cdns,phy-type = ;
+   };
+
-- 
1.9.0

[RFC PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/cdns-sierra.c | 385 ++
 5 files changed, 398 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..c396c69
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..83568b4
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ

[RFC PATCH v2 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 +
 drivers/phy/cadence/Makefile  |   2 +
 drivers/phy/cadence/cdns-sierra.c | 385 ++
 5 files changed, 398 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..098df0f
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Cadence PHYs
+#
+config CDNS_SIERRA_PHY
+   tristate "Cadence Sierra PHY Driver"
+   depends on OF && HAS_IOMEM && RESET_CONTROLLER
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..c396c69
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..83568b4
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PHY register offsets */
+#define SIERRA_PHY_PLL_CFG (0xc00e << 2)
+#define SIERRA_DET_STANDEC_A   (0x4000 << 2)
+#define SIERRA_DET_STANDEC_B   (0x4001 << 2)
+#define SIERRA_DET_STANDEC_C   (0x4002 << 2)
+#define SIERRA_DET_STANDEC_D   (0x4003 << 2)
+#define SIERRA_DET_STANDEC_E   (0x4004 << 2)
+#define SIERRA_PSM_LANECAL (0x4008 << 2)
+#define SIERRA_PSM_DIAG(0x4015 << 2)
+#define SIERRA_PSC_TX_A0   (0x4028 << 2)
+#define SIERRA_PSC_TX_A1   (0x4029 << 2)
+#define SIERRA_PSC_TX_A2   (0x402A << 2)
+#define SIERRA_PSC_TX_A3   (0x402B << 2)
+#define SIERRA_PSC_RX_A0   (0x4030 << 2)
+#define SIERRA_PSC_RX_A1   (0x4031 << 2)
+#define SIERRA_PSC_RX_A2   (0x4032 << 2)
+#define SIERRA_PSC_RX_A3   (0x4033 << 2)
+#define SIERRA_PLLCTRL_SUBRATE (0x403A << 2)
+#define SIERRA_PLLCTRL_GEN_D   (0x403E << 2)
+#define SIERRA_DRVCTRL_ATTEN   (0x406A << 2)
+#define SIERRA_CLKPATHCTRL_TMR (0x4081 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE1(0x4087 << 2)
+#define SIERRA_RX_CREQ_FLTR_A_MODE0(0x4088 << 2)
+#define SIERRA_CREQ

[RFC PATCH v2 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes from v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  65 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/cdns-sierra.c  | 385 +
 6 files changed, 463 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

[RFC PATCH v2 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Cadence Sierra PHY supports a number of different protocols.  This
series adds a driver with support for USB3 and PCIe modes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Changes from v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
  device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode.  The complete PHY block
  is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers


Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  65 
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   2 +
 drivers/phy/cadence/cdns-sierra.c  | 385 +
 6 files changed, 463 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

RE: [RFC PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Hi,

Thanks for your comments.

On 20 August 2018 14:07, Kishon Vijay Abraham wrote:
> Hi,
> 
> On Friday 17 August 2018 06:01 PM, Alan Douglas wrote:
> > Add a Sierra PHY driver with PCIe and USB support.
> > There are two resets to the PHY, one to enable
> > the APB interface for programming registers, and
> > another to enable the PHY itself.
> >
> > The sequence of operation on startup is to enable
> > the APB bus, write the PHY registers and then
> > enable the PHY.
> >
> > On power-down we simply put the PHY and APB bus in
> > reset.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  drivers/phy/Kconfig   |   1 +
> >  drivers/phy/Makefile  |   1 +
> >  drivers/phy/cadence/Kconfig   |   9 ++
> >  drivers/phy/cadence/Makefile  |   3 +
> >  drivers/phy/cadence/cdns-sierra.c | 326 
> > ++
> >  5 files changed, 340 insertions(+)
> >  create mode 100644 drivers/phy/cadence/Kconfig
> >  create mode 100644 drivers/phy/cadence/Makefile
> >  create mode 100644 drivers/phy/cadence/cdns-sierra.c
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 5c8d452..cc47f85 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -43,6 +43,7 @@ config PHY_XGENE
> >  source "drivers/phy/allwinner/Kconfig"
> >  source "drivers/phy/amlogic/Kconfig"
> >  source "drivers/phy/broadcom/Kconfig"
> > +source "drivers/phy/cadence/Kconfig"
> >  source "drivers/phy/hisilicon/Kconfig"
> >  source "drivers/phy/lantiq/Kconfig"
> >  source "drivers/phy/marvell/Kconfig"
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index 84e3bd9..ba48acd 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
> >  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
> >  obj-$(CONFIG_ARCH_TEGRA)   += tegra/
> >  obj-y  += broadcom/\
> > +  cadence/ \
> >hisilicon/   \
> >marvell/ \
> >motorola/\
> > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
> > new file mode 100644
> > index 000..6bbe5a2
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Kconfig
> > @@ -0,0 +1,9 @@
> > +#
> > +# Phy drivers for cadence devices
> > +#
> > +config CDNS_SIERRA_PHY
> > +   tristate "CDNS Sierra PHY Driver"
> > +   depends on OF && HAS_IOMEM
> 
> depends on RESET_CONTROLLER?
Yes, I will add this.

> > +   select GENERIC_PHY
> > +   help
> > + Enable this to support the Cadence Sierra PHY driver
> > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
> > new file mode 100644
> > index 000..b384cb3
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
> > +
> > diff --git a/drivers/phy/cadence/cdns-sierra.c 
> > b/drivers/phy/cadence/cdns-sierra.c
> > new file mode 100644
> > index 000..0581516
> > --- /dev/null
> > +++ b/drivers/phy/cadence/cdns-sierra.c
> > @@ -0,0 +1,326 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Cadence Sierra PHY Driver
> > + *
> > + * Copyright (c) 2018 Cadence Design Systems
> > + * Author: Alan Douglas 
> > + *
> > + */
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define CDNS_PHY_PLL_CFG   (0xc00e << 2)
> > +#define CDNS_DET_STANDEC_A (0x4000 << 2)
> > +#define CDNS_DET_STANDEC_B (0x4001 << 2)
> > +#define CDNS_DET_STANDEC_C (0x4002 << 2)
> > +#define CDNS_DET_STANDEC_D (0x4003 << 2)
> > +#define CDNS_DET_STANDEC_E (0x4004 << 2)
> > +#define CDNS_PSM_LANECAL   (0x4008 << 2)
> > +#define CDNS_PSM_DIAG  (0x4015 << 2)
> > +#define CDNS_PSC_TX_A0 (0

RE: [RFC PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Hi,

Thanks for your comments.

On 20 August 2018 14:07, Kishon Vijay Abraham wrote:
> Hi,
> 
> On Friday 17 August 2018 06:01 PM, Alan Douglas wrote:
> > Add a Sierra PHY driver with PCIe and USB support.
> > There are two resets to the PHY, one to enable
> > the APB interface for programming registers, and
> > another to enable the PHY itself.
> >
> > The sequence of operation on startup is to enable
> > the APB bus, write the PHY registers and then
> > enable the PHY.
> >
> > On power-down we simply put the PHY and APB bus in
> > reset.
> >
> > Signed-off-by: Alan Douglas 
> > ---
> >  drivers/phy/Kconfig   |   1 +
> >  drivers/phy/Makefile  |   1 +
> >  drivers/phy/cadence/Kconfig   |   9 ++
> >  drivers/phy/cadence/Makefile  |   3 +
> >  drivers/phy/cadence/cdns-sierra.c | 326 
> > ++
> >  5 files changed, 340 insertions(+)
> >  create mode 100644 drivers/phy/cadence/Kconfig
> >  create mode 100644 drivers/phy/cadence/Makefile
> >  create mode 100644 drivers/phy/cadence/cdns-sierra.c
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 5c8d452..cc47f85 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -43,6 +43,7 @@ config PHY_XGENE
> >  source "drivers/phy/allwinner/Kconfig"
> >  source "drivers/phy/amlogic/Kconfig"
> >  source "drivers/phy/broadcom/Kconfig"
> > +source "drivers/phy/cadence/Kconfig"
> >  source "drivers/phy/hisilicon/Kconfig"
> >  source "drivers/phy/lantiq/Kconfig"
> >  source "drivers/phy/marvell/Kconfig"
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index 84e3bd9..ba48acd 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
> >  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
> >  obj-$(CONFIG_ARCH_TEGRA)   += tegra/
> >  obj-y  += broadcom/\
> > +  cadence/ \
> >hisilicon/   \
> >marvell/ \
> >motorola/\
> > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
> > new file mode 100644
> > index 000..6bbe5a2
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Kconfig
> > @@ -0,0 +1,9 @@
> > +#
> > +# Phy drivers for cadence devices
> > +#
> > +config CDNS_SIERRA_PHY
> > +   tristate "CDNS Sierra PHY Driver"
> > +   depends on OF && HAS_IOMEM
> 
> depends on RESET_CONTROLLER?
Yes, I will add this.

> > +   select GENERIC_PHY
> > +   help
> > + Enable this to support the Cadence Sierra PHY driver
> > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
> > new file mode 100644
> > index 000..b384cb3
> > --- /dev/null
> > +++ b/drivers/phy/cadence/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
> > +
> > diff --git a/drivers/phy/cadence/cdns-sierra.c 
> > b/drivers/phy/cadence/cdns-sierra.c
> > new file mode 100644
> > index 000..0581516
> > --- /dev/null
> > +++ b/drivers/phy/cadence/cdns-sierra.c
> > @@ -0,0 +1,326 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Cadence Sierra PHY Driver
> > + *
> > + * Copyright (c) 2018 Cadence Design Systems
> > + * Author: Alan Douglas 
> > + *
> > + */
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define CDNS_PHY_PLL_CFG   (0xc00e << 2)
> > +#define CDNS_DET_STANDEC_A (0x4000 << 2)
> > +#define CDNS_DET_STANDEC_B (0x4001 << 2)
> > +#define CDNS_DET_STANDEC_C (0x4002 << 2)
> > +#define CDNS_DET_STANDEC_D (0x4003 << 2)
> > +#define CDNS_DET_STANDEC_E (0x4004 << 2)
> > +#define CDNS_PSM_LANECAL   (0x4008 << 2)
> > +#define CDNS_PSM_DIAG  (0x4015 << 2)
> > +#define CDNS_PSC_TX_A0 (0

RE: [PATCH] PCI: remove unnecessary check of device_type == pci

[Alan Douglas]

Hi,

On 29 August 2018 19:35, Rob Herring wrote:
> To: Lorenzo Pieralisi 
> Cc: linux-kernel@vger.kernel.org; Will Deacon ; Bjorn 
> Helgaas ; Alan Douglas
> ; Subrahmanya Lingappa ; 
> Michal Simek ; linux-
> p...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Subject: [PATCH] PCI: remove unnecessary check of device_type == pci
> 
> EXTERNAL MAIL
> 
> 
> PCI host drivers have already matched on compatible strings, so checking
> device_type is redundant. Also, device_type is considered deprecated for
> FDT though we've still been requiring it for PCI hosts as it is useful
> for finding PCI buses.
> 
> Cc: Will Deacon 
> Cc: Lorenzo Pieralisi 
> Cc: Bjorn Helgaas 
> Cc: Alan Douglas 
> Cc: Subrahmanya Lingappa 
> Cc: Michal Simek 
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Rob Herring 
> ---
>  drivers/pci/controller/pci-host-common.c   | 8 
>  drivers/pci/controller/pcie-cadence-host.c | 7 ---
>  drivers/pci/controller/pcie-mobiveil.c | 7 ---
>  drivers/pci/controller/pcie-xilinx-nwl.c   | 9 -
>  drivers/pci/controller/pcie-xilinx.c   | 7 ---
>  5 files changed, 38 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-host-common.c 
> b/drivers/pci/controller/pci-host-common.c
> index d8f10451f273..c742881b5061 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -58,9 +58,7 @@ static struct pci_config_window *gen_pci_init(struct device 
> *dev,
>  int pci_host_common_probe(struct platform_device *pdev,
> struct pci_ecam_ops *ops)
>  {
> - const char *type;
>   struct device *dev = >dev;
> - struct device_node *np = dev->of_node;
>   struct pci_host_bridge *bridge;
>   struct pci_config_window *cfg;
>   struct list_head resources;
> @@ -70,12 +68,6 @@ int pci_host_common_probe(struct platform_device *pdev,
>   if (!bridge)
>   return -ENOMEM;
> 
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
>   of_pci_check_probe_only();
> 
>   /* Parse and map our Configuration Space windows */
> diff --git a/drivers/pci/controller/pcie-cadence-host.c 
> b/drivers/pci/controller/pcie-cadence-host.c
> index ec394f6a19c8..97e251090b4f 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -235,7 +235,6 @@ static int cdns_pcie_host_init(struct device *dev,
> 
>  static int cdns_pcie_host_probe(struct platform_device *pdev)
>  {
> - const char *type;
>   struct device *dev = >dev;
>   struct device_node *np = dev->of_node;
>   struct pci_host_bridge *bridge;
> @@ -268,12 +267,6 @@ static int cdns_pcie_host_probe(struct platform_device 
> *pdev)
>   rc->device_id = 0x;
>   of_property_read_u16(np, "device-id", >device_id);
> 
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
>   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
>   pcie->reg_base = devm_ioremap_resource(dev, res);
>   if (IS_ERR(pcie->reg_base)) {
With regards to drivers/pci/controller/pcie-cadence-host.c
Acked-by: Alan Douglas 

RE: [PATCH] PCI: remove unnecessary check of device_type == pci

[Alan Douglas]

Hi,

On 29 August 2018 19:35, Rob Herring wrote:
> To: Lorenzo Pieralisi 
> Cc: linux-kernel@vger.kernel.org; Will Deacon ; Bjorn 
> Helgaas ; Alan Douglas
> ; Subrahmanya Lingappa ; 
> Michal Simek ; linux-
> p...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Subject: [PATCH] PCI: remove unnecessary check of device_type == pci
> 
> EXTERNAL MAIL
> 
> 
> PCI host drivers have already matched on compatible strings, so checking
> device_type is redundant. Also, device_type is considered deprecated for
> FDT though we've still been requiring it for PCI hosts as it is useful
> for finding PCI buses.
> 
> Cc: Will Deacon 
> Cc: Lorenzo Pieralisi 
> Cc: Bjorn Helgaas 
> Cc: Alan Douglas 
> Cc: Subrahmanya Lingappa 
> Cc: Michal Simek 
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Rob Herring 
> ---
>  drivers/pci/controller/pci-host-common.c   | 8 
>  drivers/pci/controller/pcie-cadence-host.c | 7 ---
>  drivers/pci/controller/pcie-mobiveil.c | 7 ---
>  drivers/pci/controller/pcie-xilinx-nwl.c   | 9 -
>  drivers/pci/controller/pcie-xilinx.c   | 7 ---
>  5 files changed, 38 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-host-common.c 
> b/drivers/pci/controller/pci-host-common.c
> index d8f10451f273..c742881b5061 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -58,9 +58,7 @@ static struct pci_config_window *gen_pci_init(struct device 
> *dev,
>  int pci_host_common_probe(struct platform_device *pdev,
> struct pci_ecam_ops *ops)
>  {
> - const char *type;
>   struct device *dev = >dev;
> - struct device_node *np = dev->of_node;
>   struct pci_host_bridge *bridge;
>   struct pci_config_window *cfg;
>   struct list_head resources;
> @@ -70,12 +68,6 @@ int pci_host_common_probe(struct platform_device *pdev,
>   if (!bridge)
>   return -ENOMEM;
> 
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
>   of_pci_check_probe_only();
> 
>   /* Parse and map our Configuration Space windows */
> diff --git a/drivers/pci/controller/pcie-cadence-host.c 
> b/drivers/pci/controller/pcie-cadence-host.c
> index ec394f6a19c8..97e251090b4f 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -235,7 +235,6 @@ static int cdns_pcie_host_init(struct device *dev,
> 
>  static int cdns_pcie_host_probe(struct platform_device *pdev)
>  {
> - const char *type;
>   struct device *dev = >dev;
>   struct device_node *np = dev->of_node;
>   struct pci_host_bridge *bridge;
> @@ -268,12 +267,6 @@ static int cdns_pcie_host_probe(struct platform_device 
> *pdev)
>   rc->device_id = 0x;
>   of_property_read_u16(np, "device-id", >device_id);
> 
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
>   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
>   pcie->reg_base = devm_ioremap_resource(dev, res);
>   if (IS_ERR(pcie->reg_base)) {
With regards to drivers/pci/controller/pcie-cadence-host.c
Acked-by: Alan Douglas 

[RFC PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.
There are two resets to the PHY, one to enable
the APB interface for programming registers, and
another to enable the PHY itself.

The sequence of operation on startup is to enable
the APB bus, write the PHY registers and then
enable the PHY.

On power-down we simply put the PHY and APB bus in
reset.

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 ++
 drivers/phy/cadence/Makefile  |   3 +
 drivers/phy/cadence/cdns-sierra.c | 326 ++
 5 files changed, 340 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..6bbe5a2
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for cadence devices
+#
+config CDNS_SIERRA_PHY
+   tristate "CDNS Sierra PHY Driver"
+   depends on OF && HAS_IOMEM
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..b384cb3
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
+
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..0581516
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CDNS_PHY_PLL_CFG   (0xc00e << 2)
+#define CDNS_DET_STANDEC_A (0x4000 << 2)
+#define CDNS_DET_STANDEC_B (0x4001 << 2)
+#define CDNS_DET_STANDEC_C (0x4002 << 2)
+#define CDNS_DET_STANDEC_D (0x4003 << 2)
+#define CDNS_DET_STANDEC_E (0x4004 << 2)
+#define CDNS_PSM_LANECAL   (0x4008 << 2)
+#define CDNS_PSM_DIAG  (0x4015 << 2)
+#define CDNS_PSC_TX_A0 (0x4028 << 2)
+#define CDNS_PSC_TX_A1 (0x4029 << 2)
+#define CDNS_PSC_TX_A2 (0x402A << 2)
+#define CDNS_PSC_TX_A3 (0x402B << 2)
+#define CDNS_PSC_RX_A0 (0x4030 << 2)
+#define CDNS_PSC_RX_A1 (0x4031 << 2)
+#define CDNS_PSC_RX_A2 (0x4032 << 2)
+#define CDNS_PSC_RX_A3 (0x4033 << 2)
+#define CDNS_PLLCTRL_SUBRATE   (0x403A << 2)
+#define CDNS_PLLCTRL_GEN_D (0x403E << 2)
+#define CDNS_DRVCTRL_ATTEN (0x406A << 2)
+#define CDNS_CLKPATHCTRL_TMR   (0x4081 << 2)
+#define CDNS_RX_CREQ_FLTR_A_MODE1  (0x4087 << 2)
+#define CDNS_RX_CREQ_FLTR_A_MODE0  (0x4088 << 2)
+#define CDNS_CREQ_CCLKDET_MODE01   (0x408E << 2)
+#define CDNS_RX_CTLE_MAINTENANCE   (0x4091 << 2)
+#define CDNS_CREQ_FSMCLK_SEL   (0x4092 << 2)
+#define CDNS_CTLELUT_CTRL  (0x4098 << 2)
+#define CDNS_DFE_ECMP_RATESEL  (0x40C0 << 2)
+#define CDNS_DFE_SMP_RATESEL   (0x40C1 << 2)
+#define CDNS_DEQ_VGATUNE_CTRL  (0x40E1 << 2)
+#define CDNS_TMRVAL_MODE3  (0x416E << 2)
+#define CDNS_TMRV

[RFC PATCH 2/2] phy: cadence: Add driver for Sierra PHY

[Alan Douglas]

Add a Sierra PHY driver with PCIe and USB support.
There are two resets to the PHY, one to enable
the APB interface for programming registers, and
another to enable the PHY itself.

The sequence of operation on startup is to enable
the APB bus, write the PHY registers and then
enable the PHY.

On power-down we simply put the PHY and APB bus in
reset.

Signed-off-by: Alan Douglas 
---
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/cadence/Kconfig   |   9 ++
 drivers/phy/cadence/Makefile  |   3 +
 drivers/phy/cadence/cdns-sierra.c | 326 ++
 5 files changed, 340 insertions(+)
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c8d452..cc47f85 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,7 @@ config PHY_XGENE
 source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
+source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 84e3bd9..ba48acd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_RENESAS)+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y  += broadcom/\
+  cadence/ \
   hisilicon/   \
   marvell/ \
   motorola/\
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
new file mode 100644
index 000..6bbe5a2
--- /dev/null
+++ b/drivers/phy/cadence/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for cadence devices
+#
+config CDNS_SIERRA_PHY
+   tristate "CDNS Sierra PHY Driver"
+   depends on OF && HAS_IOMEM
+   select GENERIC_PHY
+   help
+ Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
new file mode 100644
index 000..b384cb3
--- /dev/null
+++ b/drivers/phy/cadence/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CDNS_SIERRA_PHY)  += cdns-sierra.o
+
diff --git a/drivers/phy/cadence/cdns-sierra.c 
b/drivers/phy/cadence/cdns-sierra.c
new file mode 100644
index 000..0581516
--- /dev/null
+++ b/drivers/phy/cadence/cdns-sierra.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence Sierra PHY Driver
+ *
+ * Copyright (c) 2018 Cadence Design Systems
+ * Author: Alan Douglas 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CDNS_PHY_PLL_CFG   (0xc00e << 2)
+#define CDNS_DET_STANDEC_A (0x4000 << 2)
+#define CDNS_DET_STANDEC_B (0x4001 << 2)
+#define CDNS_DET_STANDEC_C (0x4002 << 2)
+#define CDNS_DET_STANDEC_D (0x4003 << 2)
+#define CDNS_DET_STANDEC_E (0x4004 << 2)
+#define CDNS_PSM_LANECAL   (0x4008 << 2)
+#define CDNS_PSM_DIAG  (0x4015 << 2)
+#define CDNS_PSC_TX_A0 (0x4028 << 2)
+#define CDNS_PSC_TX_A1 (0x4029 << 2)
+#define CDNS_PSC_TX_A2 (0x402A << 2)
+#define CDNS_PSC_TX_A3 (0x402B << 2)
+#define CDNS_PSC_RX_A0 (0x4030 << 2)
+#define CDNS_PSC_RX_A1 (0x4031 << 2)
+#define CDNS_PSC_RX_A2 (0x4032 << 2)
+#define CDNS_PSC_RX_A3 (0x4033 << 2)
+#define CDNS_PLLCTRL_SUBRATE   (0x403A << 2)
+#define CDNS_PLLCTRL_GEN_D (0x403E << 2)
+#define CDNS_DRVCTRL_ATTEN (0x406A << 2)
+#define CDNS_CLKPATHCTRL_TMR   (0x4081 << 2)
+#define CDNS_RX_CREQ_FLTR_A_MODE1  (0x4087 << 2)
+#define CDNS_RX_CREQ_FLTR_A_MODE0  (0x4088 << 2)
+#define CDNS_CREQ_CCLKDET_MODE01   (0x408E << 2)
+#define CDNS_RX_CTLE_MAINTENANCE   (0x4091 << 2)
+#define CDNS_CREQ_FSMCLK_SEL   (0x4092 << 2)
+#define CDNS_CTLELUT_CTRL  (0x4098 << 2)
+#define CDNS_DFE_ECMP_RATESEL  (0x40C0 << 2)
+#define CDNS_DFE_SMP_RATESEL   (0x40C1 << 2)
+#define CDNS_DEQ_VGATUNE_CTRL  (0x40E1 << 2)
+#define CDNS_TMRVAL_MODE3  (0x416E << 2)
+#define CDNS_TMRV

[RFC PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.  The
number of lanes can also be configured.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..846bdfc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,29 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+ - compatible: cdns,sierra-phy
+ - clocks: Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "phy_clk"
+ - resets: Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names: Must include "sierra_reset" and "sierra_apb"
+   "sierra_reset" must control the reset line to the PHY
+   "sierra_apb" must control the reset line to the APB PHY interface
+ - #phy-cells: must be 2
+ - reg : register range for the PHY
+ - reg-names: Must be "reg"
+
+
+Example:
+   pcie_phy4: pcie-phy4@fd24 {
+   compatible = "cdns,sierra-phy";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   reg-names = "reg";
+   #phy-cells = <2>;
+   resets = < 0>, < 0>;
+   reset-names = "sierra_reset","sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   };
-- 
1.9.0

[RFC PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings

[Alan Douglas]

Add DT binding documentation for Sierra PHY.  The PHY supports
a number of different protocols, including PCIe and USB.  The
number of lanes can also be configured.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/phy/cdns-sierra-phy.txt| 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt 
b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
new file mode 100644
index 000..846bdfc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
@@ -0,0 +1,29 @@
+Cadence Sierra PHY
+---
+
+Required properties:
+ - compatible: cdns,sierra-phy
+ - clocks: Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "phy_clk"
+ - resets: Must contain an entry for each in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names: Must include "sierra_reset" and "sierra_apb"
+   "sierra_reset" must control the reset line to the PHY
+   "sierra_apb" must control the reset line to the APB PHY interface
+ - #phy-cells: must be 2
+ - reg : register range for the PHY
+ - reg-names: Must be "reg"
+
+
+Example:
+   pcie_phy4: pcie-phy4@fd24 {
+   compatible = "cdns,sierra-phy";
+   reg = <0x0 0xfd24 0x0 0x4>;
+   reg-names = "reg";
+   #phy-cells = <2>;
+   resets = < 0>, < 0>;
+   reset-names = "sierra_reset","sierra_apb";
+   clocks = <>;
+   clock-names = "phy_clk";
+   };
-- 
1.9.0

[RFC PATCH 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Sierra PHY supports a number of different protocol.  This series adds
a driver with support for USB3 and PCIe modes.

Two phy-cells are required in device tree bindings, one to specify the
protocol to be supported, and the second to specify the number of lanes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  29 ++
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   3 +
 drivers/phy/cadence/cdns-sierra.c  | 326 +
 6 files changed, 369 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

[RFC PATCH 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY

[Alan Douglas]

The Sierra PHY supports a number of different protocol.  This series adds
a driver with support for USB3 and PCIe modes.

Two phy-cells are required in device tree bindings, one to specify the
protocol to be supported, and the second to specify the number of lanes.

Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.

Alan Douglas (2):
  dt-bindings: phy: Document cadence Sierra PHY bindings
  phy: cadence: Add driver for Sierra PHY

 .../devicetree/bindings/phy/cdns-sierra-phy.txt|  29 ++
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/cadence/Kconfig|   9 +
 drivers/phy/cadence/Makefile   |   3 +
 drivers/phy/cadence/cdns-sierra.c  | 326 +
 6 files changed, 369 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
 create mode 100644 drivers/phy/cadence/Kconfig
 create mode 100644 drivers/phy/cadence/Makefile
 create mode 100644 drivers/phy/cadence/cdns-sierra.c

-- 
1.9.0

RE: [PATCH] PCI: pcie-candence-ep: remove redundant variable mmc

[Alan Douglas]

On 11 July 2018 09:01, Colin King wrote:
> From: Colin Ian King 
> 
> Variable mmc is being assigned but is never used hence it is redundant
> and can be removed.
> 
> Cleans up clang warning:
> warning: variable 'mmc' set but not used [-Wunused-but-set-variable]
> 
> Signed-off-by: Colin Ian King 
> ---
>  drivers/pci/controller/pcie-cadence-ep.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-cadence-ep.c 
> b/drivers/pci/controller/pcie-cadence-ep.c
> index e3fe4124e3af..63549e03eae8 100644
> --- a/drivers/pci/controller/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/pcie-cadence-ep.c
> @@ -238,7 +238,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 
> fn)
>   struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
>   struct cdns_pcie *pcie = >pcie;
>   u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
> - u16 flags, mmc, mme;
> + u16 flags, mme;
> 
>   /* Validate that the MSI feature is actually enabled. */
>   flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
> @@ -249,7 +249,6 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 
> fn)
>* Get the Multiple Message Enable bitfield from the Message Control
>* register.
>*/
> - mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
>   mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
> 
>   return mme;
> --
> 2.17.1
Thanks for spotting this, mmc is not needed here, just interested in mme.
Acked-by: Alan Douglas 

RE: [PATCH] PCI: pcie-candence-ep: remove redundant variable mmc

[Alan Douglas]

On 11 July 2018 09:01, Colin King wrote:
> From: Colin Ian King 
> 
> Variable mmc is being assigned but is never used hence it is redundant
> and can be removed.
> 
> Cleans up clang warning:
> warning: variable 'mmc' set but not used [-Wunused-but-set-variable]
> 
> Signed-off-by: Colin Ian King 
> ---
>  drivers/pci/controller/pcie-cadence-ep.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-cadence-ep.c 
> b/drivers/pci/controller/pcie-cadence-ep.c
> index e3fe4124e3af..63549e03eae8 100644
> --- a/drivers/pci/controller/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/pcie-cadence-ep.c
> @@ -238,7 +238,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 
> fn)
>   struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
>   struct cdns_pcie *pcie = >pcie;
>   u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
> - u16 flags, mmc, mme;
> + u16 flags, mme;
> 
>   /* Validate that the MSI feature is actually enabled. */
>   flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
> @@ -249,7 +249,6 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 
> fn)
>* Get the Multiple Message Enable bitfield from the Message Control
>* register.
>*/
> - mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
>   mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
> 
>   return mme;
> --
> 2.17.1
Thanks for spotting this, mmc is not needed here, just interested in mme.
Acked-by: Alan Douglas 

[PATCH v2 0/4] PCI: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

This is a series of patches for the cadence PCIe host and EP drivers, to:
 - Add optional list of generic PHYs to host and EP drivers
 - Add PHY bindings to devicetree
 - Add Power Management ops, which will enable/disable PHYs if present
- Update cdns_pcie_writel function signature

Changes in v2:
Split commit into four patches
Re-based on v4.17-rc1

Alan Douglas (4):
  PCI: cadence: Update cdns_pcie_writel function signature
  PCI: cadence: Add generic PHY support to host and EP drivers
  dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
  PCI: cadence: Add Power Management ops for host and EP

 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |   4 +
 .../bindings/pci/cdns,cdns-pcie-host.txt   |   2 +
 drivers/pci/cadence/pcie-cadence-ep.c  |  15 ++-
 drivers/pci/cadence/pcie-cadence-host.c|  34 ++
 drivers/pci/cadence/pcie-cadence.c | 123 +
 drivers/pci/cadence/pcie-cadence.h |  13 ++-
 6 files changed, 189 insertions(+), 2 deletions(-)

--

[PATCH v2 0/4] PCI: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

This is a series of patches for the cadence PCIe host and EP drivers, to:
 - Add optional list of generic PHYs to host and EP drivers
 - Add PHY bindings to devicetree
 - Add Power Management ops, which will enable/disable PHYs if present
- Update cdns_pcie_writel function signature

Changes in v2:
Split commit into four patches
Re-based on v4.17-rc1

Alan Douglas (4):
  PCI: cadence: Update cdns_pcie_writel function signature
  PCI: cadence: Add generic PHY support to host and EP drivers
  dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
  PCI: cadence: Add Power Management ops for host and EP

 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |   4 +
 .../bindings/pci/cdns,cdns-pcie-host.txt   |   2 +
 drivers/pci/cadence/pcie-cadence-ep.c  |  15 ++-
 drivers/pci/cadence/pcie-cadence-host.c|  34 ++
 drivers/pci/cadence/pcie-cadence.c | 123 +
 drivers/pci/cadence/pcie-cadence.h |  13 ++-
 6 files changed, 189 insertions(+), 2 deletions(-)

--

[PATCH v2 1/4] PCI: cadence: Update cdns_pcie_writel function signature

[Alan Douglas]

From: Alan Douglas <adoug...@cadence.com>

Change cdns_pcie_writel() signature, u16 value changed to u32, since
this function should write a long value

Signed-off-by: Alan Douglas <adoug...@cadence.com>
---
 drivers/pci/cadence/pcie-cadence.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/cadence/pcie-cadence.h 
b/drivers/pci/cadence/pcie-cadence.h
index 4bb2733..ed336cc 100644
--- a/drivers/pci/cadence/pcie-cadence.h
+++ b/drivers/pci/cadence/pcie-cadence.h
@@ -279,7 +279,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie 
*pcie, u8 fn,
 }
 
 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
- u32 reg, u16 value)
+ u32 reg, u32 value)
 {
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
 }
-- 
2.2.2

[PATCH v2 1/4] PCI: cadence: Update cdns_pcie_writel function signature

[Alan Douglas]

From: Alan Douglas 

Change cdns_pcie_writel() signature, u16 value changed to u32, since
this function should write a long value

Signed-off-by: Alan Douglas 
---
 drivers/pci/cadence/pcie-cadence.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/cadence/pcie-cadence.h 
b/drivers/pci/cadence/pcie-cadence.h
index 4bb2733..ed336cc 100644
--- a/drivers/pci/cadence/pcie-cadence.h
+++ b/drivers/pci/cadence/pcie-cadence.h
@@ -279,7 +279,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie 
*pcie, u8 fn,
 }
 
 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
- u32 reg, u16 value)
+ u32 reg, u32 value)
 {
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
 }
-- 
2.2.2

[PATCH] pci: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

From: Alan Douglas <adoug...@cadence.com>

This patch is based on next branch in Bjorn Helgaas' linux-pci git repository.

Allow optional list of generic PHYs to be provided via DTS for cadence RP and 
EP drivers.
Added power management ops which will enable/disable these PHYs.  
Corrected parameters for cdns_pcie_writel function, value to be written had too 
small width.

Signed-off-by: Alan Douglas <adoug...@cadence.com>
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |4 +
 .../bindings/pci/cdns,cdns-pcie-host.txt   |5 +
 drivers/pci/cadence/pcie-cadence-ep.c  |   15 +++-
 drivers/pci/cadence/pcie-cadence-host.c|   36 ++-
 drivers/pci/cadence/pcie-cadence.c |  123 
 drivers/pci/cadence/pcie-cadence.h |   13 ++-
 6 files changed, 193 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt 
b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..e40c635 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 
1).
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +21,6 @@ pcie@fc00 {
reg-names = "reg", "mem";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <8>;
+   phys = <_phy0 _phy1>;
+   phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt 
b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..13be218 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,8 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +59,7 @@ pcie@fb00 {
interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
msi-parent = <_pci>;
+
+   phys = <_phy0>;
+   phy-names = "pcie-phy";
 };
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c 
b/drivers/pci/cadence/pcie-cadence-ep.c
index 3d8283e..e74b8a4 100644
--- a/drivers/pci/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -439,6 +439,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
struct pci_epc *epc;
struct resource *res;
int ret;
+   int phy_count;
 
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
if (!ep)
@@ -472,6 +473,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
if (!ep->ob_addr)
return -ENOMEM;
 
+   ret = cdns_pcie_init_phy(dev, pcie);
+   if (ret) {
+   dev_err(dev, "failed to init phy\n");
+   return ret;
+   }
+   platform_set_drvdata(pdev, pcie);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
@@ -520,6 +527,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 
  err_get_sync:
pm_runtime_disable(dev);
+   cdns_pcie_disable_phy(pcie);
+   phy_count = pcie->phy_count;
+   while (phy_count--)
+   device_link_del(pcie->link[phy_count]);
 
return ret;
 }
@@ -527,6 +538,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 {
struct device *dev = >dev;
+   struct cdns_pcie *pcie = dev_get_drvdata(dev);
int ret;
 
ret = pm_runtime_put_sync(dev);
@@ -535,13 +547,14 @@ static void cdns_pcie_ep_shutdown(struct platform_device 
*pdev)
 
pm_runtime_disable(dev);
 
-   /* The PCIe controller can't be disabled. */
+   cdns_pcie_disable_phy(pcie);
 }
 
 static struct platform_driver cdns_pcie_ep_driver = {
.driver = {
.name = "cdns-pcie-ep",
.of_match_table = cdns_pcie_ep_of_match,
+   .pm = _pcie_pm_ops,
},
.probe = cdns_pcie_ep_probe,
.shutdown = cdns_pcie_ep_shutdown,
diff --git a/drivers/pci/cadence/pcie-cadence-host.c 
b/drivers/pci/cadence/pcie-cadence-host.c
index a4ebbd3..992ebe2 100644
--- a/drivers/pci/cadence/pcie-cadence-host.c
+++ b/drivers/pci/cadence/pcie-cadence-host.c
@@ -37,7 +37,6 @@ struct cdns_pcie_rc {
u16 vendor_id;
u16 device_id;

[PATCH] pci: cadence: Host and EP driver updates for PHY and power management

[Alan Douglas]

From: Alan Douglas 

This patch is based on next branch in Bjorn Helgaas' linux-pci git repository.

Allow optional list of generic PHYs to be provided via DTS for cadence RP and 
EP drivers.
Added power management ops which will enable/disable these PHYs.  
Corrected parameters for cdns_pcie_writel function, value to be written had too 
small width.

Signed-off-by: Alan Douglas 
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |4 +
 .../bindings/pci/cdns,cdns-pcie-host.txt   |5 +
 drivers/pci/cadence/pcie-cadence-ep.c  |   15 +++-
 drivers/pci/cadence/pcie-cadence-host.c|   36 ++-
 drivers/pci/cadence/pcie-cadence.c |  123 
 drivers/pci/cadence/pcie-cadence.h |   13 ++-
 6 files changed, 193 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt 
b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..e40c635 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,8 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 
1).
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +21,6 @@ pcie@fc00 {
reg-names = "reg", "mem";
cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <8>;
+   phys = <_phy0 _phy1>;
+   phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt 
b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..13be218 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,8 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles.
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +59,7 @@ pcie@fb00 {
interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
msi-parent = <_pci>;
+
+   phys = <_phy0>;
+   phy-names = "pcie-phy";
 };
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c 
b/drivers/pci/cadence/pcie-cadence-ep.c
index 3d8283e..e74b8a4 100644
--- a/drivers/pci/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -439,6 +439,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
struct pci_epc *epc;
struct resource *res;
int ret;
+   int phy_count;
 
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
if (!ep)
@@ -472,6 +473,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
if (!ep->ob_addr)
return -ENOMEM;
 
+   ret = cdns_pcie_init_phy(dev, pcie);
+   if (ret) {
+   dev_err(dev, "failed to init phy\n");
+   return ret;
+   }
+   platform_set_drvdata(pdev, pcie);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
@@ -520,6 +527,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 
  err_get_sync:
pm_runtime_disable(dev);
+   cdns_pcie_disable_phy(pcie);
+   phy_count = pcie->phy_count;
+   while (phy_count--)
+   device_link_del(pcie->link[phy_count]);
 
return ret;
 }
@@ -527,6 +538,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
 {
struct device *dev = >dev;
+   struct cdns_pcie *pcie = dev_get_drvdata(dev);
int ret;
 
ret = pm_runtime_put_sync(dev);
@@ -535,13 +547,14 @@ static void cdns_pcie_ep_shutdown(struct platform_device 
*pdev)
 
pm_runtime_disable(dev);
 
-   /* The PCIe controller can't be disabled. */
+   cdns_pcie_disable_phy(pcie);
 }
 
 static struct platform_driver cdns_pcie_ep_driver = {
.driver = {
.name = "cdns-pcie-ep",
.of_match_table = cdns_pcie_ep_of_match,
+   .pm = _pcie_pm_ops,
},
.probe = cdns_pcie_ep_probe,
.shutdown = cdns_pcie_ep_shutdown,
diff --git a/drivers/pci/cadence/pcie-cadence-host.c 
b/drivers/pci/cadence/pcie-cadence-host.c
index a4ebbd3..992ebe2 100644
--- a/drivers/pci/cadence/pcie-cadence-host.c
+++ b/drivers/pci/cadence/pcie-cadence-host.c
@@ -37,7 +37,6 @@ struct cdns_pcie_rc {
u16 vendor_id;
u16 device_id;
 };
-
 static void __iomem *cdns_pci_map_bus(struct pc

RE: [PATCH 06/10] misc: pci_endpoint_test: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On April 27, 2018, 4:57 p.m. Gustavo Pimentel wrote:
> Add MSI-X support and update driver documentation accordingly.
> 
> Add new driver parameter to allow interruption type selection.
> 
> Modify the Legacy/MSI/MSI-X test process, by:
>  - Add and use a specific register located in a BAR, which defines the 
> interrupt
> type is been triggered.
>  - Move the interrupt ID number from the command section to a register
> located in a BAR.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 121 
> +++
>  drivers/pci/endpoint/functions/pci-epf-test.c|  78 +++
>  3 files changed, 143 insertions(+), 59 deletions(-)
> 
In testing these changes  I found that pci_epc_raise_irq() also needs to be
updated in pci-epc-core.c, since it has interrupt_num parameter as u8

Thanks,
Alan

RE: [PATCH 06/10] misc: pci_endpoint_test: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On April 27, 2018, 4:57 p.m. Gustavo Pimentel wrote:
> Add MSI-X support and update driver documentation accordingly.
> 
> Add new driver parameter to allow interruption type selection.
> 
> Modify the Legacy/MSI/MSI-X test process, by:
>  - Add and use a specific register located in a BAR, which defines the 
> interrupt
> type is been triggered.
>  - Move the interrupt ID number from the command section to a register
> located in a BAR.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 121 
> +++
>  drivers/pci/endpoint/functions/pci-epf-test.c|  78 +++
>  3 files changed, 143 insertions(+), 59 deletions(-)
> 
In testing these changes  I found that pci_epc_raise_irq() also needs to be
updated in pci-epc-core.c, since it has interrupt_num parameter as u8

Thanks,
Alan

RE: [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler

[Alan Douglas]

Hi Kishon,

On 24 April 2018 10:36 Gustavo Pimentel wrote:
> Hi Kishon,
> 
> On 24/04/2018 08:07, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Monday 23 April 2018 03:06 PM, Gustavo Pimentel wrote:
> >> Hi Kishon,
> >>
> >> On 16/04/2018 10:29, Kishon Vijay Abraham I wrote:
> >>> Hi Gustavo,
> >>>
> >>> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
>  Changes the pcie_raise_irq function signature, namely the
>  interrupt_num variable type from u8 to u16 to accommodate the MSI-X
>  maximum interrupts of 2048.
> 
>  Implements a PCIe config space capability iterator function to
>  search and save the MSI and MSI-X pointers. With this method the
>  code becomes more generic and flexible.
> 
>  Implements MSI-X set/get functions for sysfs interface in order to
>  change the EP entries number.
> 
>  Implements EP MSI-X interface for triggering interruptions.
> 
>  Signed-off-by: Gustavo Pimentel 
>  ---
>   drivers/pci/dwc/pci-dra7xx.c   |   2 +-
>   drivers/pci/dwc/pcie-artpec6.c |   2 +-
>   drivers/pci/dwc/pcie-designware-ep.c   | 145
> -
>   drivers/pci/dwc/pcie-designware-plat.c |   6 +-
>   drivers/pci/dwc/pcie-designware.h  |  23 +-
>   5 files changed, 173 insertions(+), 5 deletions(-)
> 
>  diff --git a/drivers/pci/dwc/pci-dra7xx.c
>  b/drivers/pci/dwc/pci-dra7xx.c index ed8558d..5265725 100644
>  --- a/drivers/pci/dwc/pci-dra7xx.c
>  +++ b/drivers/pci/dwc/pci-dra7xx.c
>  @@ -369,7 +369,7 @@ static void dra7xx_pcie_raise_msi_irq(struct
>  dra7xx_pcie *dra7xx,  }
> 
>   static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  - enum pci_epc_irq_type type, u8
> interrupt_num)
>  + enum pci_epc_irq_type type, u16
> interrupt_num)
>   {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); diff --git
>  a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
>  index e66cede..96dc259 100644
>  --- a/drivers/pci/dwc/pcie-artpec6.c
>  +++ b/drivers/pci/dwc/pcie-artpec6.c
>  @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct
>  dw_pcie_ep *ep)  }
> 
>   static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  -  enum pci_epc_irq_type type, u8
> interrupt_num)
>  +  enum pci_epc_irq_type type, u16
> interrupt_num)
>   {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> 
>  diff --git a/drivers/pci/dwc/pcie-designware-ep.c
>  b/drivers/pci/dwc/pcie-designware-ep.c
>  index 15b22a6..874d4c2 100644
>  --- a/drivers/pci/dwc/pcie-designware-ep.c
>  +++ b/drivers/pci/dwc/pcie-designware-ep.c
>  @@ -40,6 +40,44 @@ void dw_pcie_ep_reset_bar(struct dw_pcie
> *pci, enum pci_barno bar)
>   __dw_pcie_ep_reset_bar(pci, bar, 0);  }
> 
>  +void dw_pcie_ep_find_cap_addr(struct dw_pcie_ep *ep) {
> >>>
> >>> This should be implemented in a generic way similar to
> pci_find_capability().
> >>> It'll be useful when we try to implement other capabilities as well.
> >>
> >> Hum, what you suggest? Something implemented on the pci-epf-core?
> >
> > yeah, Initially thought it could be implemented as a helper function
> > in pci-epc-core so that both designware and cadence can use it.
> 
> That would be nice, however I couldn't find out how to access the config
> space, through the pci_epf or pci_epc structs.
> 
> So, I reworked the functions like this:
> 
> (on pcie-designware-ep.c)
> 
> u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
>   u8 cap)
> {
> u8 cap_id, next_cap_ptr;
> u16 reg;
> 
> reg = dw_pcie_readw_dbi(pci, cap_ptr);
> next_cap_ptr = (reg & 0xff00) >> 8;
> cap_id = (reg & 0x00ff);
> 
> if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
> return 0;
> 
> if (cap_id == cap)
> return cap_ptr;
> 
> return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }
> 
> u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) {
> u8 next_cap_ptr;
> u16 reg;
> 
> reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
> next_cap_ptr = (reg & 0x00ff);
> 
> if (!next_cap_ptr)
> return 0;
> 
> return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }
> 
> int dw_pcie_ep_init(struct dw_pcie_ep *ep) { [...]
> ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
> ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); [...]
> }
> 
> >
> > But do we really have to find the address like this? since all
> > designware IP's will 

RE: [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler

[Alan Douglas]

Hi Kishon,

On 24 April 2018 10:36 Gustavo Pimentel wrote:
> Hi Kishon,
> 
> On 24/04/2018 08:07, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Monday 23 April 2018 03:06 PM, Gustavo Pimentel wrote:
> >> Hi Kishon,
> >>
> >> On 16/04/2018 10:29, Kishon Vijay Abraham I wrote:
> >>> Hi Gustavo,
> >>>
> >>> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote:
>  Changes the pcie_raise_irq function signature, namely the
>  interrupt_num variable type from u8 to u16 to accommodate the MSI-X
>  maximum interrupts of 2048.
> 
>  Implements a PCIe config space capability iterator function to
>  search and save the MSI and MSI-X pointers. With this method the
>  code becomes more generic and flexible.
> 
>  Implements MSI-X set/get functions for sysfs interface in order to
>  change the EP entries number.
> 
>  Implements EP MSI-X interface for triggering interruptions.
> 
>  Signed-off-by: Gustavo Pimentel 
>  ---
>   drivers/pci/dwc/pci-dra7xx.c   |   2 +-
>   drivers/pci/dwc/pcie-artpec6.c |   2 +-
>   drivers/pci/dwc/pcie-designware-ep.c   | 145
> -
>   drivers/pci/dwc/pcie-designware-plat.c |   6 +-
>   drivers/pci/dwc/pcie-designware.h  |  23 +-
>   5 files changed, 173 insertions(+), 5 deletions(-)
> 
>  diff --git a/drivers/pci/dwc/pci-dra7xx.c
>  b/drivers/pci/dwc/pci-dra7xx.c index ed8558d..5265725 100644
>  --- a/drivers/pci/dwc/pci-dra7xx.c
>  +++ b/drivers/pci/dwc/pci-dra7xx.c
>  @@ -369,7 +369,7 @@ static void dra7xx_pcie_raise_msi_irq(struct
>  dra7xx_pcie *dra7xx,  }
> 
>   static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  - enum pci_epc_irq_type type, u8
> interrupt_num)
>  + enum pci_epc_irq_type type, u16
> interrupt_num)
>   {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); diff --git
>  a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
>  index e66cede..96dc259 100644
>  --- a/drivers/pci/dwc/pcie-artpec6.c
>  +++ b/drivers/pci/dwc/pcie-artpec6.c
>  @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct
>  dw_pcie_ep *ep)  }
> 
>   static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  -  enum pci_epc_irq_type type, u8
> interrupt_num)
>  +  enum pci_epc_irq_type type, u16
> interrupt_num)
>   {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> 
>  diff --git a/drivers/pci/dwc/pcie-designware-ep.c
>  b/drivers/pci/dwc/pcie-designware-ep.c
>  index 15b22a6..874d4c2 100644
>  --- a/drivers/pci/dwc/pcie-designware-ep.c
>  +++ b/drivers/pci/dwc/pcie-designware-ep.c
>  @@ -40,6 +40,44 @@ void dw_pcie_ep_reset_bar(struct dw_pcie
> *pci, enum pci_barno bar)
>   __dw_pcie_ep_reset_bar(pci, bar, 0);  }
> 
>  +void dw_pcie_ep_find_cap_addr(struct dw_pcie_ep *ep) {
> >>>
> >>> This should be implemented in a generic way similar to
> pci_find_capability().
> >>> It'll be useful when we try to implement other capabilities as well.
> >>
> >> Hum, what you suggest? Something implemented on the pci-epf-core?
> >
> > yeah, Initially thought it could be implemented as a helper function
> > in pci-epc-core so that both designware and cadence can use it.
> 
> That would be nice, however I couldn't find out how to access the config
> space, through the pci_epf or pci_epc structs.
> 
> So, I reworked the functions like this:
> 
> (on pcie-designware-ep.c)
> 
> u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
>   u8 cap)
> {
> u8 cap_id, next_cap_ptr;
> u16 reg;
> 
> reg = dw_pcie_readw_dbi(pci, cap_ptr);
> next_cap_ptr = (reg & 0xff00) >> 8;
> cap_id = (reg & 0x00ff);
> 
> if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
> return 0;
> 
> if (cap_id == cap)
> return cap_ptr;
> 
> return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }
> 
> u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) {
> u8 next_cap_ptr;
> u16 reg;
> 
> reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
> next_cap_ptr = (reg & 0x00ff);
> 
> if (!next_cap_ptr)
> return 0;
> 
> return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }
> 
> int dw_pcie_ep_init(struct dw_pcie_ep *ep) { [...]
> ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
> ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); [...]
> }
> 
> >
> > But do we really have to find the address like this? since all
> > designware IP's will have a particular capability at a 

RE: [RFC 10/10] tools: PCI: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15, Gustavo Pimentel wrote:
> Adds MSI-X support to the pcitest tool and modified the pcitest.sh script to
> accomodate this new type of interruption test.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  include/uapi/linux/pcitest.h |  1 +
>  tools/pci/pcitest.c  | 18 +-
>  tools/pci/pcitest.sh | 25 +
>  3 files changed, 43 insertions(+), 1 deletion(-)
I found some possible problems when testing with the Cadence EP driver.  The 
problem
is that pcitest uses the BARs for tests, but we also use one for the MSI-X 
tables

In Cadence core the MSI-X table is in BAR0 by default, but this is configured 
to a size
of 0x80 in the test driver, since it is used as the test_reg_bar.  So, I 
changed the 
configuration to use BAR4 instead, which is configured to a size of 131072 
in pci-efp-test.c, and this gives me enough space.

However, if I run the BAR tests in pcitest before running the MSI-X tests, the
MSI-X tests fail, since the BAR content is overwritten.  It's not a problem 
with the 
scenario in pcitest.sh, but it would be if the module wasn't re-loaded.

So, wondering if we need to come up with some mechanism to specify that a 
specific
BAR will be used for MSI-X, and that its size and content shouldn't be modified 
by
pcitest?

Regards,
Alan

RE: [RFC 10/10] tools: PCI: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15, Gustavo Pimentel wrote:
> Adds MSI-X support to the pcitest tool and modified the pcitest.sh script to
> accomodate this new type of interruption test.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  include/uapi/linux/pcitest.h |  1 +
>  tools/pci/pcitest.c  | 18 +-
>  tools/pci/pcitest.sh | 25 +
>  3 files changed, 43 insertions(+), 1 deletion(-)
I found some possible problems when testing with the Cadence EP driver.  The 
problem
is that pcitest uses the BARs for tests, but we also use one for the MSI-X 
tables

In Cadence core the MSI-X table is in BAR0 by default, but this is configured 
to a size
of 0x80 in the test driver, since it is used as the test_reg_bar.  So, I 
changed the 
configuration to use BAR4 instead, which is configured to a size of 131072 
in pci-efp-test.c, and this gives me enough space.

However, if I run the BAR tests in pcitest before running the MSI-X tests, the
MSI-X tests fail, since the BAR content is overwritten.  It's not a problem 
with the 
scenario in pcitest.sh, but it would be if the module wasn't re-loaded.

So, wondering if we need to come up with some mechanism to specify that a 
specific
BAR will be used for MSI-X, and that its size and content shouldn't be modified 
by
pcitest?

Regards,
Alan

RE: [RFC 00/10] Adds pcitest tool support for MSI-X

[Alan Douglas]

On 24 April 2018 09:50, Gustavo Pimentel wrote:
> Hi Alan,
> 
> On 24/04/2018 07:48, Alan Douglas wrote:
> > Hi Gustavo,
> >
> > On 10 April 2018 18:15 Gustavo Pimentel wrote:
> >>  https://lkml.org/lkml/2018/4/10/421
> >>  This series aims to add pcitest tool support for MSI-X.
> >> Includes new callbacks methods and handlers to trigger the MSI-X
> >> interruptions on the EP Designware IP driver.
> >>
> >> Provides new methods on pci_epf_test driver that allows to set/get EP
> >> maximum number of MSI-X entries (similar to set/get MSI methods).
> >>
> >> Reworks on MSI set/get and triggering methods on EP Designware IP
> >> driver to be more generic and flexible.
> >>
> >> Adds a new input parameter (msix) and replicates the whole MSI
> >> mechanism applied to the MSI-X feature on pcitest tool. Also updates
> >> the pcitest script with the new test set applied to this new feature.
> >>
> >> Gustavo Pimentel (10):
> >>   PCI: dwc: Add MSI-X callbacks handler
> >>   PCI: cadence: Update cdns_pcie_ep_raise_irq function signature
> >>   PCI: endpoint: Add MSI-X interfaces
> >>   PCI: dwc: MSI callbacks handler rework
> >>   PCI: dwc: Add legacy interrupt callback handler
> >>   misc: pci_endpoint_test: Add MSI-X support
> >>   misc: pci_endpoint_test: Replace lower into upper case characters
> >>   PCI: endpoint: functions/pci-epf-test: Add MSI-X support
> >>   PCI: endpoint: functions/pci-epf-test: Replace lower into upper case
> >> characters
> >>   tools: PCI: Add MSI-X support
> >>
> >>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
> >>  drivers/misc/pci_endpoint_test.c | 120 ++
> >>  drivers/pci/cadence/pcie-cadence-ep.c|   2 +-
> >>  drivers/pci/dwc/pci-dra7xx.c |   2 +-
> >>  drivers/pci/dwc/pcie-artpec6.c   |   2 +-
> >>  drivers/pci/dwc/pcie-designware-ep.c | 201
> >> +--
> >>  drivers/pci/dwc/pcie-designware-plat.c   |   9 +-
> >>  drivers/pci/dwc/pcie-designware.h|  40 +++--
> >>  drivers/pci/endpoint/functions/pci-epf-test.c| 113 +
> >>  drivers/pci/endpoint/pci-ep-cfs.c|  24 +++
> >>  drivers/pci/endpoint/pci-epc-core.c  |  60 ++-
> >>  include/linux/pci-epc.h  |  11 +-
> >>  include/linux/pci-epf.h  |   1 +
> >>  include/uapi/linux/pcitest.h |   1 +
> >>  tools/pci/pcitest.c  |  18 +-
> >>  tools/pci/pcitest.sh |  25 +++
> >>  16 files changed, 528 insertions(+), 104 deletions(-)
> >>
> >> --
> >> 2.7.4
> >>
> > Nice set of patches.  I have tested this with the Cadence EP driver after
> adding MSI-X support, and found a few changes required.
> > I will send you comments.
> 
> Ok, great news!
> 
> Maybe after this patch series submission we could start a new thread about
> new features that could be tested/verified using pcitest. I think this could 
> be
> helpful for everybody.
> 
Great, I think that would definitely be of benefit.
> >
> > Thanks,
> > Alan
> >
> 
> Thanks,
> Gustavo
Thanks,
Alan

RE: [RFC 00/10] Adds pcitest tool support for MSI-X

[Alan Douglas]

On 24 April 2018 09:50, Gustavo Pimentel wrote:
> Hi Alan,
> 
> On 24/04/2018 07:48, Alan Douglas wrote:
> > Hi Gustavo,
> >
> > On 10 April 2018 18:15 Gustavo Pimentel wrote:
> >>  https://lkml.org/lkml/2018/4/10/421
> >>  This series aims to add pcitest tool support for MSI-X.
> >> Includes new callbacks methods and handlers to trigger the MSI-X
> >> interruptions on the EP Designware IP driver.
> >>
> >> Provides new methods on pci_epf_test driver that allows to set/get EP
> >> maximum number of MSI-X entries (similar to set/get MSI methods).
> >>
> >> Reworks on MSI set/get and triggering methods on EP Designware IP
> >> driver to be more generic and flexible.
> >>
> >> Adds a new input parameter (msix) and replicates the whole MSI
> >> mechanism applied to the MSI-X feature on pcitest tool. Also updates
> >> the pcitest script with the new test set applied to this new feature.
> >>
> >> Gustavo Pimentel (10):
> >>   PCI: dwc: Add MSI-X callbacks handler
> >>   PCI: cadence: Update cdns_pcie_ep_raise_irq function signature
> >>   PCI: endpoint: Add MSI-X interfaces
> >>   PCI: dwc: MSI callbacks handler rework
> >>   PCI: dwc: Add legacy interrupt callback handler
> >>   misc: pci_endpoint_test: Add MSI-X support
> >>   misc: pci_endpoint_test: Replace lower into upper case characters
> >>   PCI: endpoint: functions/pci-epf-test: Add MSI-X support
> >>   PCI: endpoint: functions/pci-epf-test: Replace lower into upper case
> >> characters
> >>   tools: PCI: Add MSI-X support
> >>
> >>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
> >>  drivers/misc/pci_endpoint_test.c | 120 ++
> >>  drivers/pci/cadence/pcie-cadence-ep.c|   2 +-
> >>  drivers/pci/dwc/pci-dra7xx.c |   2 +-
> >>  drivers/pci/dwc/pcie-artpec6.c   |   2 +-
> >>  drivers/pci/dwc/pcie-designware-ep.c | 201
> >> +--
> >>  drivers/pci/dwc/pcie-designware-plat.c   |   9 +-
> >>  drivers/pci/dwc/pcie-designware.h|  40 +++--
> >>  drivers/pci/endpoint/functions/pci-epf-test.c| 113 +
> >>  drivers/pci/endpoint/pci-ep-cfs.c|  24 +++
> >>  drivers/pci/endpoint/pci-epc-core.c  |  60 ++-
> >>  include/linux/pci-epc.h  |  11 +-
> >>  include/linux/pci-epf.h  |   1 +
> >>  include/uapi/linux/pcitest.h |   1 +
> >>  tools/pci/pcitest.c  |  18 +-
> >>  tools/pci/pcitest.sh |  25 +++
> >>  16 files changed, 528 insertions(+), 104 deletions(-)
> >>
> >> --
> >> 2.7.4
> >>
> > Nice set of patches.  I have tested this with the Cadence EP driver after
> adding MSI-X support, and found a few changes required.
> > I will send you comments.
> 
> Ok, great news!
> 
> Maybe after this patch series submission we could start a new thread about
> new features that could be tested/verified using pcitest. I think this could 
> be
> helpful for everybody.
> 
Great, I think that would definitely be of benefit.
> >
> > Thanks,
> > Alan
> >
> 
> Thanks,
> Gustavo
Thanks,
Alan

RE: [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler

[Alan Douglas]

Hi,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> Changes the pcie_raise_irq function signature, namely the interrupt_num
> variable type from u8 to u16 to accommodate the MSI-X maximum interrupts
> of 2048.
> 
> Implements a PCIe config space capability iterator function to search and save
> the MSI and MSI-X pointers. With this method the code becomes more
> generic and flexible.
> 
> Implements MSI-X set/get functions for sysfs interface in order to change the
> EP entries number.
> 
> Implements EP MSI-X interface for triggering interruptions.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  drivers/pci/dwc/pci-dra7xx.c   |   2 +-
>  drivers/pci/dwc/pcie-artpec6.c |   2 +-
>  drivers/pci/dwc/pcie-designware-ep.c   | 145
> -
>  drivers/pci/dwc/pcie-designware-plat.c |   6 +-
>  drivers/pci/dwc/pcie-designware.h  |  23 +-
>  5 files changed, 173 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index
> ed8558d..5265725 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -369,7 +369,7 @@ static void dra7xx_pcie_raise_msi_irq(struct
> dra7xx_pcie *dra7xx,  }
> 
>  static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> -  enum pci_epc_irq_type type, u8
> interrupt_num)
> +  enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); diff --git
> a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index
> e66cede..96dc259 100644
> --- a/drivers/pci/dwc/pcie-artpec6.c
> +++ b/drivers/pci/dwc/pcie-artpec6.c
> @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep
> *ep)  }
> 
>  static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> -   enum pci_epc_irq_type type, u8
> interrupt_num)
> +   enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> 
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-
> designware-ep.c
> index 15b22a6..874d4c2 100644
> --- a/drivers/pci/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -40,6 +40,44 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci,
> enum pci_barno bar)
>   __dw_pcie_ep_reset_bar(pci, bar, 0);
>  }
> 
> +void dw_pcie_ep_find_cap_addr(struct dw_pcie_ep *ep) {
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u8 next_ptr, curr_ptr, cap_id;
> + u16 reg;
> +
> + memset(>cap_addr, 0, sizeof(ep->cap_addr));
> +
> + reg = dw_pcie_readw_dbi(pci, PCI_STATUS);
> + if (!(reg & PCI_STATUS_CAP_LIST))
> + return;
> +
> + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
> + next_ptr = (reg & 0x00ff);
> + if (!next_ptr)
> + return;
> +
> + reg = dw_pcie_readw_dbi(pci, next_ptr);
> + curr_ptr = next_ptr;
> + next_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> +
> + while (next_ptr && (cap_id <= PCI_CAP_ID_MAX)) {
> + switch (cap_id) {
> + case PCI_CAP_ID_MSI:
> + ep->cap_addr.msi_addr = curr_ptr;
> + break;
> + case PCI_CAP_ID_MSIX:
> + ep->cap_addr.msix_addr = curr_ptr;
> + break;
> + }
> + reg = dw_pcie_readw_dbi(pci, next_ptr);
> + curr_ptr = next_ptr;
> + next_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> + }
> +}
> +
>  static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
>  struct pci_epf_header *hdr)
>  {
> @@ -241,8 +279,47 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc,
> u8 func_no, u8 encode_int)
>   return 0;
>  }
> 
> +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) {
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u32 val, reg;
> +
> + if (ep->cap_addr.msix_addr == 0)
> + return 0;
> +
> + reg = ep->cap_addr.msix_addr + PCI_MSIX_FLAGS;
> + val = dw_pcie_readw_dbi(pci, reg);
> + if (!(val & PCI_MSIX_FLAGS_ENABLE))
> + return -EINVAL;
> +
> + val &= PCI_MSIX_FLAGS_QSIZE;
> +
> + return val;
> +}
> +
> +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16
> +interrupts) {
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u32 val, reg;
> +
> + if (ep->cap_addr.msix_addr == 0)
> + return 0;
> +
> + reg = ep->cap_addr.msix_addr + PCI_MSIX_FLAGS;
> + val = dw_pcie_readw_dbi(pci, reg);
> + val &= ~PCI_MSIX_FLAGS_QSIZE;
> + val |= 

RE: [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler

[Alan Douglas]

Hi,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> Changes the pcie_raise_irq function signature, namely the interrupt_num
> variable type from u8 to u16 to accommodate the MSI-X maximum interrupts
> of 2048.
> 
> Implements a PCIe config space capability iterator function to search and save
> the MSI and MSI-X pointers. With this method the code becomes more
> generic and flexible.
> 
> Implements MSI-X set/get functions for sysfs interface in order to change the
> EP entries number.
> 
> Implements EP MSI-X interface for triggering interruptions.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  drivers/pci/dwc/pci-dra7xx.c   |   2 +-
>  drivers/pci/dwc/pcie-artpec6.c |   2 +-
>  drivers/pci/dwc/pcie-designware-ep.c   | 145
> -
>  drivers/pci/dwc/pcie-designware-plat.c |   6 +-
>  drivers/pci/dwc/pcie-designware.h  |  23 +-
>  5 files changed, 173 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index
> ed8558d..5265725 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -369,7 +369,7 @@ static void dra7xx_pcie_raise_msi_irq(struct
> dra7xx_pcie *dra7xx,  }
> 
>  static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> -  enum pci_epc_irq_type type, u8
> interrupt_num)
> +  enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); diff --git
> a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index
> e66cede..96dc259 100644
> --- a/drivers/pci/dwc/pcie-artpec6.c
> +++ b/drivers/pci/dwc/pcie-artpec6.c
> @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep
> *ep)  }
> 
>  static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> -   enum pci_epc_irq_type type, u8
> interrupt_num)
> +   enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> 
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-
> designware-ep.c
> index 15b22a6..874d4c2 100644
> --- a/drivers/pci/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -40,6 +40,44 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci,
> enum pci_barno bar)
>   __dw_pcie_ep_reset_bar(pci, bar, 0);
>  }
> 
> +void dw_pcie_ep_find_cap_addr(struct dw_pcie_ep *ep) {
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u8 next_ptr, curr_ptr, cap_id;
> + u16 reg;
> +
> + memset(>cap_addr, 0, sizeof(ep->cap_addr));
> +
> + reg = dw_pcie_readw_dbi(pci, PCI_STATUS);
> + if (!(reg & PCI_STATUS_CAP_LIST))
> + return;
> +
> + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
> + next_ptr = (reg & 0x00ff);
> + if (!next_ptr)
> + return;
> +
> + reg = dw_pcie_readw_dbi(pci, next_ptr);
> + curr_ptr = next_ptr;
> + next_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> +
> + while (next_ptr && (cap_id <= PCI_CAP_ID_MAX)) {
> + switch (cap_id) {
> + case PCI_CAP_ID_MSI:
> + ep->cap_addr.msi_addr = curr_ptr;
> + break;
> + case PCI_CAP_ID_MSIX:
> + ep->cap_addr.msix_addr = curr_ptr;
> + break;
> + }
> + reg = dw_pcie_readw_dbi(pci, next_ptr);
> + curr_ptr = next_ptr;
> + next_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> + }
> +}
> +
>  static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
>  struct pci_epf_header *hdr)
>  {
> @@ -241,8 +279,47 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc,
> u8 func_no, u8 encode_int)
>   return 0;
>  }
> 
> +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) {
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u32 val, reg;
> +
> + if (ep->cap_addr.msix_addr == 0)
> + return 0;
> +
> + reg = ep->cap_addr.msix_addr + PCI_MSIX_FLAGS;
> + val = dw_pcie_readw_dbi(pci, reg);
> + if (!(val & PCI_MSIX_FLAGS_ENABLE))
> + return -EINVAL;
> +
> + val &= PCI_MSIX_FLAGS_QSIZE;
> +
> + return val;
> +}
> +
> +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16
> +interrupts) {
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u32 val, reg;
> +
> + if (ep->cap_addr.msix_addr == 0)
> + return 0;
> +
> + reg = ep->cap_addr.msix_addr + PCI_MSIX_FLAGS;
> + val = dw_pcie_readw_dbi(pci, reg);
> + val &= ~PCI_MSIX_FLAGS_QSIZE;
> + val |= interrupts;
> + 

RE: [RFC 06/10] misc: pci_endpoint_test: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> 
> Adds the MSI-X support and updates driver documentation accordingly.
> 
> Changes the driver parameter in order to allow the interruption type
> selection.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 102 
> +--
>  2 files changed, 79 insertions(+), 26 deletions(-)
> 
> diff --git a/Documentation/misc-devices/pci-endpoint-test.txt
> b/Documentation/misc-devices/pci-endpoint-test.txt
> index 4ebc359..fdfa0f6 100644
> --- a/Documentation/misc-devices/pci-endpoint-test.txt
> +++ b/Documentation/misc-devices/pci-endpoint-test.txt
> @@ -10,6 +10,7 @@ The PCI driver for the test device performs the
> following tests
>   *) verifying addresses programmed in BAR
>   *) raise legacy IRQ
>   *) raise MSI IRQ
> + *) raise MSI-X IRQ
>   *) read data
>   *) write data
>   *) copy data
> @@ -25,6 +26,8 @@ ioctl
>   PCITEST_LEGACY_IRQ: Tests legacy IRQ
>   PCITEST_MSI: Tests message signalled interrupts. The MSI number
> to be tested should be passed as argument.
> + PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
> +   to be tested should be passed as argument.
>   PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
>   as argument.
>   PCITEST_READ: Perform read tests. The size of the buffer should be passed
> diff --git a/drivers/misc/pci_endpoint_test.c
> b/drivers/misc/pci_endpoint_test.c
> index 37db0fc..a7d9354 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -42,11 +42,16 @@
>  #define PCI_ENDPOINT_TEST_COMMAND0x4
>  #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
>  #define COMMAND_RAISE_MSI_IRQBIT(1)
> -#define MSI_NUMBER_SHIFT 2
> -/* 6 bits for MSI number */
> -#define COMMAND_READBIT(8)
> -#define COMMAND_WRITE   BIT(9)
> -#define COMMAND_COPYBIT(10)
> +#define COMMAND_RAISE_MSIX_IRQ   BIT(2)
> +#define IRQ_TYPE_SHIFT   3
> +#define IRQ_TYPE_LEGACY  0
> +#define IRQ_TYPE_MSI 1
> +#define IRQ_TYPE_MSIX2
> +#define MSI_NUMBER_SHIFT 5
> +/* 12 bits for MSI number */
> +#define COMMAND_READBIT(17)
> +#define COMMAND_WRITE   BIT(18)
> +#define COMMAND_COPYBIT(19)
> 
>  #define PCI_ENDPOINT_TEST_STATUS 0x8
>  #define STATUS_READ_SUCCESS BIT(0)
> @@ -73,9 +78,9 @@ static DEFINE_IDA(pci_endpoint_test_ida);
>  #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test,
> \
>   miscdev)
> 
> -static bool no_msi;
> -module_param(no_msi, bool, 0444);
> -MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in
> pci_endpoint_test");
> +static int irq_type = IRQ_TYPE_MSIX;
> +module_param(irq_type, int, 0444);
> +MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test
> (0
> +- Legacy, 1 - MSI, 2 - MSI-X)");
> 
>  enum pci_barno {
>   BAR_0,
> @@ -103,7 +108,7 @@ struct pci_endpoint_test {  struct
> pci_endpoint_test_data {
>   enum pci_barno test_reg_bar;
>   size_t alignment;
> - bool no_msi;
> + int irq_type;
>  };
> 
>  static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
> @@ -177,10 +182,10 @@ static bool pci_endpoint_test_bar(struct
> pci_endpoint_test *test,
> 
>  static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)  {
> - u32 val;
> + u32 val = COMMAND_RAISE_LEGACY_IRQ;
> 
> - pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
> -  COMMAND_RAISE_LEGACY_IRQ);
> + val |= (IRQ_TYPE_LEGACY << IRQ_TYPE_SHIFT);
> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, val);
>   val = wait_for_completion_timeout(>irq_raised,
> msecs_to_jiffies(1000));
>   if (!val)
> @@ -192,12 +197,12 @@ static bool pci_endpoint_test_legacy_irq(struct
> pci_endpoint_test *test)  static bool pci_endpoint_test_msi_irq(struct
> pci_endpoint_test *test,
> u8 msi_num)
>  {
> - u32 val;
> + u32 val = COMMAND_RAISE_MSI_IRQ;
>   struct pci_dev *pdev = test->pdev;
> 
> - pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
> -  msi_num << MSI_NUMBER_SHIFT |
> -  COMMAND_RAISE_MSI_IRQ);
> + val |= (msi_num << MSI_NUMBER_SHIFT);
> + val |= (IRQ_TYPE_MSI << IRQ_TYPE_SHIFT);
> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, val);
>   val = wait_for_completion_timeout(>irq_raised,
> msecs_to_jiffies(1000));
>   if 

RE: [RFC 06/10] misc: pci_endpoint_test: Add MSI-X support

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> 
> Adds the MSI-X support and updates driver documentation accordingly.
> 
> Changes the driver parameter in order to allow the interruption type
> selection.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 102 
> +--
>  2 files changed, 79 insertions(+), 26 deletions(-)
> 
> diff --git a/Documentation/misc-devices/pci-endpoint-test.txt
> b/Documentation/misc-devices/pci-endpoint-test.txt
> index 4ebc359..fdfa0f6 100644
> --- a/Documentation/misc-devices/pci-endpoint-test.txt
> +++ b/Documentation/misc-devices/pci-endpoint-test.txt
> @@ -10,6 +10,7 @@ The PCI driver for the test device performs the
> following tests
>   *) verifying addresses programmed in BAR
>   *) raise legacy IRQ
>   *) raise MSI IRQ
> + *) raise MSI-X IRQ
>   *) read data
>   *) write data
>   *) copy data
> @@ -25,6 +26,8 @@ ioctl
>   PCITEST_LEGACY_IRQ: Tests legacy IRQ
>   PCITEST_MSI: Tests message signalled interrupts. The MSI number
> to be tested should be passed as argument.
> + PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
> +   to be tested should be passed as argument.
>   PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
>   as argument.
>   PCITEST_READ: Perform read tests. The size of the buffer should be passed
> diff --git a/drivers/misc/pci_endpoint_test.c
> b/drivers/misc/pci_endpoint_test.c
> index 37db0fc..a7d9354 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -42,11 +42,16 @@
>  #define PCI_ENDPOINT_TEST_COMMAND0x4
>  #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
>  #define COMMAND_RAISE_MSI_IRQBIT(1)
> -#define MSI_NUMBER_SHIFT 2
> -/* 6 bits for MSI number */
> -#define COMMAND_READBIT(8)
> -#define COMMAND_WRITE   BIT(9)
> -#define COMMAND_COPYBIT(10)
> +#define COMMAND_RAISE_MSIX_IRQ   BIT(2)
> +#define IRQ_TYPE_SHIFT   3
> +#define IRQ_TYPE_LEGACY  0
> +#define IRQ_TYPE_MSI 1
> +#define IRQ_TYPE_MSIX2
> +#define MSI_NUMBER_SHIFT 5
> +/* 12 bits for MSI number */
> +#define COMMAND_READBIT(17)
> +#define COMMAND_WRITE   BIT(18)
> +#define COMMAND_COPYBIT(19)
> 
>  #define PCI_ENDPOINT_TEST_STATUS 0x8
>  #define STATUS_READ_SUCCESS BIT(0)
> @@ -73,9 +78,9 @@ static DEFINE_IDA(pci_endpoint_test_ida);
>  #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test,
> \
>   miscdev)
> 
> -static bool no_msi;
> -module_param(no_msi, bool, 0444);
> -MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in
> pci_endpoint_test");
> +static int irq_type = IRQ_TYPE_MSIX;
> +module_param(irq_type, int, 0444);
> +MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test
> (0
> +- Legacy, 1 - MSI, 2 - MSI-X)");
> 
>  enum pci_barno {
>   BAR_0,
> @@ -103,7 +108,7 @@ struct pci_endpoint_test {  struct
> pci_endpoint_test_data {
>   enum pci_barno test_reg_bar;
>   size_t alignment;
> - bool no_msi;
> + int irq_type;
>  };
> 
>  static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
> @@ -177,10 +182,10 @@ static bool pci_endpoint_test_bar(struct
> pci_endpoint_test *test,
> 
>  static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)  {
> - u32 val;
> + u32 val = COMMAND_RAISE_LEGACY_IRQ;
> 
> - pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
> -  COMMAND_RAISE_LEGACY_IRQ);
> + val |= (IRQ_TYPE_LEGACY << IRQ_TYPE_SHIFT);
> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, val);
>   val = wait_for_completion_timeout(>irq_raised,
> msecs_to_jiffies(1000));
>   if (!val)
> @@ -192,12 +197,12 @@ static bool pci_endpoint_test_legacy_irq(struct
> pci_endpoint_test *test)  static bool pci_endpoint_test_msi_irq(struct
> pci_endpoint_test *test,
> u8 msi_num)
>  {
> - u32 val;
> + u32 val = COMMAND_RAISE_MSI_IRQ;
>   struct pci_dev *pdev = test->pdev;
> 
> - pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
> -  msi_num << MSI_NUMBER_SHIFT |
> -  COMMAND_RAISE_MSI_IRQ);
> + val |= (msi_num << MSI_NUMBER_SHIFT);
> + val |= (IRQ_TYPE_MSI << IRQ_TYPE_SHIFT);
> + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND, val);
>   val = wait_for_completion_timeout(>irq_raised,
> msecs_to_jiffies(1000));
>   if (!val)
> @@ -209,6 +214,26 @@ 

RE: [RFC 00/10] Adds pcitest tool support for MSI-X

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> This patch set depends the following series:
> https://lkml.org/lkml/2018/4/10/421> This series aims to add pcitest tool 
> support for MSI-X.
> 
> Includes new callbacks methods and handlers to trigger the MSI-X
> interruptions on the EP Designware IP driver.
> 
> Provides new methods on pci_epf_test driver that allows to set/get EP
> maximum number of MSI-X entries (similar to set/get MSI methods).
> 
> Reworks on MSI set/get and triggering methods on EP Designware IP driver to
> be more generic and flexible.
> 
> Adds a new input parameter (msix) and replicates the whole MSI mechanism
> applied to the MSI-X feature on pcitest tool. Also updates the pcitest script
> with the new test set applied to this new feature.
> 
> Gustavo Pimentel (10):
>   PCI: dwc: Add MSI-X callbacks handler
>   PCI: cadence: Update cdns_pcie_ep_raise_irq function signature
>   PCI: endpoint: Add MSI-X interfaces
>   PCI: dwc: MSI callbacks handler rework
>   PCI: dwc: Add legacy interrupt callback handler
>   misc: pci_endpoint_test: Add MSI-X support
>   misc: pci_endpoint_test: Replace lower into upper case characters
>   PCI: endpoint: functions/pci-epf-test: Add MSI-X support
>   PCI: endpoint: functions/pci-epf-test: Replace lower into upper case
> characters
>   tools: PCI: Add MSI-X support
> 
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 120 ++
>  drivers/pci/cadence/pcie-cadence-ep.c|   2 +-
>  drivers/pci/dwc/pci-dra7xx.c |   2 +-
>  drivers/pci/dwc/pcie-artpec6.c   |   2 +-
>  drivers/pci/dwc/pcie-designware-ep.c | 201
> +--
>  drivers/pci/dwc/pcie-designware-plat.c   |   9 +-
>  drivers/pci/dwc/pcie-designware.h|  40 +++--
>  drivers/pci/endpoint/functions/pci-epf-test.c| 113 +
>  drivers/pci/endpoint/pci-ep-cfs.c|  24 +++
>  drivers/pci/endpoint/pci-epc-core.c  |  60 ++-
>  include/linux/pci-epc.h  |  11 +-
>  include/linux/pci-epf.h  |   1 +
>  include/uapi/linux/pcitest.h |   1 +
>  tools/pci/pcitest.c  |  18 +-
>  tools/pci/pcitest.sh |  25 +++
>  16 files changed, 528 insertions(+), 104 deletions(-)
> 
> --
> 2.7.4
> 
Nice set of patches.  I have tested this with the Cadence EP driver after 
adding MSI-X support, and found a few changes required.
I will send you comments.

Thanks,
Alan

RE: [RFC 00/10] Adds pcitest tool support for MSI-X

[Alan Douglas]

Hi Gustavo,

On 10 April 2018 18:15 Gustavo Pimentel wrote:
> This patch set depends the following series:
> https://lkml.org/lkml/2018/4/10/421> This series aims to add pcitest tool 
> support for MSI-X.
> 
> Includes new callbacks methods and handlers to trigger the MSI-X
> interruptions on the EP Designware IP driver.
> 
> Provides new methods on pci_epf_test driver that allows to set/get EP
> maximum number of MSI-X entries (similar to set/get MSI methods).
> 
> Reworks on MSI set/get and triggering methods on EP Designware IP driver to
> be more generic and flexible.
> 
> Adds a new input parameter (msix) and replicates the whole MSI mechanism
> applied to the MSI-X feature on pcitest tool. Also updates the pcitest script
> with the new test set applied to this new feature.
> 
> Gustavo Pimentel (10):
>   PCI: dwc: Add MSI-X callbacks handler
>   PCI: cadence: Update cdns_pcie_ep_raise_irq function signature
>   PCI: endpoint: Add MSI-X interfaces
>   PCI: dwc: MSI callbacks handler rework
>   PCI: dwc: Add legacy interrupt callback handler
>   misc: pci_endpoint_test: Add MSI-X support
>   misc: pci_endpoint_test: Replace lower into upper case characters
>   PCI: endpoint: functions/pci-epf-test: Add MSI-X support
>   PCI: endpoint: functions/pci-epf-test: Replace lower into upper case
> characters
>   tools: PCI: Add MSI-X support
> 
>  Documentation/misc-devices/pci-endpoint-test.txt |   3 +
>  drivers/misc/pci_endpoint_test.c | 120 ++
>  drivers/pci/cadence/pcie-cadence-ep.c|   2 +-
>  drivers/pci/dwc/pci-dra7xx.c |   2 +-
>  drivers/pci/dwc/pcie-artpec6.c   |   2 +-
>  drivers/pci/dwc/pcie-designware-ep.c | 201
> +--
>  drivers/pci/dwc/pcie-designware-plat.c   |   9 +-
>  drivers/pci/dwc/pcie-designware.h|  40 +++--
>  drivers/pci/endpoint/functions/pci-epf-test.c| 113 +
>  drivers/pci/endpoint/pci-ep-cfs.c|  24 +++
>  drivers/pci/endpoint/pci-epc-core.c  |  60 ++-
>  include/linux/pci-epc.h  |  11 +-
>  include/linux/pci-epf.h  |   1 +
>  include/uapi/linux/pcitest.h |   1 +
>  tools/pci/pcitest.c  |  18 +-
>  tools/pci/pcitest.sh |  25 +++
>  16 files changed, 528 insertions(+), 104 deletions(-)
> 
> --
> 2.7.4
> 
Nice set of patches.  I have tested this with the Cadence EP driver after 
adding MSI-X support, and found a few changes required.
I will send you comments.

Thanks,
Alan

RE: [RFC 02/10] PCI: cadence: Update cdns_pcie_ep_raise_irq function signature

[Alan Douglas]

On Tue, Apr 10 at 18.15, Gustavo Pimentel wrote:
> From: Gustavo Pimentel [mailto:gustavo.pimen...@synopsys.com]
> Changes the cdns_pcie_ep_raise_irq function signature, namely the
> interrupt_num variable type from u8 to u16 to accommodate the MSI-X
> maximum interrupts of 2048.
> 
> Signed-off-by: Gustavo Pimentel <gustavo.pimen...@synopsys.com>
> ---
>  drivers/pci/cadence/pcie-cadence-ep.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/cadence/pcie-cadence-ep.c
> b/drivers/pci/cadence/pcie-cadence-ep.c
> index 3d8283e..6d6322c 100644
> --- a/drivers/pci/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/cadence/pcie-cadence-ep.c
> @@ -363,7 +363,7 @@ static int cdns_pcie_ep_send_msi_irq(struct
> cdns_pcie_ep *ep, u8 fn,  }
> 
>  static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
> -   enum pci_epc_irq_type type, u8
> interrupt_num)
> +   enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
> 
> --
> 2.7.4
> 
Acked-by: Alan Douglas <adoug...@cadence.com>

RE: [RFC 02/10] PCI: cadence: Update cdns_pcie_ep_raise_irq function signature

[Alan Douglas]

On Tue, Apr 10 at 18.15, Gustavo Pimentel wrote:
> From: Gustavo Pimentel [mailto:gustavo.pimen...@synopsys.com]
> Changes the cdns_pcie_ep_raise_irq function signature, namely the
> interrupt_num variable type from u8 to u16 to accommodate the MSI-X
> maximum interrupts of 2048.
> 
> Signed-off-by: Gustavo Pimentel 
> ---
>  drivers/pci/cadence/pcie-cadence-ep.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/cadence/pcie-cadence-ep.c
> b/drivers/pci/cadence/pcie-cadence-ep.c
> index 3d8283e..6d6322c 100644
> --- a/drivers/pci/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/cadence/pcie-cadence-ep.c
> @@ -363,7 +363,7 @@ static int cdns_pcie_ep_send_msi_irq(struct
> cdns_pcie_ep *ep, u8 fn,  }
> 
>  static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
> -   enum pci_epc_irq_type type, u8
> interrupt_num)
> +   enum pci_epc_irq_type type, u16
> interrupt_num)
>  {
>   struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
> 
> --
> 2.7.4
> 
Acked-by: Alan Douglas 

RE: [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up

[Alan Douglas]

On Wed, Mar 28, 2018 at 20:37, Bjorn Helgaas wrote:
> On Wed, Mar 28, 2018 at 01:24:10PM +0000, Alan Douglas wrote:
> > > On 28/03/2018 12:51, Niklas Cassel wrote:
> > > cdns_pcie_ep_set_bar() does some round-up of the BAR size, which
> > > means that a 64-bit BAR can be set-up, even when the flag
> > > PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
> >
> > > If a 64-bit BAR was set-up, set the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64, so that the calling function can know
> what BAR width that was actually set-up.
> >
> > > I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to
> fix, since there might be a reason why > this flag is ignored.
> > Will investigate and fix this in future patch
> >
> > > Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
> > > ---
> > >  drivers/pci/cadence/pcie-cadence-ep.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > >
> > Change looks good to me.
> 
> It will be helpful to Lorenzo if you spell this out, e.g.,
> 
>   Acked-by: Alan Douglas <adoug...@cadence.com>
Acked-by: Alan Douglas <adoug...@cadence.com>
> 
> Also, it looks like we need a MAINTAINERS update to add drivers/pci/cadence/
> to the "PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
> filename patterns.
Lorenzo please let me know if I should create a patch for this, it sounds good 
to me.

RE: [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up

[Alan Douglas]

On Wed, Mar 28, 2018 at 20:37, Bjorn Helgaas wrote:
> On Wed, Mar 28, 2018 at 01:24:10PM +0000, Alan Douglas wrote:
> > > On 28/03/2018 12:51, Niklas Cassel wrote:
> > > cdns_pcie_ep_set_bar() does some round-up of the BAR size, which
> > > means that a 64-bit BAR can be set-up, even when the flag
> > > PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
> >
> > > If a 64-bit BAR was set-up, set the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64, so that the calling function can know
> what BAR width that was actually set-up.
> >
> > > I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to
> fix, since there might be a reason why > this flag is ignored.
> > Will investigate and fix this in future patch
> >
> > > Signed-off-by: Niklas Cassel 
> > > ---
> > >  drivers/pci/cadence/pcie-cadence-ep.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > >
> > Change looks good to me.
> 
> It will be helpful to Lorenzo if you spell this out, e.g.,
> 
>   Acked-by: Alan Douglas 
Acked-by: Alan Douglas 
> 
> Also, it looks like we need a MAINTAINERS update to add drivers/pci/cadence/
> to the "PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
> filename patterns.
Lorenzo please let me know if I should create a patch for this, it sounds good 
to me.

RE: [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up

[Alan Douglas]

> On 28/03/2018 12:51, Niklas Cassel wrote:
> cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means that a 
> 64-bit BAR can be set-up, even when the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.

> If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64, so 
> that the calling function can know what BAR width that was actually set-up.

> I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag 
> PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to fix, 
> since there might be a reason why > this flag is ignored.
Will investigate and fix this in future patch

> Signed-off-by: Niklas Cassel 
> ---
>  drivers/pci/cadence/pcie-cadence-ep.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/pci/cadence/pcie-cadence-ep.c 
> b/drivers/pci/cadence/pcie-cadence-ep.c
> index cef36cd6b710..2905e098678c 100644
> --- a/drivers/pci/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/cadence/pcie-cadence-ep.c
> @@ -106,6 +106,9 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 
> fn,
>   if (is_64bits && (bar & 1))
>   return -EINVAL;
>  
> + if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
> + epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
> +
>   if (is_64bits && is_prefetch)
>   ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
>   else if (is_prefetch)
> --
> 2.14.2
Change looks good to me.

RE: [PATCH v5 07/12] PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up

[Alan Douglas]

> On 28/03/2018 12:51, Niklas Cassel wrote:
> cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means that a 
> 64-bit BAR can be set-up, even when the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.

> If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64, so 
> that the calling function can know what BAR width that was actually set-up.

> I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag 
> PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to fix, 
> since there might be a reason why > this flag is ignored.
Will investigate and fix this in future patch

> Signed-off-by: Niklas Cassel 
> ---
>  drivers/pci/cadence/pcie-cadence-ep.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/pci/cadence/pcie-cadence-ep.c 
> b/drivers/pci/cadence/pcie-cadence-ep.c
> index cef36cd6b710..2905e098678c 100644
> --- a/drivers/pci/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/cadence/pcie-cadence-ep.c
> @@ -106,6 +106,9 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 
> fn,
>   if (is_64bits && (bar & 1))
>   return -EINVAL;
>  
> + if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
> + epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
> +
>   if (is_64bits && is_prefetch)
>   ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
>   else if (is_prefetch)
> --
> 2.14.2
Change looks good to me.