[PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.

This patch adds support for core power down idle state.

Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in a set of 10 cpuidle transactions,
   with varying load.

Exit latency and min residency values are supplied as per HW team.

Signed-off-by: Chander Kashyap 
Acked-by: Lorenzo Pieralisi 
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
www.spinics.net/lists/arm-kernel/msg375961.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
Changes in v5:
- Commit message modified

 arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..891eef4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x2>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x3>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x001>;
+   entry-latency-us = <34>;
+   exit-latency-us = <150>;
+   min-residency-us = <2100>;
+   };
};
};
 
-- 
1.9.1

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Re: [PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
On Fri, Nov 7, 2014 at 5:28 PM, Lorenzo Pieralisi
 wrote:
> On Wed, Nov 05, 2014 at 01:15:31PM +0000, Chander Kashyap wrote:
>> Exynos7 has core power down state where cores can be powered off 
>> independently.
>
> "...has a core power down idle state..."
>
>> This patch adds support for this state.
>
> "...for this idle state."
>
>> Entry latency for the core power down is calculated as follows:
>> 1. Time difference is measured between cpuidle entry and exit.
>> 2. WFI is skipped for measuring the time.
>> 3. Select the worst case time in the set of 10 cpuidle transactions,
>>with varying load.
>>
>> Exit latency and target residency are supplied as per HW team
>
> "Exit latency and min residency values are supplied by the HW team."
>
> Target residency is a kernel naming scheme, non-existent in the idle state
> bindings.
>
> Please take time to write proper commit logs, thanks.
>
>> Signed-off-by: Chander Kashyap 
>> ---
>> This patch has following dependencies:
>>   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
>>   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
>> Changes in v2:
>>   - Moved the cpu-idle-state property after reg property
>>   - removed the status property.
>>
>> Changes in v3:
>>   - Added the Entry latency calculation in commit message.
>> Changes in v4:
>>   - Corrected the commit message.
>>   - Corrected the entry latency value.
>>
>>  arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
>> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> index 50ae936..444dde1 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> @@ -37,6 +37,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>
> enable-method should be after reg, it is not an ordering issues added
> by this patch but I still do not like that.

This is being taken care in new patch for Exynos7 support.

>
> Other than that, please take some time to rewrite the commit log and
> ask to fix the ordering above, you can add my:
>

Yes i will change as suggested.

Thanks for the review.

> Acked-by: Lorenzo Pieralisi 
>
>>   reg = <0x0>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@1 {
>> @@ -44,6 +45,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x1>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@2 {
>> @@ -51,6 +53,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x2>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@3 {
>> @@ -58,6 +61,20 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x3>;
>> + cpu-idle-states = <_SLEEP>;
>> + };
>> +
>> + idle-states {
>> + entry-method = "arm,psci";
>> +
>> + CPU_SLEEP: cpu-sleep {
>> + compatible = "arm,idle-state";
>> + local-timer-stop;
>> + arm,psci-suspend-param = <0x001>;
>> + entry-latency-us = <34>;
>> + exit-latency-us = <150>;
>> + min-residency-us = <2100>;
>> + };
>>   };
>>   };
>>
>> --
>> 1.7.9.5
>>
>>
>
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Re: [PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
On Fri, Nov 7, 2014 at 5:28 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Nov 05, 2014 at 01:15:31PM +, Chander Kashyap wrote:
 Exynos7 has core power down state where cores can be powered off 
 independently.

 ...has a core power down idle state...

 This patch adds support for this state.

 ...for this idle state.

 Entry latency for the core power down is calculated as follows:
 1. Time difference is measured between cpuidle entry and exit.
 2. WFI is skipped for measuring the time.
 3. Select the worst case time in the set of 10 cpuidle transactions,
with varying load.

 Exit latency and target residency are supplied as per HW team

 Exit latency and min residency values are supplied by the HW team.

 Target residency is a kernel naming scheme, non-existent in the idle state
 bindings.

 Please take time to write proper commit logs, thanks.

 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 This patch has following dependencies:
   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
 Changes in v2:
   - Moved the cpu-idle-state property after reg property
   - removed the status property.

 Changes in v3:
   - Added the Entry latency calculation in commit message.
 Changes in v4:
   - Corrected the commit message.
   - Corrected the entry latency value.

  arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
  1 file changed, 17 insertions(+)

 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
 b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 index 50ae936..444dde1 100644
 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
 +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 @@ -37,6 +37,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;

 enable-method should be after reg, it is not an ordering issues added
 by this patch but I still do not like that.

This is being taken care in new patch for Exynos7 support.


 Other than that, please take some time to rewrite the commit log and
 ask to fix the ordering above, you can add my:


Yes i will change as suggested.

Thanks for the review.

 Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com

   reg = 0x0;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@1 {
 @@ -44,6 +45,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x1;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@2 {
 @@ -51,6 +53,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x2;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@3 {
 @@ -58,6 +61,20 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x3;
 + cpu-idle-states = CPU_SLEEP;
 + };
 +
 + idle-states {
 + entry-method = arm,psci;
 +
 + CPU_SLEEP: cpu-sleep {
 + compatible = arm,idle-state;
 + local-timer-stop;
 + arm,psci-suspend-param = 0x001;
 + entry-latency-us = 34;
 + exit-latency-us = 150;
 + min-residency-us = 2100;
 + };
   };
   };

 --
 1.7.9.5



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[PATCH v5] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-10 Thread Chander Kashyap
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.

This patch adds support for core power down idle state.

Entry latency for core power down idle state is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in a set of 10 cpuidle transactions,
   with varying load.

Exit latency and min residency values are supplied as per HW team.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
www.spinics.net/lists/arm-kernel/msg375961.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.
Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.
Changes in v5:
- Commit message modified

 arch/arm64/boot/dts/exynos/exynos7.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index d7a37c3..891eef4 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x0;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x1;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x2;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
reg = 0x3;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 34;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.9.1

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[PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in the set of 10 cpuidle transactions,
   with varying load.

Exit latency and target residency are supplied as per HW team

Signed-off-by: Chander Kashyap 
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x0>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x1>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x2>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x3>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x001>;
+   entry-latency-us = <34>;
+   exit-latency-us = <150>;
+   min-residency-us = <2100>;
+   };
};
};
 
-- 
1.7.9.5

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Re: [PATCH v3] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
On Wed, Nov 5, 2014 at 4:42 PM, Lorenzo Pieralisi
 wrote:
> On Wed, Nov 05, 2014 at 10:15:36AM +0000, Chander Kashyap wrote:
>> Exynos7 has core power down state where cores can be powered off 
>> independently.
>> This patch adds support for this state.
>>
>> Entry latency for the core power down is calculated as follows:
>> 1. Time difference is measured between cpuidle entry and exit.
>> 2. WFI is skipped measuring the time.
>> 3. The time is averaged out for 10 cpuidle transactions with varying 
>> load.
> - entry-latency-us
> Usage: Required
> "Definition: u32 value representing worst case latency in microseconds
>  required to enter the idle state. ..."
>
> Is that an average value in your opinion ? I am being pedantic, I know,
> but we define bindings to be followed, not interpreted.

Sorry i missed the point.
The worst case value in a test set of 10 cpuidle transactions is ~34us
I will update this and resend the patch.
>
> Thanks,
> Lorenzo
>
>> Exit latency and target residency are supplied as per HW team
>>
>> Signed-off-by: Chander Kashyap 
>> ---
>> This patch has following dependencies:
>>   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
>>   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
>> Changes in v2:
>>   - Moved the cpu-idle-state property after reg property
>>   - removed the status property.
>>
>> Changes in v3:
>>   - Added the Entry latency calculation in commit message.
>>
>>  arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
>> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> index 50ae936..444dde1 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> @@ -37,6 +37,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x0>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@1 {
>> @@ -44,6 +45,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x1>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@2 {
>> @@ -51,6 +53,7 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x2>;
>> + cpu-idle-states = <_SLEEP>;
>>   };
>>
>>   cpu@3 {
>> @@ -58,6 +61,20 @@
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>>   reg = <0x3>;
>> + cpu-idle-states = <_SLEEP>;
>> + };
>> +
>> + idle-states {
>> + entry-method = "arm,psci";
>> +
>> + CPU_SLEEP: cpu-sleep {
>> + compatible = "arm,idle-state";
>> + local-timer-stop;
>> + arm,psci-suspend-param = <0x001>;
>> + entry-latency-us = <20>;
>> + exit-latency-us = <150>;
>> + min-residency-us = <2100>;
>> + };
>>   };
>>   };
>>
>> --
>> 1.7.9.5
>>
>>
>
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[PATCH v3] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped measuring the time.
3. The time is averaged out for 10 cpuidle transactions with varying load.

Exit latency and target residency are supplied as per HW team

Signed-off-by: Chander Kashyap 
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

Changes in v3:
- Added the Entry latency calculation in commit message.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x0>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x1>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x2>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x3>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x001>;
+   entry-latency-us = <20>;
+   exit-latency-us = <150>;
+   min-residency-us = <2100>;
+   };
};
};
 
-- 
1.7.9.5

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Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Sorry for very late response. As i was on vacation so couldn’t reply.

On Tue, Oct 21, 2014 at 10:03 PM, Lorenzo Pieralisi
 wrote:
> On Fri, Oct 17, 2014 at 10:43:59AM +0100, Chander Kashyap wrote:
>> Hi Lorenzo,
>>
>> On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
>>  wrote:
>> > On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
>> >> Exynos7 has core power down state where cores can be powered off 
>> >> independently.
>> >> This patch adds support for this state.
>> >
>> > Please tell us more about the idle-state values you are adding, in 
>> > particular
>> > entry, exit latencies and min-residency values.
>>
>> Entry latency: This value is calculated as follows:
>>
>> On entry to arm64_enter_idle_state:
>> timestamp1 = ktimeget();
>>
>> after returning from cpu_suspend()
>>
>> timestamp2 = ktimeget();
>>
>> latency = timestamp2-timestamp1;
>>
>> Cpu is not allowed to enter core powerdown by skipping wfi instruction at 
>> end.
> This may not be the worst case (because the worst case depends on the state
> of the cache in the core unless the latency is power down command dominated,
> so at the cost of being pedantic, please make sure that's what you are
> measuring and document it in the commit log).
>

If i understood correctly you are referring to cache flush time.
The measured entry latency time is averaged time for 10
transactions with varying load.
I will document entry latency calculation in the commit message.

>> Hence calculated time contains entry time + failure exit time.
>>
>>
>> Regarding
>> exit-latency and target-residency time, got these values from HW team.
>>
>> I am using these as initial values and I will be working on optimizing
>> these values with further experiments.
>> If you could suggest any formal method of deriving these values, i can
>> try those methods as well.
>
> Well, you have to set the core/cluster in worst case scenario and
> compute the break-even residency against wfi (since you have two
> states); it certainly has a dependency on PSCI implementation too among
> other things.
>
> exit-latency should come from HW design even though there is a cache
> refill factor to be considered too and should be factored in.

Exit and target residency are provided by HW team.

I will post the V3 with changed commit message.
>
> Lorenzo
>
>>
>> >
>> >> Signed-off-by: Chander Kashyap 
>> >> ---
>> >> This patch has following dependencies:
>> >>   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
>> >>   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
>> >>   - [PATCH v9 0/8] ARM generic idle states
>> >>   
>> >> http://permalink.gmane.org/gmane.linux.power-management.general/49224
>> >
>> > Series above was merged, so dependency is stale.
>>
>> i will remove this
>>
>> >
>> >>  arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
>> >>  1 file changed, 18 insertions(+)dont
>> >>
>> >> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
>> >> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> >> index ce221ac..8e0a034 100644
>> >> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> >> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> >> @@ -36,6 +36,7 @@
>> >>   device_type = "cpu";
>> >>   compatible = "arm,cortex-a57", "arm,armv8";
>> >>   enable-method = "psci";
>> >> + cpu-idle-states = <_SLEEP>;
>> >
>> > I would add cpu-idle-states phandle after the reg property, as defined
>> > in the idle states bindings.
>>
>> i will move this after reg property.
>>
>> >
>> >>   reg = <0x0>;
>> >>   };
>> >>
>> >> @@ -43,6 +44,7 @@
>> >>   device_type = "cpu";
>> >>   compatible = "arm,cortex-a57", "arm,armv8";
>> >>   enable-method = "psci";
>> >> + cpu-idle-states = <_SLEEP>;
>> >>   reg = <0x1>;
>> >>   };
>> >>
>> >> @@ -50,6 +52,7 @@
>> >> 

Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Sorry for very late response. As i was on vacation so couldn’t reply.

On Tue, Oct 21, 2014 at 10:03 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Fri, Oct 17, 2014 at 10:43:59AM +0100, Chander Kashyap wrote:
 Hi Lorenzo,

 On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
 lorenzo.pieral...@arm.com wrote:
  On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
  Exynos7 has core power down state where cores can be powered off 
  independently.
  This patch adds support for this state.
 
  Please tell us more about the idle-state values you are adding, in 
  particular
  entry, exit latencies and min-residency values.

 Entry latency: This value is calculated as follows:

 On entry to arm64_enter_idle_state:
 timestamp1 = ktimeget();

 after returning from cpu_suspend()

 timestamp2 = ktimeget();

 latency = timestamp2-timestamp1;

 Cpu is not allowed to enter core powerdown by skipping wfi instruction at 
 end.
 This may not be the worst case (because the worst case depends on the state
 of the cache in the core unless the latency is power down command dominated,
 so at the cost of being pedantic, please make sure that's what you are
 measuring and document it in the commit log).


If i understood correctly you are referring to cache flush time.
The measured entry latency time is averaged time for 10
transactions with varying load.
I will document entry latency calculation in the commit message.

 Hence calculated time contains entry time + failure exit time.


 Regarding
 exit-latency and target-residency time, got these values from HW team.

 I am using these as initial values and I will be working on optimizing
 these values with further experiments.
 If you could suggest any formal method of deriving these values, i can
 try those methods as well.

 Well, you have to set the core/cluster in worst case scenario and
 compute the break-even residency against wfi (since you have two
 states); it certainly has a dependency on PSCI implementation too among
 other things.

 exit-latency should come from HW design even though there is a cache
 refill factor to be considered too and should be factored in.

Exit and target residency are provided by HW team.

I will post the V3 with changed commit message.

 Lorenzo


 
  Signed-off-by: Chander Kashyap k.chan...@samsung.com
  ---
  This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states

  http://permalink.gmane.org/gmane.linux.power-management.general/49224
 
  Series above was merged, so dependency is stale.

 i will remove this

 
   arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
   1 file changed, 18 insertions(+)dont
 
  diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
  b/arch/arm64/boot/dts/exynos/exynos7.dtsi
  index ce221ac..8e0a034 100644
  --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
  +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
  @@ -36,6 +36,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
 
  I would add cpu-idle-states phandle after the reg property, as defined
  in the idle states bindings.

 i will move this after reg property.

 
reg = 0x0;
};
 
  @@ -43,6 +44,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x1;
};
 
  @@ -50,6 +52,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x2;
};
 
  @@ -57,8 +60,23 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
  + cpu-idle-states = CPU_SLEEP;
reg = 0x3;
};
  +
  + idle-states {
  + entry-method = arm,psci;
  +
  + CPU_SLEEP: cpu-sleep {
  + compatible = arm,idle-state;
  + local-timer-stop;
  + arm,psci-suspend-param = 0x001;
  + entry-latency-us = 20;
  + exit-latency-us = 150;
  + min-residency-us = 2100;
  + status = enabled;
 
  status ? This is not a documented property. If you need it please explain
  why, define its

[PATCH v3] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped measuring the time.
3. The time is averaged out for 10 cpuidle transactions with varying load.

Exit latency and target residency are supplied as per HW team

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

Changes in v3:
- Added the Entry latency calculation in commit message.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 20;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.7.9.5

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Re: [PATCH v3] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
On Wed, Nov 5, 2014 at 4:42 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
 Exynos7 has core power down state where cores can be powered off 
 independently.
 This patch adds support for this state.

 Entry latency for the core power down is calculated as follows:
 1. Time difference is measured between cpuidle entry and exit.
 2. WFI is skipped measuring the time.
 3. The time is averaged out for 10 cpuidle transactions with varying 
 load.
 - entry-latency-us
 Usage: Required
 Definition: u32 value representing worst case latency in microseconds
  required to enter the idle state. ...

 Is that an average value in your opinion ? I am being pedantic, I know,
 but we define bindings to be followed, not interpreted.

Sorry i missed the point.
The worst case value in a test set of 10 cpuidle transactions is ~34us
I will update this and resend the patch.

 Thanks,
 Lorenzo

 Exit latency and target residency are supplied as per HW team

 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 This patch has following dependencies:
   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
 Changes in v2:
   - Moved the cpu-idle-state property after reg property
   - removed the status property.

 Changes in v3:
   - Added the Entry latency calculation in commit message.

  arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
  1 file changed, 17 insertions(+)

 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
 b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 index 50ae936..444dde1 100644
 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
 +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 @@ -37,6 +37,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x0;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@1 {
 @@ -44,6 +45,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x1;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@2 {
 @@ -51,6 +53,7 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x2;
 + cpu-idle-states = CPU_SLEEP;
   };

   cpu@3 {
 @@ -58,6 +61,20 @@
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
   reg = 0x3;
 + cpu-idle-states = CPU_SLEEP;
 + };
 +
 + idle-states {
 + entry-method = arm,psci;
 +
 + CPU_SLEEP: cpu-sleep {
 + compatible = arm,idle-state;
 + local-timer-stop;
 + arm,psci-suspend-param = 0x001;
 + entry-latency-us = 20;
 + exit-latency-us = 150;
 + min-residency-us = 2100;
 + };
   };
   };

 --
 1.7.9.5



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[PATCH v4] arm64: dts: exynos7: add support for cpuidle core power down

2014-11-05 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Entry latency for the core power down is calculated as follows:
1. Time difference is measured between cpuidle entry and exit.
2. WFI is skipped for measuring the time.
3. Select the worst case time in the set of 10 cpuidle transactions,
   with varying load.

Exit latency and target residency are supplied as per HW team

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

Changes in v3:
- Added the Entry latency calculation in commit message.
Changes in v4:
- Corrected the commit message.
- Corrected the entry latency value.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 34;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.7.9.5

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[PATCH v2] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-20 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap 
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x0>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x1>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x2>;
+   cpu-idle-states = <_SLEEP>;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
reg = <0x3>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x001>;
+   entry-latency-us = <20>;
+   exit-latency-us = <150>;
+   min-residency-us = <2100>;
+   };
};
};
 
-- 
1.7.9.5

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Please read the FAQ at  http://www.tux.org/lkml/


[PATCH v2] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-20 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
Changes in v2:
- Moved the cpu-idle-state property after reg property
- removed the status property.

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 50ae936..444dde1 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -37,6 +37,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x0;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@1 {
@@ -44,6 +45,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x1;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@2 {
@@ -51,6 +53,7 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x2;
+   cpu-idle-states = CPU_SLEEP;
};
 
cpu@3 {
@@ -58,6 +61,20 @@
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
reg = 0x3;
+   cpu-idle-states = CPU_SLEEP;
+   };
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 20;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   };
};
};
 
-- 
1.7.9.5

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Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-17 Thread Chander Kashyap
Hi Lorenzo,

On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
 wrote:
> On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
>> Exynos7 has core power down state where cores can be powered off 
>> independently.
>> This patch adds support for this state.
>
> Please tell us more about the idle-state values you are adding, in particular
> entry, exit latencies and min-residency values.

Entry latency: This value is calculated as follows:

On entry to arm64_enter_idle_state:
timestamp1 = ktimeget();

after returning from cpu_suspend()

timestamp2 = ktimeget();

latency = timestamp2-timestamp1;

Cpu is not allowed to enter core powerdown by skipping wfi instruction at end.
Hence calculated time contains entry time + failure exit time.


Regarding
exit-latency and target-residency time, got these values from HW team.

I am using these as initial values and I will be working on optimizing
these values with further experiments.
If you could suggest any formal method of deriving these values, i can
try those methods as well.

>
>> Signed-off-by: Chander Kashyap 
>> ---
>> This patch has following dependencies:
>>   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
>>   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
>>   - [PATCH v9 0/8] ARM generic idle states
>>   
>> http://permalink.gmane.org/gmane.linux.power-management.general/49224
>
> Series above was merged, so dependency is stale.

i will remove this

>
>>  arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
>>  1 file changed, 18 insertions(+)dont
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
>> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> index ce221ac..8e0a034 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
>> @@ -36,6 +36,7 @@
>>   device_type = "cpu";
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>> + cpu-idle-states = <_SLEEP>;
>
> I would add cpu-idle-states phandle after the reg property, as defined
> in the idle states bindings.

i will move this after reg property.

>
>>   reg = <0x0>;
>>   };
>>
>> @@ -43,6 +44,7 @@
>>   device_type = "cpu";
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>> + cpu-idle-states = <_SLEEP>;
>>   reg = <0x1>;
>>   };
>>
>> @@ -50,6 +52,7 @@
>>   device_type = "cpu";
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>> + cpu-idle-states = <_SLEEP>;
>>   reg = <0x2>;
>>   };
>>
>> @@ -57,8 +60,23 @@
>>   device_type = "cpu";
>>   compatible = "arm,cortex-a57", "arm,armv8";
>>   enable-method = "psci";
>> + cpu-idle-states = <_SLEEP>;
>>   reg = <0x3>;
>>   };
>> +
>> + idle-states {
>> + entry-method = "arm,psci";
>> +
>> + CPU_SLEEP: cpu-sleep {
>> + compatible = "arm,idle-state";
>> + local-timer-stop;
>> + arm,psci-suspend-param = <0x001>;
>> + entry-latency-us = <20>;
>> + exit-latency-us = <150>;
>> + min-residency-us = <2100>;
>> + status = "enabled";
>
> status ? This is not a documented property. If you need it please explain
> why, define its bindings and we can see how to accommodate it.

I will add okay for status property. As per the bindings posted by you.

regards,
>
> Thank you,
> Lorenzo
>
>> + };
>> + };
>>   };
>>
>>   psci {
>> --
>> 1.7.9.5
>>
>>
>
>
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Re: [PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-17 Thread Chander Kashyap
Hi Lorenzo,

On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
 Exynos7 has core power down state where cores can be powered off 
 independently.
 This patch adds support for this state.

 Please tell us more about the idle-state values you are adding, in particular
 entry, exit latencies and min-residency values.

Entry latency: This value is calculated as follows:

On entry to arm64_enter_idle_state:
timestamp1 = ktimeget();

after returning from cpu_suspend()

timestamp2 = ktimeget();

latency = timestamp2-timestamp1;

Cpu is not allowed to enter core powerdown by skipping wfi instruction at end.
Hence calculated time contains entry time + failure exit time.


Regarding
exit-latency and target-residency time, got these values from HW team.

I am using these as initial values and I will be working on optimizing
these values with further experiments.
If you could suggest any formal method of deriving these values, i can
try those methods as well.


 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 ---
 This patch has following dependencies:
   - [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
   http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
   - [PATCH v9 0/8] ARM generic idle states
   
 http://permalink.gmane.org/gmane.linux.power-management.general/49224

 Series above was merged, so dependency is stale.

i will remove this


  arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
  1 file changed, 18 insertions(+)dont

 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
 b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 index ce221ac..8e0a034 100644
 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
 +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
 @@ -36,6 +36,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;

 I would add cpu-idle-states phandle after the reg property, as defined
 in the idle states bindings.

i will move this after reg property.


   reg = 0x0;
   };

 @@ -43,6 +44,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x1;
   };

 @@ -50,6 +52,7 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x2;
   };

 @@ -57,8 +60,23 @@
   device_type = cpu;
   compatible = arm,cortex-a57, arm,armv8;
   enable-method = psci;
 + cpu-idle-states = CPU_SLEEP;
   reg = 0x3;
   };
 +
 + idle-states {
 + entry-method = arm,psci;
 +
 + CPU_SLEEP: cpu-sleep {
 + compatible = arm,idle-state;
 + local-timer-stop;
 + arm,psci-suspend-param = 0x001;
 + entry-latency-us = 20;
 + exit-latency-us = 150;
 + min-residency-us = 2100;
 + status = enabled;

 status ? This is not a documented property. If you need it please explain
 why, define its bindings and we can see how to accommodate it.

I will add okay for status property. As per the bindings posted by you.

regards,

 Thank you,
 Lorenzo

 + };
 + };
   };

   psci {
 --
 1.7.9.5




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[PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-15 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap 
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states

http://permalink.gmane.org/gmane.linux.power-management.general/49224

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..8e0a034 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -36,6 +36,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
reg = <0x0>;
};
 
@@ -43,6 +44,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
reg = <0x1>;
};
 
@@ -50,6 +52,7 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
reg = <0x2>;
};
 
@@ -57,8 +60,23 @@
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
enable-method = "psci";
+   cpu-idle-states = <_SLEEP>;
reg = <0x3>;
};
+
+   idle-states {
+   entry-method = "arm,psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x001>;
+   entry-latency-us = <20>;
+   exit-latency-us = <150>;
+   min-residency-us = <2100>;
+   status = "enabled";
+   };
+   };
};
 
psci {
-- 
1.7.9.5

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[PATCH] arm64: dts: exynos7: add support for cpuidle core power down

2014-10-15 Thread Chander Kashyap
Exynos7 has core power down state where cores can be powered off independently.
This patch adds support for this state.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
This patch has following dependencies:
- [PATCH v5 0/8] arch: arm64: Enable support for Samsung Exynos7 SoC
http://www.spinics.net/lists/linux-samsung-soc/msg37047.html
- [PATCH v9 0/8] ARM generic idle states

http://permalink.gmane.org/gmane.linux.power-management.general/49224

 arch/arm64/boot/dts/exynos/exynos7.dtsi |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi 
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index ce221ac..8e0a034 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -36,6 +36,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x0;
};
 
@@ -43,6 +44,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x1;
};
 
@@ -50,6 +52,7 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x2;
};
 
@@ -57,8 +60,23 @@
device_type = cpu;
compatible = arm,cortex-a57, arm,armv8;
enable-method = psci;
+   cpu-idle-states = CPU_SLEEP;
reg = 0x3;
};
+
+   idle-states {
+   entry-method = arm,psci;
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = arm,idle-state;
+   local-timer-stop;
+   arm,psci-suspend-param = 0x001;
+   entry-latency-us = 20;
+   exit-latency-us = 150;
+   min-residency-us = 2100;
+   status = enabled;
+   };
+   };
};
 
psci {
-- 
1.7.9.5

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Re: [PATCH v2 5/6] ARM: EXYNOS: Fix suspend/resume sequences

2014-07-15 Thread Chander Kashyap
On Tue, Jul 15, 2014 at 5:45 PM, Tomasz Figa  wrote:
> On 15.07.2014 13:19, Bartlomiej Zolnierkiewicz wrote:
>>
>> Hi,
>>
>> On Monday, July 14, 2014 11:54:48 AM Tomasz Figa wrote:
>>> Hi Kukjin,
>>>
>>> On 25.06.2014 13:52, Tomasz Figa wrote:
 Due to recent consolidation of Exynos suspend and cpuidle code, some
 parts of suspend and resume sequences are executed two times, once from
 exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
 breaks suspend, at least on Exynos4-based boards.

 This patch fixes the issue by removing exynos_pm_syscore_ops completely
 and making the code rely only on CPU PM notifier.

 Tested on Exynos4210-based Trats board.

 Signed-off-by: Tomasz Figa 
 ---
  arch/arm/mach-exynos/pm.c | 23 ---
  1 file changed, 4 insertions(+), 19 deletions(-)

 Changes since v1:
  - rebased onto Kukjin's fixes branch.

 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index 202ca73..f23cc77 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -364,11 +364,6 @@ early_wakeup:
 return;
  }

 -static struct syscore_ops exynos_pm_syscore_ops = {
 -   .suspend= exynos_pm_suspend,
 -   .resume = exynos_pm_resume,
 -};
 -
  /*
   * Suspend Ops
   */
 @@ -438,22 +433,13 @@ static int exynos_cpu_pm_notifier(struct 
 notifier_block *self,

 switch (cmd) {
 case CPU_PM_ENTER:
 -   if (cpu == 0) {
 -   exynos_pm_central_suspend();
 -   if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_save_register();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_suspend();
 break;

 case CPU_PM_EXIT:
 -   if (cpu == 0) {
 -   if (read_cpuid_part_number() ==
 -   ARM_CPU_PART_CORTEX_A9) {
 -   scu_enable(S5P_VA_SCU);
 -   exynos_cpu_restore_register();
 -   }
 -   exynos_pm_central_resume();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_resume();
 break;
 }

 @@ -478,6 +464,5 @@ void __init exynos_pm_init(void)
 tmp |= ((0xFF << 8) | (0x1F << 1));
 __raw_writel(tmp, S5P_WAKEUP_MASK);

 -   register_syscore_ops(_pm_syscore_ops);
 suspend_set_ops(_suspend_ops);
  }

>>>
>>> Please consider this patch for next fixes pull request. Without it
>>> suspend/resume is broken for Exynos4 and probably other SoCs. This patch
>>> just restores the sequence from before the patch moving things to PM
>>> notifier, so I don't think it should need any special treatment.
>>
>> Your patch fixes the regression and is a step in the good direction but it
>> seems that it needs a bit more work:
>>
>> Your patch adds to cpuidle AFTR code path restoring of exynos_core_save and
>> exynos5_sys_save registers without saving them first (restoring is done
>> through exynos_pm_resume() which is used by both suspend and cpuidle while
>> saving is done through exynos_pm_prepare() which is used only by suspend).
>
> That's right, unfortunately. Interestingly enough AFTR worked fine on
> Exynos4210 with this patch, but still this needs to be fixed.
>
> Now, in fact, I recall that Chander had some objections to this patch as
> well and we decided that he will send another patch to replace mine [1],
> but I haven't heard from him since that.

Patch for the same has been already posted.
Below is the link for the same
http://www.spinics.net/lists/arm-kernel/msg343402.html

This patch has conflict with Russel's patch, so i will rebase on his
tree and resend

This patch can be ignored in that case.

>
> Chander, do you have any progress with this? Keep in mind that we need
> this as an rc fix and we already have rc5, so not much time left. If you
> don't have time to work on this I can take care of this, proceeding as
> we discussed in [1].
>
> [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29085/focus=33975
>
> Best regards,
> Tomasz
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> in
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Re: [PATCH v2 5/6] ARM: EXYNOS: Fix suspend/resume sequences

2014-07-15 Thread Chander Kashyap
On Tue, Jul 15, 2014 at 5:45 PM, Tomasz Figa t.f...@samsung.com wrote:
 On 15.07.2014 13:19, Bartlomiej Zolnierkiewicz wrote:

 Hi,

 On Monday, July 14, 2014 11:54:48 AM Tomasz Figa wrote:
 Hi Kukjin,

 On 25.06.2014 13:52, Tomasz Figa wrote:
 Due to recent consolidation of Exynos suspend and cpuidle code, some
 parts of suspend and resume sequences are executed two times, once from
 exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
 breaks suspend, at least on Exynos4-based boards.

 This patch fixes the issue by removing exynos_pm_syscore_ops completely
 and making the code rely only on CPU PM notifier.

 Tested on Exynos4210-based Trats board.

 Signed-off-by: Tomasz Figa t.f...@samsung.com
 ---
  arch/arm/mach-exynos/pm.c | 23 ---
  1 file changed, 4 insertions(+), 19 deletions(-)

 Changes since v1:
  - rebased onto Kukjin's fixes branch.

 diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
 index 202ca73..f23cc77 100644
 --- a/arch/arm/mach-exynos/pm.c
 +++ b/arch/arm/mach-exynos/pm.c
 @@ -364,11 +364,6 @@ early_wakeup:
 return;
  }

 -static struct syscore_ops exynos_pm_syscore_ops = {
 -   .suspend= exynos_pm_suspend,
 -   .resume = exynos_pm_resume,
 -};
 -
  /*
   * Suspend Ops
   */
 @@ -438,22 +433,13 @@ static int exynos_cpu_pm_notifier(struct 
 notifier_block *self,

 switch (cmd) {
 case CPU_PM_ENTER:
 -   if (cpu == 0) {
 -   exynos_pm_central_suspend();
 -   if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 -   exynos_cpu_save_register();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_suspend();
 break;

 case CPU_PM_EXIT:
 -   if (cpu == 0) {
 -   if (read_cpuid_part_number() ==
 -   ARM_CPU_PART_CORTEX_A9) {
 -   scu_enable(S5P_VA_SCU);
 -   exynos_cpu_restore_register();
 -   }
 -   exynos_pm_central_resume();
 -   }
 +   if (cpu == 0)
 +   exynos_pm_resume();
 break;
 }

 @@ -478,6 +464,5 @@ void __init exynos_pm_init(void)
 tmp |= ((0xFF  8) | (0x1F  1));
 __raw_writel(tmp, S5P_WAKEUP_MASK);

 -   register_syscore_ops(exynos_pm_syscore_ops);
 suspend_set_ops(exynos_suspend_ops);
  }


 Please consider this patch for next fixes pull request. Without it
 suspend/resume is broken for Exynos4 and probably other SoCs. This patch
 just restores the sequence from before the patch moving things to PM
 notifier, so I don't think it should need any special treatment.

 Your patch fixes the regression and is a step in the good direction but it
 seems that it needs a bit more work:

 Your patch adds to cpuidle AFTR code path restoring of exynos_core_save and
 exynos5_sys_save registers without saving them first (restoring is done
 through exynos_pm_resume() which is used by both suspend and cpuidle while
 saving is done through exynos_pm_prepare() which is used only by suspend).

 That's right, unfortunately. Interestingly enough AFTR worked fine on
 Exynos4210 with this patch, but still this needs to be fixed.

 Now, in fact, I recall that Chander had some objections to this patch as
 well and we decided that he will send another patch to replace mine [1],
 but I haven't heard from him since that.

Patch for the same has been already posted.
Below is the link for the same
http://www.spinics.net/lists/arm-kernel/msg343402.html

This patch has conflict with Russel's patch, so i will rebase on his
tree and resend

This patch can be ignored in that case.


 Chander, do you have any progress with this? Keep in mind that we need
 this as an rc fix and we already have rc5, so not much time left. If you
 don't have time to work on this I can take care of this, proceeding as
 we discussed in [1].

 [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29085/focus=33975

 Best regards,
 Tomasz
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[Patch v7 0/6] add cpuidle support for Exynos5420

2014-06-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.
Rebased on 3.16-rc1

Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[Patch v7 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
Acked-by: Daniel Lezcano 
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = "arm,vexpress,v2p-ca15_a7" },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path("/");
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible("arm,vexpress,v2p-ca15_a7"))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[Patch v7 2/6] arm: exynos: add generic function to calculate cpu number

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08..aff23bd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -323,4 +323,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include 
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[Patch v7 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

Add "samsung,exynos5420" compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
Acked-by: Daniel Lezcano 
---
Changes in v5: None
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = "arm,vexpress,v2p-ca15_a7" },
+   { .compatible = "samsung,exynos5420" },
{},
 };
 
-- 
1.7.9.5

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[Patch v7 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index 0498d0b..fc47e68 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -258,10 +258,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: "This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register."
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.wait_for_powerdown = exynos_wait_for_powerdown,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[Patch v7 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
Acked-by: Daniel Lezcano 
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..2f6b33e 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -9,7 +9,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
 
 config ARM_BIG_LITTLE_CPUIDLE
bool "Support for ARM big.LITTLE processors"
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v7 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap 

Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Reviewed-by: Tomasz Figa 
Acked-by: Daniel Lezcano 
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use "samsung,exynos5420" compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 90aab4d..f4c08d6 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -271,7 +271,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible("samsung,exynos5420"))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-16 Thread Chander Kashyap
Hi Doug,

On 13 June 2014 20:40, Doug Anderson  wrote:
> Chander,
>
> On Fri, Jun 13, 2014 at 4:54 AM, Chander Kashyap  
> wrote:
>> This patch is effectively changing the mcpm_entry_point address from
>> nsbase + 0x1c to nsbase + 0x8
>>
>> Hence while integrating with mainline u-boot we need to take care for
>> new mcpm_entry_point address.
>>
>> With Chromebook it works straightforward.
>
> Can you explain more and point to the code that is using the nsbase +
> 0x1c?  Specifically the only code I see that uses the nsbase + 0x1c is
> the code that is located at nsbase, which is the code we're
> overwriting here.  I'd imagine you're using U-Boot code that looks
> something like the bits that start at code_base here:
>
> https://chromium.googlesource.com/chromiumos/third_party/u-boot/+/ce358daf5069f1dc145b0f9d403cfbb028271807/arch/arm/cpu/armv7/exynos/lowlevel.S
>
> With my kernel change you can completely eliminate U-Boot's
> installation of this code (or keep it, it makes no difference).

Yes i agree with your point.
What i am saying is when there is full support for Exynos5420 in
mainline u-boot we need to take care for the mcpm_entry_point address.

>
> -Doug



-- 
with warm regards,
Chander Kashyap
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-16 Thread Chander Kashyap
Hi Doug,

On 13 June 2014 20:40, Doug Anderson diand...@chromium.org wrote:
 Chander,

 On Fri, Jun 13, 2014 at 4:54 AM, Chander Kashyap k.chan...@samsung.com 
 wrote:
 This patch is effectively changing the mcpm_entry_point address from
 nsbase + 0x1c to nsbase + 0x8

 Hence while integrating with mainline u-boot we need to take care for
 new mcpm_entry_point address.

 With Chromebook it works straightforward.

 Can you explain more and point to the code that is using the nsbase +
 0x1c?  Specifically the only code I see that uses the nsbase + 0x1c is
 the code that is located at nsbase, which is the code we're
 overwriting here.  I'd imagine you're using U-Boot code that looks
 something like the bits that start at code_base here:

 https://chromium.googlesource.com/chromiumos/third_party/u-boot/+/ce358daf5069f1dc145b0f9d403cfbb028271807/arch/arm/cpu/armv7/exynos/lowlevel.S

 With my kernel change you can completely eliminate U-Boot's
 installation of this code (or keep it, it makes no difference).

Yes i agree with your point.
What i am saying is when there is full support for Exynos5420 in
mainline u-boot we need to take care for the mcpm_entry_point address.


 -Doug



-- 
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Chander Kashyap
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[Patch v7 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use samsung,exynos5420 compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 90aab4d..f4c08d6 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -271,7 +271,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible(samsung,exynos5420))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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[Patch v7 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..2f6b33e 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -9,7 +9,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[Patch v7 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v5: None
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[Patch v7 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index 0498d0b..fc47e68 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -258,10 +258,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.wait_for_powerdown = exynos_wait_for_powerdown,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[Patch v7 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[Patch v7 2/6] arm: exynos: add generic function to calculate cpu number

2014-06-16 Thread Chander Kashyap
From: Chander Kashyap chander.kash...@linaro.org

The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 1d13b08..aff23bd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -323,4 +323,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[Patch v7 0/6] add cpuidle support for Exynos5420

2014-06-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.
Rebased on 3.16-rc1

Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-13 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 8:58 PM, Kukjin Kim  wrote:
> On 06/12/14 00:19, Doug Anderson wrote:
>>
>> Chander,
>>
>> On Tue, Jun 10, 2014 at 9:52 PM, Chander Kashyap
>> wrote:
>>>
>>> Hi Doug,
>>>
>>> On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre
>>> wrote:
>>>>
>>>> On Tue, 10 Jun 2014, Doug Anderson wrote:
>>>>
>>>>> My S-state knowledge is not strong, but I believe that Lorenzo's
>>>>> questions matter if we're using S2 for CPUidle (where we actually turn
>>>>> off power and hot unplug CPUs) but not when we're using S1 for CPUidle
>>>>> (where we just enter WFI/WFE).
>>>>>
>>>
>>> No Its not plain WFI.
>>>
>>> All cores in Exynos5420 can be powered off independently.
>>> This functionality has been tested.
>>>
>>> Below is the link for the posted patches.
>>>
>>> https://lkml.org/lkml/2014/6/10/194
>>>
>>> And as Nicolas wrote, these patches need MCPM for that.
>>
>>
>> Most excellent!  I should have been more clear that I only knew about
>> how CPUidle worked in our local production kernel.  There I'm pretty
>> sure CPUidle is just WFI/WFE.  If you've got patches to do better then
>> that's great!
>>
>> ...can you confirm that my patch doesn't interfere with your improved
>> CPUidle?  It's been Acked by Nicolas (thanks!) so I'd imagine it will
>> land shortly.  Kukjin: I assume you'll be taking this?
>>

This patch is effectively changing the mcpm_entry_point address from
nsbase + 0x1c to nsbase + 0x8

Hence while integrating with mainline u-boot we need to take care for
new mcpm_entry_point address.

With Chromebook it works straightforward.


> Sure, I will ;-)
>
> Thanks,
> Kukjin
>
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-13 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 8:58 PM, Kukjin Kim kgene@samsung.com wrote:
 On 06/12/14 00:19, Doug Anderson wrote:

 Chander,

 On Tue, Jun 10, 2014 at 9:52 PM, Chander Kashyapk.chan...@samsung.com
 wrote:

 Hi Doug,

 On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitrenicolas.pi...@linaro.org
 wrote:

 On Tue, 10 Jun 2014, Doug Anderson wrote:

 My S-state knowledge is not strong, but I believe that Lorenzo's
 questions matter if we're using S2 for CPUidle (where we actually turn
 off power and hot unplug CPUs) but not when we're using S1 for CPUidle
 (where we just enter WFI/WFE).


 No Its not plain WFI.

 All cores in Exynos5420 can be powered off independently.
 This functionality has been tested.

 Below is the link for the posted patches.

 https://lkml.org/lkml/2014/6/10/194

 And as Nicolas wrote, these patches need MCPM for that.


 Most excellent!  I should have been more clear that I only knew about
 how CPUidle worked in our local production kernel.  There I'm pretty
 sure CPUidle is just WFI/WFE.  If you've got patches to do better then
 that's great!

 ...can you confirm that my patch doesn't interfere with your improved
 CPUidle?  It's been Acked by Nicolas (thanks!) so I'd imagine it will
 land shortly.  Kukjin: I assume you'll be taking this?


This patch is effectively changing the mcpm_entry_point address from
nsbase + 0x1c to nsbase + 0x8

Hence while integrating with mainline u-boot we need to take care for
new mcpm_entry_point address.

With Chromebook it works straightforward.


 Sure, I will ;-)

 Thanks,
 Kukjin

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On 11 June 2014 18:45, Lorenzo Pieralisi  wrote:
> On Wed, Jun 11, 2014 at 01:14:21PM +0100, Chander Kashyap wrote:
>> On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
>>  wrote:
>> > On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
>> >> Hi Doug,
>> >>
>> >> On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre  
>> >> wrote:
>> >> > On Tue, 10 Jun 2014, Doug Anderson wrote:
>> >> >
>> >> >> My S-state knowledge is not strong, but I believe that Lorenzo's
>> >> >> questions matter if we're using S2 for CPUidle (where we actually turn
>> >> >> off power and hot unplug CPUs) but not when we're using S1 for CPUidle
>> >> >> (where we just enter WFI/WFE).
>> >> >>
>> >>
>> >> No Its not plain WFI.
>> >>
>> >> All cores in Exynos5420 can be powered off independently.
>> >> This functionality has been tested.
>> >>
>> >> Below is the link for the posted patches.
>> >>
>> >> https://lkml.org/lkml/2014/6/10/194
>> >>
>> >> And as Nicolas wrote, these patches need MCPM for that.
>> >
>> > Chander, I cast a look into the code and I have a question
>> > (you also told me on CPUidle review that only core off
>> > is supported in CPUidle).
>> >
>> > When you say all cores can be powered off independently, do
>> > you also mean that clusters can be powered off (in CPUidle) ?
>> >
>> > I am pointing this out since in the MCPM backend I noticed:
>> >
>> > "/* TODO: Turn off the cluster here to save power. */"
>> >
>> > I do not see any cluster power down request in the down path.
>> >
>> > If I am wrong, ignore my message, I am just writing to help.
>> >
>> > If you can only power down cores, but not the clusters on idle,
>> > please keep in mind that you are currently cleaning and invalidating
>> > the L2 when last man is running and this must not be taken
>> > lightly since, if L2 stays on, that's a massive energy waste
>> > for nothing.
>> >
>> > So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
>> > to avoid cleaning L2, that's pivotal.
>>
>> Hi Lorenzo,
>> Cluster shutdown is in progress. Abhilash will add support for that.
>>
>> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html
>

Hi Lorenzo,

> Hi Chander,
>
> thanks. So, as a heads-up:
>
> 1) if you merge CPUidle support now, as it is it is at least suboptimal, may
>even burn more energy than it saves. Latencies in the bL idle driver
>are likely to be wrong, since they are for cluster shutdown and for
>TC2, not core power gating that should require shorter target_residencies.
>On top of that, L2 is cleaned and invalidated for nothing.

Yes true.

> 2) when cluster support is merged, you might want to extend the CPUidle
>driver to add an additional state (ie C1 core gating, C2 cluster
>gating) and to do that you should extend the driver and the MCPM
>back-end accordingly, I discussed that with Nico already some time ago
>and actually it should be fairly easy to do but we have got to talk
>about that.
>

Yes thats the final goal to add two states (C1 core gating, C2 cluster gating).
But that will be done in combination with yours patches(to pass
cpuidle data thru DT).

So finally the mcpm backend will take care for c1 and c2 cpuidle state
implementation.

> Thank you,
> Lorenzo
>
>>
>>
>> >
>> > Lorenzo
>> >
>> >>
>> >> >> I believe that in ChromeOS we use S1 CPUidle and that it works fine.
>> >> >> We've never implemented S2 that I'm aware of.
>> >> >
>> >> > You'll have to rely on MCPM for that.  That's probably why it hasn't
>> >> > been implemented before.
>> >> >
>> >> >
>> >> > Nicolas
>> >> >
>> >> > ___
>> >> > linux-arm-kernel mailing list
>> >> > linux-arm-ker...@lists.infradead.org
>> >> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >> --
>> >> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> >> the body of a message to majord...@vger.kernel.org
>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> >> Please read the FAQ at  http://www.tux.org/lkml/
>> >>
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe 
>> > linux-samsung-soc" in
>> > the body of a message to majord...@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>



-- 
with warm regards,
Chander Kashyap
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
 wrote:
> On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
>> Hi Doug,
>>
>> On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre  
>> wrote:
>> > On Tue, 10 Jun 2014, Doug Anderson wrote:
>> >
>> >> My S-state knowledge is not strong, but I believe that Lorenzo's
>> >> questions matter if we're using S2 for CPUidle (where we actually turn
>> >> off power and hot unplug CPUs) but not when we're using S1 for CPUidle
>> >> (where we just enter WFI/WFE).
>> >>
>>
>> No Its not plain WFI.
>>
>> All cores in Exynos5420 can be powered off independently.
>> This functionality has been tested.
>>
>> Below is the link for the posted patches.
>>
>> https://lkml.org/lkml/2014/6/10/194
>>
>> And as Nicolas wrote, these patches need MCPM for that.
>
> Chander, I cast a look into the code and I have a question
> (you also told me on CPUidle review that only core off
> is supported in CPUidle).
>
> When you say all cores can be powered off independently, do
> you also mean that clusters can be powered off (in CPUidle) ?
>
> I am pointing this out since in the MCPM backend I noticed:
>
> "/* TODO: Turn off the cluster here to save power. */"
>
> I do not see any cluster power down request in the down path.
>
> If I am wrong, ignore my message, I am just writing to help.
>
> If you can only power down cores, but not the clusters on idle,
> please keep in mind that you are currently cleaning and invalidating
> the L2 when last man is running and this must not be taken
> lightly since, if L2 stays on, that's a massive energy waste
> for nothing.
>
> So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
> to avoid cleaning L2, that's pivotal.

Hi Lorenzo,
Cluster shutdown is in progress. Abhilash will add support for that.

https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html


>
> Lorenzo
>
>>
>> >> I believe that in ChromeOS we use S1 CPUidle and that it works fine.
>> >> We've never implemented S2 that I'm aware of.
>> >
>> > You'll have to rely on MCPM for that.  That's probably why it hasn't
>> > been implemented before.
>> >
>> >
>> > Nicolas
>> >
>> > ___
>> > linux-arm-kernel mailing list
>> > linux-arm-ker...@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majord...@vger.kernel.org
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>>
>
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
 On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
 Hi Doug,

 On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org 
 wrote:
  On Tue, 10 Jun 2014, Doug Anderson wrote:
 
  My S-state knowledge is not strong, but I believe that Lorenzo's
  questions matter if we're using S2 for CPUidle (where we actually turn
  off power and hot unplug CPUs) but not when we're using S1 for CPUidle
  (where we just enter WFI/WFE).
 

 No Its not plain WFI.

 All cores in Exynos5420 can be powered off independently.
 This functionality has been tested.

 Below is the link for the posted patches.

 https://lkml.org/lkml/2014/6/10/194

 And as Nicolas wrote, these patches need MCPM for that.

 Chander, I cast a look into the code and I have a question
 (you also told me on CPUidle review that only core off
 is supported in CPUidle).

 When you say all cores can be powered off independently, do
 you also mean that clusters can be powered off (in CPUidle) ?

 I am pointing this out since in the MCPM backend I noticed:

 /* TODO: Turn off the cluster here to save power. */

 I do not see any cluster power down request in the down path.

 If I am wrong, ignore my message, I am just writing to help.

 If you can only power down cores, but not the clusters on idle,
 please keep in mind that you are currently cleaning and invalidating
 the L2 when last man is running and this must not be taken
 lightly since, if L2 stays on, that's a massive energy waste
 for nothing.

 So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
 to avoid cleaning L2, that's pivotal.

Hi Lorenzo,
Cluster shutdown is in progress. Abhilash will add support for that.

https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html



 Lorenzo


  I believe that in ChromeOS we use S1 CPUidle and that it works fine.
  We've never implemented S2 that I'm aware of.
 
  You'll have to rely on MCPM for that.  That's probably why it hasn't
  been implemented before.
 
 
  Nicolas
 
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-11 Thread Chander Kashyap
On 11 June 2014 18:45, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Wed, Jun 11, 2014 at 01:14:21PM +0100, Chander Kashyap wrote:
 On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
 lorenzo.pieral...@arm.com wrote:
  On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
  Hi Doug,
 
  On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org 
  wrote:
   On Tue, 10 Jun 2014, Doug Anderson wrote:
  
   My S-state knowledge is not strong, but I believe that Lorenzo's
   questions matter if we're using S2 for CPUidle (where we actually turn
   off power and hot unplug CPUs) but not when we're using S1 for CPUidle
   (where we just enter WFI/WFE).
  
 
  No Its not plain WFI.
 
  All cores in Exynos5420 can be powered off independently.
  This functionality has been tested.
 
  Below is the link for the posted patches.
 
  https://lkml.org/lkml/2014/6/10/194
 
  And as Nicolas wrote, these patches need MCPM for that.
 
  Chander, I cast a look into the code and I have a question
  (you also told me on CPUidle review that only core off
  is supported in CPUidle).
 
  When you say all cores can be powered off independently, do
  you also mean that clusters can be powered off (in CPUidle) ?
 
  I am pointing this out since in the MCPM backend I noticed:
 
  /* TODO: Turn off the cluster here to save power. */
 
  I do not see any cluster power down request in the down path.
 
  If I am wrong, ignore my message, I am just writing to help.
 
  If you can only power down cores, but not the clusters on idle,
  please keep in mind that you are currently cleaning and invalidating
  the L2 when last man is running and this must not be taken
  lightly since, if L2 stays on, that's a massive energy waste
  for nothing.
 
  So, if clusters stay up, you _have_ to tweak the MCPM backend slightly
  to avoid cleaning L2, that's pivotal.

 Hi Lorenzo,
 Cluster shutdown is in progress. Abhilash will add support for that.

 https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31104.html


Hi Lorenzo,

 Hi Chander,

 thanks. So, as a heads-up:

 1) if you merge CPUidle support now, as it is it is at least suboptimal, may
even burn more energy than it saves. Latencies in the bL idle driver
are likely to be wrong, since they are for cluster shutdown and for
TC2, not core power gating that should require shorter target_residencies.
On top of that, L2 is cleaned and invalidated for nothing.

Yes true.

 2) when cluster support is merged, you might want to extend the CPUidle
driver to add an additional state (ie C1 core gating, C2 cluster
gating) and to do that you should extend the driver and the MCPM
back-end accordingly, I discussed that with Nico already some time ago
and actually it should be fairly easy to do but we have got to talk
about that.


Yes thats the final goal to add two states (C1 core gating, C2 cluster gating).
But that will be done in combination with yours patches(to pass
cpuidle data thru DT).

So finally the mcpm backend will take care for c1 and c2 cpuidle state
implementation.

 Thank you,
 Lorenzo



 
  Lorenzo
 
 
   I believe that in ChromeOS we use S1 CPUidle and that it works fine.
   We've never implemented S2 that I'm aware of.
  
   You'll have to rely on MCPM for that.  That's probably why it hasn't
   been implemented before.
  
  
   Nicolas
  
   ___
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   linux-arm-ker...@lists.infradead.org
   http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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-- 
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
Hi Doug,

On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre  wrote:
> On Tue, 10 Jun 2014, Doug Anderson wrote:
>
>> My S-state knowledge is not strong, but I believe that Lorenzo's
>> questions matter if we're using S2 for CPUidle (where we actually turn
>> off power and hot unplug CPUs) but not when we're using S1 for CPUidle
>> (where we just enter WFI/WFE).
>>

No Its not plain WFI.

All cores in Exynos5420 can be powered off independently.
This functionality has been tested.

Below is the link for the posted patches.

https://lkml.org/lkml/2014/6/10/194

And as Nicolas wrote, these patches need MCPM for that.

>> I believe that in ChromeOS we use S1 CPUidle and that it works fine.
>> We've never implemented S2 that I'm aware of.
>
> You'll have to rely on MCPM for that.  That's probably why it hasn't
> been implemented before.
>
>
> Nicolas
>
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
On 10 June 2014 04:08, Lorenzo Pieralisi  wrote:
> On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
>
> [...]
>
>> Cold boot and resume from suspend are detected via various special
>> flags in various special locations.  Resume from suspend looks at
>> INFORM1 (0x10048004) for flags.  This register is 0 during a cold boot
>> and has special values set by the kernel at resume time.
>>
>> It also looks as if some code looks at 0x10040900 (PMU_SPARE0) to help
>> tell initial cold boot and secondary CPU bringup.
>
> Ok, thanks a lot. It looks like firmware paths should be ready to
> detect cold vs warm boot, and hopefully do not rely on a specific
> MPIDR to come up first out of power states.
>
>> > I am asking to check if on this platform CPUidle (where the notion of
>> > primary CPU disappears) has a chance to run properly.
>>
>> I believe it should be possible, but we don't have CPUidle implemented
>> in our current system.  Abhilash may be able to comment more.
>

Cpuidle is implemented for exynos5420, and is tested on chromebook.


> I am interested in more insights, that's very helpful thanks.
>
>> > Probably CPUidle won't attain idle states where IRAM content is lost, but I
>> > am still worried about the primary vs secondaries firmware boot behaviour.
>>
>> I don't think iRAM can be turned off for CPUidle.

Yes thats true.
>
> It might be added a system state but I doubt that too and if you are
> relying on registers for jump addresses that's not even a problem in
> the first place.
>
>> > What happens on reboot from suspend to RAM (or to put it differently,
>> > what does secure firmware do on reboot from suspend to RAM - in
>> > particular how is the "jump" address to bootloader/kernel set ?)
>>
>> Should be described above now.
>
> Thank you very much.
>
> Lorenzo
>
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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
On 10 June 2014 04:08, Lorenzo Pieralisi lorenzo.pieral...@arm.com wrote:
 On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:

 [...]

 Cold boot and resume from suspend are detected via various special
 flags in various special locations.  Resume from suspend looks at
 INFORM1 (0x10048004) for flags.  This register is 0 during a cold boot
 and has special values set by the kernel at resume time.

 It also looks as if some code looks at 0x10040900 (PMU_SPARE0) to help
 tell initial cold boot and secondary CPU bringup.

 Ok, thanks a lot. It looks like firmware paths should be ready to
 detect cold vs warm boot, and hopefully do not rely on a specific
 MPIDR to come up first out of power states.

  I am asking to check if on this platform CPUidle (where the notion of
  primary CPU disappears) has a chance to run properly.

 I believe it should be possible, but we don't have CPUidle implemented
 in our current system.  Abhilash may be able to comment more.


Cpuidle is implemented for exynos5420, and is tested on chromebook.


 I am interested in more insights, that's very helpful thanks.

  Probably CPUidle won't attain idle states where IRAM content is lost, but I
  am still worried about the primary vs secondaries firmware boot behaviour.

 I don't think iRAM can be turned off for CPUidle.

Yes thats true.

 It might be added a system state but I doubt that too and if you are
 relying on registers for jump addresses that's not even a problem in
 the first place.

  What happens on reboot from suspend to RAM (or to put it differently,
  what does secure firmware do on reboot from suspend to RAM - in
  particular how is the jump address to bootloader/kernel set ?)

 Should be described above now.

 Thank you very much.

 Lorenzo

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Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

2014-06-10 Thread Chander Kashyap
Hi Doug,

On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre nicolas.pi...@linaro.org wrote:
 On Tue, 10 Jun 2014, Doug Anderson wrote:

 My S-state knowledge is not strong, but I believe that Lorenzo's
 questions matter if we're using S2 for CPUidle (where we actually turn
 off power and hot unplug CPUs) but not when we're using S1 for CPUidle
 (where we just enter WFI/WFE).


No Its not plain WFI.

All cores in Exynos5420 can be powered off independently.
This functionality has been tested.

Below is the link for the posted patches.

https://lkml.org/lkml/2014/6/10/194

And as Nicolas wrote, these patches need MCPM for that.

 I believe that in ChromeOS we use S1 CPUidle and that it works fine.
 We've never implemented S2 that I'm aware of.

 You'll have to rely on MCPM for that.  That's probably why it hasn't
 been implemented before.


 Nicolas

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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-28 Thread Chander Kashyap
On 28 May 2014 14:32, Daniel Lezcano  wrote:
> On 05/28/2014 06:35 AM, Kukjin Kim wrote:
>>
>> Chander Kashyap wrote:
>>>
>>>
>>> On 26 May 2014 15:59, Tomasz Figa  wrote:
>>>>
>>>> Hi Chander,
>>>>
>>>> On 16.05.2014 10:03, Chander Kashyap wrote:
>>>>>
>>>>> Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7
>>>
>>> cores.
>>>>>
>>>>>
>>>>> This patchset adds cpuidle support for Exynos5420 SoC based on
>>>>> generic big.little cpuidle driver.
>>>>>
>>>>> Tested on SMDK5420.
>>>>>
>>>>> This patch set depends on:
>>>>>1. [PATCH 0/5] MCPM backend for Exynos5420
>>>>>   http://www.spinics.net/lists/arm-kernel/msg331100.html
>>>>> Changelog is in respective patches.
>>>>> Chander Kashyap (5):
>>>>>driver: cpuidle-big-little: add of_device_id structure
>>>>>arm: exynos: add generic function to calculate cpu number
>>>>>cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
>>>>>  driver
>>>>>driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
>>>>>exynos: cpuidle: do not allow cpuidle registration for Exynos5420
>>>>>mcpm: exynos: populate suspend and powered_up callbacks
>>>>>
>>>>>   arch/arm/mach-exynos/exynos.c|4 +++-
>>>>>   arch/arm/mach-exynos/mcpm-exynos.c   |   36
>>>
>>> ++
>>>>>
>>>>>   arch/arm/mach-exynos/regs-pmu.h  |9 +
>>>>>   drivers/cpuidle/Kconfig.arm  |2 +-
>>>>>   drivers/cpuidle/cpuidle-big_little.c |   12 +++-
>>>>>   5 files changed, 60 insertions(+), 3 deletions(-)
>>>>>
>>>>
>>>> For the whole series,
>>>>
>>>> Reviewed-by: Tomasz Figa 
>>>
>>>
>>> Thanks Tomasz.
>>>
>>> Dear Kukjin,
>>> Can you take these patches.
>>>>
>>>>
>> When I looked at this series quickly, looks good to me but I need to get
>> ack from cpuidle maintainer Rafael or Daniel.
>
>
> Acked the different cpuidle bits.

Hi Kukjin,
Can you take it now?


>
> Thanks
>   -- Daniel
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>



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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-28 Thread Chander Kashyap
On 28 May 2014 14:32, Daniel Lezcano daniel.lezc...@linaro.org wrote:
 On 05/28/2014 06:35 AM, Kukjin Kim wrote:

 Chander Kashyap wrote:


 On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:

 Hi Chander,

 On 16.05.2014 10:03, Chander Kashyap wrote:

 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7

 cores.


 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
driver: cpuidle-big-little: add of_device_id structure
arm: exynos: add generic function to calculate cpu number
cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
  driver
driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
exynos: cpuidle: do not allow cpuidle registration for Exynos5420
mcpm: exynos: populate suspend and powered_up callbacks

   arch/arm/mach-exynos/exynos.c|4 +++-
   arch/arm/mach-exynos/mcpm-exynos.c   |   36

 ++

   arch/arm/mach-exynos/regs-pmu.h  |9 +
   drivers/cpuidle/Kconfig.arm  |2 +-
   drivers/cpuidle/cpuidle-big_little.c |   12 +++-
   5 files changed, 60 insertions(+), 3 deletions(-)


 For the whole series,

 Reviewed-by: Tomasz Figa t.f...@samsung.com


 Thanks Tomasz.

 Dear Kukjin,
 Can you take these patches.


 When I looked at this series quickly, looks good to me but I need to get
 ack from cpuidle maintainer Rafael or Daniel.


 Acked the different cpuidle bits.

Hi Kukjin,
Can you take it now?



 Thanks
   -- Daniel


 --
  http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs

 Follow Linaro:  http://www.facebook.com/pages/Linaro Facebook |
 http://twitter.com/#!/linaroorg Twitter |
 http://www.linaro.org/linaro-blog/ Blog




-- 
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Chander Kashyap
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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-27 Thread Chander Kashyap
On 26 May 2014 15:59, Tomasz Figa  wrote:
> Hi Chander,
>
> On 16.05.2014 10:03, Chander Kashyap wrote:
>> Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
>>
>> This patchset adds cpuidle support for Exynos5420 SoC based on
>> generic big.little cpuidle driver.
>>
>> Tested on SMDK5420.
>>
>> This patch set depends on:
>>   1. [PATCH 0/5] MCPM backend for Exynos5420
>>  http://www.spinics.net/lists/arm-kernel/msg331100.html
>> Changelog is in respective patches.
>> Chander Kashyap (5):
>>   driver: cpuidle-big-little: add of_device_id structure
>>   arm: exynos: add generic function to calculate cpu number
>>   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
>> driver
>>   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
>>   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
>>   mcpm: exynos: populate suspend and powered_up callbacks
>>
>>  arch/arm/mach-exynos/exynos.c|4 +++-
>>  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
>> ++
>>  arch/arm/mach-exynos/regs-pmu.h  |9 +
>>  drivers/cpuidle/Kconfig.arm  |2 +-
>>  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
>>  5 files changed, 60 insertions(+), 3 deletions(-)
>>
>
> For the whole series,
>
> Reviewed-by: Tomasz Figa 

Thanks Tomasz.

Dear Kukjin,
Can you take these patches.
>
> Best regards,
> Tomasz



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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-27 Thread Chander Kashyap
On 26 May 2014 15:59, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Chander,

 On 16.05.2014 10:03, Chander Kashyap wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
   1. [PATCH 0/5] MCPM backend for Exynos5420
  http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)


 For the whole series,

 Reviewed-by: Tomasz Figa t.f...@samsung.com

Thanks Tomasz.

Dear Kukjin,
Can you take these patches.

 Best regards,
 Tomasz



-- 
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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-25 Thread Chander Kashyap
On 19 May 2014 11:10, Chander Kashyap  wrote:
> Hi Daniel/Kgene,
>
> On 16 May 2014 13:33, Chander Kashyap  wrote:
>> Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
>>
>> This patchset adds cpuidle support for Exynos5420 SoC based on
>> generic big.little cpuidle driver.
>>
>> Tested on SMDK5420.
>>
>> This patch set depends on:
>> 1. [PATCH 0/5] MCPM backend for Exynos5420
>>http://www.spinics.net/lists/arm-kernel/msg331100.html
>> Changelog is in respective patches.
>> Chander Kashyap (5):
>>   driver: cpuidle-big-little: add of_device_id structure
>>   arm: exynos: add generic function to calculate cpu number
>>   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
>> driver
>>   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
>>   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
>>   mcpm: exynos: populate suspend and powered_up callbacks
>>
>>  arch/arm/mach-exynos/exynos.c|4 +++-
>>  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
>> ++
>>  arch/arm/mach-exynos/regs-pmu.h  |9 +
>>  drivers/cpuidle/Kconfig.arm  |2 +-
>>  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
>>  5 files changed, 60 insertions(+), 3 deletions(-)
>>
>> --
>> 1.7.9.5
>>
>
> As dependency patches are merged. If their are no further comment, can
> these patches be taken?
>

ping

> --
> with warm regards,
> Chander Kashyap



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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-25 Thread Chander Kashyap
On 19 May 2014 11:10, Chander Kashyap chander.kash...@linaro.org wrote:
 Hi Daniel/Kgene,

 On 16 May 2014 13:33, Chander Kashyap chander.kash...@linaro.org wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
 1. [PATCH 0/5] MCPM backend for Exynos5420
http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)

 --
 1.7.9.5


 As dependency patches are merged. If their are no further comment, can
 these patches be taken?


ping

 --
 with warm regards,
 Chander Kashyap



-- 
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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-18 Thread Chander Kashyap
Hi Daniel/Kgene,

On 16 May 2014 13:33, Chander Kashyap  wrote:
> Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
>
> This patchset adds cpuidle support for Exynos5420 SoC based on
> generic big.little cpuidle driver.
>
> Tested on SMDK5420.
>
> This patch set depends on:
> 1. [PATCH 0/5] MCPM backend for Exynos5420
>http://www.spinics.net/lists/arm-kernel/msg331100.html
> Changelog is in respective patches.
> Chander Kashyap (5):
>   driver: cpuidle-big-little: add of_device_id structure
>   arm: exynos: add generic function to calculate cpu number
>   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
> driver
>   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
>   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
>   mcpm: exynos: populate suspend and powered_up callbacks
>
>  arch/arm/mach-exynos/exynos.c|4 +++-
>  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
> ++
>  arch/arm/mach-exynos/regs-pmu.h  |9 +
>  drivers/cpuidle/Kconfig.arm  |2 +-
>  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
>  5 files changed, 60 insertions(+), 3 deletions(-)
>
> --
> 1.7.9.5
>

As dependency patches are merged. If their are no further comment, can
these patches be taken?

-- 
with warm regards,
Chander Kashyap
--
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Re: [PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-18 Thread Chander Kashyap
Hi Daniel/Kgene,

On 16 May 2014 13:33, Chander Kashyap chander.kash...@linaro.org wrote:
 Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

 This patchset adds cpuidle support for Exynos5420 SoC based on
 generic big.little cpuidle driver.

 Tested on SMDK5420.

 This patch set depends on:
 1. [PATCH 0/5] MCPM backend for Exynos5420
http://www.spinics.net/lists/arm-kernel/msg331100.html
 Changelog is in respective patches.
 Chander Kashyap (5):
   driver: cpuidle-big-little: add of_device_id structure
   arm: exynos: add generic function to calculate cpu number
   cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
 driver
   driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
   exynos: cpuidle: do not allow cpuidle registration for Exynos5420
   mcpm: exynos: populate suspend and powered_up callbacks

  arch/arm/mach-exynos/exynos.c|4 +++-
  arch/arm/mach-exynos/mcpm-exynos.c   |   36 
 ++
  arch/arm/mach-exynos/regs-pmu.h  |9 +
  drivers/cpuidle/Kconfig.arm  |2 +-
  drivers/cpuidle/cpuidle-big_little.c |   12 +++-
  5 files changed, 60 insertions(+), 3 deletions(-)

 --
 1.7.9.5


As dependency patches are merged. If their are no further comment, can
these patches be taken?

-- 
with warm regards,
Chander Kashyap
--
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the body of a message to majord...@vger.kernel.org
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[PATCH] PM / OPP: fix incorrect OPP count handling in of_init_opp_table

2014-05-16 Thread Chander Kashyap
In of_init_opp_table function, if a failure to add an OPP is
detected, the count of OPPs, yet to be added is not updated.
Fix this by decrementing this count on failure as well.

Signed-off-by: Chander Kashyap 
Signed-off-by: Inderpal Singh 
---
 drivers/base/power/opp.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index d9e376a..faae9cf 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -643,11 +643,9 @@ int of_init_opp_table(struct device *dev)
unsigned long freq = be32_to_cpup(val++) * 1000;
unsigned long volt = be32_to_cpup(val++);
 
-   if (dev_pm_opp_add(dev, freq, volt)) {
+   if (dev_pm_opp_add(dev, freq, volt))
dev_warn(dev, "%s: Failed to add OPP %ld\n",
 __func__, freq);
-   continue;
-   }
nr -= 2;
}
 
-- 
1.7.9.5

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Re: [RESEND][PATCH] cpuidle: governor: menu: move repeated correction factor check to init

2014-05-16 Thread Chander Kashyap
On 16 May 2014 15:16, Rafael J. Wysocki  wrote:
> On 5/16/2014 10:16 AM, Chander Kashyap wrote:
>>
>> On 22 April 2014 18:08, Chander Kashyap 
>> wrote:
>>>
>>> In menu_select function we check for correction factor every time.
>>> If it is zero we are initializing to unity. Hence move it to init
>>> function
>>> and initialise by unity, hence avoid repeated comparisons.
>>>
>>> Signed-off-by: Chander Kashyap 
>>> Reviewed-by: Tuukka Tikkanen 
>>> ---
>>>   drivers/cpuidle/governors/menu.c |   15 ---
>>>   1 file changed, 8 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/cpuidle/governors/menu.c
>>> b/drivers/cpuidle/governors/menu.c
>>> index 71b5232..9b7918c 100644
>>> --- a/drivers/cpuidle/governors/menu.c
>>> +++ b/drivers/cpuidle/governors/menu.c
>>> @@ -311,13 +311,6 @@ static int menu_select(struct cpuidle_driver *drv,
>>> struct cpuidle_device *dev)
>>>  data->bucket = which_bucket(data->next_timer_us);
>>>
>>>  /*
>>> -* if the correction factor is 0 (eg first time init or cpu
>>> hotplug
>>> -* etc), we actually want to start out with a unity factor.
>>> -*/
>>> -   if (data->correction_factor[data->bucket] == 0)
>>> -   data->correction_factor[data->bucket] = RESOLUTION *
>>> DECAY;
>>> -
>>> -   /*
>>>   * Force the result of multiplication to be 64 bits even if both
>>>   * operands are 32 bits.
>>>   * Make sure to round up for half microseconds.
>>> @@ -466,9 +459,17 @@ static int menu_enable_device(struct cpuidle_driver
>>> *drv,
>>>  struct cpuidle_device *dev)
>>>   {
>>>  struct menu_device *data = _cpu(menu_devices, dev->cpu);
>>> +   int i;
>>>
>>>  memset(data, 0, sizeof(struct menu_device));
>>>
>>> +   /*
>>> +    * if the correction factor is 0 (eg first time init or cpu
>>> hotplug
>>> +* etc), we actually want to start out with a unity factor.
>>> +*/
>>> +   for(i = 0; i < BUCKETS; i++)
>>> +   data->correction_factor[i] = RESOLUTION * DECAY;
>>> +
>>>  return 0;
>>>   }
>>>
>> ping.
>
>
> I believe this is in linux-next today, care to check?
>
> Rafael
>

Thanks, Rafael

-- 
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[PATCH v3] PM / OPP: discard duplicate OPPs

2014-05-16 Thread Chander Kashyap
From: Chander Kashyap 

This patch detects the duplicate OPP entries and discards them

Signed-off-by: Chander Kashyap 
Signed-off-by: Inderpal Singh 
---
 Changes in v3:
- Modify the commit log
 Changes in v2:
- Reorder check for duplicate opp

 drivers/base/power/opp.c |   13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ca521e1..973da78 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -443,15 +443,24 @@ int dev_pm_opp_add(struct device *dev, unsigned long 
freq, unsigned long u_volt)
new_opp->u_volt = u_volt;
new_opp->available = true;
 
-   /* Insert new OPP in order of increasing frequency */
+   /*
+* Insert new OPP in order of increasing frequency
+* and discard if already present
+*/
head = _opp->opp_list;
list_for_each_entry_rcu(opp, _opp->opp_list, node) {
-   if (new_opp->rate < opp->rate)
+   if (new_opp->rate <= opp->rate)
break;
else
head = >node;
}
 
+   if (new_opp->rate == opp->rate) {
+   mutex_unlock(_opp_list_lock);
+   kfree(new_opp);
+   return 0;
+   }
+
list_add_rcu(_opp->node, head);
mutex_unlock(_opp_list_lock);
 
-- 
1.7.9.5

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Re: [PATCH v2] PM / OPP: discard duplicate OPP additions

2014-05-16 Thread Chander Kashyap
On 16 May 2014 13:54, Viresh Kumar  wrote:
> On 16 May 2014 13:43, Chander Kashyap  wrote:
>> From: Chander Kashyap 
>>
>> It may be possible to unregister and re-register the cpufreq driver.
>> One such example is arm big-little IKS cpufreq driver. While
>> re-registering the driver, same OPPs may get added again.
>>
>> This patch detects the duplicacy and discards them.
>
> Diff looks fine but not the log ofcourse. It doesn't have anything to do with
> big LITTLE.. Its just a patch to avoid addition of duplicate OPPs..
>

Big little reference is provided as an example. Nothing much

> Also fix spelling mistakes in log..
>
> And subject should be:
> PM / OPP: discard duplicate OPPs

Duplicates are discarded during OPP addition, and subject line indicates that.

-- 
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[PATCH v6 2/6] arm: exynos: add generic function to calculate cpu number

2014-05-16 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4179f6a..485aefd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -325,4 +325,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include 
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH v6 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-16 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool "Support for ARM big.LITTLE processors"
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[PATCH v6 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-16 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = "arm,vexpress,v2p-ca15_a7" },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path("/");
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible("arm,vexpress,v2p-ca15_a7"))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH v6 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-16 Thread Chander Kashyap
Add "samsung,exynos5420" compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Acked-by: Daniel Lezcano 
---
Changes in v5: None
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = "arm,vexpress,v2p-ca15_a7" },
+   { .compatible = "samsung,exynos5420" },
{},
 };
 
-- 
1.7.9.5

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[PATCH v6 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-16 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: "This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register."
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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Re: [RESEND][PATCH] cpuidle: governor: menu: move repeated correction factor check to init

2014-05-16 Thread Chander Kashyap
On 22 April 2014 18:08, Chander Kashyap  wrote:
> In menu_select function we check for correction factor every time.
> If it is zero we are initializing to unity. Hence move it to init function
> and initialise by unity, hence avoid repeated comparisons.
>
> Signed-off-by: Chander Kashyap 
> Reviewed-by: Tuukka Tikkanen 
> ---
>  drivers/cpuidle/governors/menu.c |   15 ---
>  1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cpuidle/governors/menu.c 
> b/drivers/cpuidle/governors/menu.c
> index 71b5232..9b7918c 100644
> --- a/drivers/cpuidle/governors/menu.c
> +++ b/drivers/cpuidle/governors/menu.c
> @@ -311,13 +311,6 @@ static int menu_select(struct cpuidle_driver *drv, 
> struct cpuidle_device *dev)
> data->bucket = which_bucket(data->next_timer_us);
>
> /*
> -* if the correction factor is 0 (eg first time init or cpu hotplug
> -* etc), we actually want to start out with a unity factor.
> -*/
> -   if (data->correction_factor[data->bucket] == 0)
> -   data->correction_factor[data->bucket] = RESOLUTION * DECAY;
> -
> -   /*
>  * Force the result of multiplication to be 64 bits even if both
>  * operands are 32 bits.
>  * Make sure to round up for half microseconds.
> @@ -466,9 +459,17 @@ static int menu_enable_device(struct cpuidle_driver *drv,
> struct cpuidle_device *dev)
>  {
> struct menu_device *data = _cpu(menu_devices, dev->cpu);
> +   int i;
>
> memset(data, 0, sizeof(struct menu_device));
>
> +   /*
> +* if the correction factor is 0 (eg first time init or cpu hotplug
> +* etc), we actually want to start out with a unity factor.
> +*/
> +   for(i = 0; i < BUCKETS; i++)
> +   data->correction_factor[i] = RESOLUTION * DECAY;
> +
> return 0;
>  }
>

ping.

> --
> 1.7.9.5
>



-- 
with warm regards,
Chander Kashyap
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[PATCH v2] PM / OPP: discard duplicate OPP additions

2014-05-16 Thread Chander Kashyap
From: Chander Kashyap 

It may be possible to unregister and re-register the cpufreq driver.
One such example is arm big-little IKS cpufreq driver. While
re-registering the driver, same OPPs may get added again.

This patch detects the duplicacy and discards them.

Signed-off-by: Chander Kashyap 
Signed-off-by: Inderpal Singh 
---
 Changes in v2:
- Reorder check for duplicate opp

 drivers/base/power/opp.c |   13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ca521e1..973da78 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -443,15 +443,24 @@ int dev_pm_opp_add(struct device *dev, unsigned long 
freq, unsigned long u_volt)
new_opp->u_volt = u_volt;
new_opp->available = true;
 
-   /* Insert new OPP in order of increasing frequency */
+   /*
+* Insert new OPP in order of increasing frequency
+* and discard if already present
+*/
head = _opp->opp_list;
list_for_each_entry_rcu(opp, _opp->opp_list, node) {
-   if (new_opp->rate < opp->rate)
+   if (new_opp->rate <= opp->rate)
break;
else
head = >node;
}
 
+   if (new_opp->rate == opp->rate) {
+   mutex_unlock(_opp_list_lock);
+   kfree(new_opp);
+   return 0;
+   }
+
list_add_rcu(_opp->node, head);
mutex_unlock(_opp_list_lock);
 
-- 
1.7.9.5

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[PATCH v6 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Acked-by: Daniel Lezcano 
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use "samsung,exynos5420" compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4df3452..ef24edf 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -286,7 +286,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible("samsung,exynos5420"))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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[PATCH v6 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v6:
1. Move cpuidle registration check to exynos.c from cpuidle.c and
   use samsung,exynos5420 compatible string to avvoid registration
 arch/arm/mach-exynos/exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 4df3452..ef24edf 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -286,7 +286,9 @@ static void __init exynos_dt_machine_init(void)
}
}
 
-   exynos_cpuidle_init();
+   if (!of_machine_is_compatible(samsung,exynos5420))
+   exynos_cpuidle_init();
+
exynos_cpufreq_init();
 
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-- 
1.7.9.5

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[PATCH v2] PM / OPP: discard duplicate OPP additions

2014-05-16 Thread Chander Kashyap
From: Chander Kashyap k.chan...@samsung.com

It may be possible to unregister and re-register the cpufreq driver.
One such example is arm big-little IKS cpufreq driver. While
re-registering the driver, same OPPs may get added again.

This patch detects the duplicacy and discards them.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
Signed-off-by: Inderpal Singh inderpa...@samsung.com
---
 Changes in v2:
- Reorder check for duplicate opp

 drivers/base/power/opp.c |   13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ca521e1..973da78 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -443,15 +443,24 @@ int dev_pm_opp_add(struct device *dev, unsigned long 
freq, unsigned long u_volt)
new_opp-u_volt = u_volt;
new_opp-available = true;
 
-   /* Insert new OPP in order of increasing frequency */
+   /*
+* Insert new OPP in order of increasing frequency
+* and discard if already present
+*/
head = dev_opp-opp_list;
list_for_each_entry_rcu(opp, dev_opp-opp_list, node) {
-   if (new_opp-rate  opp-rate)
+   if (new_opp-rate = opp-rate)
break;
else
head = opp-node;
}
 
+   if (new_opp-rate == opp-rate) {
+   mutex_unlock(dev_opp_list_lock);
+   kfree(new_opp);
+   return 0;
+   }
+
list_add_rcu(new_opp-node, head);
mutex_unlock(dev_opp_list_lock);
 
-- 
1.7.9.5

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Re: [RESEND][PATCH] cpuidle: governor: menu: move repeated correction factor check to init

2014-05-16 Thread Chander Kashyap
On 22 April 2014 18:08, Chander Kashyap chander.kash...@linaro.org wrote:
 In menu_select function we check for correction factor every time.
 If it is zero we are initializing to unity. Hence move it to init function
 and initialise by unity, hence avoid repeated comparisons.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Reviewed-by: Tuukka Tikkanen tuukka.tikka...@linaro.org
 ---
  drivers/cpuidle/governors/menu.c |   15 ---
  1 file changed, 8 insertions(+), 7 deletions(-)

 diff --git a/drivers/cpuidle/governors/menu.c 
 b/drivers/cpuidle/governors/menu.c
 index 71b5232..9b7918c 100644
 --- a/drivers/cpuidle/governors/menu.c
 +++ b/drivers/cpuidle/governors/menu.c
 @@ -311,13 +311,6 @@ static int menu_select(struct cpuidle_driver *drv, 
 struct cpuidle_device *dev)
 data-bucket = which_bucket(data-next_timer_us);

 /*
 -* if the correction factor is 0 (eg first time init or cpu hotplug
 -* etc), we actually want to start out with a unity factor.
 -*/
 -   if (data-correction_factor[data-bucket] == 0)
 -   data-correction_factor[data-bucket] = RESOLUTION * DECAY;
 -
 -   /*
  * Force the result of multiplication to be 64 bits even if both
  * operands are 32 bits.
  * Make sure to round up for half microseconds.
 @@ -466,9 +459,17 @@ static int menu_enable_device(struct cpuidle_driver *drv,
 struct cpuidle_device *dev)
  {
 struct menu_device *data = per_cpu(menu_devices, dev-cpu);
 +   int i;

 memset(data, 0, sizeof(struct menu_device));

 +   /*
 +* if the correction factor is 0 (eg first time init or cpu hotplug
 +* etc), we actually want to start out with a unity factor.
 +*/
 +   for(i = 0; i  BUCKETS; i++)
 +   data-correction_factor[i] = RESOLUTION * DECAY;
 +
 return 0;
  }


ping.

 --
 1.7.9.5




-- 
with warm regards,
Chander Kashyap
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[PATCH v6 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-16 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v6: None
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH v6 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-16 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v5: None
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[PATCH v6 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-16 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH v6 0/6] add cpuidle support for Exynos5420

2014-05-16 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/exynos.c|4 +++-
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 3 deletions(-)

-- 
1.7.9.5

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[PATCH v6 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-16 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-llittle SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool Support for ARM big.LITTLE processors
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[PATCH v6 2/6] arm: exynos: add generic function to calculate cpu number

2014-05-16 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4179f6a..485aefd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -325,4 +325,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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Re: [PATCH v2] PM / OPP: discard duplicate OPP additions

2014-05-16 Thread Chander Kashyap
On 16 May 2014 13:54, Viresh Kumar viresh.ku...@linaro.org wrote:
 On 16 May 2014 13:43, Chander Kashyap chander.kash...@linaro.org wrote:
 From: Chander Kashyap k.chan...@samsung.com

 It may be possible to unregister and re-register the cpufreq driver.
 One such example is arm big-little IKS cpufreq driver. While
 re-registering the driver, same OPPs may get added again.

 This patch detects the duplicacy and discards them.

 Diff looks fine but not the log ofcourse. It doesn't have anything to do with
 big LITTLE.. Its just a patch to avoid addition of duplicate OPPs..


Big little reference is provided as an example. Nothing much

 Also fix spelling mistakes in log..

 And subject should be:
 PM / OPP: discard duplicate OPPs

Duplicates are discarded during OPP addition, and subject line indicates that.

-- 
with warm regards,
Chander Kashyap
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[PATCH v3] PM / OPP: discard duplicate OPPs

2014-05-16 Thread Chander Kashyap
From: Chander Kashyap k.chan...@samsung.com

This patch detects the duplicate OPP entries and discards them

Signed-off-by: Chander Kashyap k.chan...@samsung.com
Signed-off-by: Inderpal Singh inderpa...@samsung.com
---
 Changes in v3:
- Modify the commit log
 Changes in v2:
- Reorder check for duplicate opp

 drivers/base/power/opp.c |   13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ca521e1..973da78 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -443,15 +443,24 @@ int dev_pm_opp_add(struct device *dev, unsigned long 
freq, unsigned long u_volt)
new_opp-u_volt = u_volt;
new_opp-available = true;
 
-   /* Insert new OPP in order of increasing frequency */
+   /*
+* Insert new OPP in order of increasing frequency
+* and discard if already present
+*/
head = dev_opp-opp_list;
list_for_each_entry_rcu(opp, dev_opp-opp_list, node) {
-   if (new_opp-rate  opp-rate)
+   if (new_opp-rate = opp-rate)
break;
else
head = opp-node;
}
 
+   if (new_opp-rate == opp-rate) {
+   mutex_unlock(dev_opp_list_lock);
+   kfree(new_opp);
+   return 0;
+   }
+
list_add_rcu(new_opp-node, head);
mutex_unlock(dev_opp_list_lock);
 
-- 
1.7.9.5

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Re: [RESEND][PATCH] cpuidle: governor: menu: move repeated correction factor check to init

2014-05-16 Thread Chander Kashyap
On 16 May 2014 15:16, Rafael J. Wysocki rafael.j.wyso...@intel.com wrote:
 On 5/16/2014 10:16 AM, Chander Kashyap wrote:

 On 22 April 2014 18:08, Chander Kashyap chander.kash...@linaro.org
 wrote:

 In menu_select function we check for correction factor every time.
 If it is zero we are initializing to unity. Hence move it to init
 function
 and initialise by unity, hence avoid repeated comparisons.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Reviewed-by: Tuukka Tikkanen tuukka.tikka...@linaro.org
 ---
   drivers/cpuidle/governors/menu.c |   15 ---
   1 file changed, 8 insertions(+), 7 deletions(-)

 diff --git a/drivers/cpuidle/governors/menu.c
 b/drivers/cpuidle/governors/menu.c
 index 71b5232..9b7918c 100644
 --- a/drivers/cpuidle/governors/menu.c
 +++ b/drivers/cpuidle/governors/menu.c
 @@ -311,13 +311,6 @@ static int menu_select(struct cpuidle_driver *drv,
 struct cpuidle_device *dev)
  data-bucket = which_bucket(data-next_timer_us);

  /*
 -* if the correction factor is 0 (eg first time init or cpu
 hotplug
 -* etc), we actually want to start out with a unity factor.
 -*/
 -   if (data-correction_factor[data-bucket] == 0)
 -   data-correction_factor[data-bucket] = RESOLUTION *
 DECAY;
 -
 -   /*
   * Force the result of multiplication to be 64 bits even if both
   * operands are 32 bits.
   * Make sure to round up for half microseconds.
 @@ -466,9 +459,17 @@ static int menu_enable_device(struct cpuidle_driver
 *drv,
  struct cpuidle_device *dev)
   {
  struct menu_device *data = per_cpu(menu_devices, dev-cpu);
 +   int i;

  memset(data, 0, sizeof(struct menu_device));

 +   /*
 +* if the correction factor is 0 (eg first time init or cpu
 hotplug
 +* etc), we actually want to start out with a unity factor.
 +*/
 +   for(i = 0; i  BUCKETS; i++)
 +   data-correction_factor[i] = RESOLUTION * DECAY;
 +
  return 0;
   }

 ping.


 I believe this is in linux-next today, care to check?

 Rafael


Thanks, Rafael

-- 
with warm regards,
Chander Kashyap
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[PATCH] PM / OPP: fix incorrect OPP count handling in of_init_opp_table

2014-05-16 Thread Chander Kashyap
In of_init_opp_table function, if a failure to add an OPP is
detected, the count of OPPs, yet to be added is not updated.
Fix this by decrementing this count on failure as well.

Signed-off-by: Chander Kashyap k.chan...@samsung.com
Signed-off-by: Inderpal Singh inderpa...@samsung.com
---
 drivers/base/power/opp.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index d9e376a..faae9cf 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -643,11 +643,9 @@ int of_init_opp_table(struct device *dev)
unsigned long freq = be32_to_cpup(val++) * 1000;
unsigned long volt = be32_to_cpup(val++);
 
-   if (dev_pm_opp_add(dev, freq, volt)) {
+   if (dev_pm_opp_add(dev, freq, volt))
dev_warn(dev, %s: Failed to add OPP %ld\n,
 __func__, freq);
-   continue;
-   }
nr -= 2;
}
 
-- 
1.7.9.5

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Re: [PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-15 Thread Chander Kashyap
Hi Tomasz,

On 16 May 2014 02:56, Tomasz Figa  wrote:
> Hi Chander,
>
> On 14.05.2014 10:03, Chander Kashyap wrote:
>> Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle 
>> driver.
>> Hence do not allow exynos cpuidle driver registration for Exynos5420.
>>
>> Signed-off-by: Chander Kashyap 
>> Signed-off-by: Chander Kashyap 
>> Acked-by: Daniel Lezcano 
>> ---
>>  arch/arm/mach-exynos/cpuidle.c |3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
>> index 3dd385e..807a386 100644
>> --- a/arch/arm/mach-exynos/cpuidle.c
>> +++ b/arch/arm/mach-exynos/cpuidle.c
>> @@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
>> *pdev)
>>   int cpu_id, ret;
>>   struct cpuidle_device *device;
>>
>> + if (soc_is_exynos5420())
>> + return -ENODEV;
>> +
>>   if (soc_is_exynos5250())
>>   exynos5_core_down_clk();
>>
>>
>
> Why not put this in exynos.c in exynos_dt_machine_init(), so
> exynos_cpuidle_init() is called only if not running on Exynos5420?
>

That makes more sense.
I will update this

Thanks
> Best regards,
> Tomasz



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Re: [PATCH] PM / OPP: discard duplicate OPP additions

2014-05-15 Thread Chander Kashyap
On 15 May 2014 13:57, Viresh Kumar  wrote:
> On 15 May 2014 13:55, Chander Kashyap  wrote:
>> Then in that case the caller must take care for two type of errors:
>> -EEXIST and -ENOMEM
>
> Actually, success: (0 or -EEXIST), failure: Anything else.

Yes exactly. All users of this API need to be modified to handle
EEXIST as success.

To avoid this returning 0 was suggested,

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Re: [PATCH] PM / OPP: discard duplicate OPP additions

2014-05-15 Thread Chander Kashyap
On 14 May 2014 19:57, Nishanth Menon  wrote:
> On 05/14/2014 06:08 AM, Viresh Kumar wrote:
>> On 14 May 2014 15:01, Chander Kashyap  wrote:
>>>> say we do at this point:
>>>> if (new_opp->rate == opp->rate) {
>>>>   dev_err(dev, "%s: attempt to add duplicate OPP entry (rate=%ld)\n",
>>>> __func__, new_opp->rate)
>>>>kfree(new_opp);
>>>> return -EINVAL;
>>>> }
>>>
>>> Yes this is more cleaner.
>>> But instead of dev_err,  we should use dev_warn and secondly
>>
>> Correct
>>
>>> return 0 rather than EINVAL, as there are independent users for this 
>>> function
>>
>> Why? We should actually use EEXIST here instead of EINVAL though..
>>
> Yep -EEXIST is the right return value here. As Viresh indicated,
> reporting back 0 when the requested operation actually was not
> performed is wrong. Caller is supposed to know when it makes an error
> - hiding it is not correct.
>

Then in that case the caller must take care for two type of errors:
-EEXIST and -ENOMEM

> --
> Regards,
> Nishanth Menon



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Re: [PATCH] PM / OPP: discard duplicate OPP additions

2014-05-15 Thread Chander Kashyap
On 14 May 2014 19:57, Nishanth Menon n...@ti.com wrote:
 On 05/14/2014 06:08 AM, Viresh Kumar wrote:
 On 14 May 2014 15:01, Chander Kashyap chander.kash...@linaro.org wrote:
 say we do at this point:
 if (new_opp-rate == opp-rate) {
   dev_err(dev, %s: attempt to add duplicate OPP entry (rate=%ld)\n,
 __func__, new_opp-rate)
kfree(new_opp);
 return -EINVAL;
 }

 Yes this is more cleaner.
 But instead of dev_err,  we should use dev_warn and secondly

 Correct

 return 0 rather than EINVAL, as there are independent users for this 
 function

 Why? We should actually use EEXIST here instead of EINVAL though..

 Yep -EEXIST is the right return value here. As Viresh indicated,
 reporting back 0 when the requested operation actually was not
 performed is wrong. Caller is supposed to know when it makes an error
 - hiding it is not correct.


Then in that case the caller must take care for two type of errors:
-EEXIST and -ENOMEM

 --
 Regards,
 Nishanth Menon



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Re: [PATCH] PM / OPP: discard duplicate OPP additions

2014-05-15 Thread Chander Kashyap
On 15 May 2014 13:57, Viresh Kumar viresh.ku...@linaro.org wrote:
 On 15 May 2014 13:55, Chander Kashyap chander.kash...@linaro.org wrote:
 Then in that case the caller must take care for two type of errors:
 -EEXIST and -ENOMEM

 Actually, success: (0 or -EEXIST), failure: Anything else.

Yes exactly. All users of this API need to be modified to handle
EEXIST as success.

To avoid this returning 0 was suggested,

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Re: [PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-15 Thread Chander Kashyap
Hi Tomasz,

On 16 May 2014 02:56, Tomasz Figa tomasz.f...@gmail.com wrote:
 Hi Chander,

 On 14.05.2014 10:03, Chander Kashyap wrote:
 Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle 
 driver.
 Hence do not allow exynos cpuidle driver registration for Exynos5420.

 Signed-off-by: Chander Kashyap chander.kash...@linaro.org
 Signed-off-by: Chander Kashyap k.chan...@samsung.com
 Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
 ---
  arch/arm/mach-exynos/cpuidle.c |3 +++
  1 file changed, 3 insertions(+)

 diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
 index 3dd385e..807a386 100644
 --- a/arch/arm/mach-exynos/cpuidle.c
 +++ b/arch/arm/mach-exynos/cpuidle.c
 @@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
 *pdev)
   int cpu_id, ret;
   struct cpuidle_device *device;

 + if (soc_is_exynos5420())
 + return -ENODEV;
 +
   if (soc_is_exynos5250())
   exynos5_core_down_clk();



 Why not put this in exynos.c in exynos_dt_machine_init(), so
 exynos_cpuidle_init() is called only if not running on Exynos5420?


That makes more sense.
I will update this

Thanks
 Best regards,
 Tomasz



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Re: [PATCH v5 0/6] add cpuidle support for Exynos5420

2014-05-14 Thread Chander Kashyap
Hi Daniel,

On 14 May 2014 15:26, Daniel Lezcano  wrote:
> On 05/14/2014 10:03 AM, Chander Kashyap wrote:
>>
>> Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.
>>
>> This patchset adds cpuidle support for Exynos5420 SoC based on
>> generic big.little cpuidle driver.
>
>
> Hi Chander,
>
> just a side question. I am not succeeding to have both cluster A7/A15 with
> the upstream kernel.
>
> How can I test your driver ?

Hmm on octa can be tested only for 4 cores. as cci is disabled.

>
> Did I miss something ?
>
> Thanks
>   -- Daniel
>
>
>> Tested on SMDK5420.
>>
>> This patch set depends on:
>> 1. [PATCH 0/5] MCPM backend for Exynos5420
>>        http://www.spinics.net/lists/arm-kernel/msg331100.html
>> Changelog is in respective patches.
>> Chander Kashyap (5):
>>driver: cpuidle-big-little: add of_device_id structure
>>arm: exynos: add generic function to calculate cpu number
>>cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
>>  driver
>>driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
>>exynos: cpuidle: do not allow cpuidle registration for Exynos5420
>>mcpm: exynos: populate suspend and powered_up callbacks
>>
>>   arch/arm/mach-exynos/cpuidle.c   |3 +++
>>   arch/arm/mach-exynos/mcpm-exynos.c   |   36
>> ++
>>   arch/arm/mach-exynos/regs-pmu.h  |9 +
>>   drivers/cpuidle/Kconfig.arm  |2 +-
>>   drivers/cpuidle/cpuidle-big_little.c |   12 +++-
>>   5 files changed, 60 insertions(+), 2 deletions(-)
>>
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>



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Re: [PATCH] PM / OPP: discard duplicate OPP additions

2014-05-14 Thread Chander Kashyap
Hi Nishant,

On 13 May 2014 18:53, Nishanth Menon  wrote:
> On Tue, May 13, 2014 at 2:41 AM, [Chander Kashyap
>  wrote:
>> From: Chander Kashyap 
>>
>> It may be possible to unregister and re-register the cpufreq driver.
>> One such example is arm big-little IKS cpufreq driver. While
>> re-registering the driver, same OPPs may get added again.
>>
>> This patch detects the duplicacy and discards them.
>
> Nice catch. Thanks for the same.
>
> That said, instead of ignoring it (skipping addition), should we do
> the following:
> a) if we find the same OPP being added, return error
> b) add a cleanup routine dev_pm_opp_remove ?
>
> Original design required OPP entries added by platform code and used
> by driver code, but things have changed over time.
>
>>
>> Signed-off-by: Chander Kashyap 
>> Signed-off-by: Inderpal Singh 
>> ---
>>  drivers/base/power/opp.c |   28 +++-
>>  1 file changed, 19 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
>> index 2553867..2e803a9 100644
>> --- a/drivers/base/power/opp.c
>> +++ b/drivers/base/power/opp.c
>> @@ -443,23 +443,33 @@ int dev_pm_opp_add(struct device *dev, unsigned long 
>> freq, unsigned long u_volt)
>> new_opp->u_volt = u_volt;
>> new_opp->available = true;
>>
>> -   /* Insert new OPP in order of increasing frequency */
>> +   /*
>> +* Insert new OPP in order of increasing frequency
>> +* and discard if already present
>> +*/
>> head = _opp->opp_list;
>> list_for_each_entry_rcu(opp, _opp->opp_list, node) {
>> -   if (new_opp->rate < opp->rate)
>> +   if (new_opp->rate <= opp->rate)
>> break;
>> else
>> head = >node;
>> }
>>
>
> say we do at this point:
> if (new_opp->rate == opp->rate) {
>   dev_err(dev, "%s: attempt to add duplicate OPP entry (rate=%ld)\n",
> __func__, new_opp->rate)
>kfree(new_opp);
> return -EINVAL;
> }

Yes this is more cleaner.
But instead of dev_err,  we should use dev_warn and secondly
return 0 rather than EINVAL, as there are independent users for this function

> we could avoid the change below, right?
>
>> -   list_add_rcu(_opp->node, head);
>> -   mutex_unlock(_opp_list_lock);
>> +   if (new_opp->rate != opp->rate) {
>> +   list_add_rcu(_opp->node, head);
>> +   mutex_unlock(_opp_list_lock);
>> +
>> +   /*
>> +* Notify the changes in the availability of the operable
>> +* frequency/voltage list.
>> +*/
>> +   srcu_notifier_call_chain(_opp->head,
>> +   OPP_EVENT_ADD, new_opp);
>> +   } else {
>> +   mutex_unlock(_opp_list_lock);
>> +   kfree(new_opp);
>> +   }
>>
>> -   /*
>> -* Notify the changes in the availability of the operable
>> -* frequency/voltage list.
>> -*/
>> -   srcu_notifier_call_chain(_opp->head, OPP_EVENT_ADD, new_opp);
>> return 0;
>>  }
>>  EXPORT_SYMBOL_GPL(dev_pm_opp_add);
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>> the body of a message to majord...@vger.kernel.org
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[PATCH v5 2/6] arm: exynos: add generic function to calculate cpu number

2014-05-14 Thread Chander Kashyap
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multi-cluster SoC's e.g Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
 arch/arm/mach-exynos/regs-pmu.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4179f6a..485aefd 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -325,4 +325,13 @@
 
 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
 
+#include 
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+   return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

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[PATCH v5 3/6] cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little driver

2014-05-14 Thread Chander Kashyap
Add support to select generic big-little cpuidle driver for Samsung Exynos
series SoC's. This is required for Exynos big-little SoC's eg, Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
Changes in v4:
1. Typo fixed from SOC_EXYNOS5420 to ARCH_EXYNOS
2. Commit message updated
Changes in v3: None
Changes in v2:
1. Changed config macro from SOC_EXYNOS5420 to ARCH_EXYNOS
 drivers/cpuidle/Kconfig.arm |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 97ccc31..d9596e7 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_BIG_LITTLE_CPUIDLE
bool "Support for ARM big.LITTLE processors"
-   depends on ARCH_VEXPRESS_TC2_PM
+   depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
help
-- 
1.7.9.5

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[PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Acked-by: Daniel Lezcano 
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 3dd385e..807a386 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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[PATCH v5 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-14 Thread Chander Kashyap
Add "samsung,exynos5420" compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
Acked-by: Daniel Lezcano 
---
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = "arm,vexpress,v2p-ca15_a7" },
+   { .compatible = "samsung,exynos5420" },
{},
 };
 
-- 
1.7.9.5

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[PATCH v5 0/6] add cpuidle support for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 +++
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v5 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-14 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = "arm,vexpress,v2p-ca15_a7" },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path("/");
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible("arm,vexpress,v2p-ca15_a7"))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH v5 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-14 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap 
Signed-off-by: Chander Kashyap 
---
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: "This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register."
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH v5 6/6] mcpm: exynos: populate suspend and powered_up callbacks

2014-05-14 Thread Chander Kashyap
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
Changes in v5:
1. Add comment to address cache access while c-bit is cleared in SCLTR
2. Make exynos_powered_up static
Changes in v4: None
Changes in v3:
1. Removed coherency enablement after suspend failure.
2. Use generic function to poweron cpu.
changes in v2:
1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr
 arch/arm/mach-exynos/mcpm-exynos.c |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-exynos/mcpm-exynos.c 
b/arch/arm/mach-exynos/mcpm-exynos.c
index c6bb3a4..623dfa7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -253,10 +253,46 @@ static int exynos_power_down_finish(unsigned int cpu, 
unsigned int cluster)
return -ETIMEDOUT; /* timeout */
 }
 
+static void exynos_powered_up(void)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   arch_spin_lock(exynos_mcpm_lock);
+   if (cpu_use_count[cpu][cluster] == 0)
+   cpu_use_count[cpu][cluster] = 1;
+   arch_spin_unlock(exynos_mcpm_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+   unsigned int mpidr, cpunr;
+
+   exynos_power_down();
+
+   /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+*
+* CAUTION: This function requires the stack data to be visible through
+* power down and can only be executed on processors like A15 and A7
+* that hit the cache with the C bit clear in the SCTLR register.
+   */
+   mpidr = read_cpuid_mpidr();
+   cpunr = exynos_pmu_cpunr(mpidr);
+
+   exynos_cpu_power_up(cpunr);
+}
+
 static const struct mcpm_platform_ops exynos_power_ops = {
.power_up   = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish  = exynos_power_down_finish,
+   .suspend= exynos_suspend,
+   .powered_up = exynos_powered_up,
 };
 
 static void __init exynos_mcpm_usage_count_init(void)
-- 
1.7.9.5

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[PATCH v5 0/6] add cpuidle support for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores.

This patchset adds cpuidle support for Exynos5420 SoC based on
generic big.little cpuidle driver.

Tested on SMDK5420.

This patch set depends on:
1. [PATCH 0/5] MCPM backend for Exynos5420
   http://www.spinics.net/lists/arm-kernel/msg331100.html
Changelog is in respective patches.
Chander Kashyap (5):
  driver: cpuidle-big-little: add of_device_id structure
  arm: exynos: add generic function to calculate cpu number
  cpuidle: config: Add ARCH_EXYNOS entry to select cpuidle-big-little
driver
  driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
  exynos: cpuidle: do not allow cpuidle registration for Exynos5420
  mcpm: exynos: populate suspend and powered_up callbacks

 arch/arm/mach-exynos/cpuidle.c   |3 +++
 arch/arm/mach-exynos/mcpm-exynos.c   |   36 ++
 arch/arm/mach-exynos/regs-pmu.h  |9 +
 drivers/cpuidle/Kconfig.arm  |2 +-
 drivers/cpuidle/cpuidle-big_little.c |   12 +++-
 5 files changed, 60 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v5 4/6] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420

2014-05-14 Thread Chander Kashyap
Add samsung,exynos5420 compatible string to initialize generic
big-little cpuidle driver for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
Changes in v4: None
Changes in v3:
1. Add compatible string to of_device_id table insted comparing 
directoly
Changes in v2: none

 drivers/cpuidle/cpuidle-big_little.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index 4cd02bd..344d79fa 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -165,6 +165,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver 
*drv, int cpu_id)
 
 static const struct of_device_id compatible_machine_match[] = {
{ .compatible = arm,vexpress,v2p-ca15_a7 },
+   { .compatible = samsung,exynos5420 },
{},
 };
 
-- 
1.7.9.5

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[PATCH v5 1/6] driver: cpuidle-big-little: add of_device_id structure

2014-05-14 Thread Chander Kashyap
This driver will be used by many big.Little Soc's. As of now it does
string matching of hardcoded compatible string to init the driver. This
comparison list will keep on growing with addition of new SoC's.
Hence add of_device_id structure to collect the compatible strings of
SoC's using this driver.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
 drivers/cpuidle/cpuidle-big_little.c |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/cpuidle/cpuidle-big_little.c 
b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..4cd02bd 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -163,14 +163,23 @@ static int __init bl_idle_driver_init(struct 
cpuidle_driver *drv, int cpu_id)
return 0;
 }
 
+static const struct of_device_id compatible_machine_match[] = {
+   { .compatible = arm,vexpress,v2p-ca15_a7 },
+   {},
+};
+
 static int __init bl_idle_init(void)
 {
int ret;
+   struct device_node *root = of_find_node_by_path(/);
+
+   if (!root)
+   return -ENODEV;
 
/*
 * Initialize the driver just for a compliant set of machines
 */
-   if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7))
+   if (!of_match_node(compatible_machine_match, root))
return -ENODEV;
/*
 * For now the differentiation between little and big cores
-- 
1.7.9.5

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[PATCH v5 5/6] exynos: cpuidle: do not allow cpuidle registration for Exynos5420

2014-05-14 Thread Chander Kashyap
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver.
Hence do not allow exynos cpuidle driver registration for Exynos5420.

Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
 arch/arm/mach-exynos/cpuidle.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 3dd385e..807a386 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -218,6 +218,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
int cpu_id, ret;
struct cpuidle_device *device;
 
+   if (soc_is_exynos5420())
+   return -ENODEV;
+
if (soc_is_exynos5250())
exynos5_core_down_clk();
 
-- 
1.7.9.5

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